{
  "area": 22.5216,
  "cell_footprint": "sky130_fd_sc_hd__sdlclkp",
  "cell_leakage_power": 0.0005517864,
  "clock_gating_integrated_cell": "latch_posedge_precontrol",
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "leakage_power": [
    {
      "value": 0.0006504,
      "when": "CLK&!GATE&!GCLK&!SCE"
    },
    {
      "value": 0.0005593,
      "when": "!CLK&GATE&!GCLK&!SCE"
    },
    {
      "value": 0.0004683,
      "when": "!CLK&!GATE&!GCLK&SCE"
    },
    {
      "value": 0.0003505,
      "when": "CLK&!GATE&GCLK&SCE"
    },
    {
      "value": 0.0005591,
      "when": "!CLK&GATE&!GCLK&SCE"
    },
    {
      "value": 0.0006089,
      "when": "!CLK&!GATE&!GCLK&!SCE"
    },
    {
      "value": 0.0004415,
      "when": "CLK&GATE&GCLK&!SCE"
    },
    {
      "value": 0.0004413,
      "when": "CLK&GATE&GCLK&SCE"
    },
    {
      "value": 0.0007194,
      "when": "CLK&GATE&!GCLK&!SCE"
    },
    {
      "value": 0.0006284,
      "when": "CLK&!GATE&!GCLK&SCE"
    },
    {
      "value": 0.0007192,
      "when": "CLK&GATE&!GCLK&SCE"
    },
    {
      "value": 0.0004753,
      "when": "CLK&!GATE&GCLK&!SCE"
    }
  ],
  "pg_pin,VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
    "voltage_name": "VNB"
  },
  "pg_pin,VPB": {
    "pg_type": "pwell",
    "physical_connection": "device_layer",
    "voltage_name": "VPB"
  },
  "pg_pin,VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
  },
  "pin,CLK": {
    "capacitance": 0.003652,
    "clock": "true",
    "clock_gate_clock_pin": "true",
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    "fall_capacitance": 0.003398,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
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          0.0316228,
          0.1,
          0.316228,
          1.0,
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          9.9999999
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        "values": [
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          0.0094073,
          0.0094461,
          0.0095691,
          0.0099578,
          0.0111871
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      },
      "rise_power,power_inputs_1": {
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          0.1,
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        "values": [
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          0.0040727,
          0.0040855,
          0.0041258
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.003907,
    "timing": {
      "fall_constraint,constraint_3_0_1": {
        "index_1": [
          0.01,
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        "values": [
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          16.6666666
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      "related_output_pin": "GCLK",
      "related_pin": "CLK",
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10
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  },
  "pin,GATE": {
    "capacitance": 0.001637,
    "clock": "false",
    "clock_gate_enable_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.00146,
    "internal_power": {
      "fall_power,power_inputs_1": {
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          0.1,
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          1.0,
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          9.9999999
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        "values": [
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      },
      "rise_power,power_inputs_1": {
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        "values": [
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          0.0086238
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001813,
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      {
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          "index_2": [
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              1.1171123,
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              -0.8860534,
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              4.8111633
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              3.3564922
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        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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          "index_2": [
            0.01,
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            9.9999999
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          "values": [
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              0.4011699,
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              4.0787336
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              -1.142401,
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              2.4362854
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            [
              -2.153957,
              -0.1562845,
              1.3917705
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
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      {
        "fall_constraint,vio_3_3_1": {
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          "index_2": [
            0.01,
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            9.9999999
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          "values": [
            [
              -1.0764912,
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              -6.803005
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              0.9156881,
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              -4.7742043
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              2.3337384,
              -0.6197448,
              -3.3268574
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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            0.01,
            5.0,
            9.9999999
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          "index_2": [
            0.01,
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            9.9999999
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          "values": [
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              -0.1536397,
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              -3.6810567
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            [
              1.2233054,
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              -2.2619974
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            [
              2.2476788,
              0.2921204,
              -1.2174824
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin,GCLK": {
    "clock_gate_out_pin": "true",
    "direction": "output",
    "internal_power": {
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            0.0095732,
            -0.0041747,
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            0.0149812,
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            0.0103485,
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            -0.2387969,
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            0.0148557,
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            0.0100484,
            -0.0034159,
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            -0.2388866,
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          [
            0.0144934,
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            0.009743,
            -0.0038467,
            -0.0552558,
            -0.2392503,
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          [
            0.0137433,
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            0.0089557,
            -0.0047479,
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            -0.2399558,
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      "related_pin": "CLK",
      "rise_power,power_outputs_1": {
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            0.9128842
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        ]
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    },
    "max_capacitance": 0.922404,
    "max_transition": 9.989407,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "state_function": "(CLK*M0)",
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      "cell_rise,del_1_7_7": {
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      "fall_transition,del_1_7_7": {
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        "index_2": [
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      "related_pin": "CLK",
      "rise_transition,del_1_7_7": {
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        ]
      },
      "timing_sense": "positive_unate",
      "timing_type": "combinational"
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  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VNB",
    "related_power_pin": "VPWR"
  },
  "pin,SCE": {
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    "clock": "false",
    "clock_gate_test_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001426,
    "internal_power": {
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        "values": [
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      "rise_power,power_inputs_1": {
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        "values": [
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001661,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
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          "index_2": [
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          "values": [
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              1.140916,
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              -2.322414,
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        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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          "index_2": [
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          "values": [
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              -2.056911,
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              1.6169903
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint,vio_3_3_1": {
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            0.01,
            5.0,
            9.9999999
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          "index_2": [
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          "values": [
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              -1.0966329,
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            [
              0.910195,
              -1.9865253,
              -4.6295511
            ],
            [
              2.3355693,
              -0.557489,
              -3.1840352
            ]
          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
            5.0,
            9.9999999
          ],
          "values": [
            [
              -0.1719502,
              -2.2758239,
              -3.8843037
            ],
            [
              1.1573873,
              -0.8860615,
              -2.4725688
            ],
            [
              2.157957,
              0.1328187,
              -1.440871
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "statetable,CLK GATE SCE,M0": {
    "table": [
      "L L L : - : L",
      "L L H : - : H",
      "L H L : - : H",
      "L H H : - : H",
      "H - - : - : N"
    ]
  }
}