{
  "area": 22.5216,
  "cell_footprint": "sky130_fd_sc_hd__sdlclkp",
  "cell_leakage_power": 0.0003579837,
  "clock_gating_integrated_cell": "latch_posedge_precontrol",
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "leakage_power": [
    {
      "value": 0.0004315,
      "when": "CLK&!GATE&!GCLK&!SCE"
    },
    {
      "value": 0.0003438,
      "when": "!CLK&GATE&!GCLK&!SCE"
    },
    {
      "value": 0.0002924,
      "when": "!CLK&!GATE&!GCLK&SCE"
    },
    {
      "value": 0.0002348,
      "when": "CLK&!GATE&GCLK&SCE"
    },
    {
      "value": 0.0003437,
      "when": "!CLK&GATE&!GCLK&SCE"
    },
    {
      "value": 0.0003946,
      "when": "!CLK&!GATE&!GCLK&!SCE"
    },
    {
      "value": 0.0002862,
      "when": "CLK&GATE&GCLK&!SCE"
    },
    {
      "value": 0.0002861,
      "when": "CLK&GATE&GCLK&SCE"
    },
    {
      "value": 0.0004625,
      "when": "CLK&GATE&!GCLK&!SCE"
    },
    {
      "value": 0.0004111,
      "when": "CLK&!GATE&!GCLK&SCE"
    },
    {
      "value": 0.0004624,
      "when": "CLK&GATE&!GCLK&SCE"
    },
    {
      "value": 0.0003467,
      "when": "CLK&!GATE&GCLK&!SCE"
    }
  ],
  "pg_pin,VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
    "voltage_name": "VNB"
  },
  "pg_pin,VPB": {
    "pg_type": "pwell",
    "physical_connection": "device_layer",
    "voltage_name": "VPB"
  },
  "pg_pin,VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
  },
  "pin,CLK": {
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    "clock": "true",
    "clock_gate_clock_pin": "true",
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    "fall_capacitance": 0.003426,
    "internal_power": {
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        "index_1": [
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          0.0316228,
          0.1,
          0.316228,
          1.0,
          3.16228,
          9.9999999
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        "values": [
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          0.0087913,
          0.0073111,
          0.007378,
          0.0075893,
          0.0082578,
          0.0103716
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      },
      "rise_power,power_inputs_1": {
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          0.0316228,
          0.1,
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          9.9999999
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        "values": [
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          0.003249,
          0.0032944,
          0.003438,
          0.003892
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.003499,
    "timing": {
      "fall_constraint,constraint_3_0_1": {
        "index_1": [
          0.01,
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          9.9999999
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        "values": [
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          8.3333333,
          16.6666666
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      },
      "related_output_pin": "GCLK",
      "related_pin": "CLK",
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10
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  },
  "pin,GATE": {
    "capacitance": 0.001598,
    "clock": "false",
    "clock_gate_enable_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001424,
    "internal_power": {
      "fall_power,power_inputs_1": {
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          0.1,
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          1.0,
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          9.9999999
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        "values": [
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      },
      "rise_power,power_inputs_1": {
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        "values": [
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          0.0060628,
          0.0080379
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001771,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
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            9.9999999
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          "index_2": [
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              1.4375469,
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              7.5046367
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              -0.7945006,
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              5.2249816
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              -2.4212911,
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              3.5743877
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        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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            0.01,
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          "index_2": [
            0.01,
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            9.9999999
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          "values": [
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              0.4670879,
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              4.5346658
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            [
              -1.2687438,
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              2.7109437
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            [
              -2.4322774,
              -0.2441751,
              1.508958
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint,vio_3_3_1": {
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            0.01,
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          "index_2": [
            0.01,
            5.0,
            9.9999999
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          "values": [
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              -1.3877705,
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              -7.4420432
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              0.8351217,
              -2.2282247,
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              2.4472638,
              -0.6160827,
              -3.5429219
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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            0.01,
            5.0,
            9.9999999
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          "index_2": [
            0.01,
            5.0,
            9.9999999
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          "values": [
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              -0.1774434,
              -2.3875181,
              -4.1021992
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            [
              1.3569724,
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              -2.5238382
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            [
              2.5369853,
              0.3891663,
              -1.3236836
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin,GCLK": {
    "clock_gate_out_pin": "true",
    "direction": "output",
    "internal_power": {
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          0.2207279,
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            -0.1835939,
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            0.0140276,
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            -0.0012011,
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            0.0151981,
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            0.0113598,
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            -0.0406478,
            -0.1818968,
            -0.6606245
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            0.0152324,
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            0.0112999,
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            -0.0407507,
            -0.1819816,
            -0.6607503
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            0.0147871,
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            0.010785,
            -0.0004892,
            -0.0412327,
            -0.1823966,
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            0.0138203,
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            0.009727,
            -0.0016221,
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            -0.1833324,
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            0.011821,
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            -0.6643319
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      "related_pin": "CLK",
      "rise_power,power_outputs_1": {
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            0.6888877
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        ]
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    },
    "max_capacitance": 0.746165,
    "max_transition": 10.040416,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "state_function": "(CLK*M0)",
    "timing": {
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      },
      "cell_rise,del_1_7_7": {
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      "fall_transition,del_1_7_7": {
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        "values": [
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      "related_pin": "CLK",
      "rise_transition,del_1_7_7": {
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            10.0112381
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        ]
      },
      "timing_sense": "positive_unate",
      "timing_type": "combinational"
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  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VNB",
    "related_power_pin": "VPWR"
  },
  "pin,SCE": {
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    "clock": "false",
    "clock_gate_test_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001396,
    "internal_power": {
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        "values": [
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      "rise_power,power_inputs_1": {
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        "values": [
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001628,
    "timing": [
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        "fall_constraint,vio_3_3_1": {
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            9.9999999
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          "index_2": [
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          "values": [
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              1.4613505,
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              5.1041321
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              3.4535382
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        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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          "index_2": [
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          "values": [
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              -1.1936706,
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              -2.3260762,
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint,vio_3_3_1": {
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            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
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            9.9999999
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          "values": [
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              -1.4097432,
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              -7.3157002
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            [
              0.8241354,
              -2.1970967,
              -5.0506938
            ],
            [
              2.4490947,
              -0.5757995,
              -3.414748
            ]
          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
            5.0,
            9.9999999
          ],
          "values": [
            [
              -0.199416,
              -2.4955504,
              -4.3054464
            ],
            [
              1.2873922,
              -0.9519795,
              -2.7362405
            ],
            [
              2.4344462,
              0.2207093,
              -1.5543965
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "statetable,CLK GATE SCE,M0": {
    "table": [
      "L L L : - : L",
      "L L H : - : H",
      "L H L : - : H",
      "L H H : - : H",
      "H - - : - : N"
    ]
  }
}