{
  "area": 22.5216,
  "cell_footprint": "sky130_fd_sc_hd__sdlclkp",
  "cell_leakage_power": 18.18696,
  "clock_gating_integrated_cell": "latch_posedge_precontrol",
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "leakage_power": [
    {
      "value": 19.9379979,
      "when": "CLK&!GATE&!GCLK&!SCE"
    },
    {
      "value": 15.3683875,
      "when": "!CLK&GATE&!GCLK&!SCE"
    },
    {
      "value": 15.3568838,
      "when": "!CLK&!GATE&!GCLK&SCE"
    },
    {
      "value": 17.0933738,
      "when": "CLK&!GATE&GCLK&SCE"
    },
    {
      "value": 13.2671483,
      "when": "!CLK&GATE&!GCLK&SCE"
    },
    {
      "value": 18.6796321,
      "when": "!CLK&!GATE&!GCLK&!SCE"
    },
    {
      "value": 17.1048846,
      "when": "CLK&GATE&GCLK&!SCE"
    },
    {
      "value": 15.0036872,
      "when": "CLK&GATE&GCLK&SCE"
    },
    {
      "value": 23.2957582,
      "when": "CLK&GATE&!GCLK&!SCE"
    },
    {
      "value": 23.2842421,
      "when": "CLK&!GATE&!GCLK&SCE"
    },
    {
      "value": 21.1946709,
      "when": "CLK&GATE&!GCLK&SCE"
    },
    {
      "value": 18.6569071,
      "when": "CLK&!GATE&GCLK&!SCE"
    }
  ],
  "pg_pin,VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
    "voltage_name": "VNB"
  },
  "pg_pin,VPB": {
    "pg_type": "pwell",
    "physical_connection": "device_layer",
    "voltage_name": "VPB"
  },
  "pg_pin,VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
  },
  "pin,CLK": {
    "capacitance": 0.004372,
    "clock": "true",
    "clock_gate_clock_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.004124,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
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          0.0230506,
          0.0531329,
          0.122474,
          0.282311,
          0.650743,
          1.5
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        "values": [
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          0.0168501,
          0.0165766,
          0.0169194,
          0.0177401,
          0.019662,
          0.0241227
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      },
      "rise_power,power_inputs_1": {
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          0.0230506,
          0.0531329,
          0.122474,
          0.282311,
          0.650743,
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        "values": [
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          0.0064301,
          0.0067258,
          0.0074314,
          0.0090816,
          0.0129092
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    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.004619,
    "timing": {
      "fall_constraint,constraint_3_0_1": {
        "index_1": [
          0.01,
          0.5,
          1.5
        ],
        "values": [
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          0.8333333,
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      },
      "related_output_pin": "GCLK",
      "related_pin": "CLK",
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10
    }
  },
  "pin,GATE": {
    "capacitance": 0.001964,
    "clock": "false",
    "clock_gate_enable_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001838,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
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          0.0230506,
          0.0531329,
          0.122474,
          0.282311,
          0.650743,
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        "values": [
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          0.022352,
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          0.025298,
          0.0295514
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      },
      "rise_power,power_inputs_1": {
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          0.650743,
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        "values": [
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          0.0130474,
          0.0133074,
          0.013935,
          0.0154104,
          0.01884
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      }
    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.00209,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            0.5,
            1.5
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          "index_2": [
            0.01,
            0.5,
            1.5
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          "values": [
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              0.1338359,
              0.2919088,
              0.4949525
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            [
              0.0648744,
              0.224168,
              0.4308737
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            [
              0.0351706,
              0.1920228,
              0.3999492
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            0.5,
            1.5
          ],
          "index_2": [
            0.01,
            0.5,
            1.5
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          "values": [
            [
              0.1167461,
              0.2076803,
              0.245929
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            [
              0.099054,
              0.1851055,
              0.2160299
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            [
              0.2219382,
              0.3079896,
              0.3376934
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
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            1.5
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          "index_2": [
            0.01,
            0.5,
            1.5
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          "values": [
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              -0.1115254,
              -0.2634948,
              -0.4470072
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            [
              -0.0572122,
              -0.2140645,
              -0.413446
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            [
              -0.0299499,
              -0.1855814,
              -0.3910664
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            0.5,
            1.5
          ],
          "index_2": [
            0.01,
            0.5,
            1.5
          ],
          "values": [
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              -0.0443867,
              -0.1304382,
              -0.1528177
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            [
              -0.0108255,
              -0.0907734,
              -0.113153
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            [
              -0.0153014,
              -0.0952493,
              -0.1225117
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
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    ]
  },
  "pin,GCLK": {
    "clock_gate_out_pin": "true",
    "direction": "output",
    "internal_power": {
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          0.1224745,
          0.2823108,
          0.6507428,
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          0.005389619,
          0.01769506,
          0.05809599,
          0.1907393,
          0.6262305
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        "values": [
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            0.0276287,
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            0.0072998,
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            -0.2168814,
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            0.0274434,
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            0.0206863,
            0.007065,
            -0.0380431,
            -0.2170406,
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            0.0274772,
            0.0257433,
            0.020658,
            0.0069946,
            -0.0380702,
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            0.0274708,
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            0.0206492,
            0.0070388,
            -0.0382172,
            -0.2171566,
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          [
            0.0308679,
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            0.0235989,
            0.0097956,
            -0.0373863,
            -0.2166272,
            -0.809435
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          [
            0.0478317,
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            0.0392073,
            0.020495,
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            -0.2143504,
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          [
            0.0613598,
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            0.0520463,
            0.0322766,
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            -0.2076197,
            -0.801064
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      "related_pin": "CLK",
      "rise_power,power_outputs_1": {
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          0.6262305
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        "values": [
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    },
    "max_capacitance": 0.626231,
    "max_transition": 1.498972,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "state_function": "(CLK*M0)",
    "timing": {
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      },
      "cell_rise,del_1_7_7": {
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      "fall_transition,del_1_7_7": {
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        "index_2": [
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        "values": [
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            0.0233523,
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            0.0314246,
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            0.0235144,
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            0.0233985,
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            0.0413572,
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      "related_pin": "CLK",
      "rise_transition,del_1_7_7": {
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        "index_2": [
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        "values": [
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            1.4970174
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            0.0239771,
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            0.0243881,
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            1.4960396
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        ]
      },
      "timing_sense": "positive_unate",
      "timing_type": "combinational"
    }
  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VNB",
    "related_power_pin": "VPWR"
  },
  "pin,SCE": {
    "capacitance": 0.001891,
    "clock": "false",
    "clock_gate_test_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001826,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
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          0.0531329,
          0.122474,
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          0.650743,
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        "values": [
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      "rise_power,power_inputs_1": {
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          0.0531329,
          0.122474,
          0.282311,
          0.650743,
          1.5
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        "values": [
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    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001955,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            0.5,
            1.5
          ],
          "index_2": [
            0.01,
            0.5,
            1.5
          ],
          "values": [
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              0.1436016,
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            [
              0.0734193,
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              0.3710593
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              0.0412741,
              0.1700501,
              0.3425762
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            0.5,
            1.5
          ],
          "index_2": [
            0.01,
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            1.5
          ],
          "values": [
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              0.1277324,
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            [
              0.1100404,
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              0.2685202
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            [
              0.2329245,
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              0.3901836
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            0.5,
            1.5
          ],
          "index_2": [
            0.01,
            0.5,
            1.5
          ],
          "values": [
            [
              -0.1225117,
              -0.2415221,
              -0.3896341
            ],
            [
              -0.0657572,
              -0.1933125,
              -0.3560729
            ],
            [
              -0.0372741,
              -0.1648294,
              -0.3349141
            ]
          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            0.5,
            1.5
          ],
          "index_2": [
            0.01,
            0.5,
            1.5
          ],
          "values": [
            [
              -0.0541523,
              -0.1536315,
              -0.2053079
            ],
            [
              -0.0242533,
              -0.1151875,
              -0.1656432
            ],
            [
              -0.0323913,
              -0.1221048,
              -0.175002
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "statetable,CLK GATE SCE,M0": {
    "table": [
      "L L L : - : L",
      "L L H : - : H",
      "L H L : - : H",
      "L H H : - : H",
      "H - - : - : N"
    ]
  }
}