{
  "area": 20.0192,
  "cell_footprint": "sky130_fd_sc_hd__sdlclkp",
  "cell_leakage_power": 15.83396,
  "clock_gating_integrated_cell": "latch_posedge_precontrol",
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "leakage_power": [
    {
      "value": 17.6431385,
      "when": "CLK&!GATE&!GCLK&!SCE"
    },
    {
      "value": 13.4343088,
      "when": "!CLK&GATE&!GCLK&!SCE"
    },
    {
      "value": 13.4427598,
      "when": "!CLK&!GATE&!GCLK&SCE"
    },
    {
      "value": 14.4126835,
      "when": "CLK&!GATE&GCLK&SCE"
    },
    {
      "value": 11.5568044,
      "when": "!CLK&GATE&!GCLK&SCE"
    },
    {
      "value": 16.5442486,
      "when": "!CLK&!GATE&!GCLK&!SCE"
    },
    {
      "value": 14.4042342,
      "when": "CLK&GATE&GCLK&!SCE"
    },
    {
      "value": 12.5267521,
      "when": "CLK&GATE&GCLK&SCE"
    },
    {
      "value": 20.677092,
      "when": "CLK&GATE&!GCLK&!SCE"
    },
    {
      "value": 20.6855315,
      "when": "CLK&!GATE&!GCLK&SCE"
    },
    {
      "value": 18.7997191,
      "when": "CLK&GATE&!GCLK&SCE"
    },
    {
      "value": 15.8802216,
      "when": "CLK&!GATE&GCLK&!SCE"
    }
  ],
  "pg_pin,VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
    "voltage_name": "VNB"
  },
  "pg_pin,VPB": {
    "pg_type": "pwell",
    "physical_connection": "device_layer",
    "voltage_name": "VPB"
  },
  "pg_pin,VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
  },
  "pin,CLK": {
    "capacitance": 0.003442,
    "clock": "true",
    "clock_gate_clock_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.003162,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
          0.01,
          0.0281727,
          0.0793701,
          0.223607,
          0.629961,
          1.77477,
          5.0
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        "values": [
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          0.0145044,
          0.0147406,
          0.0146919,
          0.0146858,
          0.0147994,
          0.0152503
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      },
      "rise_power,power_inputs_1": {
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          0.0793701,
          0.223607,
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        "values": [
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          0.0067687,
          0.0067504,
          0.0068008
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    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.003721,
    "timing": {
      "fall_constraint,constraint_3_0_1": {
        "index_1": [
          0.01,
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          5.0
        ],
        "values": [
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          4.1666666,
          8.3333333
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      },
      "related_output_pin": "GCLK",
      "related_pin": "CLK",
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10
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  },
  "pin,GATE": {
    "capacitance": 0.001798,
    "clock": "false",
    "clock_gate_enable_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.0017,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
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          0.0793701,
          0.223607,
          0.629961,
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        "values": [
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          0.019592
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      },
      "rise_power,power_inputs_1": {
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        "values": [
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          0.0116507,
          0.0115688
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    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001897,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            2.5,
            5.0
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          "index_2": [
            0.01,
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            5.0
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          "values": [
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              0.4139873,
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              1.8934714
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              -0.1642109,
              0.7179424,
              1.2914694
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            [
              -0.4447692,
              0.4227357,
              0.9926006
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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            0.01,
            2.5,
            5.0
          ],
          "index_2": [
            0.01,
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            5.0
          ],
          "values": [
            [
              0.2382061,
              0.8969707,
              1.2434469
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            [
              -0.1349141,
              0.4908916,
              0.8117331
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            [
              -0.2213805,
              0.400763,
              0.7234355
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
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      {
        "fall_constraint,vio_3_3_1": {
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            5.0
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          "index_2": [
            0.01,
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            5.0
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          "values": [
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              -0.3697041,
              -1.2573506,
              -1.7979187
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            [
              0.1773662,
              -0.701125,
              -1.2654968
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            [
              0.4542624,
              -0.4095804,
              -0.9757832
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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            0.01,
            2.5,
            5.0
          ],
          "index_2": [
            0.01,
            2.5,
            5.0
          ],
          "values": [
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              -0.1096943,
              -0.7300068,
              -1.0307067
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            [
              0.2304668,
              -0.367873,
              -0.6630798
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            [
              0.3920065,
              -0.2063333,
              -0.50154
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
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    ]
  },
  "pin,GCLK": {
    "clock_gate_out_pin": "true",
    "direction": "output",
    "internal_power": {
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          1.774768,
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          0.6439308
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            -0.2366651,
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            0.0044075,
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            -0.2368556,
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            0.0099779,
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            0.0046817,
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          [
            0.0096372,
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            0.0043075,
            -0.0106292,
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          [
            0.0095277,
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            -0.237062,
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          [
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            -0.2372816,
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      "related_pin": "CLK",
      "rise_power,power_outputs_1": {
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    },
    "max_capacitance": 0.19044,
    "max_transition": 1.500622,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "state_function": "(CLK*M0)",
    "timing": {
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      },
      "cell_rise,del_1_7_7": {
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      "fall_transition,del_1_7_7": {
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        "index_2": [
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        "values": [
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            0.0376542,
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      "related_pin": "CLK",
      "rise_transition,del_1_7_7": {
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        "index_2": [
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        "values": [
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        ]
      },
      "timing_sense": "positive_unate",
      "timing_type": "combinational"
    }
  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VNB",
    "related_power_pin": "VPWR"
  },
  "pin,SCE": {
    "capacitance": 0.001744,
    "clock": "false",
    "clock_gate_test_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001678,
    "internal_power": {
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        ],
        "values": [
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      "rise_power,power_inputs_1": {
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          0.629961,
          1.77477,
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        ],
        "values": [
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    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.00181,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            2.5,
            5.0
          ],
          "index_2": [
            0.01,
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            5.0
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          "values": [
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              0.4322979,
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              -0.1587178,
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              -0.4447692,
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              0.8534404
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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            2.5,
            5.0
          ],
          "index_2": [
            0.01,
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            5.0
          ],
          "values": [
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              0.2583477,
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              -0.100124,
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            [
              -0.1829284,
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              0.8754131
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            2.5,
            5.0
          ],
          "index_2": [
            0.01,
            2.5,
            5.0
          ],
          "values": [
            [
              -0.3880147,
              -1.1804463,
              -1.6624206
            ],
            [
              0.170042,
              -0.6242207,
              -1.1245056
            ],
            [
              0.4542624,
              -0.3363382,
              -0.8366231
            ]
          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            2.5,
            5.0
          ],
          "index_2": [
            0.01,
            2.5,
            5.0
          ],
          "values": [
            [
              -0.1280049,
              -0.8178975,
              -1.1845153
            ],
            [
              0.1920146,
              -0.4630879,
              -0.8187194
            ],
            [
              0.342568,
              -0.3052103,
              -0.6590107
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "statetable,CLK GATE SCE,M0": {
    "table": [
      "L L L : - : L",
      "L L H : - : H",
      "L H L : - : H",
      "L H H : - : H",
      "H - - : - : N"
    ]
  }
}