{
  "area": 20.0192,
  "cell_footprint": "sky130_fd_sc_hd__sdlclkp",
  "cell_leakage_power": 10.57664,
  "clock_gating_integrated_cell": "latch_posedge_precontrol",
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "leakage_power": [
    {
      "value": 11.7535137,
      "when": "CLK&!GATE&!GCLK&!SCE"
    },
    {
      "value": 8.8979553,
      "when": "!CLK&GATE&!GCLK&!SCE"
    },
    {
      "value": 8.9559498,
      "when": "!CLK&!GATE&!GCLK&SCE"
    },
    {
      "value": 9.6616875,
      "when": "CLK&!GATE&GCLK&SCE"
    },
    {
      "value": 7.7277651,
      "when": "!CLK&GATE&!GCLK&SCE"
    },
    {
      "value": 10.9843477,
      "when": "!CLK&!GATE&!GCLK&!SCE"
    },
    {
      "value": 9.6036965,
      "when": "CLK&GATE&GCLK&!SCE"
    },
    {
      "value": 8.4335241,
      "when": "CLK&GATE&GCLK&SCE"
    },
    {
      "value": 13.7479379,
      "when": "CLK&GATE&!GCLK&!SCE"
    },
    {
      "value": 13.8059209,
      "when": "CLK&!GATE&!GCLK&SCE"
    },
    {
      "value": 12.577825,
      "when": "CLK&GATE&!GCLK&SCE"
    },
    {
      "value": 10.7695008,
      "when": "CLK&!GATE&GCLK&!SCE"
    }
  ],
  "pg_pin,VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
    "voltage_name": "VNB"
  },
  "pg_pin,VPB": {
    "pg_type": "pwell",
    "physical_connection": "device_layer",
    "voltage_name": "VPB"
  },
  "pg_pin,VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
  },
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    "capacitance": 0.00324,
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    "clock_gate_clock_pin": "true",
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    "fall_capacitance": 0.00307,
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          0.1,
          0.316228,
          1.0,
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          9.9999999
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        "values": [
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          0.0106637,
          0.0105766,
          0.0105108,
          0.0105121,
          0.0107262
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      },
      "rise_power,power_inputs_1": {
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        "values": [
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          0.0046303
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.00341,
    "timing": {
      "fall_constraint,constraint_3_0_1": {
        "index_1": [
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        "values": [
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          16.6666666
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      "related_output_pin": "GCLK",
      "related_pin": "CLK",
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10
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  },
  "pin,GATE": {
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    "clock": "false",
    "clock_gate_enable_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.00166,
    "internal_power": {
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      },
      "rise_power,power_inputs_1": {
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        "values": [
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001771,
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      {
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          "index_2": [
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              -0.7560485,
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              2.4545961
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              1.6041728
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        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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          "index_2": [
            0.01,
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            9.9999999
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          "values": [
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              0.3334209,
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              2.8665752
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              -0.6406921,
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              1.7624573
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            [
              -1.1029316,
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              1.2855694
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
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      {
        "fall_constraint,vio_3_3_1": {
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          "index_2": [
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          "values": [
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              -0.6059102,
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              0.7692038,
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              -2.4194681
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              1.5610332,
              -0.2956481,
              -1.5818623
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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            0.01,
            5.0,
            9.9999999
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          "index_2": [
            0.01,
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            9.9999999
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          "values": [
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              -0.1554707,
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              0.7417379,
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              -1.5625345
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              1.2552471,
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              -1.036208
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
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    ]
  },
  "pin,GCLK": {
    "clock_gate_out_pin": "true",
    "direction": "output",
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            0.0032313,
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            -0.2538831,
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            0.0077277,
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            -0.0649646,
            -0.2540134,
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          [
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            -0.2543071,
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      "related_pin": "CLK",
      "rise_power,power_outputs_1": {
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    },
    "max_capacitance": 0.949107,
    "max_transition": 10.026098,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "state_function": "(CLK*M0)",
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      "cell_rise,del_1_7_7": {
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      "fall_transition,del_1_7_7": {
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        "values": [
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      "related_pin": "CLK",
      "rise_transition,del_1_7_7": {
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        ]
      },
      "timing_sense": "positive_unate",
      "timing_type": "combinational"
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  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VNB",
    "related_power_pin": "VPWR"
  },
  "pin,SCE": {
    "capacitance": 0.001707,
    "clock": "false",
    "clock_gate_test_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001668,
    "internal_power": {
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        "values": [
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      "rise_power,power_inputs_1": {
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        "values": [
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001746,
    "timing": [
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        "fall_constraint,vio_3_3_1": {
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          "index_2": [
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          "values": [
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        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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          "index_2": [
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          "values": [
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              -0.5747741,
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              -1.0187031,
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint,vio_3_3_1": {
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          "index_2": [
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          "values": [
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              -0.6297138,
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            [
              0.7673727,
              -1.0050801,
              -2.1942483
            ],
            [
              1.5756816,
              -0.1784606,
              -1.3584736
            ]
          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
            5.0,
            9.9999999
          ],
          "values": [
            [
              -0.1792744,
              -1.8034118,
              -2.7984883
            ],
            [
              0.67582,
              -0.8805684,
              -1.8555033
            ],
            [
              1.1636943,
              -0.3725524,
              -1.3419941
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "statetable,CLK GATE SCE,M0": {
    "table": [
      "L L L : - : L",
      "L L H : - : H",
      "L H L : - : H",
      "L H H : - : H",
      "H - - : - : N"
    ]
  }
}