{
  "area": 18.768,
  "cell_footprint": "sky130_fd_sc_hd__sdlclkp",
  "cell_leakage_power": 0.0004138534,
  "clock_gating_integrated_cell": "latch_posedge_precontrol",
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "leakage_power": [
    {
      "value": 0.0004456,
      "when": "CLK&!GATE&!GCLK&!SCE"
    },
    {
      "value": 0.0003522,
      "when": "!CLK&GATE&!GCLK&!SCE"
    },
    {
      "value": 0.0002612,
      "when": "!CLK&!GATE&!GCLK&SCE"
    },
    {
      "value": 0.0003537,
      "when": "CLK&!GATE&GCLK&SCE"
    },
    {
      "value": 0.000352,
      "when": "!CLK&GATE&!GCLK&SCE"
    },
    {
      "value": 0.0003812,
      "when": "!CLK&!GATE&!GCLK&!SCE"
    },
    {
      "value": 0.0004447,
      "when": "CLK&GATE&GCLK&!SCE"
    },
    {
      "value": 0.0004445,
      "when": "CLK&GATE&GCLK&SCE"
    },
    {
      "value": 0.0005146,
      "when": "CLK&GATE&!GCLK&!SCE"
    },
    {
      "value": 0.0004236,
      "when": "CLK&!GATE&!GCLK&SCE"
    },
    {
      "value": 0.0005144,
      "when": "CLK&GATE&!GCLK&SCE"
    },
    {
      "value": 0.0004784,
      "when": "CLK&!GATE&GCLK&!SCE"
    }
  ],
  "pg_pin,VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
    "voltage_name": "VNB"
  },
  "pg_pin,VPB": {
    "pg_type": "pwell",
    "physical_connection": "device_layer",
    "voltage_name": "VPB"
  },
  "pg_pin,VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
  },
  "pin,CLK": {
    "capacitance": 0.003045,
    "clock": "true",
    "clock_gate_clock_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.002818,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
          0.01,
          0.0316228,
          0.1,
          0.316228,
          1.0,
          3.16228,
          9.9999999
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        "values": [
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          0.0099555,
          0.0088485,
          0.0088855,
          0.0090026,
          0.0093729,
          0.0105439
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      },
      "rise_power,power_inputs_1": {
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          0.01,
          0.0316228,
          0.1,
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          1.0,
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          9.9999999
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        "values": [
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          0.0047376,
          0.0047396,
          0.0047457,
          0.0047651
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.003272,
    "timing": {
      "fall_constraint,constraint_3_0_1": {
        "index_1": [
          0.01,
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        "values": [
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          8.3333333,
          16.6666666
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      },
      "related_output_pin": "GCLK",
      "related_pin": "CLK",
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10
    }
  },
  "pin,GATE": {
    "capacitance": 0.001623,
    "clock": "false",
    "clock_gate_enable_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001452,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
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          0.0316228,
          0.1,
          0.316228,
          1.0,
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          9.9999999
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        "values": [
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          0.0036202,
          0.0043265,
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      },
      "rise_power,power_inputs_1": {
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          9.9999999
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        "values": [
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          0.0066245,
          0.0070083,
          0.0082221
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001795,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
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            0.01,
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            9.9999999
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          "index_2": [
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          "values": [
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              1.1226055,
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              6.8637676
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            [
              -0.8878844,
              2.074754,
              4.8184877
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              -2.3114277,
              0.6402243,
              3.3564922
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
            5.0,
            9.9999999
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          "values": [
            [
              0.2913066,
              2.3695455,
              3.965208
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            [
              -1.1533873,
              0.8625957,
              2.4051575
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            [
              -2.1612813,
              -0.172764,
              1.3679668
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint,vio_3_3_1": {
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            0.01,
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          "index_2": [
            0.01,
            5.0,
            9.9999999
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          "values": [
            [
              -1.1204365,
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              -6.8469503
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            [
              0.8900534,
              -2.0744159,
              -4.8163186
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            [
              2.3172589,
              -0.6325622,
              -3.3616474
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
            5.0,
            9.9999999
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          "values": [
            [
              -0.1499775,
              -2.1622985,
              -3.6700702
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            [
              1.2233054,
              -0.7487324,
              -2.2510111
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            [
              2.2476788,
              0.2994447,
              -1.204665
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin,GCLK": {
    "clock_gate_out_pin": "true",
    "direction": "output",
    "internal_power": {
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        "index_1": [
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          10
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          0.004272897,
          0.01249104,
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          0.1067459,
          0.3120522
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        "values": [
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            -0.09773,
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          [
            0.0054535,
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            0.0029581,
            -0.0046939,
            -0.0281903,
            -0.0970172,
            -0.2982343
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            0.0063657,
            0.0059881,
            0.0038778,
            -0.0037775,
            -0.0272712,
            -0.0960814,
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          [
            0.0062682,
            0.0058889,
            0.003748,
            -0.0039066,
            -0.0273853,
            -0.0962015,
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          [
            0.0060303,
            0.005572,
            0.0033881,
            -0.0042767,
            -0.0277104,
            -0.0965114,
            -0.2977186
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          [
            0.0052807,
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            0.0025429,
            -0.0049279,
            -0.0283177,
            -0.0970721,
            -0.2982598
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            0.0050659,
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            -0.2995537
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      "related_pin": "CLK",
      "rise_power,power_outputs_1": {
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        "values": [
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            0.3081249
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        ]
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    },
    "max_capacitance": 0.312052,
    "max_transition": 10.010612,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "state_function": "(CLK*M0)",
    "timing": {
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      },
      "cell_rise,del_1_7_7": {
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        "index_2": [
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            4.6217297,
            6.2839618,
            11.1443716
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      },
      "fall_transition,del_1_7_7": {
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          1,
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          10
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        "index_2": [
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        "values": [
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            0.0469828,
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            0.3616853,
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            0.0469666,
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            0.1817708,
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            1.0200694,
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        ]
      },
      "related_pin": "CLK",
      "rise_transition,del_1_7_7": {
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        "index_2": [
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        "values": [
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          [
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            1.2219447,
            3.4745273,
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        ]
      },
      "timing_sense": "positive_unate",
      "timing_type": "combinational"
    }
  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VNB",
    "related_power_pin": "VPWR"
  },
  "pin,SCE": {
    "capacitance": 0.001544,
    "clock": "false",
    "clock_gate_test_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001426,
    "internal_power": {
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          0.1,
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          1.0,
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        "values": [
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      },
      "rise_power,power_inputs_1": {
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        "values": [
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001662,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
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            5.0,
            9.9999999
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          "index_2": [
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          "values": [
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              1.1482402,
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              4.6701721
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              -2.318752,
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              3.2136698
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        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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            0.01,
            5.0,
            9.9999999
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          "index_2": [
            0.01,
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          "values": [
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              -1.0874694,
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              2.6138978
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              -2.0642354,
              -0.0152933,
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
            5.0,
            9.9999999
          ],
          "values": [
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              -1.1405781,
              -4.0556089,
              -6.709621
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            [
              0.8845602,
              -2.0139912,
              -4.6661721
            ],
            [
              2.3190899,
              -0.5739684,
              -3.2188252
            ]
          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
            5.0,
            9.9999999
          ],
          "values": [
            [
              -0.1701191,
              -2.2703308,
              -3.8714864
            ],
            [
              1.1628805,
              -0.8787373,
              -2.4597512
            ],
            [
              2.1597882,
              0.1401429,
              -1.4298847
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "statetable,CLK GATE SCE,M0": {
    "table": [
      "L L L : - : L",
      "L L H : - : H",
      "L H L : - : H",
      "L H H : - : H",
      "H - - : - : N"
    ]
  }
}