{
  "area": 18.768,
  "cell_footprint": "sky130_fd_sc_hd__sdlclkp",
  "cell_leakage_power": 0.0002779064,
  "clock_gating_integrated_cell": "latch_posedge_precontrol",
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "leakage_power": [
    {
      "value": 0.0003198,
      "when": "CLK&!GATE&!GCLK&!SCE"
    },
    {
      "value": 0.0002302,
      "when": "!CLK&GATE&!GCLK&!SCE"
    },
    {
      "value": 0.0001788,
      "when": "!CLK&!GATE&!GCLK&SCE"
    },
    {
      "value": 0.0002245,
      "when": "CLK&!GATE&GCLK&SCE"
    },
    {
      "value": 0.00023,
      "when": "!CLK&GATE&!GCLK&SCE"
    },
    {
      "value": 0.0002625,
      "when": "!CLK&!GATE&!GCLK&!SCE"
    },
    {
      "value": 0.0002759,
      "when": "CLK&GATE&GCLK&!SCE"
    },
    {
      "value": 0.0002758,
      "when": "CLK&GATE&GCLK&SCE"
    },
    {
      "value": 0.0003508,
      "when": "CLK&GATE&!GCLK&!SCE"
    },
    {
      "value": 0.0002995,
      "when": "CLK&!GATE&!GCLK&SCE"
    },
    {
      "value": 0.0003507,
      "when": "CLK&GATE&!GCLK&SCE"
    },
    {
      "value": 0.0003363,
      "when": "CLK&!GATE&GCLK&!SCE"
    }
  ],
  "pg_pin,VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
    "voltage_name": "VNB"
  },
  "pg_pin,VPB": {
    "pg_type": "pwell",
    "physical_connection": "device_layer",
    "voltage_name": "VPB"
  },
  "pg_pin,VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
  },
  "pin,CLK": {
    "capacitance": 0.00281,
    "clock": "true",
    "clock_gate_clock_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.0027,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
          0.01,
          0.0316228,
          0.1,
          0.316228,
          1.0,
          3.16228,
          9.9999999
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        "values": [
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          0.0068175,
          0.0068824,
          0.0070875,
          0.0077361,
          0.009787
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      },
      "rise_power,power_inputs_1": {
        "index_1": [
          0.01,
          0.0316228,
          0.1,
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          1.0,
          3.16228,
          9.9999999
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        "values": [
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          0.0038406,
          0.0038546,
          0.0038989,
          0.0040388,
          0.0044813
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.00292,
    "timing": {
      "fall_constraint,constraint_3_0_1": {
        "index_1": [
          0.01,
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          9.9999999
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        "values": [
          0.566768,
          8.3333333,
          16.6666666
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      },
      "related_output_pin": "GCLK",
      "related_pin": "CLK",
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10
    }
  },
  "pin,GATE": {
    "capacitance": 0.001586,
    "clock": "false",
    "clock_gate_enable_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001417,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
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          0.0316228,
          0.1,
          0.316228,
          1.0,
          3.16228,
          9.9999999
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        "values": [
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          0.0028099,
          0.0030243,
          0.0037026,
          0.0058474,
          0.01263
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      },
      "rise_power,power_inputs_1": {
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          0.01,
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        "values": [
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          0.0053764,
          0.0059259,
          0.0076636
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001754,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
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          "index_2": [
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          "values": [
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              1.4485332,
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              7.5101301
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            [
              -0.7963317,
              2.27617,
              5.228644
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            [
              -2.4176289,
              0.6530417,
              3.5780499
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
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          "index_2": [
            0.01,
            5.0,
            9.9999999
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          "values": [
            [
              0.337083,
              2.6039207,
              4.4046613
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            [
              -1.2797302,
              0.9340068,
              2.6798157
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            [
              -2.4396016,
              -0.2624857,
              1.4833233
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
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          "index_2": [
            0.01,
            5.0,
            9.9999999
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          "values": [
            [
              -1.4445332,
              -4.5335142,
              -7.4969748
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            [
              0.8021628,
              -2.2703388,
              -5.226475
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            [
              2.4234599,
              -0.6472106,
              -3.5740499
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
            5.0,
            9.9999999
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          "values": [
            [
              -0.1756123,
              -2.380194,
              -4.0893819
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            [
              1.3588033,
              -0.8109883,
              -2.5128519
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            [
              2.5333232,
              0.3964906,
              -1.3090352
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin,GCLK": {
    "clock_gate_out_pin": "true",
    "direction": "output",
    "internal_power": {
      "fall_power,power_outputs_1": {
        "index_1": [
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          0.03162278,
          0.1,
          0.3162278,
          1,
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          10
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        "index_2": [
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          0.004017679,
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          0.09151307,
          0.2594094
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        "values": [
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            0.0051402,
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            -0.0223668,
            -0.0763222,
            -0.2292931
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          [
            0.0059652,
            0.005646,
            0.0038258,
            -0.0025375,
            -0.0215251,
            -0.0754747,
            -0.2284469
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            0.0073462,
            0.0070135,
            0.0051825,
            -0.0011578,
            -0.020134,
            -0.0740949,
            -0.2270813
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          [
            0.0071089,
            0.006764,
            0.0049189,
            -0.0014189,
            -0.0203787,
            -0.0743381,
            -0.2273184
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          [
            0.0068942,
            0.0064996,
            0.0046255,
            -0.001733,
            -0.02066,
            -0.0746299,
            -0.2276022
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          [
            0.0061831,
            0.0056468,
            0.0037688,
            -0.002622,
            -0.021522,
            -0.0754308,
            -0.2284023
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          [
            0.0047277,
            0.0039215,
            0.001601,
            -0.0050426,
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            -0.0776177,
            -0.2305585
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      "related_pin": "CLK",
      "rise_power,power_outputs_1": {
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          0.1,
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        "values": [
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            0.0878781,
            0.2402032
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            0.0051918,
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            0.0152488,
            0.0343488,
            0.0874656,
            0.2393185
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        ]
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    },
    "max_capacitance": 0.259409,
    "max_transition": 9.972293,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "state_function": "(CLK*M0)",
    "timing": {
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          0.1,
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            0.6080059,
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            1.365532,
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            1.0588694,
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            6.3200098,
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        ]
      },
      "cell_rise,del_1_7_7": {
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        "index_2": [
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          [
            4.1534061,
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            5.1018505,
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            11.5229914
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      },
      "fall_transition,del_1_7_7": {
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          1,
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          10
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        "index_2": [
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        "values": [
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            0.0559205,
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            0.1631341,
            0.3667716,
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            0.0555828,
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            0.0556119,
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            0.055888,
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            0.0701339,
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            0.247161,
            0.4189568,
            0.9877331,
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      },
      "related_pin": "CLK",
      "rise_transition,del_1_7_7": {
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        "index_2": [
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        "values": [
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            0.082271,
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            1.3052499,
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            0.0827154,
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            3.5346781,
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          [
            0.0831499,
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            1.3089883,
            3.5397956,
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        ]
      },
      "timing_sense": "positive_unate",
      "timing_type": "combinational"
    }
  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VNB",
    "related_power_pin": "VPWR"
  },
  "pin,SCE": {
    "capacitance": 0.001534,
    "clock": "false",
    "clock_gate_test_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001439,
    "internal_power": {
      "fall_power,power_inputs_1": {
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          0.1,
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          1.0,
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          9.9999999
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        "values": [
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      },
      "rise_power,power_inputs_1": {
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          0.1,
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        ],
        "values": [
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001629,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
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            5.0,
            9.9999999
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          "index_2": [
            0.01,
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            9.9999999
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          "values": [
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              1.4778301,
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              -0.7871764,
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              5.1041321
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              -2.4194599,
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              3.4553691
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
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          "index_2": [
            0.01,
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          "values": [
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              0.3645488,
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              -1.206488,
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              2.8922181
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              -2.3370625,
              -0.0940286,
              1.7158672
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
            5.0,
            9.9999999
          ],
          "values": [
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              -1.468337,
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              -7.3742938
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            [
              0.7948385,
              -2.2300557,
              -5.1001321
            ],
            [
              2.4271221,
              -0.6050964,
              -3.4550313
            ]
          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
            5.0,
            9.9999999
          ],
          "values": [
            [
              -0.197585,
              -2.4882262,
              -4.2944601
            ],
            [
              1.2910543,
              -0.9428242,
              -2.7252542
            ],
            [
              2.4381084,
              0.2298646,
              -1.5415792
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "statetable,CLK GATE SCE,M0": {
    "table": [
      "L L L : - : L",
      "L L H : - : H",
      "L H L : - : H",
      "L H H : - : H",
      "H - - : - : N"
    ]
  }
}