blob: 3e3ed93402fd95ce4a91fb32b8910f6525a45573 [file] [log] [blame]
{
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"cell_leakage_power": 14.61143,
"clock_gating_integrated_cell": "latch_posedge",
"driver_waveform_fall": "ramp",
"driver_waveform_rise": "ramp",
"leakage_power": [
{
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"when": "CLK&!GATE&!GCLK"
},
{
"value": 14.3760559,
"when": "!CLK&GATE&!GCLK"
},
{
"value": 12.633901,
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{
"value": 14.7065728,
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{
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},
{
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}
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"related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
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"physical_connection": "device_layer",
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},
"pg_pin,VPB": {
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},
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"related_pin": "CLK",
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},
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{
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}
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"power_down_function": "(!VPWR + VGND)",
"related_ground_pin": "VGND",
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"state_function": "(CLK*M0)",
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1.4932132
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},
"timing_sense": "positive_unate",
"timing_type": "combinational"
}
},
"pin,M0": {
"direction": "internal",
"internal_node": "M0",
"related_ground_pin": "VNB",
"related_power_pin": "VPWR"
},
"statetable,CLK GATE,M0": {
"table": [
"L L : - : L",
"L H : - : H",
"H - : - : N"
]
}
}