{
  "area": 21.2704,
  "cell_footprint": "sky130_fd_sc_hd__dlclkp",
  "cell_leakage_power": 0.0004730651,
  "clock_gating_integrated_cell": "latch_posedge",
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "leakage_power": [
    {
      "value": 0.0005529,
      "when": "CLK&!GATE&!GCLK"
    },
    {
      "value": 0.0004644,
      "when": "!CLK&GATE&!GCLK"
    },
    {
      "value": 0.000339,
      "when": "CLK&GATE&GCLK"
    },
    {
      "value": 0.0005474,
      "when": "!CLK&!GATE&!GCLK"
    },
    {
      "value": 0.000595,
      "when": "CLK&GATE&!GCLK"
    },
    {
      "value": 0.0003398,
      "when": "CLK&!GATE&GCLK"
    }
  ],
  "pg_pin,VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
    "voltage_name": "VNB"
  },
  "pg_pin,VPB": {
    "pg_type": "pwell",
    "physical_connection": "device_layer",
    "voltage_name": "VPB"
  },
  "pg_pin,VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
  },
  "pin,CLK": {
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    "clock": "true",
    "clock_gate_clock_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.004014,
    "internal_power": {
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          0.1,
          0.316228,
          1.0,
          3.16228,
          9.9999999
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        "values": [
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          0.0105719,
          0.0106003,
          0.0106903,
          0.0109749,
          0.011875
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      },
      "rise_power,power_inputs_1": {
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        "values": [
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          0.0030015
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.004085,
    "timing": {
      "fall_constraint,constraint_3_0_1": {
        "index_1": [
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          9.9999999
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        "values": [
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          8.3333333,
          16.6666666
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      },
      "related_output_pin": "GCLK",
      "related_pin": "CLK",
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10
    }
  },
  "pin,GATE": {
    "capacitance": 0.001427,
    "clock": "false",
    "clock_gate_enable_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001429,
    "internal_power": {
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          0.1,
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          9.9999999
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        "values": [
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      "rise_power,power_inputs_1": {
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        "values": [
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001425,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
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          "index_2": [
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              -1.4866393,
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              3.7198549
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              -3.1079365,
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              2.1901104
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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            0.01,
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          "index_2": [
            0.01,
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          "values": [
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              -1.17536,
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              2.4582581
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            [
              -2.1887471,
              -0.2002298,
              1.3917705
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint,vio_3_3_1": {
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            0.01,
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          ],
          "index_2": [
            0.01,
            5.0,
            9.9999999
          ],
          "values": [
            [
              -0.6059102,
              -3.3250182,
              -5.7391622
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            [
              1.5235983,
              -1.235793,
              -3.6755716
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            [
              3.1375714,
              0.2811341,
              -2.1494892
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
            5.0,
            9.9999999
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          "values": [
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              -0.1444844,
              -2.2080748,
              -3.8000751
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            [
              1.247109,
              -0.7285908,
              -2.2858011
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            [
              2.2678204,
              0.3269105,
              -1.2229756
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin,GCLK": {
    "clock_gate_out_pin": "true",
    "direction": "output",
    "internal_power": {
      "fall_power,power_outputs_1": {
        "index_1": [
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          0.03162278,
          0.1,
          0.3162278,
          1,
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          10
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        "index_2": [
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        "values": [
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            0.0145358,
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            0.0100413,
            -0.0033985,
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          [
            0.0142186,
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            0.0096016,
            -0.0037357,
            -0.0537947,
            -0.2328317,
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          [
            0.0139075,
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            0.0093086,
            -0.0040971,
            -0.0541812,
            -0.2331571,
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          [
            0.0131522,
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            0.0085748,
            -0.0049232,
            -0.0550314,
            -0.2338442,
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            0.008478,
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            -0.2351844,
            -0.8601613
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        ]
      },
      "related_pin": "CLK",
      "rise_power,power_outputs_1": {
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        "values": [
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        ]
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    },
    "max_capacitance": 0.894938,
    "max_transition": 9.962483,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "state_function": "(CLK*M0)",
    "timing": {
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        ]
      },
      "cell_rise,del_1_7_7": {
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        "index_2": [
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        "values": [
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      },
      "fall_transition,del_1_7_7": {
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        "index_2": [
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        "values": [
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        ]
      },
      "related_pin": "CLK",
      "rise_transition,del_1_7_7": {
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          1,
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        "index_2": [
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        "values": [
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          ],
          [
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          [
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          [
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          [
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          [
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        ]
      },
      "timing_sense": "positive_unate",
      "timing_type": "combinational"
    }
  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VNB",
    "related_power_pin": "VPWR"
  },
  "statetable,CLK GATE,M0": {
    "table": [
      "L L : - : L",
      "L H : - : H",
      "H - : - : N"
    ]
  }
}