{
  "area": 21.2704,
  "cell_footprint": "sky130_fd_sc_hd__dlclkp",
  "cell_leakage_power": 0.0003009242,
  "clock_gating_integrated_cell": "latch_posedge",
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "leakage_power": [
    {
      "value": 0.0003446,
      "when": "CLK&!GATE&!GCLK"
    },
    {
      "value": 0.0002884,
      "when": "!CLK&GATE&!GCLK"
    },
    {
      "value": 0.0002251,
      "when": "CLK&GATE&GCLK"
    },
    {
      "value": 0.0003397,
      "when": "!CLK&!GATE&!GCLK"
    },
    {
      "value": 0.000382,
      "when": "CLK&GATE&!GCLK"
    },
    {
      "value": 0.0002258,
      "when": "CLK&!GATE&GCLK"
    }
  ],
  "pg_pin,VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
    "voltage_name": "VNB"
  },
  "pg_pin,VPB": {
    "pg_type": "pwell",
    "physical_connection": "device_layer",
    "voltage_name": "VPB"
  },
  "pg_pin,VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
  },
  "pin,CLK": {
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    "clock_gate_clock_pin": "true",
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    "fall_capacitance": 0.003762,
    "internal_power": {
      "fall_power,power_inputs_1": {
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          0.1,
          0.316228,
          1.0,
          3.16228,
          9.9999999
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        "values": [
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          0.0083022,
          0.0084931,
          0.0090968,
          0.0110058
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      },
      "rise_power,power_inputs_1": {
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          9.9999999
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        "values": [
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.003981,
    "timing": {
      "fall_constraint,constraint_3_0_1": {
        "index_1": [
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          9.9999999
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        "values": [
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      },
      "related_output_pin": "GCLK",
      "related_pin": "CLK",
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10
    }
  },
  "pin,GATE": {
    "capacitance": 0.00138,
    "clock": "false",
    "clock_gate_enable_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001358,
    "internal_power": {
      "fall_power,power_inputs_1": {
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          9.9999999
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        "values": [
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      },
      "rise_power,power_inputs_1": {
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        "values": [
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          0.0045888,
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001401,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
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          "index_2": [
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              -1.5250915,
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              4.0201476
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              -3.4155538,
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              2.2853253
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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          "index_2": [
            0.01,
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          "values": [
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              4.6280498
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              -1.310858,
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              2.725592
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            [
              -2.4798847,
              -0.3009378,
              1.4961406
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint,vio_3_3_1": {
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            0.01,
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          "index_2": [
            0.01,
            5.0,
            9.9999999
          ],
          "values": [
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              -0.767043,
              -3.6308043,
              -6.2665057
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            [
              1.5840231,
              -1.3273457,
              -3.9685403
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            [
              3.4488506,
              0.4056458,
              -2.2355488
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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            0.01,
            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
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            9.9999999
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          "values": [
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              -0.1682881,
              -2.4241393,
              -4.2175558
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            [
              1.3899313,
              -0.7816914,
              -2.5348245
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            [
              2.5681133,
              0.4386048,
              -1.3126972
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin,GCLK": {
    "clock_gate_out_pin": "true",
    "direction": "output",
    "internal_power": {
      "fall_power,power_outputs_1": {
        "index_1": [
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          0.1,
          0.3162278,
          1,
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        "index_2": [
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        "values": [
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            0.0016771,
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            0.016018,
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            0.012275,
            0.0015533,
            -0.0368795,
            -0.1670106,
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          [
            0.0155944,
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            0.0118276,
            0.0011531,
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            -0.1674596,
            -0.629406
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            0.0149388,
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            0.0110792,
            0.0003374,
            -0.037216,
            -0.1683535,
            -0.6301914
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          [
            0.0205196,
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            0.0165225,
            0.0057158,
            -0.03382,
            -0.1705108,
            -0.6322559
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      "related_pin": "CLK",
      "rise_power,power_outputs_1": {
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          1,
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        ]
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    },
    "max_capacitance": 0.721751,
    "max_transition": 9.95031,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "state_function": "(CLK*M0)",
    "timing": {
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        ]
      },
      "cell_rise,del_1_7_7": {
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        "index_2": [
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        "values": [
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      "fall_transition,del_1_7_7": {
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        "index_2": [
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        "values": [
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      },
      "related_pin": "CLK",
      "rise_transition,del_1_7_7": {
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          1,
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        "index_2": [
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        "values": [
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          [
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          [
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          [
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          [
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        ]
      },
      "timing_sense": "positive_unate",
      "timing_type": "combinational"
    }
  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VNB",
    "related_power_pin": "VPWR"
  },
  "statetable,CLK GATE,M0": {
    "table": [
      "L L : - : L",
      "L H : - : H",
      "H - : - : N"
    ]
  }
}