{
  "area": 18.768,
  "cell_footprint": "sky130_fd_sc_hd__dlclkp",
  "cell_leakage_power": 0.0002549113,
  "clock_gating_integrated_cell": "latch_posedge",
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "leakage_power": [
    {
      "value": 0.0002887,
      "when": "CLK&!GATE&!GCLK"
    },
    {
      "value": 0.0002204,
      "when": "!CLK&GATE&!GCLK"
    },
    {
      "value": 0.0002265,
      "when": "CLK&GATE&GCLK"
    },
    {
      "value": 0.0002489,
      "when": "!CLK&!GATE&!GCLK"
    },
    {
      "value": 0.0003178,
      "when": "CLK&GATE&!GCLK"
    },
    {
      "value": 0.0002271,
      "when": "CLK&!GATE&GCLK"
    }
  ],
  "pg_pin,VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
    "voltage_name": "VNB"
  },
  "pg_pin,VPB": {
    "pg_type": "pwell",
    "physical_connection": "device_layer",
    "voltage_name": "VPB"
  },
  "pg_pin,VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
  },
  "pin,CLK": {
    "capacitance": 0.003261,
    "clock": "true",
    "clock_gate_clock_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.003171,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
          0.01,
          0.0316228,
          0.1,
          0.316228,
          1.0,
          3.16228,
          9.9999999
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        "values": [
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          0.0078857,
          0.0079396,
          0.00811,
          0.0086489,
          0.0103529
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      },
      "rise_power,power_inputs_1": {
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          0.01,
          0.0316228,
          0.1,
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          9.9999999
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        "values": [
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          0.0029955,
          0.002936
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.00335,
    "timing": {
      "fall_constraint,constraint_3_0_1": {
        "index_1": [
          0.01,
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          9.9999999
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        "values": [
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          8.3333333,
          16.6666666
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      },
      "related_output_pin": "GCLK",
      "related_pin": "CLK",
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10
    }
  },
  "pin,GATE": {
    "capacitance": 0.001524,
    "clock": "false",
    "clock_gate_enable_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001586,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
          0.01,
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          0.1,
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          1.0,
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          9.9999999
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        "values": [
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          0.0051469,
          0.0110037
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      },
      "rise_power,power_inputs_1": {
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          0.01,
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          9.9999999
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        "values": [
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          0.004275,
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          0.0049735,
          0.0066518
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      }
    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001462,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
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            0.01,
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          "index_2": [
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          "values": [
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              0.8809062,
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              6.3840313
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              -1.4097351,
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              4.0952209
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            [
              -3.324001,
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              2.3915264
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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            0.01,
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            9.9999999
          ],
          "index_2": [
            0.01,
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            9.9999999
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          "values": [
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              0.4084941,
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              4.6701641
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              -1.2907165,
              0.9907695,
              2.8464418
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            [
              -2.4396016,
              -0.2130472,
              1.6316386
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
            5.0,
            9.9999999
          ],
          "values": [
            [
              -0.8384541,
              -3.7022156,
              -6.339748
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            [
              1.446694,
              -1.4170674,
              -4.0472756
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            [
              3.3664532,
              0.2664857,
              -2.3673847
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
            5.0,
            9.9999999
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          "values": [
            [
              -0.1829365,
              -2.5028748,
              -4.3567156
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            [
              1.3514792,
              -0.8842305,
              -2.6959574
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            [
              2.5058573,
              0.3177552,
              -1.4921406
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin,GCLK": {
    "clock_gate_out_pin": "true",
    "direction": "output",
    "internal_power": {
      "fall_power,power_outputs_1": {
        "index_1": [
          0.01,
          0.03162278,
          0.1,
          0.3162278,
          1,
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          10
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        "index_2": [
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          0.00478947,
          0.01482334,
          0.04587805,
          0.1419919,
          0.4394631
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        "values": [
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            0.0074378,
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          [
            0.0083679,
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            0.0053169,
            -0.0028483,
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            -0.1101993,
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          [
            0.0096588,
            0.0089671,
            0.0066208,
            -0.001539,
            -0.028366,
            -0.1088936,
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          [
            0.0094399,
            0.0087362,
            0.0063507,
            -0.0017692,
            -0.0285847,
            -0.1091181,
            -0.3801
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          [
            0.0092277,
            0.0085313,
            0.0061262,
            -0.0020156,
            -0.0288025,
            -0.1093507,
            -0.3803307
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          [
            0.008684,
            0.0079608,
            0.0054838,
            -0.0026396,
            -0.0292187,
            -0.1101065,
            -0.3810723
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          [
            0.0146817,
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            0.0108985,
            0.0018342,
            -0.0249432,
            -0.1119401,
            -0.3828515
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        ]
      },
      "related_pin": "CLK",
      "rise_power,power_outputs_1": {
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          0.1,
          0.3162278,
          1,
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        "index_2": [
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        "values": [
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            0.4062751
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        ]
      }
    },
    "max_capacitance": 0.439463,
    "max_transition": 9.963983,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "state_function": "(CLK*M0)",
    "timing": {
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        "index_2": [
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        "values": [
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            7.3729103,
            7.7523605,
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        ]
      },
      "cell_rise,del_1_7_7": {
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          10
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        "index_2": [
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        "values": [
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            11.875553
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        ]
      },
      "fall_transition,del_1_7_7": {
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          1,
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        "index_2": [
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        "values": [
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            0.2089274,
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            0.7485542,
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        ]
      },
      "related_pin": "CLK",
      "rise_transition,del_1_7_7": {
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          1,
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        "index_2": [
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        "values": [
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          ],
          [
            0.0825673,
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          [
            0.0826807,
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          [
            0.0839395,
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          ],
          [
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          ],
          [
            0.1509069,
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            0.2341578,
            0.4358912,
            1.1212052,
            3.2493368,
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        ]
      },
      "timing_sense": "positive_unate",
      "timing_type": "combinational"
    }
  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VNB",
    "related_power_pin": "VPWR"
  },
  "statetable,CLK GATE,M0": {
    "table": [
      "L L : - : L",
      "L H : - : H",
      "H - : - : N"
    ]
  }
}