{
  "area": 18.768,
  "cell_footprint": "sky130_fd_sc_hd__dlclkp",
  "cell_leakage_power": 9.287907,
  "clock_gating_integrated_cell": "latch_posedge",
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "leakage_power": [
    {
      "value": 9.7509707,
      "when": "CLK&!GATE&!GCLK"
    },
    {
      "value": 9.2098036,
      "when": "!CLK&GATE&!GCLK"
    },
    {
      "value": 8.1625471,
      "when": "CLK&GATE&GCLK"
    },
    {
      "value": 9.2390327,
      "when": "!CLK&!GATE&!GCLK"
    },
    {
      "value": 10.1614406,
      "when": "CLK&GATE&!GCLK"
    },
    {
      "value": 9.2036503,
      "when": "CLK&!GATE&GCLK"
    }
  ],
  "pg_pin,VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
    "voltage_name": "VNB"
  },
  "pg_pin,VPB": {
    "pg_type": "pwell",
    "physical_connection": "device_layer",
    "voltage_name": "VPB"
  },
  "pg_pin,VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
  },
  "pin,CLK": {
    "capacitance": 0.003721,
    "clock": "true",
    "clock_gate_clock_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.00359,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
          0.01,
          0.0316228,
          0.1,
          0.316228,
          1.0,
          3.16228,
          9.9999999
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        "values": [
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          0.011451,
          0.0113781,
          0.0113216,
          0.0113168,
          0.0114757
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      },
      "rise_power,power_inputs_1": {
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          0.0316228,
          0.1,
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          1.0,
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          9.9999999
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        "values": [
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          0.002979
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      }
    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.003853,
    "timing": {
      "fall_constraint,constraint_3_0_1": {
        "index_1": [
          0.01,
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          9.9999999
        ],
        "values": [
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          8.3333333,
          16.6666666
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      },
      "related_output_pin": "GCLK",
      "related_pin": "CLK",
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10
    }
  },
  "pin,GATE": {
    "capacitance": 0.001677,
    "clock": "false",
    "clock_gate_enable_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001737,
    "internal_power": {
      "fall_power,power_inputs_1": {
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          0.01,
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          0.1,
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          1.0,
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          9.9999999
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        "values": [
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      },
      "rise_power,power_inputs_1": {
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          0.01,
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          0.1,
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          1.0,
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          9.9999999
        ],
        "values": [
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          0.0058966,
          0.0059292,
          0.0061996,
          0.0072226
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      }
    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001616,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
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          "index_2": [
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          "values": [
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              0.4414531,
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              2.9324932
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              -1.0307067,
              0.4780742,
              1.4401917
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              -1.8353535,
              -0.3467142,
              0.5934307
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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            0.01,
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          ],
          "index_2": [
            0.01,
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            9.9999999
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          "values": [
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              0.3389141,
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              3.0716534
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              -0.6095641,
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              1.9290834
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            [
              -1.0498311,
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              1.4393779
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
            5.0,
            9.9999999
          ],
          "values": [
            [
              -0.3953389,
              -1.8858092,
              -2.8021505
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            [
              1.0475241,
              -0.4521016,
              -1.4014017
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            [
              1.8503398,
              0.3617005,
              -0.567458
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
            5.0,
            9.9999999
          ],
          "values": [
            [
              -0.1737813,
              -1.777777,
              -2.787502
            ],
            [
              0.67582,
              -0.7963398,
              -1.7584573
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            [
              1.1435527,
              -0.3011413,
              -1.239455
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin,GCLK": {
    "clock_gate_out_pin": "true",
    "direction": "output",
    "internal_power": {
      "fall_power,power_outputs_1": {
        "index_1": [
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          0.03162278,
          0.1,
          0.3162278,
          1,
          3.162278,
          10
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        "index_2": [
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          0.006135637,
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          0.07529207,
          0.263751,
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        "values": [
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            0.0068543,
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            -0.0115504,
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            -0.2485679,
            -0.8955297
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          [
            0.0071685,
            0.0061494,
            0.0024969,
            -0.0117915,
            -0.0642078,
            -0.2488679,
            -0.8958616
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          [
            0.0069824,
            0.0059644,
            0.0022984,
            -0.0120093,
            -0.0643864,
            -0.2490212,
            -0.896032
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          [
            0.0068091,
            0.0057552,
            0.0020312,
            -0.0123262,
            -0.064625,
            -0.2491839,
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          [
            0.0071765,
            0.0060106,
            0.0018477,
            -0.0129911,
            -0.0649604,
            -0.2493639,
            -0.8962474
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          [
            0.0074586,
            0.0062094,
            0.0019643,
            -0.0129015,
            -0.0653074,
            -0.2495434,
            -0.896189
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        ]
      },
      "related_pin": "CLK",
      "rise_power,power_outputs_1": {
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          0.1,
          0.3162278,
          1,
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        "index_2": [
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        "values": [
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        ]
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    },
    "max_capacitance": 0.92393,
    "max_transition": 9.998738,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "state_function": "(CLK*M0)",
    "timing": {
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        "index_2": [
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        "values": [
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            4.0601233,
            4.3779331,
            5.153745,
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        ]
      },
      "cell_rise,del_1_7_7": {
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        "index_2": [
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        "values": [
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        ]
      },
      "fall_transition,del_1_7_7": {
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        "index_2": [
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        "values": [
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        ]
      },
      "related_pin": "CLK",
      "rise_transition,del_1_7_7": {
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          1,
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          10
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        "index_2": [
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        "values": [
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          [
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          ],
          [
            0.0627501,
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          [
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          [
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          [
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        ]
      },
      "timing_sense": "positive_unate",
      "timing_type": "combinational"
    }
  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VNB",
    "related_power_pin": "VPWR"
  },
  "statetable,CLK GATE,M0": {
    "table": [
      "L L : - : L",
      "L H : - : H",
      "H - : - : N"
    ]
  }
}