{
  "area": 22.5216,
  "cell_footprint": "sky130_fd_sc_hd__sdlclkp",
  "cell_leakage_power": 11.00244,
  "clock_gating_integrated_cell": "latch_posedge_precontrol",
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "leakage_power": [
    {
      "value": 11.9615073,
      "when": "CLK&!GATE&!GCLK&!SCE"
    },
    {
      "value": 9.1358086,
      "when": "!CLK&GATE&!GCLK&!SCE"
    },
    {
      "value": 9.1938031,
      "when": "!CLK&!GATE&!GCLK&SCE"
    },
    {
      "value": 10.5098721,
      "when": "CLK&!GATE&GCLK&SCE"
    },
    {
      "value": 7.9656184,
      "when": "!CLK&GATE&!GCLK&SCE"
    },
    {
      "value": 11.1557226,
      "when": "!CLK&!GATE&!GCLK&!SCE"
    },
    {
      "value": 10.451882,
      "when": "CLK&GATE&GCLK&!SCE"
    },
    {
      "value": 9.2817096,
      "when": "CLK&GATE&GCLK&SCE"
    },
    {
      "value": 13.9559324,
      "when": "CLK&GATE&!GCLK&!SCE"
    },
    {
      "value": 14.0139154,
      "when": "CLK&!GATE&!GCLK&SCE"
    },
    {
      "value": 12.7858195,
      "when": "CLK&GATE&!GCLK&SCE"
    },
    {
      "value": 11.6176873,
      "when": "CLK&!GATE&GCLK&!SCE"
    }
  ],
  "pg_pin,VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
    "voltage_name": "VNB"
  },
  "pg_pin,VPB": {
    "pg_type": "pwell",
    "physical_connection": "device_layer",
    "voltage_name": "VPB"
  },
  "pg_pin,VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
  },
  "pin,CLK": {
    "capacitance": 0.004023,
    "clock": "true",
    "clock_gate_clock_pin": "true",
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    "fall_capacitance": 0.003941,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
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          0.0316228,
          0.1,
          0.316228,
          1.0,
          3.16228,
          9.9999999
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        "values": [
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          0.011344,
          0.0112557,
          0.0111899,
          0.0111952,
          0.0114254
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      },
      "rise_power,power_inputs_1": {
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          9.9999999
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        "values": [
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          0.0042629,
          0.0041764,
          0.0040701,
          0.0039007
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.004106,
    "timing": {
      "fall_constraint,constraint_3_0_1": {
        "index_1": [
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        "values": [
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          16.6666666
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      "related_output_pin": "GCLK",
      "related_pin": "CLK",
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10
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  },
  "pin,GATE": {
    "capacitance": 0.001787,
    "clock": "false",
    "clock_gate_enable_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.00166,
    "internal_power": {
      "fall_power,power_inputs_1": {
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          0.1,
          0.316228,
          1.0,
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          9.9999999
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        "values": [
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      },
      "rise_power,power_inputs_1": {
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        "values": [
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          0.0071288,
          0.0074079,
          0.008494
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001915,
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      {
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          "index_2": [
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          "values": [
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              3.932249
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            [
              -0.7505554,
              1.1573956,
              2.4637512
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              -1.5442158,
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              1.6151592
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        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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          "index_2": [
            0.01,
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            9.9999999
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          "values": [
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              0.3663799,
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              2.9123515
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            [
              -0.6187194,
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              1.8027406
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            [
              -1.0644795,
              0.4388083,
              1.3459941
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
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      {
        "fall_constraint,vio_3_3_1": {
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          "index_2": [
            0.01,
            5.0,
            9.9999999
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          "values": [
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              -0.5894307,
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              -3.7469745
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              0.7692038,
              -1.1277607,
              -2.4249613
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              1.5592021,
              -0.2993102,
              -1.5891865
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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            0.01,
            5.0,
            9.9999999
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          "index_2": [
            0.01,
            5.0,
            9.9999999
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          "values": [
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              -0.1591328,
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              -2.5274922
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            [
              0.7380759,
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              -1.5753519
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            [
              1.2497539,
              -0.1986022,
              -1.0490254
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
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    ]
  },
  "pin,GCLK": {
    "clock_gate_out_pin": "true",
    "direction": "output",
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            0.0088866,
            -0.0102754,
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            0.0145051,
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            0.0087116,
            -0.0104395,
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            0.014443,
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            0.0086641,
            -0.0105544,
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            -0.4001403,
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            0.0140394,
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            0.0081722,
            -0.0111677,
            -0.0905028,
            -0.4004365,
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          [
            0.0152008,
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            0.0086502,
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            -0.0910405,
            -0.4007444,
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            0.0155712,
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      "related_pin": "CLK",
      "rise_power,power_outputs_1": {
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    },
    "max_capacitance": 1.649485,
    "max_transition": 10.010279,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "state_function": "(CLK*M0)",
    "timing": {
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      },
      "cell_rise,del_1_7_7": {
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      "fall_transition,del_1_7_7": {
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          10
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        "index_2": [
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        "values": [
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            0.0570674,
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      "related_pin": "CLK",
      "rise_transition,del_1_7_7": {
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        ]
      },
      "timing_sense": "positive_unate",
      "timing_type": "combinational"
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  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VNB",
    "related_power_pin": "VPWR"
  },
  "pin,SCE": {
    "capacitance": 0.00171,
    "clock": "false",
    "clock_gate_test_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001627,
    "internal_power": {
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        "values": [
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      "rise_power,power_inputs_1": {
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        "values": [
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001792,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
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            9.9999999
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          "index_2": [
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          "values": [
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              2.2312073
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        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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          "index_2": [
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          "values": [
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              -0.5528014,
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              -0.982082,
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint,vio_3_3_1": {
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            0.01,
            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
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            9.9999999
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          "values": [
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              -0.6132344,
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              -3.5437275
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            [
              0.7655417,
              -1.0105732,
              -2.1997415
            ],
            [
              1.5738505,
              -0.1821227,
              -1.3639668
            ]
          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
            5.0,
            9.9999999
          ],
          "values": [
            [
              -0.1829365,
              -1.810736,
              -2.8131368
            ],
            [
              0.6703268,
              -0.8878926,
              -1.8664896
            ],
            [
              1.1582011,
              -0.3817077,
              -1.3529805
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "statetable,CLK GATE SCE,M0": {
    "table": [
      "L L L : - : L",
      "L L H : - : H",
      "L H L : - : H",
      "L H H : - : H",
      "H - - : - : N"
    ]
  }
}