{
  "area": 20.0192,
  "cell_footprint": "sky130_fd_sc_hd__sdlclkp",
  "cell_leakage_power": 0.0003109589,
  "clock_gating_integrated_cell": "latch_posedge_precontrol",
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "leakage_power": [
    {
      "value": 0.0003652,
      "when": "CLK&!GATE&!GCLK&!SCE"
    },
    {
      "value": 0.0002757,
      "when": "!CLK&GATE&!GCLK&!SCE"
    },
    {
      "value": 0.0002244,
      "when": "!CLK&!GATE&!GCLK&SCE"
    },
    {
      "value": 0.0002331,
      "when": "CLK&!GATE&GCLK&SCE"
    },
    {
      "value": 0.0002756,
      "when": "!CLK&GATE&!GCLK&SCE"
    },
    {
      "value": 0.0003067,
      "when": "!CLK&!GATE&!GCLK&!SCE"
    },
    {
      "value": 0.0002845,
      "when": "CLK&GATE&GCLK&!SCE"
    },
    {
      "value": 0.0002843,
      "when": "CLK&GATE&GCLK&SCE"
    },
    {
      "value": 0.0003962,
      "when": "CLK&GATE&!GCLK&!SCE"
    },
    {
      "value": 0.0003448,
      "when": "CLK&!GATE&!GCLK&SCE"
    },
    {
      "value": 0.000396,
      "when": "CLK&GATE&!GCLK&SCE"
    },
    {
      "value": 0.000345,
      "when": "CLK&!GATE&GCLK&!SCE"
    }
  ],
  "pg_pin,VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
    "voltage_name": "VNB"
  },
  "pg_pin,VPB": {
    "pg_type": "pwell",
    "physical_connection": "device_layer",
    "voltage_name": "VPB"
  },
  "pg_pin,VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
  },
  "pin,CLK": {
    "capacitance": 0.002831,
    "clock": "true",
    "clock_gate_clock_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.002728,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
          0.01,
          0.0316228,
          0.1,
          0.316228,
          1.0,
          3.16228,
          9.9999999
        ],
        "values": [
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          0.008339,
          0.0068106,
          0.0068756,
          0.0070813,
          0.0077319,
          0.0097893
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      },
      "rise_power,power_inputs_1": {
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          0.01,
          0.0316228,
          0.1,
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          1.0,
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          9.9999999
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        "values": [
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          0.003833,
          0.0038476,
          0.003894,
          0.0040405,
          0.0045038
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      }
    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.002935,
    "timing": {
      "fall_constraint,constraint_3_0_1": {
        "index_1": [
          0.01,
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          9.9999999
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        "values": [
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          8.3333333,
          16.6666666
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      },
      "related_output_pin": "GCLK",
      "related_pin": "CLK",
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10
    }
  },
  "pin,GATE": {
    "capacitance": 0.001598,
    "clock": "false",
    "clock_gate_enable_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001425,
    "internal_power": {
      "fall_power,power_inputs_1": {
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          0.01,
          0.0316228,
          0.1,
          0.316228,
          1.0,
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          9.9999999
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        "values": [
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          0.0028281,
          0.0030435,
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      },
      "rise_power,power_inputs_1": {
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          9.9999999
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        "values": [
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          0.0052263,
          0.005404,
          0.005966,
          0.0077429
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.00177,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
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            9.9999999
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          "index_2": [
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          "values": [
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              1.4302227,
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              7.49365
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            [
              -0.8219665,
              2.2413798,
              5.2085023
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              -2.4615742,
              0.6090964,
              3.5377666
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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            0.01,
            5.0,
            9.9999999
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          "index_2": [
            0.01,
            5.0,
            9.9999999
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          "values": [
            [
              0.4066631,
              2.6753318,
              4.4705793
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            [
              -1.2833922,
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              2.6798157
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            [
              -2.4505879,
              -0.2716409,
              1.475999
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
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          "index_2": [
            0.01,
            5.0,
            9.9999999
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          "values": [
            [
              -1.3914326,
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              -7.4530295
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            [
              0.8570944,
              -2.208083,
              -5.160557
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            [
              2.4893779,
              -0.5812926,
              -3.5044698
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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            0.01,
            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
            5.0,
            9.9999999
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          "values": [
            [
              -0.1756123,
              -2.382025,
              -4.0912129
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            [
              1.3606344,
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              -2.5146829
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            [
              2.5406475,
              0.3964906,
              -1.3126972
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin,GCLK": {
    "clock_gate_out_pin": "true",
    "direction": "output",
    "internal_power": {
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          0.1,
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          1,
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          10
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          0.004873894,
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          0.1483321,
          0.4631142
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            -0.1253255,
            -0.4121567
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            0.0085356,
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            0.0052004,
            -0.003579,
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            -0.124453,
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            0.009915,
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            0.0066358,
            -0.0021854,
            -0.031257,
            -0.1230552,
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          [
            0.0096611,
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            0.0063484,
            -0.0024521,
            -0.0314973,
            -0.1232932,
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          [
            0.0093084,
            0.0086144,
            0.0060454,
            -0.0027731,
            -0.0318044,
            -0.1235617,
            -0.4103562
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          [
            0.0085029,
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            0.0051179,
            -0.0037475,
            -0.0327464,
            -0.1244315,
            -0.4112219
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            0.0070339,
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            -0.4134129
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      "related_pin": "CLK",
      "rise_power,power_outputs_1": {
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            0.1413419,
            0.4252515
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        ]
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    },
    "max_capacitance": 0.463114,
    "max_transition": 10.01717,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "state_function": "(CLK*M0)",
    "timing": {
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            1.033104,
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            1.2184739,
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        ]
      },
      "cell_rise,del_1_7_7": {
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            11.8717089
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      },
      "fall_transition,del_1_7_7": {
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        "index_2": [
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        "values": [
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      "related_pin": "CLK",
      "rise_transition,del_1_7_7": {
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            1.0973602,
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            10.0171702
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        ]
      },
      "timing_sense": "positive_unate",
      "timing_type": "combinational"
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  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VNB",
    "related_power_pin": "VPWR"
  },
  "pin,SCE": {
    "capacitance": 0.001532,
    "clock": "false",
    "clock_gate_test_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001438,
    "internal_power": {
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          0.1,
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        "values": [
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      "rise_power,power_inputs_1": {
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        "values": [
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    },
    "max_transition": 10.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001627,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
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            0.01,
            5.0,
            9.9999999
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          "index_2": [
            0.01,
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          "values": [
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              1.4558574,
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              5.0675111
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              -2.4634052,
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              3.4059307
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        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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          "index_2": [
            0.01,
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          "values": [
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              -1.2083191,
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              -2.3425557,
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              1.708543
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
            5.0,
            9.9999999
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          "values": [
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              -1.4134052,
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              -7.3211932
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            [
              0.8516012,
              -2.1696309,
              -5.0305522
            ],
            [
              2.4893779,
              -0.5355163,
              -3.3708027
            ]
          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            5.0,
            9.9999999
          ],
          "index_2": [
            0.01,
            5.0,
            9.9999999
          ],
          "values": [
            [
              -0.1957539,
              -2.4900572,
              -4.2944601
            ],
            [
              1.2910543,
              -0.9446553,
              -2.7307474
            ],
            [
              2.4381084,
              0.2280335,
              -1.5452412
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "statetable,CLK GATE SCE,M0": {
    "table": [
      "L L L : - : L",
      "L L H : - : H",
      "L H L : - : H",
      "L H H : - : H",
      "H - - : - : N"
    ]
  }
}