{
  "area": 23.7728,
  "cell_footprint": "sky130_fd_sc_hd__dfxbp",
  "cell_leakage_power": 0.006359155,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "ff,IQ,IQ_N": {
    "clocked_on": "CLK",
    "next_state": "D"
  },
  "leakage_power": [
    {
      "value": 0.0066049,
      "when": "CLK&D&!Q&Q_N"
    },
    {
      "value": 0.0064786,
      "when": "!CLK&!D&!Q&Q_N"
    },
    {
      "value": 0.0062334,
      "when": "CLK&!D&Q&!Q_N"
    },
    {
      "value": 0.0061117,
      "when": "!CLK&D&Q&!Q_N"
    },
    {
      "value": 0.0066115,
      "when": "!CLK&D&!Q&Q_N"
    },
    {
      "value": 0.0065562,
      "when": "CLK&!D&!Q&Q_N"
    },
    {
      "value": 0.006065,
      "when": "CLK&D&Q&!Q_N"
    },
    {
      "value": 0.006212,
      "when": "!CLK&!D&Q&!Q_N"
    }
  ],
  "pg_pin,VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
    "voltage_name": "VNB"
  },
  "pg_pin,VPB": {
    "pg_type": "pwell",
    "physical_connection": "device_layer",
    "voltage_name": "VPB"
  },
  "pg_pin,VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
  },
  "pin,CLK": {
    "capacitance": 0.001613,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.001522,
    "internal_power": {
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          0.0230506,
          0.0531329,
          0.122474,
          0.282311,
          0.650743,
          1.5
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        "values": [
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          0.0212831,
          0.0210793,
          0.021053,
          0.0209922,
          0.0208522,
          0.0205294
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      "rise_power,power_inputs_1": {
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          0.0230506,
          0.0531329,
          0.122474,
          0.282311,
          0.650743,
          1.5
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        "values": [
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          0.017032,
          0.0169352,
          0.0168716,
          0.0167249,
          0.0163868,
          0.0156076
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      }
    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001704,
    "timing": {
      "fall_constraint,constraint_3_0_1": {
        "index_1": [
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          1.5
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        "values": [
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          0.8333333,
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      },
      "related_output_pin": "Q",
      "related_pin": "CLK",
      "rise_constraint,constraint_3_0_1": {
        "index_1": [
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          0.5,
          1.5
        ],
        "values": [
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          0.8333333,
          2.5
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      },
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10
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  },
  "pin,D": {
    "capacitance": 0.001537,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.001513,
    "internal_power": {
      "fall_power,power_inputs_1": {
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          0.0531329,
          0.122474,
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          0.650743,
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        "values": [
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          0.0049746,
          0.0049704,
          0.0049606,
          0.0049379,
          0.0048858
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      "rise_power,power_inputs_1": {
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          -0.0006599,
          -0.0009346
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    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.00156,
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      {
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            0.5,
            1.5
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          "index_2": [
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            1.5
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              0.2168438,
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              0.9978822
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              0.0148255,
              0.2827617,
              0.7885397
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              -0.2236185,
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              0.5378887
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        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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          "index_2": [
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            1.5
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          "values": [
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              0.0972148,
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              -0.0437682,
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              0.3625143
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            [
              -0.1918802,
              -0.0191589,
              0.2021953
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
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      {
        "fall_constraint,vio_3_3_1": {
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          "index_2": [
            0.01,
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            1.5
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              -0.0663594,
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              -0.7814798
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              -0.6209655
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              0.3106263,
              0.0439108,
              -0.421584
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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            0.01,
            0.5,
            1.5
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          "index_2": [
            0.01,
            0.5,
            1.5
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          "values": [
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              -0.0443867,
              -0.2207702,
              -0.4335794
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            [
              0.0819479,
              -0.088332,
              -0.2986999
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            [
              0.2239564,
              0.0573385,
              -0.1493672
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
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    "direction": "output",
    "function": "IQ",
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          0.05313293,
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          0.6507428,
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          0.102549
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            -0.0046746,
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            0.0158533,
            0.0148507,
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            -0.0046386,
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            0.0158402,
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            -0.0046255,
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            0.0145835,
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            -0.0137611,
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            -0.0044301,
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            0.0143568,
            -0.0137988,
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            -0.0040626,
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      "related_pin": "CLK",
      "rise_power,power_outputs_1": {
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        ]
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    },
    "max_capacitance": 0.102549,
    "max_transition": 1.508545,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "timing": {
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      "cell_rise,del_1_7_7": {
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      "fall_transition,del_1_7_7": {
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      "related_pin": "CLK",
      "rise_transition,del_1_7_7": {
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      },
      "timing_sense": "non_unate",
      "timing_type": "rising_edge"
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  },
  "pin,Q_N": {
    "direction": "output",
    "function": "IQ_N",
    "internal_power": {
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      "related_pin": "CLK",
      "rise_power,power_outputs_1": {
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