{
  "area": 23.7728,
  "cell_footprint": "sky130_fd_sc_hd__dfxbp",
  "cell_leakage_power": 0.002876572,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "ff,IQ,IQ_N": {
    "clocked_on": "CLK",
    "next_state": "D"
  },
  "leakage_power": [
    {
      "value": 0.0029837,
      "when": "CLK&D&!Q&Q_N"
    },
    {
      "value": 0.0028833,
      "when": "!CLK&!D&!Q&Q_N"
    },
    {
      "value": 0.0028652,
      "when": "CLK&!D&Q&!Q_N"
    },
    {
      "value": 0.0027675,
      "when": "!CLK&D&Q&!Q_N"
    },
    {
      "value": 0.0029888,
      "when": "!CLK&D&!Q&Q_N"
    },
    {
      "value": 0.0029454,
      "when": "CLK&!D&!Q&Q_N"
    },
    {
      "value": 0.0027303,
      "when": "CLK&D&Q&!Q_N"
    },
    {
      "value": 0.0028484,
      "when": "!CLK&!D&Q&!Q_N"
    }
  ],
  "pg_pin,VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
    "voltage_name": "VNB"
  },
  "pg_pin,VPB": {
    "pg_type": "pwell",
    "physical_connection": "device_layer",
    "voltage_name": "VPB"
  },
  "pg_pin,VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
  },
  "pin,CLK": {
    "capacitance": 0.001739,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.001657,
    "internal_power": {
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        "index_1": [
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          0.0230506,
          0.0531329,
          0.122474,
          0.282311,
          0.650743,
          1.5
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        "values": [
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          0.0187332,
          0.0185106,
          0.0185398,
          0.018607,
          0.018762,
          0.0191192
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      "rise_power,power_inputs_1": {
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          0.0230506,
          0.0531329,
          0.122474,
          0.282311,
          0.650743,
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        "values": [
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          0.0146612,
          0.0145157,
          0.0144997,
          0.0144626,
          0.0143772,
          0.0141803
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      }
    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001822,
    "timing": {
      "fall_constraint,constraint_3_0_1": {
        "index_1": [
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          1.5
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        "values": [
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          0.8333333,
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      },
      "related_output_pin": "Q",
      "related_pin": "CLK",
      "rise_constraint,constraint_3_0_1": {
        "index_1": [
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          0.5,
          1.5
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        "values": [
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          0.8333333,
          2.5
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      },
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10
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  },
  "pin,D": {
    "capacitance": 0.001686,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.001688,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
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          0.0531329,
          0.122474,
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          0.650743,
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        "values": [
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          0.0043127,
          0.0043388,
          0.0043992,
          0.0045383,
          0.004859
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      "rise_power,power_inputs_1": {
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        "values": [
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          -0.0003875,
          -0.0001675
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    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001683,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
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            1.5
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          "index_2": [
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          "values": [
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              0.0984355,
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              -0.0010436,
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              0.5370749
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              0.4695293
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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          "index_2": [
            0.01,
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            1.5
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          "values": [
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              0.0435039,
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              0.2117493
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              -0.0144714,
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              0.1256979
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              -0.0209818,
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              0.1118633
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
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      {
        "fall_constraint,vio_3_3_1": {
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          "index_2": [
            0.01,
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            1.5
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          "values": [
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              -0.0382832,
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              -0.5153665
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              0.0550924,
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              -0.4451842
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              0.1079896,
              -0.1013529,
              -0.3959492
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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            0.01,
            0.5,
            1.5
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          "index_2": [
            0.01,
            0.5,
            1.5
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          "values": [
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              -0.0199727,
              -0.1084655,
              -0.1369486
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            [
              0.0331198,
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              -0.0850768
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            [
              0.0347474,
              -0.0476419,
              -0.0858906
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
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    ]
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    "direction": "output",
    "function": "IQ",
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          0.05313293,
          0.1224745,
          0.2823108,
          0.6507428,
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          0.1593117
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            -0.0045284,
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            0.0133712,
            0.0084427,
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            -0.1619082
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            -0.0044647,
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            0.0062354,
            0.0133687,
            0.0084502,
            -0.0330252,
            -0.1620178
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            -0.004477,
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            0.0080082,
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            -0.1625335
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      "related_pin": "CLK",
      "rise_power,power_outputs_1": {
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    },
    "max_capacitance": 0.159312,
    "max_transition": 1.508134,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "timing": {
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      "cell_rise,del_1_7_7": {
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      "fall_transition,del_1_7_7": {
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      "related_pin": "CLK",
      "rise_transition,del_1_7_7": {
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      },
      "timing_sense": "non_unate",
      "timing_type": "rising_edge"
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  },
  "pin,Q_N": {
    "direction": "output",
    "function": "IQ_N",
    "internal_power": {
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      "related_pin": "CLK",
      "rise_power,power_outputs_1": {
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