)]}'
{
  "commit": "ff0839ca3cfd45c098fa0ce837d2afa661338493",
  "tree": "6df1a1c392ba0bbbea274009846af5b48146f205",
  "parents": [
    "208389b362bb05e644aaa6e173acec1e369f7fba"
  ],
  "author": {
    "name": "QuantamHD",
    "email": "emahintorabi@gmail.com",
    "time": "Wed Nov 17 17:03:11 2021 -0800"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Thu Nov 18 10:46:37 2021 -0800"
  },
  "message": "Second release of the ReRAM PDK.\n\nThis release includes the first version of the reram_cell and example\ndesigns provided by Skywater. These are;\n * `reram_cell` - ReRAM Cell with Verilog-AMS, GDS, LEF, SVG, SPICE\n   files.\n\n * `reram_inst` - ReRAM Test Design with GDS, LEF, SVG, SPICE files.\n\n * `reram_test_lvs_property`, `reram_test_lvs_terminals` - ReRAM LVS\n   Test with GDS, LEF, SVG, SPICE files.\n\n * `reram_test_drc` - ReRAM DRC Violation Test with GDS, LEF, SVG, SPICE\n   files.\n\nSigned-off-by: Ethan Mahintorabi \u003cethanmoon@google.com\u003e\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\nSigned-off-by: Steve Kosier \u003cSteve.Kosier@skywatertechnology.com\u003e\n",
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