Updating documentation for the Skywater ReRAM technology. This doc update includes programming instructions, and technology details not included in the original release. Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com> Signed-off-by: Tim Ansell <tansell@google.com>
diff --git a/docs/background.rst b/docs/background.rst new file mode 100644 index 0000000..5396dec --- /dev/null +++ b/docs/background.rst
@@ -0,0 +1,218 @@ +############ + Background +############ + +.. |HfO2| replace:: + + HfO\ :sub:`2` + +.. |HfOx| replace:: + + HfO\ :sub:`x` + +.. |TaOx| replace:: + + TaO\ :sub:`x` + +.. |TiOx| replace:: + + TiO\ :sub:`x` + +.. |AlOx| replace:: + + AlO\ :sub:`x` + +A typical Resistive RAM (RRAM) device consists of a metal-oxide +switching layer (e.g., |HfOx|, |TaOx|, |TiOx|, |AlOx| by atomic layer +deposition) sandwiched by top and bottom metal electrodes, forming a +two-terminal metal-insulator-metal (MIM) structure. As a CMOS-compatible +NVM device, RRAM can be directly fabricated in the back-end-of-line +(BEOL) process without impacting the front-end-of-line (FEOL) portion of +a silicon chip. [[1]_] At SkyWater Technology Foundry, a |HfO2|-based +RRAM layer is fabricated within the BEOL process at multiple points as +described in the physical design rules. + +******************* + General Operation +******************* + +RRAM's general operation is as follows: an applied electric field across +the electrodes induces the creation and motion of oxygen vacancies +within the insulator oxide, resulting in the formation of conductive +filaments in the oxide. This changes the device resistance, which varies +between high and low states. [[2]_] There are thus three distinct modes +of operation: + +#. Forming, (also referred herein as FORM) during which an initial + oxygen filament is created. +#. Writing, during which the conductivity of this filament is + manipulated by the application of electric field. +#. Reading, during which the resistance or conductivity of the filament + is sensed and converted into a digital value. + +During forming, a high electric field is applied to form the filament. +The fresh (un-formed) RRAM cell starts at an ultra-high resistance +(ultra-low conductance state), through the creation of the initial +filament via the formation of oxygen vacancies, a low resistance state +(high conductance state) is reached. Writing can be further broken down +into two distinct modes: + +#. RESET – in which resistance is increased (conductance decreased) by + applying a negative electric field across the device bringing it from + a low resistance state (LRS) to a high resistance state (HRS) + +#. SET – in which resistance is decreased (conductance increased) by + applying a positive electric field across the device brining it from + HRS to LRS. The voltages applied during SET/RESET are usually of + lower magnitude than forming. Reading is usually performed with a + low-applied voltage (e.g., 0.1-0.2V) using current sensing to + determine the state of the RRAM device; often the HRS is used to + store a logical ‘0’ and the LRS stores a logical ‘1’. RRAM setup + usually follows this sequence: FORM -> RESET -> SET. Leaving cells + all in a LRS ‘1’ state. Additional SET/RESET cycling can be performed + to improve the switching reliability, and leave cells in a specified + state. + +Beyond a single RRAM cell, arrays require the use of a control +transistor, creating a 1T-1R structure. This control device is used both +to select the cell within the array but also controls the compliance +current during the FORM, SET, and RESET operations. When thinking about +an RRAM-based system, all three modes must be supported in order to +enable system functionality: e.g., built-in forming must be enabled, +otherwise the RRAM will be non-functional (e.g., SET and RESET +operations have no impact unless the cell filament is first FORMed). + +A general RRAM cell schematic, technology, and array architecture are +shown in :numref:`cell_schematic` and :numref:`rram_array` shows the +schematic of the three inputs to an RRAM cell, namely the bitline (BL), +wordline (WL), and source line (SL). The voltages at these inputs can be +used as “knobs” to program the cell resistance to a target range. The +wordline voltage (VWL) controls the compliance current through the RRAM +cell, while the bitline voltage (VBL) and source line voltage (VSL) +control the potential across the cell. In order to perform a SET +operation, VBL is increased while VSL is grounded. To perform a RESET +operation, VSL is increased while VBL is grounded. For both SET and +RESET, VWL must be above the threshold voltage of the control transistor +to enable current flow through the cell. + +.. _cell_schematic: + +.. figure:: figures/reram_document_figures/technology_figure.png + :scale: 50 % + :align: center + + \(a) Cell schematic, (b) RRAM cell TEM, and (c) die photo of array. + +.. _rram_array: + +.. figure:: figures/reram_document_figures/rram_array.png + :scale: 50 % + :align: center + + 1T1R RRAM array architecture + +Beyond monolithic integration, the use of RRAM arrays offers many +benefits at the system level: + +#. RRAM inherently promises higher memory density compared to SRAM due + to its 1T1R structure. + +#. RRAM offers low read energy and latency, due the low voltage of + reading and large resistance window between HRS and LRS. + +#. RRAM is non-volatile, power is not required to maintain an RRAM’s + resistance value; RRAM-based systems can thus be quickly turned on + and off enabling fine-grained temporal power gating [[4]_]. + +#. Additional structures beyond 1T1R (e.g., 1TnR), when monolithically + integrated, provide RRAM even greater densities [[3]_]. + +#. RRAM can support multiple bits-per-cell storage, effectively boosting + storage density [[3]_]. + +Multiple bits-per-cell storage in RRAM requires dividing up the +resistance range into multiple levels (e.g., not just the single LRS and +HRS of a binary 1-bit cell). These levels can be specified by a set of +ranges and gaps, where cells are considered to be in one digital level +if their resistance is within the corresponding range, and a cell is in +error if left in the gap. This scheme is demonstrated in +:numref:`ranges_and_gaps`. + +.. _ranges_and_gaps: + +.. figure:: figures/reram_document_figures/ranges_and_gaps.png + :scale: 50 % + :align: center + + Ranges and gaps in 2 bits-per-cell RRAM + +RRAM cells, after forming, have an available resistance window between +the lowest resistance states achievable and the highest resistance state +achievable (e.g., the LRS and HRS used in binary storage). Determining +how to optimally partition this window for the additional levels in +2-bit, 3-bit and beyond storage is currently under research. In later +sections we will discuss one such technique and show the measured +performance achievable with the SkyWater RRAM technology. Two additional +ideas that are key to understanding RRAM’s capabilities are the +following: retention, e.g., the ability for the RRAM’s resistance to +stay constant throughout time (either with or without power) and +endurance, the limited number of SET-(writing a ‘1’)–RESET-(writing a +‘0’) cycles a memory cell can undergo before permanent write failure +(stuck at the ‘1’ or ‘0’ state). RRAM’s major benefits come with some +additional challenges that must be considered in design, namely: + +#. Compared to reads, RRAM has relatively higher write energies and + latencies. + +#. RRAM has limited endurance compared to volatile technologies like + SRAM and DRAM + +#. RRAM faces potential retention challenges at very high temperatures, + especially if using multiple bits-per-cell storage (this will be In + the following sections, we provide detailed data quantifying the RRAM + technology provided at SkyWater. + +This technology is still under development and the following procedures +do not guarantee the results indicated. This document will be updated as +necessary to provide the most current data on the process. + +************ + References +************ + +.. [1] + + Rich D\. et al\. (2020) Heterogeneous 3D Nano-systems: The N3XT + Approach?. In: Murmann B., Hoefflinger B. (eds) NANO-CHIPS 2030. The + Frontiers Collection. Springer, Cham. + https://doi-org.stanford.idm.oclc.org/10.1007/978-3-030-18338-7_9 + +.. [2] + + Wong, HS., Salahuddin, S. Memory leads the way to better computing. + Nature Nanotech 10, 191–194 (2015). + https://doi-org.stanford.idm.oclc.org/10.1038/nnano.2015.29 + +.. [3] + + E\. R\. Hsieh et al., "High-Density Multiple Bits-per-Cell 1T4R RRAM + Array with Gradual SET/RESET and its Effectiveness for Deep Learning," + 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, + CA, USA, 2019, pp. 35.6.1-35.6.4, doi: 10.1109/IEDM19573.2019.8993514. + +.. [4] + + T\. F\. Wu, B. Q. Le, R. Radway, A. Bartolo, W. Hwang, S. Jeong, H. Li, + P. Tandon, E. Vianello, P. Vivet, E. Nowak, M. K. Wooters, H.-S. P. + Wong, M. M. Sabry Aly, E. Beigne, S. Mitra "14.3 A 43pJ/Cycle + Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating + 2.3-bit/Cell Resistive RAM and Resilience Techniques," 2019 IEEE + International Solid- State Circuits Conference - (ISSCC), San Francisco, + CA, USA, 2019, pp. 226-228, DOI: 10.1109/ISSCC.2019.8662402 + +.. [5] + + B\. Q\. Le, A. Grossi, E. Vianello, T. Wu, G. Lama, E. Beigne, H.-S. P. + Wong, S. Mitra, "Resistive RAM with Multiple Bits per Cell: Array-Level + Demonstration of 3 Bits per Cell," IEEE Transactions on Electron Devices + Journal, vol. 66, Issue 1, Jan. 2019. 10.1109/TED.2018.2879788
diff --git a/docs/figures/reram_document_figures/1T1R_5.csv b/docs/figures/reram_document_figures/1T1R_5.csv new file mode 100644 index 0000000..b0afe03 --- /dev/null +++ b/docs/figures/reram_document_figures/1T1R_5.csv
@@ -0,0 +1,5 @@ +1T1R #5,WL (V),BL (V),SL (V),PW (ns),Yield (%) +Pristine,,,,,99.90 +Form,1.4 - 2.0 (0.1 step),2.6 - 3.1 (0.1 step),0,1000,92.73 +Reset,2.5,0,2.6,1000,90.83 +Set,1.7,2.4,0,1000,97.45
diff --git a/docs/figures/reram_document_figures/1T4R_4.csv b/docs/figures/reram_document_figures/1T4R_4.csv new file mode 100644 index 0000000..5ba48b6 --- /dev/null +++ b/docs/figures/reram_document_figures/1T4R_4.csv
@@ -0,0 +1,5 @@ +1T4R #4,WL (V),BL (V),SL (V),PW (ns),Yield (%) +Pristine,,,,,100.00 +Form,1.4 - 2.5 (0.1 step),2.4 - 3.3 (0.1 step),0,1000,98.24 +Reset,2.5,0,2.6,1000,91.25 +Set,1.7,2.4,0,1000,99.78
diff --git a/docs/figures/reram_document_figures/1T4R_9.csv b/docs/figures/reram_document_figures/1T4R_9.csv new file mode 100644 index 0000000..25b7235 --- /dev/null +++ b/docs/figures/reram_document_figures/1T4R_9.csv
@@ -0,0 +1,5 @@ +1T4R #9,WL (V),BL (V),SL (V),PW (ns),Yield (%) +Pristine,,,,,100.00 +Form,1.4 - 2.5 (0.1 step),2.4 - 3.3 (0.1 step),0,1000,99.80 +Reset,2.5 - 3.0 (0.1 step),0,2.4 - 3.0 (0.1 step),1000,99.41 +Set,1.7,2.4,0,1000,100.00 \ No newline at end of file
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@@ -7,3 +7,5 @@ user_guide references + background + technology_specifications
diff --git a/docs/technology_specifications.rst b/docs/technology_specifications.rst new file mode 100644 index 0000000..46bb5f9 --- /dev/null +++ b/docs/technology_specifications.rst
@@ -0,0 +1,199 @@ +########################### + Technology Specifications +########################### + +.. |HfO2| replace:: + + HfO\ :sub:`2` + +********* + FORMing +********* + +The figure below shows forming data on a 1Mbit RRAM array. At fresh +(e.g., unformed) the starting conductance of the RRAM ranges below 0.1 +uS (e.g., resistance above 10MOhms). To form the cells, voltages from +2.2 to 3.1V are required (average 2.5V), with very high yields (above +99%) achieved with a max forming voltage of 3.1V. After FORM, the RRAMs +end up in an ultra-low LRS of 30-120uS. Resetting the cells after +forming results in an HRS. The forming pulse widths are 1,000ns (e.g., +1us). + +.. image:: figures/reram_document_figures/forming.png + +The initial forming conditions impact the final resistance range +achievable with the RRAM cells. Using a higher forming voltage (and +longer forming pulses) result in an initial LRS state with a lower +resistance. Depending on the initial LRS resistance, the sharpness of +the SET/RESET transition and the window between the final LRS/HRS +changes as demonstrated in the figures below. This becomes critical when +determining the multiple bits per cell as a gradual SET/RESET procedure +is needed to fine tune the resistance. + +.. image:: figures/reram_document_figures/pulse_resistance_diagram.png + +Fig. 10 provides a possible explanation for the results in Figs.7-9. We +can divide the transition curve of conductance into 4 stages. During +FORMing, in Stage 0, a major filament with a wide radius is created in +|HfO2|. In addition, small filaments extend from the tip of the major +filament to the top electrode. During RESET, in Stage 1, the major +filament recesses resulting in abrupt drop in conductance. In Stage 2, +the small filaments slowly recess resulting in gradual reduction of +conductance. During SET, in Stage 3, the major filament reconnects and +the conductance jumps. In Stage 4, the small filaments re-connect and +the conductance slowly increases. + +.. figure:: figures/reram_document_figures/forming_pulse.png + + Figure extracted from [[1]_] + +***************** + SETing/RESETing +***************** + +The standard SET/RESET pulses used with the SkyWater RRAM +characteristics are summarized below for binary (e.g., 1-bit/cell) RRAM. +Note that these are dependent on the initial forming conditions used (as +discussed above). For completeness we give those conditions as well. +Where a range is given, the procedure is as follows: first fix the BL +voltage (for FORM/SET, SL voltage for RESET) and increase the WL pulse +amplitude by the step size given until the cell is successfully +formed/set/reset. If the cell is unsuccessful, then increase the BL +voltage by the step size, and so forth. + +The following tables were manually transcribed into this format the +original :download:`png +<figures/reram_document_figures/original_tables.png>` is is provided so +that others may check the transcription. + +.. csv-table:: 1T1R #5 + :file: figures/reram_document_figures/1T1R_5.csv + :header-rows: 1 + :align: center + +.. csv-table:: 1T4R #4 + :file: figures/reram_document_figures/1T4R_4.csv + :header-rows: 1 + :align: center + +.. csv-table:: 1T4R #9 + :file: figures/reram_document_figures/1T4R_9.csv + :header-rows: 1 + :align: center + +Alternative programming schemes can be used. For example, from our data +on the 1T4R test #9 above, one could consider using a fixed reset pulse +of WL=3V, SL=3V with a 1000ns pulse to ensure high RESET yields. +Additionally, a lower voltage can be tried multiple times (e.g., a +SET/READ and verify, or RESET/READ and verify) until the operation is +successful. The pulse length is also a free variable, shorter (e.g., +100-200ns SET/RESET) pulses, with a verify scheme can also be used to +reduce average write time. + +************************************************************** + Technology Specs: SkyWater 1T(n)R and Multiple Bits-Per-Cell +************************************************************** + +1T(n)R +====== + +Multiple RRAM cells can be controlled with a single transistor. Such a +layout increases density, especially when integrated monolithically +(with multiple RRAM’s stacked above a single transistor). Below we give +schematics of such 1T4R and 1T8R arrays. + +.. image:: figures/reram_document_figures/1T4R_schematic.png + +.. image:: figures/reram_document_figures/1T8R_schematic.png + +FORMing 1T(n)R +============== + +Such arrays require a different forming scheme. The operation of a 1T4R +RRAM array is much more complex (vs. a 1T1R array) since interactions +between multiple cells (in the same 1T4R structure) Fig. 4 presents our +forming approach for 1T4R RRAM array. The conventional approach for 1T1R +FORMs a cell (i.e., induces LRS in that cell) and then proceeds to the +next cell. However, if this conventional scheme is directly applied to +1T4R (Fig. 4a), the FORMed cell, which is already in the low-resistance +state (LRS), will experience additional SET (over-SET) as another cell +inside the same 4R structure is being FORMed. After experiencing +multiple over-SETs, the resistance of a FROMed cell may fall to an +ultra-low value, and it may not be possible to RESET that cell anymore. +The FORMing scheme in Fig. 4b overcomes this challenge by RESETting a +cell (to the high-resistance state or HRS) immediately after it is +FORMed. Therefore, when a cell is being FORMed, the adjacent FROMed but +RESET cells (in the same 1T4R structure) are no longer over-SET. +Occasionally, an adjacent RESET cell may be SET accidentally. It is +necessary to check and RESET all cells in the 1T4R structure before the +next cell is FORMed. Using this strategy, the FORMing yield is 99%. The +forming voltages were given in the tables above. + +.. image:: figures/reram_document_figures/multirram_forming.png + +SETing/RESETing 1T(n)R +====================== + +While the voltages of SET/RESET are given in the tables above, there are +additional considerations in writing a 1TnR cell. Multiple bits-per-cell +operation of 1T4R RRAM requires more precise control (vs. 1T1R) since +disturbances between adjacent cells (in the same 1T4R structure) will be +more serious. For example, Fig. 14 shows that when a cell in 1T4R is +selected to be SET, the other 3 (unselected) cells can experience a +small RESET, which can disturb the values stored in those (unselected) +cells. Therefore, additional compensating SET operations are needed to +restore the values in those (unselected) cells. By applying the +compensating SETs, the disturbances in the unselected cells can be well +alleviated, as shown in the insert of Fig. 14. The few low- voltage +compensating SET pulses do not affect the other cells. + +.. image:: figures/reram_document_figures/1T4R_forming_waveform.png + +Multiple Bits-Per-Cell: 1T1R with 2 or 3 Bits-Per-Cell +====================================================== + +Programming +----------- + +Multiple bits-per-cell programming requires fine control over the cell +resistance in order for the cells to end up in the desired range. There +are two techniques that have been explored on the SkyWater RRAM, the +first is demonstrated on a 1T1R structure and can achieve 2 or 3 +bits-percell. Adjusting VWL allows for “coarse” tuning of the RRAM +resistance (relatively large resistance change per pulse, but with less +accuracy), while VBL and VSL allow for “fine” tuning (relatively small +resistance change per pulse, but with more accuracy). Fig. 4 depicts the +“tuning curves” at 6kOhm (representative resistance for illustration) in +the SkyWater technology, which shows how the cell resistance (slope) is +more sensitive to changes in VWL than to changes in VBL (for SET) and +VSL (for RESET). A smaller slope signifies that the resistance can be +tuned more slowly/accurately and indicates that voltage noise has a +reduced impact on the change in resistance. We see that SET operations +allow for finer tuning than RESET operations, since the SET operation +results in an increasing voltage drop across the select transistor and a +decreasing voltage drop across the RRAM cell. + +.. _tuning_knob: + +.. figure:: figures/reram_document_figures/tuning_knob_v.png + + Tuning curves showing the sensitivity of resistance change to different + input knobs for a representative starting resistance of 6kΩ. Slopes + are measured at 5.5kΩ for SET and 6.5kΩ for RESET. During VSL RESET + tuning, VWL=3.5V; during VBL SET tuning, VWL=3V; for VWL + RESET tuning, VSL=2.8V; for VWL SET tuning, VBL=2V. Data is averaged + across 50 cells with 10 samples per cell. We also tested different + starting resistances and step sizes (not plotted for clarity). For all + parameters tested, the data showed that resistance change is more gradual when + tuning with VBL/VSL rather than VWL. + +************ + References +************ + +.. [1] + + E\. R\. Hsieh et al., "High-Density Multiple Bits-per-Cell 1T4R RRAM + Array with Gradual SET/RESET and its Effectiveness for Deep Learning," + 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, + CA, USA, 2019, pp. 35.6.1-35.6.4, doi: 10.1109/IEDM19573.2019.8993514.
