)]}'
{
  "commit": "441f50c01b160b9f13133550e729006b79cee69a",
  "tree": "d46fc3e4c74995b5a0657a137795f2f0b4c4bacd",
  "parents": [
    "72df095a151b0582bbaef4a03749f62942951572",
    "0d1f3d57c57e074bbfefad046c67582729540e87"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Wed Jan 19 15:05:18 2022 -0800"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Wed Jan 19 15:05:42 2022 -0800"
  },
  "message": "Merge pull request #22 from VLSIDA/main\n\nThis PR contains open-source schematic files for a 1T1R example based\noff the reram documentation which uses closed source tools.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}