Second release of the ReRAM PDK.
This release includes the first version of the reram_cell and example
designs provided by Skywater. These are;
* `reram_cell` - ReRAM Cell with Verilog-AMS, GDS, LEF, SVG, SPICE
files.
* `reram_inst` - ReRAM Test Design with GDS, LEF, SVG, SPICE files.
* `reram_test_lvs_property`, `reram_test_lvs_terminals` - ReRAM LVS
Test with GDS, LEF, SVG, SPICE files.
* `reram_test_drc` - ReRAM DRC Violation Test with GDS, LEF, SVG, SPICE
files.
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
Signed-off-by: Steve Kosier <Steve.Kosier@skywatertechnology.com>
26 files changed
