tree f96e3fb6285b1348ecd62a0aaa07ddbe1faf1931
parent ef3ec3edd3d30a35ff04011fd3afc8f2cdd1d06f
parent 0effa96c32051608b5c053a46f894b47e4fd4d00
author Ethan Mahintorabi <ethanmoon@google.com> 1637812041 -0800
committer Ethan Mahintorabi <ethanmoon@google.com> 1637812309 -0800

Fixes ReRAM Verilog-A model naming convention.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>