)]}'
{
  "commit": "31cefa62c9a34b29409b8514104da4e0e68693c0",
  "tree": "f96e3fb6285b1348ecd62a0aaa07ddbe1faf1931",
  "parents": [
    "ef3ec3edd3d30a35ff04011fd3afc8f2cdd1d06f",
    "0effa96c32051608b5c053a46f894b47e4fd4d00"
  ],
  "author": {
    "name": "Ethan Mahintorabi",
    "email": "ethanmoon@google.com",
    "time": "Wed Nov 24 19:47:21 2021 -0800"
  },
  "committer": {
    "name": "Ethan Mahintorabi",
    "email": "ethanmoon@google.com",
    "time": "Wed Nov 24 19:51:49 2021 -0800"
  },
  "message": "Fixes ReRAM Verilog-A model naming convention.\n\nSigned-off-by: Ethan Mahintorabi \u003cethanmoon@google.com\u003e\n",
  "tree_diff": []
}