)]}'
{
  "commit": "0effa96c32051608b5c053a46f894b47e4fd4d00",
  "tree": "98902ac072f8fed8bdaf61e336f99a7f538038a7",
  "parents": [
    "21212f530de3b071e4737a7622ce3c7dce1527bb"
  ],
  "author": {
    "name": "Ethan Mahintorabi",
    "email": "ethanmoon@google.com",
    "time": "Wed Nov 24 19:47:21 2021 -0800"
  },
  "committer": {
    "name": "Ethan Mahintorabi",
    "email": "ethanmoon@google.com",
    "time": "Wed Nov 24 19:50:58 2021 -0800"
  },
  "message": "Fixes ReRAM Verilog-A model naming convention.\n\nSigned-off-by: Ethan Mahintorabi \u003cethanmoon@google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "978e0a8bed549c5640aebc836e26a3572e2cc87c",
      "old_mode": 33188,
      "old_path": "cells/reram_cell/sky130_fd_pr_reram__reram_cell.va",
      "new_id": "8377a90e4e7dfb4994f8f10b75080f74028fc3d4",
      "new_mode": 33188,
      "new_path": "cells/reram_cell/sky130_fd_pr_reram__reram_cell.va"
    }
  ]
}