commit 0effa96c32051608b5c053a46f894b47e4fd4d00
author Ethan Mahintorabi <ethanmoon@google.com> Wed Nov 24 19:47:21 2021 -0800
committer Ethan Mahintorabi <ethanmoon@google.com> Wed Nov 24 19:50:58 2021 -0800
tree 98902ac072f8fed8bdaf61e336f99a7f538038a7
parent 21212f530de3b071e4737a7622ce3c7dce1527bb

Fixes ReRAM Verilog-A model naming convention.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>

cells/reram_cell/sky130_fd_pr_reram__reram_cell.va

diff --git a/cells/reram_cell/sky130_fd_pr_reram__reram_cell.va b/cells/reram_cell/sky130_fd_pr_reram__reram_cell.va
index 978e0a8..8377a90 100644
--- a/cells/reram_cell/sky130_fd_pr_reram__reram_cell.va
+++ b/cells/reram_cell/sky130_fd_pr_reram__reram_cell.va
@@ -17,7 +17,7 @@
 `include "constants.vams"
 `include "disciplines.vams"
 
-module rram2(TE, BE);
+module sky130_fd_pr_reram__reram_cell(TE, BE);
     inout TE; // top electrode
     inout BE; // bottom electrode
     electrical TE, BE;