)]}'
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        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "me@mith.ro",
        "time": "Wed Feb 15 08:21:18 2023 -0800"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Wed Feb 15 08:21:18 2023 -0800"
      },
      "message": "Merge pull request #2 from proppy/patch-1\n\ngitmodules: fix url to use https"
    },
    {
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        "time": "Thu Feb 16 01:13:56 2023 +0900"
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        "email": "noreply@github.com",
        "time": "Thu Feb 16 01:13:56 2023 +0900"
      },
      "message": "gitmodules: fix url to use https"
    },
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        "email": "aagouhar@efabless.com",
        "time": "Wed Oct 14 18:16:57 2020 +0200"
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      "committer": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "me@mith.ro",
        "time": "Tue Nov 24 09:34:35 2020 -0800"
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      "message": "docs: Replace the block description list with references.\n\nMatch the listing in the Block Description subsection with the listing\nin the original source, and use references to the sections instead of\nusing an auto generated table of contents.\n\nSigned-off-by: Amr Gouhar \u003caagouhar@efabless.com\u003e\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003cme@mith.ro\u003e\n"
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        "email": "aagouhar@efabless.com",
        "time": "Wed Oct 14 18:16:57 2020 +0200"
      },
      "committer": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "me@mith.ro",
        "time": "Tue Nov 24 09:33:01 2020 -0800"
      },
      "message": "docs: Replace the block description list with references.\n\nMatch the listing in the Block Description subsection with the listing\nin the original source, and use references to the sections instead of\nusing an auto generated table of contents.\n\nSigned-off-by: Amr Gouhar \u003caagouhar@efabless.com\u003e\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003cme@mith.ro\u003e\n"
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        "email": "aagouhar@efabless.com",
        "time": "Wed Oct 14 18:16:57 2020 +0200"
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      "committer": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "me@mith.ro",
        "time": "Tue Nov 24 09:30:32 2020 -0800"
      },
      "message": "docs: Replace the block description list with references.\n\nMatch the listing in the Block Description subsection with the listing\nin the original source, and use references to the sections instead of\nusing an auto generated table of contents.\n\nSigned-off-by: Amr Gouhar \u003caagouhar@efabless.com\u003e\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003cme@mith.ro\u003e\n"
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      "author": {
        "name": "agorararmard",
        "email": "aagouhar@efabless.com",
        "time": "Wed Oct 14 18:16:57 2020 +0200"
      },
      "committer": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "me@mith.ro",
        "time": "Tue Nov 24 09:27:42 2020 -0800"
      },
      "message": "docs: Replace the block description list with references.\n\nMatch the listing in the Block Description subsection with the listing\nin the original source, and use references to the sections instead of\nusing an auto generated table of contents.\n\nSigned-off-by: Amr Gouhar \u003caagouhar@efabless.com\u003e\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003cme@mith.ro\u003e\n"
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    {
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      "author": {
        "name": "agorararmard",
        "email": "aagouhar@efabless.com",
        "time": "Wed Oct 14 18:16:57 2020 +0200"
      },
      "committer": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "me@mith.ro",
        "time": "Tue Nov 24 09:24:40 2020 -0800"
      },
      "message": "docs: Replace the block description list with references.\n\nMatch the listing in the Block Description subsection with the listing\nin the original source, and use references to the sections instead of\nusing an auto generated table of contents.\n\nSigned-off-by: Amr Gouhar \u003caagouhar@efabless.com\u003e\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003cme@mith.ro\u003e\n"
    },
    {
      "commit": "01b18699b4102d8e54ad1406b3991ecb652e5aee",
      "tree": "538a9ceada8222ba80429ec63a6138410c159894",
      "parents": [
        "80ef9b27e7e677f4c0e9f9ee39ea94b9cd261f39"
      ],
      "author": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "me@mith.ro",
        "time": "Tue Nov 10 05:43:14 2020 -0800"
      },
      "committer": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "tansell@google.com",
        "time": "Tue Nov 10 05:43:14 2020 -0800"
      },
      "message": "Release of a subset of IO into sky130_fd_io 0.2.1\n\nThis release includes;\n * Power pads;\n    - High voltage - `top_power_hvc_wpad`, `top_ground_hvc_wpad`\n    - Low voltage - `top_power_lvc_wpad`, `top_ground_lvc_wpad`\n * Reference generators - `top_refgen`, `top_refgen_new`.\n * Standard GPIO (`top_gpiov2`).\n * I2C compatible GPIO with over-voltage tolerance (`top_gpio_ovtv2`).\n * Special SIO (`top_sio`) with differential macro (`top_sio_macro`).\n * System wide reset influencing XRES cell (`top_xres4v2`).\n\nFuture release will include;\n * Original standard GPIO (`top_gpio`).\n * More power pad versions.\n * More XRES cells.\n * More reference generators (`top_vrefcapv2`, etc).\n * Spice and CDL models for the IOs.\n\nThis commit contains major improvements to all files in all modules by\nregenerating from original data, improving consistency and automated cross\nchecking of data.\n\nThese improvements should drastically reduce customer confusion when\nusing the library and further reduce future possibility for human errors to\ncreep into designs.\n\nNotable improvements include;\n\n * A large number of files have been regenerated from original source\n   data including most liberty timing files and spice simulation models\n   (compared to previous hand created versions).\n\n * Catalog and other library aggregations are now automatically\n   generated from library contents (compared to previous hand created\n   versions).\n\n * Significant improvements to documentation for all cells, including\n   producing graphical representations, verified metadata and\n   descriptions.\n\n * Names have been cross referenced between file types (such as\n   simulation, layout, schematic and timing) and now verified to match.\n\n * Names have been improved to fix a standard format across all supported\n   libraries and PDK contents.\n\n * Significant improvements to the contents of text files (like the\n   verilog files) through improving consistent style that has been\n   automatically checked.\n\n * Simplified verilog files for usage with open tools, including new\n   black box stubs have been created.\n\n * Too many numerous other changes to list here.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n"
    },
    {
      "commit": "80ef9b27e7e677f4c0e9f9ee39ea94b9cd261f39",
      "tree": "fd9e9bf658e807c179293b2974c58a61d8eca13a",
      "parents": [
        "40adf19b0baa59da5fb0b8b8b63d0e52dc8697c6"
      ],
      "author": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "me@mith.ro",
        "time": "Tue Nov 10 05:42:17 2020 -0800"
      },
      "committer": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "tansell@google.com",
        "time": "Tue Nov 10 05:42:17 2020 -0800"
      },
      "message": "Release of a subset of IO into sky130_fd_io 0.2.0\n\nThis release includes;\n * Power pads;\n    - High voltage - `top_power_hvc_wpad`, `top_ground_hvc_wpad`\n    - Low voltage - `top_power_lvc_wpad`, `top_ground_lvc_wpad`\n * Reference generators - `top_refgen`, `top_refgen_new`.\n * Standard GPIO (`top_gpiov2`).\n * I2C compatible GPIO with over-voltage tolerance (`top_gpio_ovtv2`).\n * Special SIO (`top_sio`) with differential macro (`top_sio_macro`).\n * System wide reset influencing XRES cell (`top_xres4v2`).\n\nFuture release will include;\n * Original standard GPIO (`top_gpio`).\n * More power pad versions.\n * More XRES cells.\n * More reference generators (`top_vrefcapv2`, etc).\n * Spice and CDL models for the IOs.\n\nThis commit contains major improvements to all files in all modules by\nregenerating from original data, improving consistency and automated cross\nchecking of data.\n\nThese improvements should drastically reduce customer confusion when\nusing the library and further reduce future possibility for human errors to\ncreep into designs.\n\nNotable improvements include;\n\n * A large number of files have been regenerated from original source\n   data including most liberty timing files and spice simulation models\n   (compared to previous hand created versions).\n\n * Catalog and other library aggregations are now automatically\n   generated from library contents (compared to previous hand created\n   versions).\n\n * Significant improvements to documentation for all cells, including\n   producing graphical representations, verified metadata and\n   descriptions.\n\n * Names have been cross referenced between file types (such as\n   simulation, layout, schematic and timing) and now verified to match.\n\n * Names have been improved to fix a standard format across all supported\n   libraries and PDK contents.\n\n * Significant improvements to the contents of text files (like the\n   verilog files) through improving consistent style that has been\n   automatically checked.\n\n * Simplified verilog files for usage with open tools, including new\n   black box stubs have been created.\n\n * Too many numerous other changes to list here.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n"
    },
    {
      "commit": "40adf19b0baa59da5fb0b8b8b63d0e52dc8697c6",
      "tree": "fef2b6da9bcd8645f16a5f3167320ea5011547c4",
      "parents": [
        "4048fc6e03b5a246a1287777ac4f0e4a99ef484f"
      ],
      "author": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "me@mith.ro",
        "time": "Tue Nov 10 05:40:50 2020 -0800"
      },
      "committer": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "tansell@google.com",
        "time": "Tue Nov 10 05:40:50 2020 -0800"
      },
      "message": "Release of a subset of IO into sky130_fd_io 0.1.0\n\nThis release includes;\n * Power pads;\n    - High voltage - `top_power_hvc_wpad`, `top_ground_hvc_wpad`\n    - Low voltage - `top_power_lvc_wpad`, `top_ground_lvc_wpad`\n * Reference generators - `top_refgen`, `top_refgen_new`.\n * Standard GPIO (`top_gpiov2`).\n * I2C compatible GPIO with over-voltage tolerance (`top_gpio_ovtv2`).\n * Special SIO (`top_sio`) with differential macro (`top_sio_macro`).\n * System wide reset influencing XRES cell (`top_xres4v2`).\n\nFuture release will include;\n * Original standard GPIO (`top_gpio`).\n * More power pad versions.\n * More XRES cells.\n * More reference generators (`top_vrefcapv2`, etc).\n * Spice and CDL models for the IOs.\n\nThis commit contains major improvements to all files in all modules by\nregenerating from original data, improving consistency and automated cross\nchecking of data.\n\nThese improvements should drastically reduce customer confusion when\nusing the library and further reduce future possibility for human errors to\ncreep into designs.\n\nNotable improvements include;\n\n * A large number of files have been regenerated from original source\n   data including most liberty timing files and spice simulation models\n   (compared to previous hand created versions).\n\n * Catalog and other library aggregations are now automatically\n   generated from library contents (compared to previous hand created\n   versions).\n\n * Significant improvements to documentation for all cells, including\n   producing graphical representations, verified metadata and\n   descriptions.\n\n * Names have been cross referenced between file types (such as\n   simulation, layout, schematic and timing) and now verified to match.\n\n * Names have been improved to fix a standard format across all supported\n   libraries and PDK contents.\n\n * Significant improvements to the contents of text files (like the\n   verilog files) through improving consistent style that has been\n   automatically checked.\n\n * Simplified verilog files for usage with open tools, including new\n   black box stubs have been created.\n\n * Too many numerous other changes to list here.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n"
    },
    {
      "commit": "4048fc6e03b5a246a1287777ac4f0e4a99ef484f",
      "tree": "733f9224943538b60b97ecfcf4c70189d378c7a1",
      "parents": [
        "e89f551c5b934870b1eeef1898d410554713fb74"
      ],
      "author": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "me@mith.ro",
        "time": "Tue Nov 10 05:38:59 2020 -0800"
      },
      "committer": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "tansell@google.com",
        "time": "Tue Nov 10 05:38:59 2020 -0800"
      },
      "message": "Release of a subset of IO into sky130_fd_io 0.0.2\n\nThis release includes;\n * Power pads;\n    - High voltage - `top_power_hvc_wpad`, `top_ground_hvc_wpad`\n    - Low voltage - `top_power_lvc_wpad`, `top_ground_lvc_wpad`\n * Reference generators - `top_refgen`, `top_refgen_new`.\n * Standard GPIO (`top_gpiov2`).\n * I2C compatible GPIO with over-voltage tolerance (`top_gpio_ovtv2`).\n * Special SIO (`top_sio`) with differential macro (`top_sio_macro`).\n * System wide reset influencing XRES cell (`top_xres4v2`).\n\nFuture release will include;\n * Original standard GPIO (`top_gpio`).\n * More power pad versions.\n * More XRES cells.\n * More reference generators (`top_vrefcapv2`, etc).\n * Spice and CDL models for the IOs.\n\nThis commit contains major improvements to all files in all modules by\nregenerating from original data, improving consistency and automated cross\nchecking of data.\n\nThese improvements should drastically reduce customer confusion when\nusing the library and further reduce future possibility for human errors to\ncreep into designs.\n\nNotable improvements include;\n\n * A large number of files have been regenerated from original source\n   data including most liberty timing files and spice simulation models\n   (compared to previous hand created versions).\n\n * Catalog and other library aggregations are now automatically\n   generated from library contents (compared to previous hand created\n   versions).\n\n * Significant improvements to documentation for all cells, including\n   producing graphical representations, verified metadata and\n   descriptions.\n\n * Names have been cross referenced between file types (such as\n   simulation, layout, schematic and timing) and now verified to match.\n\n * Names have been improved to fix a standard format across all supported\n   libraries and PDK contents.\n\n * Significant improvements to the contents of text files (like the\n   verilog files) through improving consistent style that has been\n   automatically checked.\n\n * Simplified verilog files for usage with open tools, including new\n   black box stubs have been created.\n\n * Too many numerous other changes to list here.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n"
    },
    {
      "commit": "e89f551c5b934870b1eeef1898d410554713fb74",
      "tree": "79dd4e9a67156af498a67e40b5d7e6b0a14c3116",
      "parents": [
        "400756d4bbf266b017bc40b19cab94e46589aeae"
      ],
      "author": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "me@mith.ro",
        "time": "Sat Nov 07 20:25:57 2020 -0800"
      },
      "committer": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "me@mith.ro",
        "time": "Sun Nov 08 10:08:56 2020 -0800"
      },
      "message": "sky130_fd_io: Initial documentation only release.\n\nThe SKY130 IO cells is a toolkit IP. It contains all the cells and\nprimitives required to construct an I/O ring in the SKY130 technology.\n\nThis sky130_fd_io library contained in this document covers different\nkinds of I/O cells,\n\n * a general purpose I/O (`sky130_fd_io__gpio`), and\n * a special I/O (`sky130_fd_io__sio`),\n * a reference generator (`sky130_fd_io__refgen`) for providing voltage\n   references to the `sky130_fd_io__sio`, and\n * Power and Ground (PG) cells that make up the I/O ring.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003cme@mith.ro\u003e\n"
    },
    {
      "commit": "400756d4bbf266b017bc40b19cab94e46589aeae",
      "tree": "b50508b90a2c6bc744d13a80cb17085726e0b2d0",
      "parents": [
        "cd01e2951f248443880054c5d840fe1f95987b03",
        "f9b4491a3316bbd80fcf9bebe2622af0d2e5567f"
      ],
      "author": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "me@mith.ro",
        "time": "Sun Nov 08 10:08:42 2020 -0800"
      },
      "committer": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "me@mith.ro",
        "time": "Sun Nov 08 10:08:42 2020 -0800"
      },
      "message": "Merge remote-tracking branch \u0027docs/master\u0027\n"
    },
    {
      "commit": "f9b4491a3316bbd80fcf9bebe2622af0d2e5567f",
      "tree": "559b9e324dc6e31dcf26df4928cbeeca0d0c03b9",
      "parents": [],
      "author": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "me@mith.ro",
        "time": "Sat Nov 07 20:39:30 2020 -0800"
      },
      "committer": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "me@mith.ro",
        "time": "Sun Nov 08 10:03:47 2020 -0800"
      },
      "message": "docs: Adding default Sphinx setup.\n\n * Uses the following sphinx extensions;\n    - [x] [sphinx-verilog-domain](https://github.com/SymbiFlow/sphinx-verilog-domain)\n    - [x] [sphinxcontrib-hdl-diagrams](https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams)\n    - [x] [Symbolator](https://github.com/SymbiFlow/symbolator)\n    - [x] [sphinx_symbiflow_theme](https://github.com/SymbiFlow/sphinx_symbiflow_theme)\n\n * Adds a few custom roles useful for interlinking the PDK modules.\n\n * Uses `make-env` to enable a conda environment containing required\n   binaries like Yosys, netlistsvg, etc.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003cme@mith.ro\u003e\n"
    },
    {
      "commit": "cd01e2951f248443880054c5d840fe1f95987b03",
      "tree": "95cb964ed51d770d46828f6fccde1052ee8752f4",
      "parents": [],
      "author": {
        "name": "Kevin Kelley",
        "email": "kevin.kelley@skywatertechnology.com",
        "time": "Wed May 06 11:00:00 2020 +0700"
      },
      "committer": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "me@mith.ro",
        "time": "Sat Nov 07 20:22:23 2020 -0800"
      },
      "message": "Initial empty repository.\n\nSigned-off-by: Kevin Kelley \u003ckevin.kelley@skywatertechnology.com\u003e\n"
    }
  ]
}