)]}'
{
  "commit": "80ef9b27e7e677f4c0e9f9ee39ea94b9cd261f39",
  "tree": "fd9e9bf658e807c179293b2974c58a61d8eca13a",
  "parents": [
    "40adf19b0baa59da5fb0b8b8b63d0e52dc8697c6"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Tue Nov 10 05:42:17 2020 -0800"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Tue Nov 10 05:42:17 2020 -0800"
  },
  "message": "Release of a subset of IO into sky130_fd_io 0.2.0\n\nThis release includes;\n * Power pads;\n    - High voltage - `top_power_hvc_wpad`, `top_ground_hvc_wpad`\n    - Low voltage - `top_power_lvc_wpad`, `top_ground_lvc_wpad`\n * Reference generators - `top_refgen`, `top_refgen_new`.\n * Standard GPIO (`top_gpiov2`).\n * I2C compatible GPIO with over-voltage tolerance (`top_gpio_ovtv2`).\n * Special SIO (`top_sio`) with differential macro (`top_sio_macro`).\n * System wide reset influencing XRES cell (`top_xres4v2`).\n\nFuture release will include;\n * Original standard GPIO (`top_gpio`).\n * More power pad versions.\n * More XRES cells.\n * More reference generators (`top_vrefcapv2`, etc).\n * Spice and CDL models for the IOs.\n\nThis commit contains major improvements to all files in all modules by\nregenerating from original data, improving consistency and automated cross\nchecking of data.\n\nThese improvements should drastically reduce customer confusion when\nusing the library and further reduce future possibility for human errors to\ncreep into designs.\n\nNotable improvements include;\n\n * A large number of files have been regenerated from original source\n   data including most liberty timing files and spice simulation models\n   (compared to previous hand created versions).\n\n * Catalog and other library aggregations are now automatically\n   generated from library contents (compared to previous hand created\n   versions).\n\n * Significant improvements to documentation for all cells, including\n   producing graphical representations, verified metadata and\n   descriptions.\n\n * Names have been cross referenced between file types (such as\n   simulation, layout, schematic and timing) and now verified to match.\n\n * Names have been improved to fix a standard format across all supported\n   libraries and PDK contents.\n\n * Significant improvements to the contents of text files (like the\n   verilog files) through improving consistent style that has been\n   automatically checked.\n\n * Simplified verilog files for usage with open tools, including new\n   black box stubs have been created.\n\n * Too many numerous other changes to list here.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
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