)]}'
{
  "log": [
    {
      "commit": "be33adbcf188fdeab5c061699847d9d440f7a084",
      "tree": "0567364d1e907f39976805af4a8d1e94e0e87722",
      "parents": [
        "9fa642baaf01110b59ac2783beba9a4fda03aeaf",
        "d5b83ad31c0617a1abfcb3b55a00dfe8b3ba5fff"
      ],
      "author": {
        "name": "Ethan Mahintorabi",
        "email": "ethanmoon@google.com",
        "time": "Wed Oct 20 15:28:37 2021 -0700"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Wed Oct 20 15:28:37 2021 -0700"
      },
      "message": "Merge pull request #5 from mithro/main\n\nAdding build space layout diagram."
    },
    {
      "commit": "d5b83ad31c0617a1abfcb3b55a00dfe8b3ba5fff",
      "tree": "0567364d1e907f39976805af4a8d1e94e0e87722",
      "parents": [
        "9fa642baaf01110b59ac2783beba9a4fda03aeaf"
      ],
      "author": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "tansell@google.com",
        "time": "Wed Oct 20 15:23:48 2021 -0700"
      },
      "committer": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "tansell@google.com",
        "time": "Wed Oct 20 15:25:47 2021 -0700"
      },
      "message": "Adding build space layout diagram.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n"
    },
    {
      "commit": "9fa642baaf01110b59ac2783beba9a4fda03aeaf",
      "tree": "643c9b7ee678456f992245e7144ee47601d3da80",
      "parents": [
        "dadadf04b78bfa2eb3662b99e20c80dc359be8bf",
        "2f8ebee0d4932c358b1447451ab094493bb74671"
      ],
      "author": {
        "name": "Ethan Mahintorabi",
        "email": "ethanmoon@google.com",
        "time": "Mon Oct 04 15:38:35 2021 -0700"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Mon Oct 04 15:38:35 2021 -0700"
      },
      "message": "Merge pull request #3 from VLSIDA/main\n\nUpdate openram cells"
    },
    {
      "commit": "2f8ebee0d4932c358b1447451ab094493bb74671",
      "tree": "643c9b7ee678456f992245e7144ee47601d3da80",
      "parents": [
        "dadadf04b78bfa2eb3662b99e20c80dc359be8bf"
      ],
      "author": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Mon Oct 04 14:58:39 2021 -0700"
      },
      "committer": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Mon Oct 04 15:00:36 2021 -0700"
      },
      "message": "Update openram cells\n\nRename openram_cell_ to openram_dp and openram_sp\nAdd new spice and LVS views\nAdd maglef view\n"
    },
    {
      "commit": "dadadf04b78bfa2eb3662b99e20c80dc359be8bf",
      "tree": "5d9d85aed9f8509a22cf4b8c481b1b4f2ba3412b",
      "parents": [
        "174f4b68adba4c9524bd7b4b141bcfa9a0671442"
      ],
      "author": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "tansell@google.com",
        "time": "Tue Sep 28 14:44:51 2021 -0700"
      },
      "committer": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "tansell@google.com",
        "time": "Tue Sep 28 15:18:21 2021 -0700"
      },
      "message": "Adding a CONTRIBUTING file.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n"
    },
    {
      "commit": "174f4b68adba4c9524bd7b4b141bcfa9a0671442",
      "tree": "20673d11714b162846781a3633e9ffb21b54b3d7",
      "parents": [
        "cb47445ac29bb5176af5e07a32d6f13bd8f6f95b"
      ],
      "author": {
        "name": "Kevin Kelley",
        "email": "kevin.kelley@skywatertechnology.com",
        "time": "Sat Nov 07 20:12:55 2020 -0800"
      },
      "committer": {
        "name": "Ethan Mahintorabi",
        "email": "ethanmoon@google.com",
        "time": "Tue Sep 28 11:56:17 2021 -0700"
      },
      "message": "Creation of the sky130_fd_bd_sram, SKY130 SRAM build space.\n\nThis commit contains major improvements to all files by regenerating\nfrom original data, improving consistency and automated cross checking\nof data.\n\nNotable improvements include;\n\n * Integration of support cells required to use the OpenRAM memory\n   compiler.\n\n * Creation of single port SRAM cells with built in OPC correction\n   layers when laid out in an array.\n\n * Creation of dual port SRAM cells with built in OPC correction layers\n   when laid out in an array.\n\n * Catalog and other library aggregations are now automatically\n   generated from library contents (compared to previous hand created\n   versions).\n\n * Significant improvements to documentation for all cells, including\n   producing graphical representations, verified metadata and\n   descriptions.\n\n * Names have been cross referenced between file types (such as\n   simulation, layout, schematic and timing) and now verified to match.\n\n * Names have been improved to fix a standard format across all supported\n   libraries and PDK contents.\n\n * Too many numerous other changes to list here.\n\nSigned-off-by: Kevin Kelley \u003ckevin.kelley@skywatertechnology.com\u003e\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003cme@mith.ro\u003e\n"
    },
    {
      "commit": "cb47445ac29bb5176af5e07a32d6f13bd8f6f95b",
      "tree": "f175c5461624ebb5f7e45858713f073640624cbf",
      "parents": [],
      "author": {
        "name": "Kevin Kelley",
        "email": "kevin.kelley@skywatertechnology.com",
        "time": "Wed May 06 11:00:00 2020 +0700"
      },
      "committer": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "me@mith.ro",
        "time": "Sat Nov 07 19:54:20 2020 -0800"
      },
      "message": "Initial empty repository.\n\nSigned-off-by: Kevin Kelley \u003ckevin.kelley@skywatertechnology.com\u003e\n"
    }
  ]
}