# Copyright 2019-2021 SkyWater PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# This code is *alternatively* available under a BSD-3-Clause license, see
# details in the README.md at the top level and the license text at
# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
#
# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
# BAG socket configuration
socket:
  # the host running the database.  localhost if on the same machine.
  host: "localhost"
  # the port to communicate with.
  port_file: "BAG_server_port.txt"
  # the log file for socket communication debugging
  log_file: "BAG_socket.log"
  # number of messages allowed in a pipeline
  pipeline: 100

# CAD database configuration
# Right now only virtuoso is supported.
database:
  # the python class that handles database interaction.
#  class: "bag.interface.oa.OAInterface"
  class: "bag.interface.skill.SkillInterface"
  # default directory to create generated libraries in.
  default_lib_path: "${BAG_WORK_DIR}/gen_libs"
  # If true, then everytime we generate schematic/layout from BAG, all opened cellviews are closed
  close_all_cellviews: False

  # configurations for schematic import and generation
  schematic:
    # technology library to configure new libraries with
    tech_lib: "s8phirs_10r"
    # libraries to exclude for schematic import
    exclude_libraries: ["analogLib", "basic", "s8phirs_10r", "veriloga_lib", "ahdllib"]
    # libraries to exclude for modeling purposes
    model_exclude_libraries: []
    # cells to exclude for modeling purposes
    model_exclude_cells:
      basic: ['noConn']
    # symbol pin master
    sympin: ["basic", "sympin", "symbolNN"]
    # input pin master
    ipin: ["basic", "ipin", "symbol"]
    # output pin master
    opin: ["basic", "opin", "symbol"]
    # inout pin master
    iopin: ["basic", "iopin", "symbolr"]
    # simulators where termOrder CDF field should be filled
    simulators: ["auLvs", "auCdl", "spectre", "hspiceD"]
  # configurations used to create a Checker object to run LVS/RCX
  checker:
    # the Checker class.
    checker_cls: 'bag.verification.calibre.Calibre'
    # program used to run extraction
    rcx_program: xrc
    # maximum number of sub-processes BAG can launch.
    max_workers: 2
    # source.added location
    source_added_file: "${BAG_TECH_CONFIG_DIR}/calibre_setup/source.added"
    # root directories
    root_dir:
      drc: '${BAG_WORK_DIR}/calibre_run/drc'
      lvs: '${BAG_WORK_DIR}/calibre_run/lvs'
      rcx: '${BAG_WORK_DIR}/calibre_run/rcx'
    # jinja template control files
    template:
      drc: '${BAG_TECH_CONFIG_DIR}/calibre_setup/drc.svrf'
      lvs: '${BAG_TECH_CONFIG_DIR}/calibre_setup/lvs.svrf'
      rcx: '${BAG_TECH_CONFIG_DIR}/calibre_setup/rcx.svrf'
    # environment variables
    env_vars:
      drc: {}
      lvs: {}
      rcx: {}
    link_files:
      drc: []
      lvs: []
      rcx: []
    # default parameters
    params:
      drc: {}
      lvs: {}
      rcx:
        # extract_type: rc_coupled  # r_only | c_only_decoupled | c_only_coupled | rc_decoupled | rc_coupled | rlc_decoupled | rlc_coupled for QRC
        # extract_type: RCc  # R | Cg | Cc | RCg | RCc for StarRC
        extract_type: rcc  # rcc | rc | r | c for xRC. See Parasitic Database (PDB) in manual
        netlist_type: SPF   # SPF or SPECTRE
    # the SubProcessManager class
    # mgr_class: 'bag.concurrent.lsf.LSFSubProcessManager'  # runs jobs on the LSF
    # mgr_kwargs:
    #   queue: rhel7  # LSF queue

# Simulation configurations
simulation:
  # python class that talks with the simulator
  class: "bag.simulation.spectre.SpectreInterface"
  # maximum number of processes BAG can launch.
  max_workers: 8
  # when simulation goes long, a reminder message will be printed at this interval
  update_timeout_ms: 120000
  # amount of time to wait for process cancellation to succeed.
  cancel_timeout_ms: 10000
  # True to show interactive log viewer.
  show_log_viewer: True
  # corner configuration file
  env_file: "${BAG_TECH_CONFIG_DIR}/corners_setup.yaml"
  # command settings
  kwargs:
    # the command to start
    command: spectre
    # environment variables.  Null for same environment as SkillOceanServer.
    env: !!null
    # True to run in 64-bit mode
    run_64: True
    # output format
    format: psfbin #psfxl
    # psf version
    psfversion: '1.1'
    options: ['++aps', '+lqtimeout', '0', '+mt=8', '+mp=8', '+postlayout']
  # True if using pysrr for SRR to HDF5 conversion. False to use executable
  # Executable runs faster for smaller simulation data, pysrr runs faster for highly parameterized simulation data
  use_pysrr: False
  # the SubProcessManager class
  # mgr_class: 'bag.concurrent.lsf.LSFSubProcessManager'  # runs jobs on the LSF
  # mgr_kwargs:
  #   queue: rhel7  # LSF queue

  compress: True
  rtol: 1.0e-8
  atol: 1.0e-22

# LEF generation configuration
lef:
  class: 'bag.interface.abstract.AbstractInterface'
  run_dir: 'abstract_run'
  options_file: '${BAG_TECH_CONFIG_DIR}/abstract_setup/bag_abstract.options'
  # the SubProcessManager class
#  mgr_class: 'bag.concurrent.lsf.LSFSubProcessManager'  # runs jobs on the LSF
#  mgr_kwargs:
#    queue: rhel7  # LSF queue

# technology specific configuration are stored in a separate file.
# this field tells BAG where to look for it.
tech_config_path: "${BAG_TECH_CONFIG_DIR}/tech_config.yaml"

# BAG design libraries definition file.
lib_defs: "bag_libs.def"

# place to put new design libraries
new_lib_path: "BagModules"