diff --git a/.idea/skywater130.iml b/.idea/skywater130.iml
index c646a1f..4c55d75 100644
--- a/.idea/skywater130.iml
+++ b/.idea/skywater130.iml
@@ -1,25 +1,4 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!--
-Copyright 2019-2021 SkyWater PDK Authors
-
-Licensed under the Apache License, Version 2.0 (the "License");
-you may not use this file except in compliance with the License.
-You may obtain a copy of the License at
-
-    https://www.apache.org/licenses/LICENSE-2.0
-
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS,
-WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
-
-This code is *alternatively* available under a BSD-3-Clause license, see
-details in the README.md at the top level and the license text at
-https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
-
-SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
--->
 <module type="PYTHON_MODULE" version="4">
   <component name="NewModuleRootManager">
     <content url="file://$MODULE_DIR$">
diff --git a/OA/BAG_prim/cdsinfo.tag b/OA/BAG_prim/cdsinfo.tag
index 4b46185..f3a24f0 100644
--- a/OA/BAG_prim/cdsinfo.tag
+++ b/OA/BAG_prim/cdsinfo.tag
@@ -46,6 +46,7 @@
 # use and behaviour of these entries when appropriate.
 #
 # Current Settings:
+#
 CDSLIBRARY
 DMTYPE none
 NAMESPACE LibraryUnix
diff --git a/OA/BAG_prim/nmos4_hv/schematic/thumbnail_128x128.png b/OA/BAG_prim/nmos4_hv/schematic/thumbnail_128x128.png
index 601157b..1d46566 100644
--- a/OA/BAG_prim/nmos4_hv/schematic/thumbnail_128x128.png
+++ b/OA/BAG_prim/nmos4_hv/schematic/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/nmos4_hv/symbol/thumbnail_128x128.png b/OA/BAG_prim/nmos4_hv/symbol/thumbnail_128x128.png
index 8cb67e4..7c02f60 100644
--- a/OA/BAG_prim/nmos4_hv/symbol/thumbnail_128x128.png
+++ b/OA/BAG_prim/nmos4_hv/symbol/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/nmos4_hvesd/schematic/thumbnail_128x128.png b/OA/BAG_prim/nmos4_hvesd/schematic/thumbnail_128x128.png
index 591c6b8..313567e 100644
--- a/OA/BAG_prim/nmos4_hvesd/schematic/thumbnail_128x128.png
+++ b/OA/BAG_prim/nmos4_hvesd/schematic/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/nmos4_hvesd/symbol/thumbnail_128x128.png b/OA/BAG_prim/nmos4_hvesd/symbol/thumbnail_128x128.png
index 8cb67e4..7c02f60 100644
--- a/OA/BAG_prim/nmos4_hvesd/symbol/thumbnail_128x128.png
+++ b/OA/BAG_prim/nmos4_hvesd/symbol/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/nmos4_lvt/schematic/thumbnail_128x128.png b/OA/BAG_prim/nmos4_lvt/schematic/thumbnail_128x128.png
index ee192cb..fc6a857 100644
--- a/OA/BAG_prim/nmos4_lvt/schematic/thumbnail_128x128.png
+++ b/OA/BAG_prim/nmos4_lvt/schematic/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/nmos4_lvt/symbol/thumbnail_128x128.png b/OA/BAG_prim/nmos4_lvt/symbol/thumbnail_128x128.png
index 8cb67e4..7c02f60 100644
--- a/OA/BAG_prim/nmos4_lvt/symbol/thumbnail_128x128.png
+++ b/OA/BAG_prim/nmos4_lvt/symbol/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/nmos4_standard/schematic/thumbnail_128x128.png b/OA/BAG_prim/nmos4_standard/schematic/thumbnail_128x128.png
index ee192cb..fc6a857 100644
--- a/OA/BAG_prim/nmos4_standard/schematic/thumbnail_128x128.png
+++ b/OA/BAG_prim/nmos4_standard/schematic/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/nmos4_standard/symbol/thumbnail_128x128.png b/OA/BAG_prim/nmos4_standard/symbol/thumbnail_128x128.png
index 8cb67e4..7c02f60 100644
--- a/OA/BAG_prim/nmos4_standard/symbol/thumbnail_128x128.png
+++ b/OA/BAG_prim/nmos4_standard/symbol/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/nmos4_svt/schematic/thumbnail_128x128.png b/OA/BAG_prim/nmos4_svt/schematic/thumbnail_128x128.png
index ee192cb..fc6a857 100644
--- a/OA/BAG_prim/nmos4_svt/schematic/thumbnail_128x128.png
+++ b/OA/BAG_prim/nmos4_svt/schematic/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/nmos4_svt/symbol/thumbnail_128x128.png b/OA/BAG_prim/nmos4_svt/symbol/thumbnail_128x128.png
index 8cb67e4..7c02f60 100644
--- a/OA/BAG_prim/nmos4_svt/symbol/thumbnail_128x128.png
+++ b/OA/BAG_prim/nmos4_svt/symbol/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/pmos4_hv/schematic/thumbnail_128x128.png b/OA/BAG_prim/pmos4_hv/schematic/thumbnail_128x128.png
index c04b5b1..e5b4335 100644
--- a/OA/BAG_prim/pmos4_hv/schematic/thumbnail_128x128.png
+++ b/OA/BAG_prim/pmos4_hv/schematic/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/pmos4_hv/symbol/thumbnail_128x128.png b/OA/BAG_prim/pmos4_hv/symbol/thumbnail_128x128.png
index 2a160dc..d44f020 100644
--- a/OA/BAG_prim/pmos4_hv/symbol/thumbnail_128x128.png
+++ b/OA/BAG_prim/pmos4_hv/symbol/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/pmos4_hvesd/schematic/thumbnail_128x128.png b/OA/BAG_prim/pmos4_hvesd/schematic/thumbnail_128x128.png
index 2058778..7e0aa55 100644
--- a/OA/BAG_prim/pmos4_hvesd/schematic/thumbnail_128x128.png
+++ b/OA/BAG_prim/pmos4_hvesd/schematic/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/pmos4_hvesd/symbol/thumbnail_128x128.png b/OA/BAG_prim/pmos4_hvesd/symbol/thumbnail_128x128.png
index 2a160dc..d44f020 100644
--- a/OA/BAG_prim/pmos4_hvesd/symbol/thumbnail_128x128.png
+++ b/OA/BAG_prim/pmos4_hvesd/symbol/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/pmos4_hvt/schematic/thumbnail_128x128.png b/OA/BAG_prim/pmos4_hvt/schematic/thumbnail_128x128.png
index 60476ed..90982fd 100644
--- a/OA/BAG_prim/pmos4_hvt/schematic/thumbnail_128x128.png
+++ b/OA/BAG_prim/pmos4_hvt/schematic/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/pmos4_hvt/symbol/thumbnail_128x128.png b/OA/BAG_prim/pmos4_hvt/symbol/thumbnail_128x128.png
index 2a160dc..d44f020 100644
--- a/OA/BAG_prim/pmos4_hvt/symbol/thumbnail_128x128.png
+++ b/OA/BAG_prim/pmos4_hvt/symbol/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/pmos4_lvt/schematic/thumbnail_128x128.png b/OA/BAG_prim/pmos4_lvt/schematic/thumbnail_128x128.png
index f4f08ae..18ef0a2 100644
--- a/OA/BAG_prim/pmos4_lvt/schematic/thumbnail_128x128.png
+++ b/OA/BAG_prim/pmos4_lvt/schematic/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/pmos4_lvt/symbol/thumbnail_128x128.png b/OA/BAG_prim/pmos4_lvt/symbol/thumbnail_128x128.png
index 2a160dc..d44f020 100644
--- a/OA/BAG_prim/pmos4_lvt/symbol/thumbnail_128x128.png
+++ b/OA/BAG_prim/pmos4_lvt/symbol/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/pmos4_standard/schematic/thumbnail_128x128.png b/OA/BAG_prim/pmos4_standard/schematic/thumbnail_128x128.png
index 4cb36e1..d96f8b1 100644
--- a/OA/BAG_prim/pmos4_standard/schematic/thumbnail_128x128.png
+++ b/OA/BAG_prim/pmos4_standard/schematic/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/pmos4_standard/symbol/thumbnail_128x128.png b/OA/BAG_prim/pmos4_standard/symbol/thumbnail_128x128.png
index 2a160dc..d44f020 100644
--- a/OA/BAG_prim/pmos4_standard/symbol/thumbnail_128x128.png
+++ b/OA/BAG_prim/pmos4_standard/symbol/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/pmos4_svt/schematic/thumbnail_128x128.png b/OA/BAG_prim/pmos4_svt/schematic/thumbnail_128x128.png
index 4cb36e1..d96f8b1 100644
--- a/OA/BAG_prim/pmos4_svt/schematic/thumbnail_128x128.png
+++ b/OA/BAG_prim/pmos4_svt/schematic/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/pmos4_svt/symbol/thumbnail_128x128.png b/OA/BAG_prim/pmos4_svt/symbol/thumbnail_128x128.png
index 2a160dc..d44f020 100644
--- a/OA/BAG_prim/pmos4_svt/symbol/thumbnail_128x128.png
+++ b/OA/BAG_prim/pmos4_svt/symbol/thumbnail_128x128.png
Binary files differ
diff --git a/pcell_setup/prim_pcell.il b/pcell_setup/prim_pcell.il
index b6714db..0afa585 100644
--- a/pcell_setup/prim_pcell.il
+++ b/pcell_setup/prim_pcell.il
@@ -446,4 +446,3 @@
 
 
 
-
diff --git a/pcell_setup/prim_pcell_jinja2.il b/pcell_setup/prim_pcell_jinja2.il
index 306db76..a257972 100644
--- a/pcell_setup/prim_pcell_jinja2.il
+++ b/pcell_setup/prim_pcell_jinja2.il
@@ -160,4 +160,4 @@
         dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "MINUS"))
     )
 )
-{% endfor %}
+{% endfor %}
\ No newline at end of file
diff --git a/src/templates_skywater130/data/tech_params.yaml b/src/templates_skywater130/data/tech_params.yaml
index b610fed..c8c49ec 100644
--- a/src/templates_skywater130/data/tech_params.yaml
+++ b/src/templates_skywater130/data/tech_params.yaml
@@ -44,11 +44,11 @@
 # mapping from metal layer ID to layer/purpose pair that defines
 # a metal resistor.
 res_metal_layer_table: {}
-#  1: [!!python/tuple ['m1res', 'drawing']]
-#  2: [!!python/tuple ['m2res', 'drawing']]
-#  3: [!!python/tuple ['m3res', 'drawing']]
-#  4: [!!python/tuple ['m4res', 'drawing']]
-#  5: [!!python/tuple ['m5res', 'drawing']]
+#  1: [!!python/tuple ['met1', 'res']]
+#  2: [!!python/tuple ['met2', 'res']]
+#  3: [!!python/tuple ['met3', 'res']]
+#  4: [!!python/tuple ['met4', 'res']]
+#  5: [!!python/tuple ['met5', 'res']]
 
 # mapping from metal layer ID to layer/purpose pair that
 # defines metal exclusion region.
@@ -68,6 +68,7 @@
   3: [!!python/tuple ['met3', 'drawing']]
   4: [!!python/tuple ['met4', 'drawing']]
   5: [!!python/tuple ['met5', 'drawing']]
+#  6: [!!python/tuple ['capm', 'drawing']]
 
 dum_lay_purp_list: *lp_list
 
@@ -87,6 +88,10 @@
   5:
     - [[284, .inf]]
     - [[284, .inf]]
+  
+  6:
+    - [[60, .inf]]
+    - [[60, 2001]]
 
 # mapping from tuple of via layers to via ID.
 via_id:
@@ -155,12 +160,13 @@
         - [.inf, [[62, 62]]]
 
 # minimum wire spacing rule.  Space is measured orthogonal to wire direction.
+# should be in resolution units
 sp_min:
   [met1, drawing]: &sp_min_1x
-    - [.inf, 28]
+    - [.inf, 100]
   [met2, drawing]: *sp_min_1x
   [met3, drawing]: &sp_min_2x
-    - [.inf, 60]
+    - [.inf, 60] #60
   [met4, drawing]: *sp_min_2x
   [met5, drawing]:
     - [.inf, 320]
@@ -168,13 +174,14 @@
 # minimum line-end spacing rule.  Space is measured parallel to wire direction.
 sp_le_min:
   [met1, drawing]: &sp_le_min_1x
-    - [.inf, 28]
+    - [.inf, 100] #change from 28
   [met2, drawing]: *sp_le_min_1x
   [met3, drawing]: &sp_le_min_2x
     - [.inf, 60]
   [met4, drawing]: *sp_le_min_2x
   [met5, drawing]:
     - [.inf, 320]
+  
 
 # minimum length/minimum area rules.
 len_min:
@@ -198,6 +205,10 @@
     w_al_list:
       - [.inf, 160000, 0]
     md_al_list: []
+  #[capm, drawing]:
+  #  w_al_list:
+  #    - [.inf, 9600, 0]
+  #  md_al_list: []
 
 margins:
   well: [40, 40]
@@ -267,6 +278,9 @@
   # nsdm.1
   imp_h_min: 76
 
+  #might be redundant, well margin from edge to implant
+  nwell_imp: 40
+
   grid_info:
     - [1, 52, 1]
     - [3, 66, 1]
@@ -864,4 +878,3 @@
     - [22, 4294967295]
     - [27902976, 4294967295]
     - [6, 4294967295]
-
diff --git a/src/templates_skywater130/mos/tech.py b/src/templates_skywater130/mos/tech.py
index 437893c..bf7d00c 100644
--- a/src/templates_skywater130/mos/tech.py
+++ b/src/templates_skywater130/mos/tech.py
@@ -42,7 +42,7 @@
     MOSRowSpecs, MOSRowInfo, BlkExtInfo, MOSEdgeInfo, MOSLayInfo, ExtWidthInfo, LayoutInfo,
     ExtEndLayInfo, RowExtInfo
 )
-from ..util import add_base, get_arr_edge_dim
+from ..util import add_base, add_base_mos, get_arr_edge_dim
 
 MConnInfoType = Tuple[int, int, Orient2D, int, Tuple[str, str]]
 
@@ -109,13 +109,41 @@
 
     @property
     def min_sep_col(self) -> int:
-        return self._get_od_sep_col(self.mos_config['od_spx'])
+        #return self._get_od_sep_col(self.mos_config['od_spx'])
+
+        #felicia copied
+        lch = self.lch
+        sd_pitch = self.sd_pitch
+        od_po_extx = self.od_po_extx
+
+        od_spx: int = self.mos_config['od_spx']
+        imp_od_encx: int = self.mos_config['imp_od_encx']
+        ans = -(-(od_spx + lch + 2 * od_po_extx + 2*imp_od_encx) // sd_pitch) - 1
+        return ans + (ans & 1)
 
     @property
     def sub_sep_col(self) -> int:
-        return self._get_od_sep_col(max(self.mos_config['od_spx'],
-                                        2 * self.mos_config['imp_od_encx']))
+        # column separation needed between transistor/substrate and substrate/substrate.
+        # This is guaranteed to be even.
 
+        #return self._get_od_sep_col(max(self.mos_config['od_spx'],
+        #                            2 * self.mos_config['imp_od_encx']))
+        
+        #felicia - copied method from cds_ff_mpt
+        #does something similar to _get_od_sep_col but seems to have 
+        #effective +1 that get_od doesn't have
+        lch = self.lch
+        sd_pitch = self.sd_pitch
+        od_po_extx = self.od_po_extx
+
+        mos_config = self.mos_config
+        od_spx: int = mos_config['od_spx']
+        imp_od_encx: int = mos_config['imp_od_encx']
+
+        od_spx = max(od_spx, 2 * imp_od_encx)
+        ans = -(-(od_spx + lch + 2 * od_po_extx) // sd_pitch) - 1
+        return ans + (ans & 1)
+        
     @property
     def min_sub_col(self) -> int:
         return self.min_od_col
@@ -144,7 +172,8 @@
     @property
     def well_w_edge(self) -> int:
         imp_od_encx: int = self.mos_config['imp_od_encx']
-        return -(self.sd_pitch - self.lch) // 2 + self.od_po_extx + imp_od_encx
+        nwell_imp: int = self.mos_config['nwell_imp']
+        return -(self.sd_pitch - self.lch) // 2 + self.od_po_extx + nwell_imp + imp_od_encx
 
     def get_conn_info(self, conn_layer: int, is_gate: bool) -> ConnInfo:
         mconf = self.mos_config
@@ -390,7 +419,7 @@
                      po_y_gate: Tuple[int, int], fg: int, conn_pitch: int, g_on_s: bool) -> None:
         lch = self.lch
         sd_pitch = self.sd_pitch
-
+        #breakpoint()
         mconf = self.mos_config
         npc_w: int = mconf['npc_w']
         npc_h: int = mconf['npc_h']
@@ -444,7 +473,8 @@
             builder.add_rect_arr(mp_lp, BBox(mp_xl, mp_yl, mp_xl + mp_w_min, mp_yh),
                                  nx=num_g, spx=conn_pitch)
         else:
-            mp_dx = g0_info.via_w // 2 + g0_info.via_top_enc
+            mp_dx = g0_info.via_w # felicia - // 2 + g0_info.via_top_enc
+                                  # for licon.5
             mp_xl = g_xc - mp_dx
             mp_xh = g_xc + (num_g - 1) * conn_pitch + mp_dx
             builder.add_rect_arr(mp_lp, BBox(mp_xl, mp_yl, mp_xh, mp_yh))
@@ -474,7 +504,6 @@
         md_box = BBox(xc - md_w2, md_y[0], xc + md_w2, md_y[1])
         builder.add_rect_arr(('licon1', 'drawing'), vc_box, nx=nx, spx=spx, ny=num_vc, spy=vc_p)
         builder.add_rect_arr(('li1', 'drawing'), md_box, nx=nx, spx=spx)
-
         # connect to M1
         builder.add_via(d1_info.get_via_info('L1M1_C', xc, od_yc, md_w, ortho=False,
                                              num=num_v0, nx=nx, spx=spx))
@@ -486,13 +515,14 @@
     def get_mos_tap_info(self, row_info: MOSRowInfo, conn_layer: int, seg: int,
                          options: Param) -> MOSLayInfo:
         assert conn_layer == 1, 'currently only work for conn_layer = 1'
-
+        #print(row_info)
         row_type = row_info.row_type
 
         guard_ring: bool = options.get('guard_ring', row_info.guard_ring)
         if guard_ring:
             sub_type: MOSType = options.get('sub_type', row_type.sub_type)
         else:
+            #print(row_type.sub_type)
             sub_type: MOSType = row_type.sub_type
 
         sd_pitch = self.sd_pitch
@@ -504,21 +534,29 @@
 
         # draw device
         builder = LayoutInfoBuilder()
+        #draws diffusion and tap
+        #if (row_type is MOSType.nch):
         od_y = self._add_mos_active(builder, row_info, 0, seg, w, is_sub=True)
-
+        #print(row_info)
+        #else:
+        #    od_y = (193, 303)
         # draw drain/source connections
         d0_info = self.get_conn_info(0, False)
         d1_info = self.get_conn_info(1, False)
         md_yl, md_yh, num_vc = self._get_conn_params(d0_info, od_y[0], od_y[1])
         num_v0 = self._get_conn_params(d1_info, md_yl, md_yh)[2]
         md_y = (md_yl, md_yh)
+
+        #draws in vias connecting tap cell to metal 1
         self._draw_ds_conn(builder, d0_info, d1_info, od_y, md_y, num_vc, num_v0,
                            0, seg + 1, sd_pitch)
 
         # draw base
-        bbox = BBox(0, 0, seg * sd_pitch, height)
-        add_base(builder, sub_type, threshold, imp_y, bbox)
-
+        # add extra imp)od_encx for ntap and ptap
+        imp_od_encx: int = self.mos_config['imp_od_encx']
+        bbox = BBox(0-2*imp_od_encx, 0, seg * sd_pitch + 2*imp_od_encx, height)
+        add_base_mos(builder, sub_type, threshold, imp_y, bbox, is_sub=True)
+        
         edge_info = MOSEdgeInfo(mos_type=sub_type, imp_y=imp_y, has_od=True)
         be = BlkExtInfo(row_type, row_info.threshold, guard_ring, ImmutableList([(seg, sub_type)]),
                         ImmutableSortedDict())
@@ -760,7 +798,15 @@
         # draw base
         imp_od_encx: int = self.mos_config['imp_od_encx']
         bbox = BBox(od_xl-imp_od_encx, 0, od_xh+imp_od_encx, row_info.height)
-        add_base(builder, row_info.row_type, row_info.threshold, row_info['imp_y'], bbox)
+        
+        #if drawing tap cells, flip the implant type so its opposite of row
+        if is_sub:
+            if (row_info.row_type is MOSType.nch):
+                add_base_mos(builder, MOSType.pch, row_info.threshold, row_info['imp_y'], bbox, is_sub=True)
+            elif (row_info.row_type is MOSType.pch):
+                add_base_mos(builder, MOSType.nch, row_info.threshold, row_info['imp_y'], bbox, is_sub=True)
+        else:    
+            add_base_mos(builder, row_info.row_type, row_info.threshold, row_info['imp_y'], bbox)
 
         return od_yl, od_yh
 
@@ -831,4 +877,3 @@
         xcur = xh
 
     return xcur
-
diff --git a/src/templates_skywater130/tech.py b/src/templates_skywater130/tech.py
index 14a7c9a..8f7d3d0 100644
--- a/src/templates_skywater130/tech.py
+++ b/src/templates_skywater130/tech.py
@@ -21,10 +21,8 @@
 #
 # SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
 
-
 from typing import Tuple, Optional, Mapping
 
-
 from pybag.core import BBox
 
 from bag.util.immutable import Param
diff --git a/src/templates_skywater130/util.py b/src/templates_skywater130/util.py
index e19eb02..39e0e6d 100644
--- a/src/templates_skywater130/util.py
+++ b/src/templates_skywater130/util.py
@@ -21,10 +21,8 @@
 #
 # SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
 
-
 from typing import Optional, Tuple
 
-
 from pybag.core import BBox
 
 from xbase.layout.enum import MOSType
@@ -33,6 +31,10 @@
 
 def add_base(builder: LayoutInfoBuilder, row_type: MOSType, threshold: str, imp_y: Tuple[int, int],
              rect: BBox, well_x: Optional[Tuple[int, int]] = None) -> None:
+    # draws nwell, n+ implant (ndsm) and p+ implant (pdsm)
+    # for non mos devices (corners, edges, etc)
+
+    pimp_lp = ('psdm', 'drawing')
     if rect.is_physical():
         if not row_type.is_pwell:
             well_lp = ('nwell', 'drawing')
@@ -40,18 +42,36 @@
                 builder.add_rect_arr(well_lp, rect)
             else:
                 builder.add_rect_arr(well_lp, BBox(well_x[0], rect.yl, well_x[1], rect.yh))
+            
+        thres_lp = _get_thres_lp(row_type, threshold)
+        if thres_lp[0] != '':
+            builder.add_rect_arr(thres_lp, rect)
+    
+def add_base_mos(builder: LayoutInfoBuilder, row_type: MOSType, threshold: str, imp_y: Tuple[int, int],
+             rect: BBox, well_x: Optional[Tuple[int, int]] = None, is_sub: bool = False) -> None:
+    # new func draws nwell, n+ implant (ndsm) and p+ implant (pdsm)
+    
+    pimp_lp = ('psdm', 'drawing')
 
-        if row_type.is_n_plus:
-            builder.add_rect_arr(('nsdm', 'drawing'), rect)
-        else:
-            pimp_lp = ('psdm', 'drawing')
-            nimp_lp = ('nsdm', 'drawing')
-            if rect.yl < imp_y[0]:
-                builder.add_rect_arr(nimp_lp, BBox(rect.xl, rect.yl, rect.xh, imp_y[0]))
-            if imp_y[1] < rect.yh:
-                builder.add_rect_arr(nimp_lp, BBox(rect.xl, imp_y[1], rect.xh, rect.yh))
-            if imp_y[0] < imp_y[1]:
-                builder.add_rect_arr(pimp_lp, BBox(rect.xl, imp_y[0], rect.xh, imp_y[1]))
+    if rect.is_physical():
+        # only draw nwells if not a tap cell and pch, or is tap cell and nch
+        if ((not row_type.is_pwell) and (not is_sub)) \
+                or (is_sub and (row_type is MOSType.nch or row_type is MOSType.ntap) ):
+            well_lp = ('nwell', 'drawing')
+            if well_x is None:
+                builder.add_rect_arr(well_lp, rect)
+            else:
+                builder.add_rect_arr(well_lp, BBox(well_x[0], rect.yl, well_x[1], rect.yh))
+            
+        #draw the respective implant called    
+        if (row_type is MOSType.nch):
+            builder.add_rect_arr(('nsdm', 'drawing'),  BBox(rect.xl, imp_y[0], rect.xh, imp_y[1]))
+        elif (row_type is MOSType.pch):
+            builder.add_rect_arr(('psdm', 'drawing'),  BBox(rect.xl, imp_y[0], rect.xh, imp_y[1]))
+        elif (row_type is MOSType.ntap):
+            builder.add_rect_arr(('nsdm', 'drawing'),  BBox(rect.xl, imp_y[0], rect.xh, imp_y[1]))
+        elif (row_type is MOSType.ptap):
+            builder.add_rect_arr(('psdm', 'drawing'),  BBox(rect.xl, imp_y[0], rect.xh, imp_y[1]))
 
         thres_lp = _get_thres_lp(row_type, threshold)
         if thres_lp[0] != '':
diff --git a/workspace_setup/.bashrc b/workspace_setup/.bashrc
index 7a214e8..4102773 100644
--- a/workspace_setup/.bashrc
+++ b/workspace_setup/.bashrc
@@ -72,4 +72,3 @@
 # clear out PYTHONPATH
 export PYTHONPATH=""
 export PYTHONPATH_CUSTOM=${SRR_HOME}/tools/srrpython
-
diff --git a/workspace_setup/.cdsinit b/workspace_setup/.cdsinit
index 26d34a2..b1b929b 100644
--- a/workspace_setup/.cdsinit
+++ b/workspace_setup/.cdsinit
@@ -137,12 +137,13 @@
 ;; Set Default Model Files.  Note the "#;" de-selects the model call.
 
 setModelFiles=strcat(
-   " " getShellEnvVar("PDK_HOME") "MODELS/SPECTRE" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;tt_fet"
-   " " getShellEnvVar("PDK_HOME") "MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;tt_cell"
-   " " getShellEnvVar("PDK_HOME") "MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;tt_parRC"
-   " " getShellEnvVar("PDK_HOME") "MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;tt_rc"
-   " " getShellEnvVar("PDK_HOME") "MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;npn_t"
+   " " getShellEnvVar("PDK_HOME") "/MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;tt_fet"
+   " " getShellEnvVar("PDK_HOME") "/MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;tt_cell"
+   " " getShellEnvVar("PDK_HOME") "/MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;tt_parRC"
+   " " getShellEnvVar("PDK_HOME") "/MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;tt_rc"
+   " " getShellEnvVar("PDK_HOME") "/MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;npn_t"
 )
+
 envSetVal("spectre.envOpts" "modelFiles" 'string setModelFiles)
 envSetVal("spectre.envOpts" "controlMode" 'string "batch")
 
diff --git a/workspace_setup/bag_config.yaml b/workspace_setup/bag_config.yaml
index 4b24bce..95c1450 100644
--- a/workspace_setup/bag_config.yaml
+++ b/workspace_setup/bag_config.yaml
@@ -104,16 +104,19 @@
   # python class that talks with the simulator
   class: "bag.simulation.spectre.SpectreInterface"
   # maximum number of processes BAG can launch.
-  max_workers: 6
+  max_workers: 8
   # when simulation goes long, a reminder message will be printed at this interval
   update_timeout_ms: 120000
   # amount of time to wait for process cancellation to succeed.
   cancel_timeout_ms: 10000
+  # True to show interactive log viewer.
+  show_log_viewer: True
   # corner configuration file
   env_file: "${BAG_TECH_CONFIG_DIR}/corners_setup.yaml"
   # command settings
   kwargs:
     # the command to start
+    #command: "bsub -q bora -o $BAG_WORK_DIR/tmp -K spectre"
     command: spectre
     # environment variables.  Null for same environment as SkillOceanServer.
     env: !!null
@@ -123,7 +126,7 @@
     format: psfxl
     # psf version
     psfversion: '1.1'
-    options: ['++aps', '+lqtimeout', '0', '+mt=1', '+mp=1', '+postlayout', '+rcnet_fmax=25']
+    options: ['++aps', '+lqtimeout', '0', '+mt=8', '+mp=8', '+postlayout', '+rcnet_fmax=25']
   compress: True
   rtol: 1.0e-8
   atol: 1.0e-22
diff --git a/workspace_setup/bag_submodules.yaml b/workspace_setup/bag_submodules.yaml
index 4251600..fcc0320 100644
--- a/workspace_setup/bag_submodules.yaml
+++ b/workspace_setup/bag_submodules.yaml
@@ -30,3 +30,4 @@
 xbase_bcad:
   url: https://github.com/bluecheetah/xbase.git
   branch: master
+
diff --git a/workspace_setup/ipython_config.py b/workspace_setup/ipython_config.py
index 810c641..a4a9cfb 100644
--- a/workspace_setup/ipython_config.py
+++ b/workspace_setup/ipython_config.py
@@ -31,13 +31,13 @@
 #------------------------------------------------------------------------------
 
 ## A Mixin for applications that start InteractiveShell instances.
-#
+#  
 #  Provides configurables for loading extensions and executing files as part of
 #  configuring a Shell environment.
-#
+#  
 #  The following methods should be called by the :meth:`initialize` method of the
 #  subclass:
-#
+#  
 #    - :meth:`init_path`
 #    - :meth:`init_shell` (to be implemented by the subclass)
 #    - :meth:`init_gui_pylab`
@@ -91,7 +91,7 @@
 
 ## If true, IPython will populate the user namespace with numpy, pylab, etc. and
 #  an ``import *`` is done from numpy and pylab, when using pylab mode.
-#
+#  
 #  When False, pylab mode should not import any names into the user namespace.
 #c.InteractiveShellApp.pylab_import_all = True
 
@@ -129,7 +129,7 @@
 #c.BaseIPythonApplication.copy_config_files = False
 
 ## Path to an extra config file to load.
-#
+#  
 #  If specified, load this config file in addition to any other IPython config.
 #c.BaseIPythonApplication.extra_config_file = u''
 
@@ -213,13 +213,13 @@
 ## Set the color scheme (NoColor, Neutral, Linux, or LightBG).
 c.InteractiveShell.colors = 'Linux'
 
-##
+## 
 #c.InteractiveShell.debug = False
 
 ## **Deprecated**
-#
+#  
 #  Will be removed in IPython 6.0
-#
+#  
 #  Enable deep (recursive) reloading by default. IPython can use the deep_reload
 #  module which reloads changes in modules recursively (it replaces the reload()
 #  function, so you don't need to change anything to use it). `deep_reload`
@@ -245,7 +245,7 @@
 #  startup.
 #c.InteractiveShell.history_load_length = 1000
 
-##
+## 
 #c.InteractiveShell.ipython_dir = ''
 
 ## Start logging to the given file in append mode. Use `logfile` to specify a log
@@ -259,7 +259,7 @@
 #  specify a log file to **append** logs to.
 #c.InteractiveShell.logstart = False
 
-##
+## 
 #c.InteractiveShell.object_info_string_level = 0
 
 ## Automatically call the pdb debugger after every exception.
@@ -281,16 +281,16 @@
 #  TerminalInteractiveShell.prompts object directly.
 #c.InteractiveShell.prompts_pad_left = True
 
-##
+## 
 #c.InteractiveShell.quiet = False
 
-##
+## 
 #c.InteractiveShell.separate_in = '\n'
 
-##
+## 
 #c.InteractiveShell.separate_out = ''
 
-##
+## 
 #c.InteractiveShell.separate_out2 = ''
 
 ## Show rewritten input, e.g. for autocall.
@@ -300,10 +300,10 @@
 #  module).
 #c.InteractiveShell.sphinxify_docstring = False
 
-##
+## 
 #c.InteractiveShell.wildcards_case_sensitive = True
 
-##
+## 
 #c.InteractiveShell.xmode = 'Context'
 
 #------------------------------------------------------------------------------
@@ -346,11 +346,11 @@
 
 ## Use `raw_input` for the REPL, without completion, multiline input, and prompt
 #  colors.
-#
+#  
 #  Useful when controlling IPython as a subprocess, and piping STDIN/OUT/ERR.
 #  Known usage are: IPython own testing machinery, and emacs inferior-shell
 #  integration through elpy.
-#
+#  
 #  This mode default to `True` if the `IPY_TEST_SIMPLE_PROMPT` environment
 #  variable is set, or the current terminal is not a tty.
 #c.TerminalInteractiveShell.simple_prompt = False
@@ -371,35 +371,35 @@
 #------------------------------------------------------------------------------
 
 ## Access the history database without adding to it.
-#
+#  
 #  This is intended for use by standalone history tools. IPython shells use
 #  HistoryManager, below, which is a subclass of this.
 
 ## Options for configuring the SQLite connection
-#
+#  
 #  These options are passed as keyword args to sqlite3.connect when establishing
 #  database conenctions.
 #c.HistoryAccessor.connection_options = {}
 
 ## enable the SQLite history
-#
+#  
 #  set enabled=False to disable the SQLite history, in which case there will be
 #  no stored history, no SQLite connection, and no background saving thread.
 #  This may be necessary in some threaded environments where IPython is embedded.
 #c.HistoryAccessor.enabled = True
 
 ## Path to file to use for SQLite history database.
-#
+#  
 #  By default, IPython will put the history database in the IPython profile
 #  directory.  If you would rather share one history among profiles, you can set
 #  this value in each, so that they are consistent.
-#
+#  
 #  Due to an issue with fcntl, SQLite is known to misbehave on some NFS mounts.
 #  If you see IPython hanging, try setting this to something on a local disk,
 #  e.g::
-#
+#  
 #      ipython --HistoryManager.hist_file=/tmp/ipython_hist.sqlite
-#
+#  
 #  you can also use the specific value `:memory:` (including the colon at both
 #  end but not the back ticks), to avoid creating an history file.
 #c.HistoryAccessor.hist_file = u''
@@ -422,10 +422,10 @@
 #------------------------------------------------------------------------------
 
 ## An object to manage the profile directory and its resources.
-#
+#  
 #  The profile directory is used by all IPython applications, to manage
 #  configuration, logging and security.
-#
+#  
 #  This object knows how to find, create and manage these directories. This
 #  should be used by any code that wants to handle profiles.
 
@@ -438,37 +438,37 @@
 #------------------------------------------------------------------------------
 
 ## A base formatter class that is configurable.
-#
+#  
 #  This formatter should usually be used as the base class of all formatters. It
 #  is a traited :class:`Configurable` class and includes an extensible API for
 #  users to determine how their objects are formatted. The following logic is
 #  used to find a function to format an given object.
-#
+#  
 #  1. The object is introspected to see if it has a method with the name
 #     :attr:`print_method`. If is does, that object is passed to that method
 #     for formatting.
 #  2. If no print method is found, three internal dictionaries are consulted
 #     to find print method: :attr:`singleton_printers`, :attr:`type_printers`
 #     and :attr:`deferred_printers`.
-#
+#  
 #  Users should use these dictionaries to register functions that will be used to
 #  compute the format data for their objects (if those objects don't have the
 #  special print methods). The easiest way of using these dictionaries is through
 #  the :meth:`for_type` and :meth:`for_type_by_name` methods.
-#
+#  
 #  If no function/callable is found to compute the format data, ``None`` is
 #  returned and this format type is not used.
 
-##
+## 
 #c.BaseFormatter.deferred_printers = {}
 
-##
+## 
 #c.BaseFormatter.enabled = True
 
-##
+## 
 #c.BaseFormatter.singleton_printers = {}
 
-##
+## 
 #c.BaseFormatter.type_printers = {}
 
 #------------------------------------------------------------------------------
@@ -476,12 +476,12 @@
 #------------------------------------------------------------------------------
 
 ## The default pretty-printer.
-#
+#  
 #  This uses :mod:`IPython.lib.pretty` to compute the format data of the object.
 #  If the object cannot be pretty printed, :func:`repr` is used. See the
 #  documentation of :mod:`IPython.lib.pretty` for details on how to write pretty
 #  printers.  Here is a simple example::
-#
+#  
 #      def dtype_pprinter(obj, p, cycle):
 #          if cycle:
 #              return p.text('dtype(...)')
@@ -497,24 +497,24 @@
 #                      p.pretty(field)
 #                  p.end_group(7, '])')
 
-##
+## 
 #c.PlainTextFormatter.float_precision = ''
 
 ## Truncate large collections (lists, dicts, tuples, sets) to this size.
-#
+#  
 #  Set to 0 to disable truncation.
 #c.PlainTextFormatter.max_seq_length = 1000
 
-##
+## 
 #c.PlainTextFormatter.max_width = 79
 
-##
+## 
 #c.PlainTextFormatter.newline = '\n'
 
-##
+## 
 #c.PlainTextFormatter.pprint = True
 
-##
+## 
 #c.PlainTextFormatter.verbose = False
 
 #------------------------------------------------------------------------------
@@ -523,7 +523,7 @@
 
 ## Activate greedy completion PENDING DEPRECTION. this is now mostly taken care
 #  of with Jedi.
-#
+#  
 #  This will enable completion on elements of lists, results of function calls,
 #  etc., but can be unsafe because the code is actually evaluated on TAB.
 #c.Completer.greedy = False
@@ -535,30 +535,30 @@
 ## Extension of the completer class with IPython-specific features
 
 ## DEPRECATED as of version 5.0.
-#
+#  
 #  Instruct the completer to use __all__ for the completion
-#
+#  
 #  Specifically, when completing on ``object.<tab>``.
-#
+#  
 #  When True: only those names in obj.__all__ will be included.
-#
+#  
 #  When False [default]: the __all__ attribute is ignored
 #c.IPCompleter.limit_to__all__ = False
 
 ## Whether to merge completion results into a single list
-#
+#  
 #  If False, only the completion results from the first non-empty completer will
 #  be returned.
 #c.IPCompleter.merge_completions = True
 
 ## Instruct the completer to omit private method names
-#
+#  
 #  Specifically, when completing on ``object.<tab>``.
-#
+#  
 #  When 2 [default]: all names that start with '_' will be excluded.
-#
+#  
 #  When 1: all 'magic' names (``__foo__``) will be excluded.
-#
+#  
 #  When 0: nothing will be excluded.
 #c.IPCompleter.omit__names = 2
 
@@ -567,21 +567,21 @@
 #------------------------------------------------------------------------------
 
 ## Magics for talking to scripts
-#
+#  
 #  This defines a base `%%script` cell magic for running a cell with a program in
 #  a subprocess, and registers a few top-level magics that call %%script with
 #  common interpreters.
 
 ## Extra script cell magics to define
-#
+#  
 #  This generates simple wrappers of `%%script foo` as `%%foo`.
-#
+#  
 #  If you want to add script magics that aren't on your path, specify them in
 #  script_paths
 #c.ScriptMagics.script_magics = []
 
 ## Dict mapping short 'ruby' names to full paths, such as '/opt/secret/bin/ruby'
-#
+#  
 #  Only necessary for items in script_magics where the default path will not find
 #  the right interpreter.
 #c.ScriptMagics.script_paths = {}
@@ -591,7 +591,7 @@
 #------------------------------------------------------------------------------
 
 ## Lightweight persistence for python variables.
-#
+#  
 #  Provides the %store magic.
 
 ## If True, any %store-d variables will be automatically restored when IPython
diff --git a/workspace_setup/leBindKeys.il b/workspace_setup/leBindKeys.il
index 7e513d6..e3cf06c 100644
--- a/workspace_setup/leBindKeys.il
+++ b/workspace_setup/leBindKeys.il
@@ -95,7 +95,6 @@
             sprintf(via_name "via%d" bot_layer)
         )
 	    sprintf(top_name "met%d" bot_layer + 1)
-
         leSetEntryLayer(list(bot_name "drawing"))
         leSetAllLayerVisible(nil)
         leSetLayerVisible(list(bot_name "drawing") t)
diff --git a/workspace_setup/tutorial_files/bootcamp_pics/1_flow_demo/flow_demo_1.png b/workspace_setup/tutorial_files/bootcamp_pics/1_flow_demo/flow_demo_1.png
index 141301d..16b9fc2 100644
--- a/workspace_setup/tutorial_files/bootcamp_pics/1_flow_demo/flow_demo_1.png
+++ b/workspace_setup/tutorial_files/bootcamp_pics/1_flow_demo/flow_demo_1.png
Binary files differ
diff --git a/workspace_setup/tutorial_files/bootcamp_pics/1_flow_demo/flow_demo_2.png b/workspace_setup/tutorial_files/bootcamp_pics/1_flow_demo/flow_demo_2.png
index 60d7b07..8463792 100644
--- a/workspace_setup/tutorial_files/bootcamp_pics/1_flow_demo/flow_demo_2.png
+++ b/workspace_setup/tutorial_files/bootcamp_pics/1_flow_demo/flow_demo_2.png
Binary files differ
diff --git a/workspace_setup/tutorial_files/bootcamp_pics/1_flow_demo/flow_demo_3.png b/workspace_setup/tutorial_files/bootcamp_pics/1_flow_demo/flow_demo_3.png
index 67d0ad8..dcc3e72 100644
--- a/workspace_setup/tutorial_files/bootcamp_pics/1_flow_demo/flow_demo_3.png
+++ b/workspace_setup/tutorial_files/bootcamp_pics/1_flow_demo/flow_demo_3.png
Binary files differ
diff --git a/workspace_setup/tutorial_files/bootcamp_pics/1_flow_demo/flow_demo_4.png b/workspace_setup/tutorial_files/bootcamp_pics/1_flow_demo/flow_demo_4.png
index 5241aec..18bff8b 100644
--- a/workspace_setup/tutorial_files/bootcamp_pics/1_flow_demo/flow_demo_4.png
+++ b/workspace_setup/tutorial_files/bootcamp_pics/1_flow_demo/flow_demo_4.png
Binary files differ
diff --git a/workspace_setup/tutorial_files/bootcamp_pics/2_xbase_routing/xbase_routing_1.png b/workspace_setup/tutorial_files/bootcamp_pics/2_xbase_routing/xbase_routing_1.png
index 93a806c..96f98a9 100644
--- a/workspace_setup/tutorial_files/bootcamp_pics/2_xbase_routing/xbase_routing_1.png
+++ b/workspace_setup/tutorial_files/bootcamp_pics/2_xbase_routing/xbase_routing_1.png
Binary files differ
diff --git a/workspace_setup/tutorial_files/bootcamp_pics/2_xbase_routing/xbase_routing_2.png b/workspace_setup/tutorial_files/bootcamp_pics/2_xbase_routing/xbase_routing_2.png
index a81d9ee..a3d7aa4 100644
--- a/workspace_setup/tutorial_files/bootcamp_pics/2_xbase_routing/xbase_routing_2.png
+++ b/workspace_setup/tutorial_files/bootcamp_pics/2_xbase_routing/xbase_routing_2.png
Binary files differ
diff --git a/workspace_setup/tutorial_files/bootcamp_pics/2_xbase_routing/xbase_routing_3.png b/workspace_setup/tutorial_files/bootcamp_pics/2_xbase_routing/xbase_routing_3.png
index a86bc69..9b7ab1e 100644
--- a/workspace_setup/tutorial_files/bootcamp_pics/2_xbase_routing/xbase_routing_3.png
+++ b/workspace_setup/tutorial_files/bootcamp_pics/2_xbase_routing/xbase_routing_3.png
Binary files differ
diff --git a/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_1.png b/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_1.png
index 2189ce8..97129cc 100644
--- a/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_1.png
+++ b/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_1.png
Binary files differ
diff --git a/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_2.png b/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_2.png
index ba44bdf..dc55bab 100644
--- a/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_2.png
+++ b/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_2.png
Binary files differ
diff --git a/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_3.png b/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_3.png
index e631931..3dfec20 100644
--- a/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_3.png
+++ b/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_3.png
Binary files differ
diff --git a/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_4.png b/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_4.png
index 70915f1..0cc6b6b 100644
--- a/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_4.png
+++ b/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_4.png
Binary files differ
diff --git a/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_5.png b/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_5.png
index 5d6a72c..db7654d 100644
--- a/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_5.png
+++ b/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_5.png
Binary files differ
diff --git a/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_6.png b/workspace_setup/tutorial_files/bootcamp_pics/3_analogbase/analogbase_6.png
index e123f96..eeecb60 100644
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