merging implant changes
diff --git a/.idea/skywater130.iml b/.idea/skywater130.iml index c646a1f..4c55d75 100644 --- a/.idea/skywater130.iml +++ b/.idea/skywater130.iml
@@ -1,25 +1,4 @@ <?xml version="1.0" encoding="UTF-8"?> -<!-- -Copyright 2019-2021 SkyWater PDK Authors - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - https://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -This code is *alternatively* available under a BSD-3-Clause license, see -details in the README.md at the top level and the license text at -https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative - -SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 ---> <module type="PYTHON_MODULE" version="4"> <component name="NewModuleRootManager"> <content url="file://$MODULE_DIR$">
diff --git a/OA/BAG_prim/.oalib b/OA/BAG_prim/.oalib index 0859910..21ffef8 100644 --- a/OA/BAG_prim/.oalib +++ b/OA/BAG_prim/.oalib
@@ -1,25 +1,5 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!-- -Copyright 2019-2021 SkyWater PDK Authors +<?xml version="1.0"?> -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - https://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -This code is *alternatively* available under a BSD-3-Clause license, see -details in the README.md at the top level and the license text at -https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative - -SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 ---> <Library DMSystem="oaDMFileSys"> <oaDMFileSys libReadOnly="No" origFileSystem="Unix"/>
diff --git a/OA/BAG_prim/cdsinfo.tag b/OA/BAG_prim/cdsinfo.tag index 4b46185..b75aa95 100644 --- a/OA/BAG_prim/cdsinfo.tag +++ b/OA/BAG_prim/cdsinfo.tag
@@ -1,22 +1,11 @@ -# Copyright 2019-2021 SkyWater PDK Authors # -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at +# This is a cdsinfo.tag file. # -# https://www.apache.org/licenses/LICENSE-2.0 +# See the "Cadence Application Infrastructure Reference Manual" for +# details on the format of this file, its semantics, and its use. # -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# This code is *alternatively* available under a BSD-3-Clause license, see -# details in the README.md at the top level and the license text at -# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative -# -# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 +# The `#' character denotes a comment. Removing the leading `#' +# character from any of the entries below will activate them. # # CDSLIBRARY entry - add this entry if the directory containing # this cdsinfo.tag file is the root of a Cadence library. @@ -46,6 +35,7 @@ # use and behaviour of these entries when appropriate. # # Current Settings: +# CDSLIBRARY DMTYPE none NAMESPACE LibraryUnix
diff --git a/OA/BAG_prim/nmos4_hv/schematic/thumbnail_128x128.png b/OA/BAG_prim/nmos4_hv/schematic/thumbnail_128x128.png index 601157b..1d46566 100644 --- a/OA/BAG_prim/nmos4_hv/schematic/thumbnail_128x128.png +++ b/OA/BAG_prim/nmos4_hv/schematic/thumbnail_128x128.png Binary files differ
diff --git a/OA/BAG_prim/nmos4_hv/symbol/thumbnail_128x128.png b/OA/BAG_prim/nmos4_hv/symbol/thumbnail_128x128.png index 8cb67e4..7c02f60 100644 --- a/OA/BAG_prim/nmos4_hv/symbol/thumbnail_128x128.png +++ b/OA/BAG_prim/nmos4_hv/symbol/thumbnail_128x128.png Binary files differ
diff --git a/OA/BAG_prim/nmos4_hvesd/schematic/thumbnail_128x128.png b/OA/BAG_prim/nmos4_hvesd/schematic/thumbnail_128x128.png index 591c6b8..313567e 100644 --- a/OA/BAG_prim/nmos4_hvesd/schematic/thumbnail_128x128.png +++ b/OA/BAG_prim/nmos4_hvesd/schematic/thumbnail_128x128.png Binary files differ
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diff --git a/OA/BAG_prim/nmos4_lvt/schematic/thumbnail_128x128.png b/OA/BAG_prim/nmos4_lvt/schematic/thumbnail_128x128.png index ee192cb..fc6a857 100644 --- a/OA/BAG_prim/nmos4_lvt/schematic/thumbnail_128x128.png +++ b/OA/BAG_prim/nmos4_lvt/schematic/thumbnail_128x128.png Binary files differ
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diff --git a/OA/BAG_prim/nmos4_standard/schematic/thumbnail_128x128.png b/OA/BAG_prim/nmos4_standard/schematic/thumbnail_128x128.png index ee192cb..fc6a857 100644 --- a/OA/BAG_prim/nmos4_standard/schematic/thumbnail_128x128.png +++ b/OA/BAG_prim/nmos4_standard/schematic/thumbnail_128x128.png Binary files differ
diff --git a/OA/BAG_prim/nmos4_standard/symbol/thumbnail_128x128.png b/OA/BAG_prim/nmos4_standard/symbol/thumbnail_128x128.png index 8cb67e4..7c02f60 100644 --- a/OA/BAG_prim/nmos4_standard/symbol/thumbnail_128x128.png +++ b/OA/BAG_prim/nmos4_standard/symbol/thumbnail_128x128.png Binary files differ
diff --git a/OA/BAG_prim/nmos4_svt/schematic/thumbnail_128x128.png b/OA/BAG_prim/nmos4_svt/schematic/thumbnail_128x128.png index ee192cb..fc6a857 100644 --- a/OA/BAG_prim/nmos4_svt/schematic/thumbnail_128x128.png +++ b/OA/BAG_prim/nmos4_svt/schematic/thumbnail_128x128.png Binary files differ
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diff --git a/OA/BAG_prim/pmos4_hv/schematic/thumbnail_128x128.png b/OA/BAG_prim/pmos4_hv/schematic/thumbnail_128x128.png index c04b5b1..e5b4335 100644 --- a/OA/BAG_prim/pmos4_hv/schematic/thumbnail_128x128.png +++ b/OA/BAG_prim/pmos4_hv/schematic/thumbnail_128x128.png Binary files differ
diff --git a/OA/BAG_prim/pmos4_hv/symbol/thumbnail_128x128.png b/OA/BAG_prim/pmos4_hv/symbol/thumbnail_128x128.png index 2a160dc..d44f020 100644 --- a/OA/BAG_prim/pmos4_hv/symbol/thumbnail_128x128.png +++ b/OA/BAG_prim/pmos4_hv/symbol/thumbnail_128x128.png Binary files differ
diff --git a/OA/BAG_prim/pmos4_hvesd/schematic/thumbnail_128x128.png b/OA/BAG_prim/pmos4_hvesd/schematic/thumbnail_128x128.png index 2058778..7e0aa55 100644 --- a/OA/BAG_prim/pmos4_hvesd/schematic/thumbnail_128x128.png +++ b/OA/BAG_prim/pmos4_hvesd/schematic/thumbnail_128x128.png Binary files differ
diff --git a/OA/BAG_prim/pmos4_hvesd/symbol/thumbnail_128x128.png b/OA/BAG_prim/pmos4_hvesd/symbol/thumbnail_128x128.png index 2a160dc..d44f020 100644 --- a/OA/BAG_prim/pmos4_hvesd/symbol/thumbnail_128x128.png +++ b/OA/BAG_prim/pmos4_hvesd/symbol/thumbnail_128x128.png Binary files differ
diff --git a/OA/BAG_prim/pmos4_hvt/schematic/thumbnail_128x128.png b/OA/BAG_prim/pmos4_hvt/schematic/thumbnail_128x128.png index 60476ed..90982fd 100644 --- a/OA/BAG_prim/pmos4_hvt/schematic/thumbnail_128x128.png +++ b/OA/BAG_prim/pmos4_hvt/schematic/thumbnail_128x128.png Binary files differ
diff --git a/OA/BAG_prim/pmos4_hvt/symbol/thumbnail_128x128.png b/OA/BAG_prim/pmos4_hvt/symbol/thumbnail_128x128.png index 2a160dc..d44f020 100644 --- a/OA/BAG_prim/pmos4_hvt/symbol/thumbnail_128x128.png +++ b/OA/BAG_prim/pmos4_hvt/symbol/thumbnail_128x128.png Binary files differ
diff --git a/OA/BAG_prim/pmos4_lvt/schematic/thumbnail_128x128.png b/OA/BAG_prim/pmos4_lvt/schematic/thumbnail_128x128.png index f4f08ae..18ef0a2 100644 --- a/OA/BAG_prim/pmos4_lvt/schematic/thumbnail_128x128.png +++ b/OA/BAG_prim/pmos4_lvt/schematic/thumbnail_128x128.png Binary files differ
diff --git a/OA/BAG_prim/pmos4_lvt/symbol/thumbnail_128x128.png b/OA/BAG_prim/pmos4_lvt/symbol/thumbnail_128x128.png index 2a160dc..d44f020 100644 --- a/OA/BAG_prim/pmos4_lvt/symbol/thumbnail_128x128.png +++ b/OA/BAG_prim/pmos4_lvt/symbol/thumbnail_128x128.png Binary files differ
diff --git a/OA/BAG_prim/pmos4_standard/schematic/thumbnail_128x128.png b/OA/BAG_prim/pmos4_standard/schematic/thumbnail_128x128.png index 4cb36e1..d96f8b1 100644 --- a/OA/BAG_prim/pmos4_standard/schematic/thumbnail_128x128.png +++ b/OA/BAG_prim/pmos4_standard/schematic/thumbnail_128x128.png Binary files differ
diff --git a/OA/BAG_prim/pmos4_standard/symbol/thumbnail_128x128.png b/OA/BAG_prim/pmos4_standard/symbol/thumbnail_128x128.png index 2a160dc..d44f020 100644 --- a/OA/BAG_prim/pmos4_standard/symbol/thumbnail_128x128.png +++ b/OA/BAG_prim/pmos4_standard/symbol/thumbnail_128x128.png Binary files differ
diff --git a/OA/BAG_prim/pmos4_svt/schematic/thumbnail_128x128.png b/OA/BAG_prim/pmos4_svt/schematic/thumbnail_128x128.png index 4cb36e1..d96f8b1 100644 --- a/OA/BAG_prim/pmos4_svt/schematic/thumbnail_128x128.png +++ b/OA/BAG_prim/pmos4_svt/schematic/thumbnail_128x128.png Binary files differ
diff --git a/OA/BAG_prim/pmos4_svt/symbol/thumbnail_128x128.png b/OA/BAG_prim/pmos4_svt/symbol/thumbnail_128x128.png index 2a160dc..d44f020 100644 --- a/OA/BAG_prim/pmos4_svt/symbol/thumbnail_128x128.png +++ b/OA/BAG_prim/pmos4_svt/symbol/thumbnail_128x128.png Binary files differ
diff --git a/calibre_setup/drc.runset b/calibre_setup/drc.runset index 05f6f1b..7908bef 100644 --- a/calibre_setup/drc.runset +++ b/calibre_setup/drc.runset
@@ -1,22 +1,3 @@ -// Copyright 2019-2021 SkyWater PDK Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// This code is *alternatively* available under a BSD-3-Clause license, see -// details in the README.md at the top level and the license text at -// https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative -// -// SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 *drcRulesFile: ${PDK_HOME}/DRC/Calibre/s8_drcRules *drcRunDir: ${BAG_WORK_DIR}/calibre_run/drc/myLib/myCell *drcLayoutPaths: myCell.calibre.db
diff --git a/calibre_setup/drc.svrf b/calibre_setup/drc.svrf index ec12374..f65cdad 100644 --- a/calibre_setup/drc.svrf +++ b/calibre_setup/drc.svrf
@@ -1,23 +1,3 @@ -// Copyright 2019-2021 SkyWater PDK Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// This code is *alternatively* available under a BSD-3-Clause license, see -// details in the README.md at the top level and the license text at -// https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative -// -// SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 - LAYOUT PATH "{{ layout_file }}" LAYOUT PRIMARY "{{ cell_name }}" LAYOUT SYSTEM {{layout_type}}
diff --git a/calibre_setup/lvs.runset b/calibre_setup/lvs.runset index aa56bfd..c1a94bf 100644 --- a/calibre_setup/lvs.runset +++ b/calibre_setup/lvs.runset
@@ -1,22 +1,3 @@ -// Copyright 2019-2021 SkyWater PDK Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// This code is *alternatively* available under a BSD-3-Clause license, see -// details in the README.md at the top level and the license text at -// https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative -// -// SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 *lvsRulesFile: ${PDK_HOME}/LVS/Calibre/lvs_s8_opts *lvsRunDir: ${BAG_WORK_DIR}/calibre_run/lvs/myLib/top_cell *lvsLayoutPaths: top_cell.calibre.db
diff --git a/calibre_setup/lvs.svrf b/calibre_setup/lvs.svrf index a10001c..73b3fff 100644 --- a/calibre_setup/lvs.svrf +++ b/calibre_setup/lvs.svrf
@@ -1,23 +1,3 @@ -// Copyright 2019-2021 SkyWater PDK Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// This code is *alternatively* available under a BSD-3-Clause license, see -// details in the README.md at the top level and the license text at -// https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative -// -// SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 - LAYOUT PATH "{{ layout_file }}" LAYOUT PRIMARY "{{ cell_name }}" LAYOUT SYSTEM {{layout_type}}
diff --git a/netlist_setup/bag_prim.scs b/netlist_setup/bag_prim.scs index 3ea4972..358feb1 100644 --- a/netlist_setup/bag_prim.scs +++ b/netlist_setup/bag_prim.scs
@@ -1,22 +1,3 @@ -// Copyright 2019-2021 SkyWater PDK Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// This code is *alternatively* available under a BSD-3-Clause license, see -// details in the README.md at the top level and the license text at -// https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative -// -// SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 subckt nmos4_hv B D G S parameters l w nf
diff --git a/netlist_setup/spectre_prim.scs b/netlist_setup/spectre_prim.scs index 8bcb34c..f8bde6b 100644 --- a/netlist_setup/spectre_prim.scs +++ b/netlist_setup/spectre_prim.scs
@@ -1,22 +1,3 @@ -// Copyright 2019-2021 SkyWater PDK Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// This code is *alternatively* available under a BSD-3-Clause license, see -// details in the README.md at the top level and the license text at -// https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative -// -// SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 simulator lang=spectre subckt ideal_balun d c p n
diff --git a/pcell_setup/gen_skill.py b/pcell_setup/gen_skill.py index 03b40c9..11b3a6f 100644 --- a/pcell_setup/gen_skill.py +++ b/pcell_setup/gen_skill.py
@@ -1,6 +1,9 @@ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# # Copyright 2019-2021 SkyWater PDK Authors # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,7 +27,6 @@ from jinja2 import Template - tech_lib = 's8phirs_10r' # mos_w_default = '0.42' # mos_l_default = '0.15'
diff --git a/pcell_setup/prim_pcell.il b/pcell_setup/prim_pcell.il index b6714db..58a6a59 100644 --- a/pcell_setup/prim_pcell.il +++ b/pcell_setup/prim_pcell.il
@@ -1,23 +1,3 @@ -;; Copyright 2019-2021 SkyWater PDK Authors -;; -;; Licensed under the Apache License, Version 2.0 (the "License"); -;; you may not use this file except in compliance with the License. -;; You may obtain a copy of the License at -;; -;; https://www.apache.org/licenses/LICENSE-2.0 -;; -;; Unless required by applicable law or agreed to in writing, software -;; distributed under the License is distributed on an "AS IS" BASIS, -;; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;; See the License for the specific language governing permissions and -;; limitations under the License. -;; -;; This code is *alternatively* available under a BSD-3-Clause license, see -;; details in the README.md at the top level and the license text at -;; https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative -;; -;; SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 - ;; This skill file compiles schematic PCells for BAG primitives lib_obj = ddGetObj("BAG_prim") @@ -26,21 +6,16 @@ ; nmos4_standard/nshort pcDefinePCell( list( lib_obj "nmos4_standard" "schematic" "schematic") - ((w string "0.42") - (l string "0.15") + ( (nf string "1") ) let((inst iopin_master io_net io_pin) - wval = atoi(w) nval = atoi(nf) inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "nfet" "symbol" "N0" -0.375:0 "R0" 1 list(list("hspiceModelMenu" "string" "nshort") - list("w" "string" w) - list("l" "string" l) list("m" "string" nf) - list("totalW" "string" sprintf(nil "%dn" wval * nval))) - ) + ) iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r") io_net = dbCreateNet(pcCellView "D") io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "D" -0.5:0.5625 "R0")
diff --git a/pcell_setup/prim_pcell_jinja2.il b/pcell_setup/prim_pcell_jinja2.il index 306db76..033bd50 100644 --- a/pcell_setup/prim_pcell_jinja2.il +++ b/pcell_setup/prim_pcell_jinja2.il
@@ -1,23 +1,3 @@ -;; Copyright 2019-2021 SkyWater PDK Authors -;; -;; Licensed under the Apache License, Version 2.0 (the "License"); -;; you may not use this file except in compliance with the License. -;; You may obtain a copy of the License at -;; -;; https://www.apache.org/licenses/LICENSE-2.0 -;; -;; Unless required by applicable law or agreed to in writing, software -;; distributed under the License is distributed on an "AS IS" BASIS, -;; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;; See the License for the specific language governing permissions and -;; limitations under the License. -;; -;; This code is *alternatively* available under a BSD-3-Clause license, see -;; details in the README.md at the top level and the license text at -;; https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative -;; -;; SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 - ;; This skill file compiles schematic PCells for BAG primitives lib_obj = ddGetObj("BAG_prim") @@ -26,20 +6,20 @@ ; {{ mtype }}_{{ threshold }}/{{ model_thres }} pcDefinePCell( list( lib_obj "{{ mtype }}_{{ threshold }}" "schematic" "schematic") - ((w string "{{ w_def }}") - (l string "{{ l_def }}") + (;(w string "{{ w_def }}") + ;(l string "{{ l_def }}") (nf string "1") ) let((inst iopin_master io_net io_pin) - wval = atoi(w) - nval = atoi(nf) + ;wval = atoi(w) + ;nval = atoi(nf) inst = dbCreateParamInstByMasterName( pcCellView "{{ tech_lib }}" "{{ model }}" "symbol" "N0" -0.375:0 "R0" 1 list(list("hspiceModelMenu" "string" "{{ model_thres }}") - list("w" "string" w) - list("l" "string" l) + ;list("w" "string" w) + ;list("l" "string" l) list("m" "string" nf) - list("totalW" "string" sprintf(nil "%dn" wval * nval))) + ;list("totalW" "string" sprintf(nil "%dn" wval * nval))) ) iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r") io_net = dbCreateNet(pcCellView "D")
diff --git a/src/BAG_prim/__init__.py b/src/BAG_prim/__init__.py index 7e4a026..0cebf6d 100644 --- a/src/BAG_prim/__init__.py +++ b/src/BAG_prim/__init__.py
@@ -1,6 +1,9 @@ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# # Copyright 2019-2021 SkyWater PDK Authors # # Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/src/BAG_prim/schematic/nmos4_hv.py b/src/BAG_prim/schematic/nmos4_hv.py index 75227ca..4edec61 100644 --- a/src/BAG_prim/schematic/nmos4_hv.py +++ b/src/BAG_prim/schematic/nmos4_hv.py
@@ -21,7 +21,6 @@ # # SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 - from typing import Any
diff --git a/src/BAG_prim/schematic/nmos4_hvesd.py b/src/BAG_prim/schematic/nmos4_hvesd.py index bbc9f14..fe7232a 100644 --- a/src/BAG_prim/schematic/nmos4_hvesd.py +++ b/src/BAG_prim/schematic/nmos4_hvesd.py
@@ -21,7 +21,6 @@ # # SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 - from typing import Any
diff --git a/src/BAG_prim/schematic/nmos4_lvt.py b/src/BAG_prim/schematic/nmos4_lvt.py index bedee15..7f37621 100644 --- a/src/BAG_prim/schematic/nmos4_lvt.py +++ b/src/BAG_prim/schematic/nmos4_lvt.py
@@ -21,7 +21,6 @@ # # SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 - from typing import Any
diff --git a/src/BAG_prim/schematic/nmos4_standard.py b/src/BAG_prim/schematic/nmos4_standard.py index 3ed932b..1b22bfe 100644 --- a/src/BAG_prim/schematic/nmos4_standard.py +++ b/src/BAG_prim/schematic/nmos4_standard.py
@@ -21,7 +21,6 @@ # # SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 - from typing import Any
diff --git a/src/BAG_prim/schematic/nmos4_svt.py b/src/BAG_prim/schematic/nmos4_svt.py index e174e82..fe11594 100644 --- a/src/BAG_prim/schematic/nmos4_svt.py +++ b/src/BAG_prim/schematic/nmos4_svt.py
@@ -21,7 +21,6 @@ # # SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 - from typing import Any
diff --git a/src/BAG_prim/schematic/pmos4_hv.py b/src/BAG_prim/schematic/pmos4_hv.py index 437df1a..2d97ea7 100644 --- a/src/BAG_prim/schematic/pmos4_hv.py +++ b/src/BAG_prim/schematic/pmos4_hv.py
@@ -21,7 +21,6 @@ # # SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 - from typing import Any
diff --git a/src/BAG_prim/schematic/pmos4_hvesd.py b/src/BAG_prim/schematic/pmos4_hvesd.py index 9a7da7b..9c8fc7c 100644 --- a/src/BAG_prim/schematic/pmos4_hvesd.py +++ b/src/BAG_prim/schematic/pmos4_hvesd.py
@@ -21,7 +21,6 @@ # # SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 - from typing import Any
diff --git a/src/BAG_prim/schematic/pmos4_hvt.py b/src/BAG_prim/schematic/pmos4_hvt.py index c7e32a0..265072d 100644 --- a/src/BAG_prim/schematic/pmos4_hvt.py +++ b/src/BAG_prim/schematic/pmos4_hvt.py
@@ -21,7 +21,6 @@ # # SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 - from typing import Any
diff --git a/src/BAG_prim/schematic/pmos4_lvt.py b/src/BAG_prim/schematic/pmos4_lvt.py index 73519c8..17e2ca7 100644 --- a/src/BAG_prim/schematic/pmos4_lvt.py +++ b/src/BAG_prim/schematic/pmos4_lvt.py
@@ -21,7 +21,6 @@ # # SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 - from typing import Any
diff --git a/src/BAG_prim/schematic/pmos4_standard.py b/src/BAG_prim/schematic/pmos4_standard.py index 5432df4..fbe206a 100644 --- a/src/BAG_prim/schematic/pmos4_standard.py +++ b/src/BAG_prim/schematic/pmos4_standard.py
@@ -21,7 +21,6 @@ # # SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 - from typing import Any
diff --git a/src/BAG_prim/schematic/pmos4_svt.py b/src/BAG_prim/schematic/pmos4_svt.py index c1ee848..8e8425c 100644 --- a/src/BAG_prim/schematic/pmos4_svt.py +++ b/src/BAG_prim/schematic/pmos4_svt.py
@@ -21,7 +21,6 @@ # # SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 - from typing import Any
diff --git a/src/templates_skywater130/__init__.py b/src/templates_skywater130/__init__.py index 09d7340..1f3ebc0 100644 --- a/src/templates_skywater130/__init__.py +++ b/src/templates_skywater130/__init__.py
@@ -21,7 +21,6 @@ # # SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 - import os import pkg_resources
diff --git a/src/templates_skywater130/data/tech_params.yaml b/src/templates_skywater130/data/tech_params.yaml index b610fed..c8c49ec 100644 --- a/src/templates_skywater130/data/tech_params.yaml +++ b/src/templates_skywater130/data/tech_params.yaml
@@ -44,11 +44,11 @@ # mapping from metal layer ID to layer/purpose pair that defines # a metal resistor. res_metal_layer_table: {} -# 1: [!!python/tuple ['m1res', 'drawing']] -# 2: [!!python/tuple ['m2res', 'drawing']] -# 3: [!!python/tuple ['m3res', 'drawing']] -# 4: [!!python/tuple ['m4res', 'drawing']] -# 5: [!!python/tuple ['m5res', 'drawing']] +# 1: [!!python/tuple ['met1', 'res']] +# 2: [!!python/tuple ['met2', 'res']] +# 3: [!!python/tuple ['met3', 'res']] +# 4: [!!python/tuple ['met4', 'res']] +# 5: [!!python/tuple ['met5', 'res']] # mapping from metal layer ID to layer/purpose pair that # defines metal exclusion region. @@ -68,6 +68,7 @@ 3: [!!python/tuple ['met3', 'drawing']] 4: [!!python/tuple ['met4', 'drawing']] 5: [!!python/tuple ['met5', 'drawing']] +# 6: [!!python/tuple ['capm', 'drawing']] dum_lay_purp_list: *lp_list @@ -87,6 +88,10 @@ 5: - [[284, .inf]] - [[284, .inf]] + + 6: + - [[60, .inf]] + - [[60, 2001]] # mapping from tuple of via layers to via ID. via_id: @@ -155,12 +160,13 @@ - [.inf, [[62, 62]]] # minimum wire spacing rule. Space is measured orthogonal to wire direction. +# should be in resolution units sp_min: [met1, drawing]: &sp_min_1x - - [.inf, 28] + - [.inf, 100] [met2, drawing]: *sp_min_1x [met3, drawing]: &sp_min_2x - - [.inf, 60] + - [.inf, 60] #60 [met4, drawing]: *sp_min_2x [met5, drawing]: - [.inf, 320] @@ -168,13 +174,14 @@ # minimum line-end spacing rule. Space is measured parallel to wire direction. sp_le_min: [met1, drawing]: &sp_le_min_1x - - [.inf, 28] + - [.inf, 100] #change from 28 [met2, drawing]: *sp_le_min_1x [met3, drawing]: &sp_le_min_2x - [.inf, 60] [met4, drawing]: *sp_le_min_2x [met5, drawing]: - [.inf, 320] + # minimum length/minimum area rules. len_min: @@ -198,6 +205,10 @@ w_al_list: - [.inf, 160000, 0] md_al_list: [] + #[capm, drawing]: + # w_al_list: + # - [.inf, 9600, 0] + # md_al_list: [] margins: well: [40, 40] @@ -267,6 +278,9 @@ # nsdm.1 imp_h_min: 76 + #might be redundant, well margin from edge to implant + nwell_imp: 40 + grid_info: - [1, 52, 1] - [3, 66, 1] @@ -864,4 +878,3 @@ - [22, 4294967295] - [27902976, 4294967295] - [6, 4294967295] -
diff --git a/src/templates_skywater130/mos/tech.py b/src/templates_skywater130/mos/tech.py index 437893c..bf7d00c 100644 --- a/src/templates_skywater130/mos/tech.py +++ b/src/templates_skywater130/mos/tech.py
@@ -42,7 +42,7 @@ MOSRowSpecs, MOSRowInfo, BlkExtInfo, MOSEdgeInfo, MOSLayInfo, ExtWidthInfo, LayoutInfo, ExtEndLayInfo, RowExtInfo ) -from ..util import add_base, get_arr_edge_dim +from ..util import add_base, add_base_mos, get_arr_edge_dim MConnInfoType = Tuple[int, int, Orient2D, int, Tuple[str, str]] @@ -109,13 +109,41 @@ @property def min_sep_col(self) -> int: - return self._get_od_sep_col(self.mos_config['od_spx']) + #return self._get_od_sep_col(self.mos_config['od_spx']) + + #felicia copied + lch = self.lch + sd_pitch = self.sd_pitch + od_po_extx = self.od_po_extx + + od_spx: int = self.mos_config['od_spx'] + imp_od_encx: int = self.mos_config['imp_od_encx'] + ans = -(-(od_spx + lch + 2 * od_po_extx + 2*imp_od_encx) // sd_pitch) - 1 + return ans + (ans & 1) @property def sub_sep_col(self) -> int: - return self._get_od_sep_col(max(self.mos_config['od_spx'], - 2 * self.mos_config['imp_od_encx'])) + # column separation needed between transistor/substrate and substrate/substrate. + # This is guaranteed to be even. + #return self._get_od_sep_col(max(self.mos_config['od_spx'], + # 2 * self.mos_config['imp_od_encx'])) + + #felicia - copied method from cds_ff_mpt + #does something similar to _get_od_sep_col but seems to have + #effective +1 that get_od doesn't have + lch = self.lch + sd_pitch = self.sd_pitch + od_po_extx = self.od_po_extx + + mos_config = self.mos_config + od_spx: int = mos_config['od_spx'] + imp_od_encx: int = mos_config['imp_od_encx'] + + od_spx = max(od_spx, 2 * imp_od_encx) + ans = -(-(od_spx + lch + 2 * od_po_extx) // sd_pitch) - 1 + return ans + (ans & 1) + @property def min_sub_col(self) -> int: return self.min_od_col @@ -144,7 +172,8 @@ @property def well_w_edge(self) -> int: imp_od_encx: int = self.mos_config['imp_od_encx'] - return -(self.sd_pitch - self.lch) // 2 + self.od_po_extx + imp_od_encx + nwell_imp: int = self.mos_config['nwell_imp'] + return -(self.sd_pitch - self.lch) // 2 + self.od_po_extx + nwell_imp + imp_od_encx def get_conn_info(self, conn_layer: int, is_gate: bool) -> ConnInfo: mconf = self.mos_config @@ -390,7 +419,7 @@ po_y_gate: Tuple[int, int], fg: int, conn_pitch: int, g_on_s: bool) -> None: lch = self.lch sd_pitch = self.sd_pitch - + #breakpoint() mconf = self.mos_config npc_w: int = mconf['npc_w'] npc_h: int = mconf['npc_h'] @@ -444,7 +473,8 @@ builder.add_rect_arr(mp_lp, BBox(mp_xl, mp_yl, mp_xl + mp_w_min, mp_yh), nx=num_g, spx=conn_pitch) else: - mp_dx = g0_info.via_w // 2 + g0_info.via_top_enc + mp_dx = g0_info.via_w # felicia - // 2 + g0_info.via_top_enc + # for licon.5 mp_xl = g_xc - mp_dx mp_xh = g_xc + (num_g - 1) * conn_pitch + mp_dx builder.add_rect_arr(mp_lp, BBox(mp_xl, mp_yl, mp_xh, mp_yh)) @@ -474,7 +504,6 @@ md_box = BBox(xc - md_w2, md_y[0], xc + md_w2, md_y[1]) builder.add_rect_arr(('licon1', 'drawing'), vc_box, nx=nx, spx=spx, ny=num_vc, spy=vc_p) builder.add_rect_arr(('li1', 'drawing'), md_box, nx=nx, spx=spx) - # connect to M1 builder.add_via(d1_info.get_via_info('L1M1_C', xc, od_yc, md_w, ortho=False, num=num_v0, nx=nx, spx=spx)) @@ -486,13 +515,14 @@ def get_mos_tap_info(self, row_info: MOSRowInfo, conn_layer: int, seg: int, options: Param) -> MOSLayInfo: assert conn_layer == 1, 'currently only work for conn_layer = 1' - + #print(row_info) row_type = row_info.row_type guard_ring: bool = options.get('guard_ring', row_info.guard_ring) if guard_ring: sub_type: MOSType = options.get('sub_type', row_type.sub_type) else: + #print(row_type.sub_type) sub_type: MOSType = row_type.sub_type sd_pitch = self.sd_pitch @@ -504,21 +534,29 @@ # draw device builder = LayoutInfoBuilder() + #draws diffusion and tap + #if (row_type is MOSType.nch): od_y = self._add_mos_active(builder, row_info, 0, seg, w, is_sub=True) - + #print(row_info) + #else: + # od_y = (193, 303) # draw drain/source connections d0_info = self.get_conn_info(0, False) d1_info = self.get_conn_info(1, False) md_yl, md_yh, num_vc = self._get_conn_params(d0_info, od_y[0], od_y[1]) num_v0 = self._get_conn_params(d1_info, md_yl, md_yh)[2] md_y = (md_yl, md_yh) + + #draws in vias connecting tap cell to metal 1 self._draw_ds_conn(builder, d0_info, d1_info, od_y, md_y, num_vc, num_v0, 0, seg + 1, sd_pitch) # draw base - bbox = BBox(0, 0, seg * sd_pitch, height) - add_base(builder, sub_type, threshold, imp_y, bbox) - + # add extra imp)od_encx for ntap and ptap + imp_od_encx: int = self.mos_config['imp_od_encx'] + bbox = BBox(0-2*imp_od_encx, 0, seg * sd_pitch + 2*imp_od_encx, height) + add_base_mos(builder, sub_type, threshold, imp_y, bbox, is_sub=True) + edge_info = MOSEdgeInfo(mos_type=sub_type, imp_y=imp_y, has_od=True) be = BlkExtInfo(row_type, row_info.threshold, guard_ring, ImmutableList([(seg, sub_type)]), ImmutableSortedDict()) @@ -760,7 +798,15 @@ # draw base imp_od_encx: int = self.mos_config['imp_od_encx'] bbox = BBox(od_xl-imp_od_encx, 0, od_xh+imp_od_encx, row_info.height) - add_base(builder, row_info.row_type, row_info.threshold, row_info['imp_y'], bbox) + + #if drawing tap cells, flip the implant type so its opposite of row + if is_sub: + if (row_info.row_type is MOSType.nch): + add_base_mos(builder, MOSType.pch, row_info.threshold, row_info['imp_y'], bbox, is_sub=True) + elif (row_info.row_type is MOSType.pch): + add_base_mos(builder, MOSType.nch, row_info.threshold, row_info['imp_y'], bbox, is_sub=True) + else: + add_base_mos(builder, row_info.row_type, row_info.threshold, row_info['imp_y'], bbox) return od_yl, od_yh @@ -831,4 +877,3 @@ xcur = xh return xcur -
diff --git a/src/templates_skywater130/tech.py b/src/templates_skywater130/tech.py index 14a7c9a..8f7d3d0 100644 --- a/src/templates_skywater130/tech.py +++ b/src/templates_skywater130/tech.py
@@ -21,10 +21,8 @@ # # SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 - from typing import Tuple, Optional, Mapping - from pybag.core import BBox from bag.util.immutable import Param
diff --git a/src/templates_skywater130/util.py b/src/templates_skywater130/util.py index e19eb02..39e0e6d 100644 --- a/src/templates_skywater130/util.py +++ b/src/templates_skywater130/util.py
@@ -21,10 +21,8 @@ # # SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 - from typing import Optional, Tuple - from pybag.core import BBox from xbase.layout.enum import MOSType @@ -33,6 +31,10 @@ def add_base(builder: LayoutInfoBuilder, row_type: MOSType, threshold: str, imp_y: Tuple[int, int], rect: BBox, well_x: Optional[Tuple[int, int]] = None) -> None: + # draws nwell, n+ implant (ndsm) and p+ implant (pdsm) + # for non mos devices (corners, edges, etc) + + pimp_lp = ('psdm', 'drawing') if rect.is_physical(): if not row_type.is_pwell: well_lp = ('nwell', 'drawing') @@ -40,18 +42,36 @@ builder.add_rect_arr(well_lp, rect) else: builder.add_rect_arr(well_lp, BBox(well_x[0], rect.yl, well_x[1], rect.yh)) + + thres_lp = _get_thres_lp(row_type, threshold) + if thres_lp[0] != '': + builder.add_rect_arr(thres_lp, rect) + +def add_base_mos(builder: LayoutInfoBuilder, row_type: MOSType, threshold: str, imp_y: Tuple[int, int], + rect: BBox, well_x: Optional[Tuple[int, int]] = None, is_sub: bool = False) -> None: + # new func draws nwell, n+ implant (ndsm) and p+ implant (pdsm) + + pimp_lp = ('psdm', 'drawing') - if row_type.is_n_plus: - builder.add_rect_arr(('nsdm', 'drawing'), rect) - else: - pimp_lp = ('psdm', 'drawing') - nimp_lp = ('nsdm', 'drawing') - if rect.yl < imp_y[0]: - builder.add_rect_arr(nimp_lp, BBox(rect.xl, rect.yl, rect.xh, imp_y[0])) - if imp_y[1] < rect.yh: - builder.add_rect_arr(nimp_lp, BBox(rect.xl, imp_y[1], rect.xh, rect.yh)) - if imp_y[0] < imp_y[1]: - builder.add_rect_arr(pimp_lp, BBox(rect.xl, imp_y[0], rect.xh, imp_y[1])) + if rect.is_physical(): + # only draw nwells if not a tap cell and pch, or is tap cell and nch + if ((not row_type.is_pwell) and (not is_sub)) \ + or (is_sub and (row_type is MOSType.nch or row_type is MOSType.ntap) ): + well_lp = ('nwell', 'drawing') + if well_x is None: + builder.add_rect_arr(well_lp, rect) + else: + builder.add_rect_arr(well_lp, BBox(well_x[0], rect.yl, well_x[1], rect.yh)) + + #draw the respective implant called + if (row_type is MOSType.nch): + builder.add_rect_arr(('nsdm', 'drawing'), BBox(rect.xl, imp_y[0], rect.xh, imp_y[1])) + elif (row_type is MOSType.pch): + builder.add_rect_arr(('psdm', 'drawing'), BBox(rect.xl, imp_y[0], rect.xh, imp_y[1])) + elif (row_type is MOSType.ntap): + builder.add_rect_arr(('nsdm', 'drawing'), BBox(rect.xl, imp_y[0], rect.xh, imp_y[1])) + elif (row_type is MOSType.ptap): + builder.add_rect_arr(('psdm', 'drawing'), BBox(rect.xl, imp_y[0], rect.xh, imp_y[1])) thres_lp = _get_thres_lp(row_type, threshold) if thres_lp[0] != '':
diff --git a/workspace_setup/.bashrc b/workspace_setup/.bashrc index 7a214e8..08c470c 100644 --- a/workspace_setup/.bashrc +++ b/workspace_setup/.bashrc
@@ -1,75 +1,62 @@ #! /usr/bin/env bash +export PYTHONPATH="" ### Setup BAG -export BAG_TOOLS_ROOT=/tools/bag3/core source .bashrc_bag -# PDK specific stuff -export SW_PDK_ROOT=${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK_root -export PDK_HOME=${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK -export METAL_STACK=s8phirs_10r +export PDK_HOME=/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.0 +export SW_PDK_ROOT=/tools/commercial/skywater +export SW_IP_HOME=${SW_PDK_ROOT}/s8_ip +export METAL_STACK="s8phirs_10r" -# calibre setup -export MGLS_LICENSE_FILE=5282@login1.bcanalog.com -export MGC_HOME=/tools/mentor/aoi_cal_2018.1_27.18 -export MGLS_HOME=/tools/mentor/mgls -export CALIBRE_HOME=$MGC_HOME # location of various tools -export CDS_INST_DIR=/tools/cadence/IC618 -export PEGASUS_HOME=/tools/cadence/PEGASUS184 -export SRR_HOME=/tools/cadence/SRR -# export CDS_INST_DIR=/tools/cadence/IC618 -export SPECTRE_HOME=/tools/cadence/SPECTRE181 -export QRC_HOME=/tools/cadence/EXT191 -export INNOVUSHOME=/tools/cadence/installs/INNOVUS181 -export CDSLIB_HOME=/tools/bag3/programs/cdsLibPlugin -export LATEX_BIN=/tools/texlive/2019/bin/x86_64-linux +export MGC_HOME=/tools/mentor/calibre/current +export CDS_INST_DIR=/tools/cadence/ICADVM/ICADVM181 +export PVS_HOME=/tools/cadence/PVS/PVS151 +export SPECTRE_HOME=/tools/cadence/SPECTRE/SPECTRE181_ISR7 +export QRC_HOME=/tools/cadence/EXT/EXT191_ISR3 +export SRR_HOME=/tools/cadence/SRR/SRR_0618 +export CMAKE_HOME=/tools/B/ayan_biswas/programs/cmake-3.17.0-Linux-x86_64 -export CDSHOME=$CDS_INST_DIR -export CDSLIB_TOOL=${CDSLIB_HOME}/tools.lnx86 +export CDSHOME=${CDS_INST_DIR} export MMSIM_HOME=${SPECTRE_HOME} # OA settings -export OA_SRC_ROOT=/tools/bag3/programs/oa_22d6 -export OA_LINK_DIR=${OA_SRC_ROOT}/lib/linux_rhel60_64/opt -# export OA_LINK_DIR=${OA_SRC_ROOT}/lib/linux_rhel50_gcc48x_64/opt -export OA_CDS_ROOT=${CDS_INST_DIR}/oa_v22.60.007 +export OA_SRC_ROOT=/tools/B/ayan_biswas/programs/oa_new +export OA_LINK_DIR=${OA_SRC_ROOT}/lib/linux_rhel70_gcc83x_64/opt export OA_INCLUDE_DIR=${OA_SRC_ROOT}/include -export OA_PLUGIN_PATH=${CDSLIB_HOME}/share/oaPlugIns:${OA_CDS_ROOT}/data/plugins:${OA_PLUGIN_PATH:-} +export OA_CDS_ROOT=${CDS_INST_DIR}/oa_v22.60.s007 +export OA_PLUGIN_PATH=${OA_CDS_ROOT}/data/plugins:${OA_PLUGIN_PATH:-} export OA_BIT=64 # PATH setup -export PATH=${MGLS_HOME}/bin:${PATH} -export PATH=${CALIBRE_HOME}/bin:${PATH} -export PATH=${CDSLIB_TOOL}/bin:${PATH} -export PATH=${PEGASUS_HOME}/bin:${PATH} +export PATH=${MGC_HOME}/bin:${PATH} +export PATH=${PVS_HOME}/bin:${PATH} +export PATH=${QRC_HOME}/bin:${PATH} export PATH=${CDS_INST_DIR}/tools/plot/bin:${PATH} export PATH=${CDS_INST_DIR}/tools/dfII/bin:${PATH} export PATH=${CDS_INST_DIR}/tools/bin:${PATH} export PATH=${MMSIM_HOME}/bin:${PATH} -export PATH=${QRC_HOME}/bin:${PATH} -export PATH=${LATEX_BIN}:${PATH} export PATH=${BAG_TOOLS_ROOT}/bin:${PATH} +export PATH=${CMAKE_HOME}/bin:${PATH} +export PATH=/tools/B/ayan_biswas/programs/core/bin:${PATH} # LD_LIBRARY_PATH setup -export LD_LIBRARY_PATH=${CDSLIB_TOOL}/lib/64bit:${LD_LIBRARY_PATH:-} export LD_LIBRARY_PATH=${OA_LINK_DIR}:${LD_LIBRARY_PATH} -export LD_LIBRARY_PATH=${BAG_TOOLS_ROOT}/lib64:${LD_LIBRARY_PATH} +export LD_LIBRARY_PATH=${BAG_WORK_DIR}/cadence_libs:${LD_LIBRARY_PATH} +export LD_LIBRARY_PATH=${SRR_HOME}/tools/lib/64bit:${LD_LIBRARY_PATH:-} export LD_LIBRARY_PATH=${BAG_TOOLS_ROOT}/lib:${LD_LIBRARY_PATH} -export LD_LIBRARY_PATH=${SRR_HOME}/tools/lib/64bit:${LD_LIBRARY_PATH} +export LD_LIBRARY_PATH=$/tools/B/ayan_biswas/programs/core/lib:${LD_LIBRARY_PATH} +export LD_LIBRARY_PATH=$/tools/B/ayan_biswas/programs/core/lib64:${LD_LIBRARY_PATH} # Virtuoso options export SPECTRE_DEFAULTS=-E export CDS_Netlisting_Mode="Analog" export CDS_AUTO_64BIT=ALL -export CDS_LIC_FILE=5280@login1.bcanalog.com + +# License setup +source /tools/flexlm/flexlm.sh # pybag compiler settings export CMAKE_PREFIX_PATH=${BAG_TOOLS_ROOT} -export HDF5_PLUGIN_PATH=${BAG_TOOLS_ROOT}/lib/hdf5/plugin - -# clear out PYTHONPATH -export PYTHONPATH="" -export PYTHONPATH_CUSTOM=${SRR_HOME}/tools/srrpython -
diff --git a/workspace_setup/.bashrc_bag b/workspace_setup/.bashrc_bag index 01a90fc..59108c6 100644 --- a/workspace_setup/.bashrc_bag +++ b/workspace_setup/.bashrc_bag
@@ -1,23 +1,18 @@ #! /usr/bin/env bash -# set directory variables export BAG_WORK_DIR=$(pwd) +export BAG_TOOLS_ROOT=/tools/commercial/bcanalog/bag/bag3d0_rhel60_64 export BAG_FRAMEWORK=${BAG_WORK_DIR}/BAG_framework export BAG_TECH_CONFIG_DIR=${BAG_WORK_DIR}/skywater130 -export BAG_TEMP_DIR=${BAG_WORK_DIR}/BAGTMP +export BAG_TEMP_DIR=/tools/scratch/${USER}/BAGTMP export IPYTHONDIR=${BAG_WORK_DIR}/.ipython # disable hash-salting. We need stable hashing across sessions for caching purposes. export PYTHONHASHSEED=0 - # set program locations export BAG_PYTHON=${BAG_TOOLS_ROOT}/bin/python3 -export BAG_JUPYTER=${BAG_TOOLS_ROOT}/bin/jupyter-notebook # set location of BAG configuration file export BAG_CONFIG_PATH=${BAG_WORK_DIR}/bag_config.yaml -# change pycharm config file location -export PYCHARM_PROPERTIES=/scratch/projects/${USER}/pycharm_setup/idea.properties - # setup pybag export PYBAG_PYTHON=${BAG_PYTHON}
diff --git a/workspace_setup/.cdsinit b/workspace_setup/.cdsinit index 26d34a2..b1b929b 100644 --- a/workspace_setup/.cdsinit +++ b/workspace_setup/.cdsinit
@@ -137,12 +137,13 @@ ;; Set Default Model Files. Note the "#;" de-selects the model call. setModelFiles=strcat( - " " getShellEnvVar("PDK_HOME") "MODELS/SPECTRE" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;tt_fet" - " " getShellEnvVar("PDK_HOME") "MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;tt_cell" - " " getShellEnvVar("PDK_HOME") "MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;tt_parRC" - " " getShellEnvVar("PDK_HOME") "MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;tt_rc" - " " getShellEnvVar("PDK_HOME") "MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;npn_t" + " " getShellEnvVar("PDK_HOME") "/MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;tt_fet" + " " getShellEnvVar("PDK_HOME") "/MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;tt_cell" + " " getShellEnvVar("PDK_HOME") "/MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;tt_parRC" + " " getShellEnvVar("PDK_HOME") "/MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;tt_rc" + " " getShellEnvVar("PDK_HOME") "/MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;npn_t" ) + envSetVal("spectre.envOpts" "modelFiles" 'string setModelFiles) envSetVal("spectre.envOpts" "controlMode" 'string "batch")
diff --git a/workspace_setup/bag_config.yaml b/workspace_setup/bag_config.yaml index 4b24bce..95c1450 100644 --- a/workspace_setup/bag_config.yaml +++ b/workspace_setup/bag_config.yaml
@@ -104,16 +104,19 @@ # python class that talks with the simulator class: "bag.simulation.spectre.SpectreInterface" # maximum number of processes BAG can launch. - max_workers: 6 + max_workers: 8 # when simulation goes long, a reminder message will be printed at this interval update_timeout_ms: 120000 # amount of time to wait for process cancellation to succeed. cancel_timeout_ms: 10000 + # True to show interactive log viewer. + show_log_viewer: True # corner configuration file env_file: "${BAG_TECH_CONFIG_DIR}/corners_setup.yaml" # command settings kwargs: # the command to start + #command: "bsub -q bora -o $BAG_WORK_DIR/tmp -K spectre" command: spectre # environment variables. Null for same environment as SkillOceanServer. env: !!null @@ -123,7 +126,7 @@ format: psfxl # psf version psfversion: '1.1' - options: ['++aps', '+lqtimeout', '0', '+mt=1', '+mp=1', '+postlayout', '+rcnet_fmax=25'] + options: ['++aps', '+lqtimeout', '0', '+mt=8', '+mp=8', '+postlayout', '+rcnet_fmax=25'] compress: True rtol: 1.0e-8 atol: 1.0e-22
diff --git a/workspace_setup/bag_submodules.yaml b/workspace_setup/bag_submodules.yaml index 4251600..2e713eb 100644 --- a/workspace_setup/bag_submodules.yaml +++ b/workspace_setup/bag_submodules.yaml
@@ -19,14 +19,15 @@ # SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 BAG_framework: - url: https://github.com/bluecheetah/bag.git - branch: master + url: git@10.8.0.1:bag/BAG_framework.git + branch: sim_refactor bag3_digital: - url: https://github.com/bluecheetah/bag3_digital.git - branch: master + url: git@10.8.0.1:bag/bag3_digital.git + branch: sim_refactor bag3_testbenches: - url: https://github.com/bluecheetah/bag3_testbenches.git - branch: master + url: git@10.8.0.1:bag/bag3_testbenches.git + branch: sim_refactor xbase_bcad: - url: https://github.com/bluecheetah/xbase.git - branch: master + url: git@10.8.0.1:bag/xbase_bcad.git + branch: sim_refactor +
diff --git a/workspace_setup/ipython_config.py b/workspace_setup/ipython_config.py index 810c641..b53ec95 100644 --- a/workspace_setup/ipython_config.py +++ b/workspace_setup/ipython_config.py
@@ -1,6 +1,9 @@ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# # Copyright 2019-2021 SkyWater PDK Authors # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -31,13 +34,13 @@ #------------------------------------------------------------------------------ ## A Mixin for applications that start InteractiveShell instances. -# +# # Provides configurables for loading extensions and executing files as part of # configuring a Shell environment. -# +# # The following methods should be called by the :meth:`initialize` method of the # subclass: -# +# # - :meth:`init_path` # - :meth:`init_shell` (to be implemented by the subclass) # - :meth:`init_gui_pylab` @@ -91,7 +94,7 @@ ## If true, IPython will populate the user namespace with numpy, pylab, etc. and # an ``import *`` is done from numpy and pylab, when using pylab mode. -# +# # When False, pylab mode should not import any names into the user namespace. #c.InteractiveShellApp.pylab_import_all = True @@ -129,7 +132,7 @@ #c.BaseIPythonApplication.copy_config_files = False ## Path to an extra config file to load. -# +# # If specified, load this config file in addition to any other IPython config. #c.BaseIPythonApplication.extra_config_file = u'' @@ -213,13 +216,13 @@ ## Set the color scheme (NoColor, Neutral, Linux, or LightBG). c.InteractiveShell.colors = 'Linux' -## +## #c.InteractiveShell.debug = False ## **Deprecated** -# +# # Will be removed in IPython 6.0 -# +# # Enable deep (recursive) reloading by default. IPython can use the deep_reload # module which reloads changes in modules recursively (it replaces the reload() # function, so you don't need to change anything to use it). `deep_reload` @@ -245,7 +248,7 @@ # startup. #c.InteractiveShell.history_load_length = 1000 -## +## #c.InteractiveShell.ipython_dir = '' ## Start logging to the given file in append mode. Use `logfile` to specify a log @@ -259,7 +262,7 @@ # specify a log file to **append** logs to. #c.InteractiveShell.logstart = False -## +## #c.InteractiveShell.object_info_string_level = 0 ## Automatically call the pdb debugger after every exception. @@ -281,16 +284,16 @@ # TerminalInteractiveShell.prompts object directly. #c.InteractiveShell.prompts_pad_left = True -## +## #c.InteractiveShell.quiet = False -## +## #c.InteractiveShell.separate_in = '\n' -## +## #c.InteractiveShell.separate_out = '' -## +## #c.InteractiveShell.separate_out2 = '' ## Show rewritten input, e.g. for autocall. @@ -300,10 +303,10 @@ # module). #c.InteractiveShell.sphinxify_docstring = False -## +## #c.InteractiveShell.wildcards_case_sensitive = True -## +## #c.InteractiveShell.xmode = 'Context' #------------------------------------------------------------------------------ @@ -346,11 +349,11 @@ ## Use `raw_input` for the REPL, without completion, multiline input, and prompt # colors. -# +# # Useful when controlling IPython as a subprocess, and piping STDIN/OUT/ERR. # Known usage are: IPython own testing machinery, and emacs inferior-shell # integration through elpy. -# +# # This mode default to `True` if the `IPY_TEST_SIMPLE_PROMPT` environment # variable is set, or the current terminal is not a tty. #c.TerminalInteractiveShell.simple_prompt = False @@ -371,35 +374,35 @@ #------------------------------------------------------------------------------ ## Access the history database without adding to it. -# +# # This is intended for use by standalone history tools. IPython shells use # HistoryManager, below, which is a subclass of this. ## Options for configuring the SQLite connection -# +# # These options are passed as keyword args to sqlite3.connect when establishing # database conenctions. #c.HistoryAccessor.connection_options = {} ## enable the SQLite history -# +# # set enabled=False to disable the SQLite history, in which case there will be # no stored history, no SQLite connection, and no background saving thread. # This may be necessary in some threaded environments where IPython is embedded. #c.HistoryAccessor.enabled = True ## Path to file to use for SQLite history database. -# +# # By default, IPython will put the history database in the IPython profile # directory. If you would rather share one history among profiles, you can set # this value in each, so that they are consistent. -# +# # Due to an issue with fcntl, SQLite is known to misbehave on some NFS mounts. # If you see IPython hanging, try setting this to something on a local disk, # e.g:: -# +# # ipython --HistoryManager.hist_file=/tmp/ipython_hist.sqlite -# +# # you can also use the specific value `:memory:` (including the colon at both # end but not the back ticks), to avoid creating an history file. #c.HistoryAccessor.hist_file = u'' @@ -422,10 +425,10 @@ #------------------------------------------------------------------------------ ## An object to manage the profile directory and its resources. -# +# # The profile directory is used by all IPython applications, to manage # configuration, logging and security. -# +# # This object knows how to find, create and manage these directories. This # should be used by any code that wants to handle profiles. @@ -438,37 +441,37 @@ #------------------------------------------------------------------------------ ## A base formatter class that is configurable. -# +# # This formatter should usually be used as the base class of all formatters. It # is a traited :class:`Configurable` class and includes an extensible API for # users to determine how their objects are formatted. The following logic is # used to find a function to format an given object. -# +# # 1. The object is introspected to see if it has a method with the name # :attr:`print_method`. If is does, that object is passed to that method # for formatting. # 2. If no print method is found, three internal dictionaries are consulted # to find print method: :attr:`singleton_printers`, :attr:`type_printers` # and :attr:`deferred_printers`. -# +# # Users should use these dictionaries to register functions that will be used to # compute the format data for their objects (if those objects don't have the # special print methods). The easiest way of using these dictionaries is through # the :meth:`for_type` and :meth:`for_type_by_name` methods. -# +# # If no function/callable is found to compute the format data, ``None`` is # returned and this format type is not used. -## +## #c.BaseFormatter.deferred_printers = {} -## +## #c.BaseFormatter.enabled = True -## +## #c.BaseFormatter.singleton_printers = {} -## +## #c.BaseFormatter.type_printers = {} #------------------------------------------------------------------------------ @@ -476,12 +479,12 @@ #------------------------------------------------------------------------------ ## The default pretty-printer. -# +# # This uses :mod:`IPython.lib.pretty` to compute the format data of the object. # If the object cannot be pretty printed, :func:`repr` is used. See the # documentation of :mod:`IPython.lib.pretty` for details on how to write pretty # printers. Here is a simple example:: -# +# # def dtype_pprinter(obj, p, cycle): # if cycle: # return p.text('dtype(...)') @@ -497,24 +500,24 @@ # p.pretty(field) # p.end_group(7, '])') -## +## #c.PlainTextFormatter.float_precision = '' ## Truncate large collections (lists, dicts, tuples, sets) to this size. -# +# # Set to 0 to disable truncation. #c.PlainTextFormatter.max_seq_length = 1000 -## +## #c.PlainTextFormatter.max_width = 79 -## +## #c.PlainTextFormatter.newline = '\n' -## +## #c.PlainTextFormatter.pprint = True -## +## #c.PlainTextFormatter.verbose = False #------------------------------------------------------------------------------ @@ -523,7 +526,7 @@ ## Activate greedy completion PENDING DEPRECTION. this is now mostly taken care # of with Jedi. -# +# # This will enable completion on elements of lists, results of function calls, # etc., but can be unsafe because the code is actually evaluated on TAB. #c.Completer.greedy = False @@ -535,30 +538,30 @@ ## Extension of the completer class with IPython-specific features ## DEPRECATED as of version 5.0. -# +# # Instruct the completer to use __all__ for the completion -# +# # Specifically, when completing on ``object.<tab>``. -# +# # When True: only those names in obj.__all__ will be included. -# +# # When False [default]: the __all__ attribute is ignored #c.IPCompleter.limit_to__all__ = False ## Whether to merge completion results into a single list -# +# # If False, only the completion results from the first non-empty completer will # be returned. #c.IPCompleter.merge_completions = True ## Instruct the completer to omit private method names -# +# # Specifically, when completing on ``object.<tab>``. -# +# # When 2 [default]: all names that start with '_' will be excluded. -# +# # When 1: all 'magic' names (``__foo__``) will be excluded. -# +# # When 0: nothing will be excluded. #c.IPCompleter.omit__names = 2 @@ -567,21 +570,21 @@ #------------------------------------------------------------------------------ ## Magics for talking to scripts -# +# # This defines a base `%%script` cell magic for running a cell with a program in # a subprocess, and registers a few top-level magics that call %%script with # common interpreters. ## Extra script cell magics to define -# +# # This generates simple wrappers of `%%script foo` as `%%foo`. -# +# # If you want to add script magics that aren't on your path, specify them in # script_paths #c.ScriptMagics.script_magics = [] ## Dict mapping short 'ruby' names to full paths, such as '/opt/secret/bin/ruby' -# +# # Only necessary for items in script_magics where the default path will not find # the right interpreter. #c.ScriptMagics.script_paths = {} @@ -591,7 +594,7 @@ #------------------------------------------------------------------------------ ## Lightweight persistence for python variables. -# +# # Provides the %store magic. ## If True, any %store-d variables will be automatically restored when IPython
diff --git a/workspace_setup/leBindKeys.il b/workspace_setup/leBindKeys.il index 7e513d6..701d345 100644 --- a/workspace_setup/leBindKeys.il +++ b/workspace_setup/leBindKeys.il
@@ -1,23 +1,3 @@ -;; Copyright 2019-2021 SkyWater PDK Authors -;; -;; Licensed under the Apache License, Version 2.0 (the "License"); -;; you may not use this file except in compliance with the License. -;; You may obtain a copy of the License at -;; -;; https://www.apache.org/licenses/LICENSE-2.0 -;; -;; Unless required by applicable law or agreed to in writing, software -;; distributed under the License is distributed on an "AS IS" BASIS, -;; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;; See the License for the specific language governing permissions and -;; limitations under the License. -;; -;; This code is *alternatively* available under a BSD-3-Clause license, see -;; details in the README.md at the top level and the license text at -;; https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative -;; -;; SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0 - ;;----------------------------------------------------------------------------- ;; Bindkeys for 'Layout' ;; Inherited by: @@ -95,7 +75,7 @@ sprintf(via_name "via%d" bot_layer) ) sprintf(top_name "met%d" bot_layer + 1) - + leSetEntryLayer(list(bot_name "drawing")) leSetAllLayerVisible(nil) leSetLayerVisible(list(bot_name "drawing") t)
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