)]}'
{
  "commit": "f3ed3d715481735d2768f5bf51c7c28164020c6e",
  "tree": "7b92a30f5778b46d329cfbd2d990f3fded842ef7",
  "parents": [
    "3ac9f24a1bdf3e1ca388d643bf547e7acc1a03e9",
    "795158aa4bbfa7c3b76dde32e1eb52be04687a1f"
  ],
  "author": {
    "name": "Tim Ansell",
    "email": "me@mith.ro",
    "time": "Tue Oct 06 08:29:53 2020 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Oct 06 08:29:53 2020 -0700"
  },
  "message": "Merge pull request #167 from mithro/verilog-fix-3\n\nverilog: Fix ordering of ports on mux primitives.",
  "tree_diff": []
}