diff --git a/.gitmodules b/.gitmodules
index 3a0a8fa..e02f407 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -156,3 +156,87 @@
 	branch = branch-0.1.0
 	shallow = true
 	fetchRecurseSubmodules = false
+
+# sky130_fd_sc_lp
+[submodule "libraries/sky130_fd_sc_lp/latest"]
+	path = libraries/sky130_fd_sc_lp/latest
+	url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_lp.git
+	branch = master
+	shallow = true
+	fetchRecurseSubmodules = true
+[submodule "libraries/sky130_fd_sc_lp/v0.0.2"]
+	path = libraries/sky130_fd_sc_lp/v0.0.2
+	url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_lp.git
+	branch = branch-0.0.2
+	shallow = true
+	fetchRecurseSubmodules = false
+[submodule "libraries/sky130_fd_sc_lp/v0.0.1"]
+	path = libraries/sky130_fd_sc_lp/v0.0.1
+	url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_lp.git
+	branch = branch-0.0.1
+	shallow = true
+	fetchRecurseSubmodules = false
+
+# sky130_fd_sc_hvl
+[submodule "libraries/sky130_fd_sc_hvl/latest"]
+	path = libraries/sky130_fd_sc_hvl/latest
+	url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hvl.git
+	branch = master
+	shallow = true
+	fetchRecurseSubmodules = true
+[submodule "libraries/sky130_fd_sc_hvl/v0.0.3"]
+	path = libraries/sky130_fd_sc_hvl/v0.0.3
+	url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hvl.git
+	branch = branch-0.0.3
+	shallow = true
+	fetchRecurseSubmodules = false
+[submodule "libraries/sky130_fd_sc_hvl/v0.0.2"]
+	path = libraries/sky130_fd_sc_hvl/v0.0.2
+	url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hvl.git
+	branch = branch-0.0.2
+	shallow = true
+	fetchRecurseSubmodules = false
+[submodule "libraries/sky130_fd_sc_hvl/v0.0.1"]
+	path = libraries/sky130_fd_sc_hvl/v0.0.1
+	url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hvl.git
+	branch = branch-0.0.1
+	shallow = true
+	fetchRecurseSubmodules = false
+
+# sky130_fd_io
+[submodule "libraries/sky130_fd_io/latest"]
+	path = libraries/sky130_fd_io/latest
+	url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_io.git
+	branch = master
+	shallow = true
+	fetchRecurseSubmodules = true
+[submodule "libraries/sky130_fd_io/v0.2.1"]
+	path = libraries/sky130_fd_io/v0.2.1
+	url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_io.git
+	branch = branch-0.2.1
+	shallow = true
+	fetchRecurseSubmodules = false
+[submodule "libraries/sky130_fd_io/v0.2.0"]
+	path = libraries/sky130_fd_io/v0.2.0
+	url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_io.git
+	branch = branch-0.2.0
+	shallow = true
+	fetchRecurseSubmodules = false
+[submodule "libraries/sky130_fd_io/v0.1.0"]
+	path = libraries/sky130_fd_io/v0.1.0
+	url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_io.git
+	branch = branch-0.1.0
+	shallow = true
+	fetchRecurseSubmodules = false
+[submodule "libraries/sky130_fd_io/v0.0.2"]
+	path = libraries/sky130_fd_io/v0.0.2
+	url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_io.git
+	branch = branch-0.1.0
+	shallow = true
+	fetchRecurseSubmodules = false
+[submodule "libraries/sky130_fd_io/v0.0.1"]
+	path = libraries/sky130_fd_io/v0.0.1
+	url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_io.git
+	branch = branch-0.0.1
+	shallow = true
+	fetchRecurseSubmodules = false
diff --git a/.readthedocs.yml b/.readthedocs.yml
index 4b63f51..2546fc3 100644
--- a/.readthedocs.yml
+++ b/.readthedocs.yml
@@ -27,3 +27,8 @@
 
 conda:
   environment: environment.yml
+
+submodules:
+  include:
+   - libraries/sky130_fd_io/latest
+  recursive: false
diff --git a/README.rst b/README.rst
index 008d8d5..31c2643 100644
--- a/README.rst
+++ b/README.rst
@@ -55,6 +55,15 @@
 
 See both the `Known Issues <docs/known_issues.rst>`_ section and the `SkyWater PDK GitHub issue list <https://github.com/google/skywater-pdk/issues>`_ to get more detailed information around currently known issues.
 
+Resources
+=========
+
+The latest SkyWater SKY130 PDK design resources can be viewed at the following locations:
+
+* `On Github @ google/skywater-pdk <https://github.com/google/skywater-pdk>`_
+* `Google CodeSearch interface @ https://cs.opensource.google/skywater-pdk <https://cs.opensource.google/skywater-pdk>`_
+* `foss-eda-tools.googlesource.com/skywater-pdk <https://foss-eda-tools.googlesource.com/skywater-pdk/>`_
+
 SKY130 Process Node
 ===================
 
diff --git a/README.src.rst b/README.src.rst
index 9f6f63c..694895f 100644
--- a/README.src.rst
+++ b/README.src.rst
@@ -37,6 +37,15 @@
 
 See both the :ref:`Known Issues` section and the `SkyWater PDK GitHub issue list <https://github.com/google/skywater-pdk/issues>`_ to get more detailed information around currently known issues.
 
+Resources
+=========
+
+The latest SkyWater SKY130 PDK design resources can be viewed at the following locations:
+
+* `On Github @ google/skywater-pdk <https://github.com/google/skywater-pdk>`_
+* `Google CodeSearch interface @ https://cs.opensource.google/skywater-pdk <https://cs.opensource.google/skywater-pdk>`_
+* `foss-eda-tools.googlesource.com/skywater-pdk <https://foss-eda-tools.googlesource.com/skywater-pdk/>`_
+
 SKY130 Process Node
 ===================
 
diff --git a/docs/index.rst b/docs/index.rst
index 1d30453..828ea9b 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -46,6 +46,14 @@
 .. include:: status.rst
     :start-after: current_status_text
 
+Resources
+=========
+
+The latest SkyWater SKY130 PDK design resources can be downloaded from the following repositories:
+
+* `On Github @ google/skywater-pdk <https://github.com/google/skywater-pdk>`_
+* `Google CodeSearch interface @ https://cs.opensource.google/skywater-pdk <https://cs.opensource.google/skywater-pdk>`_
+* `foss-eda-tools.googlesource.com/skywater-pdk <https://foss-eda-tools.googlesource.com/skywater-pdk/>`_
 
 Indices and tables
 ==================
diff --git a/docs/rules/periphery-rules.rst b/docs/rules/periphery-rules.rst
index 199aae2..4b70e5d 100644
--- a/docs/rules/periphery-rules.rst
+++ b/docs/rules/periphery-rules.rst
@@ -113,100 +113,122 @@
 .. list-table:: Function: Defines General (FIXME)
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(x.1a)`
-     - p1m.md (OPC), DECA and AMKOR layers (pi1.dg, pmm.dg, rdl.dg, pi2.dg, ubm.dg, bump.dg) and mask data for p1m, met1, via, met2 must be on a grid of [mm]
+     - p1m.md (OPC), DECA and AMKOR layers (pi1.dg, pmm.dg, rdl.dg, pi2.dg, ubm.dg, bump.dg) and mask data for p1m, met1, via, met2 must be on a grid of mm
      - 
      - 0.001
+     - mm
    * - :drc_rule:`(x.1b)`
-     - Data for SKY130 layout and mask on all layers except those mentioned in 1a must be on a grid of [mm] (except inside Seal ring)
+     - Data for SKY130 layout and mask on all layers except those mentioned in 1a must be on a grid of mm (except inside Seal ring)
      - 
      - 0.005
+     - mm
    * - :drc_rule:`(x.2)`
      - Angles permitted on: diff
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(x.2)`
      - Angles permitted on: diff except for:
-         - diff inside "advSeal_6um* OR cuPillarAdvSeal_6um*" pcell, 
-         - diff rings around the die at min total L>1000 um and W=0.3 um
+         - diff inside "advSeal_6µm* OR cuPillarAdvSeal_6µm*" pcell, 
+         - diff rings around the die at min total L>1000 µm and W=0.3 µm
      - 
      - n x 90
+     - deg
    * - :drc_rule:`(x.2)`
      - Angles permitted on: tap (except inside :drc_tag:`areaid.en`), poly (except for ESD flare gates or gated_npn), li1(periphery), licon1, capm, mcon, via, via2. Anchors are exempted.
      - 
      - n x 90
+     - deg
    * - :drc_rule:`(x.2)`
      - Angles permitted on: via3 and via4. Anchors are exempted.
      - 
      - n x 90
+     - deg
    * - :drc_rule:`(x.2a)`
      - Analog circuits identified by :drc_tag:`areaid.analog` to use rectangular diff and tap geometries only; that are not to be merged into more complex shapes (T's or L's)
      - 
      - 
+     - 
    * - :drc_rule:`(x.2c)`
      - 45 degree angles allowed on diff, tap inside UHVI
      - 
      - 
+     - 
    * - :drc_rule:`(x.3)`
      - Angles permitted on all other layers and in the seal ring for all the layers
      - 
      - 
+     - 
    * - :drc_rule:`(x.3a)`
      - Angles permitted on all other layers except WLCSP layers (pmm, rdl, pmm2, ubm and bump)
      - 
      - n x 45
+     - deg
    * - :drc_rule:`(x.4)`
      - Electrical DR cover layout guidelines for electromigration
      - :drc_flag:`NC`
      - 
+     - 
    * - :drc_rule:`(x.5)`
      - All "pin"polygons must be within the "drawing" polygons of the layer
      - :drc_flag:`AL`
      - 
+     - 
    * - :drc_rule:`(x.6)`
      - All intra-layer separation checks will include a notch check
      - 
      - 
+     - 
    * - :drc_rule:`(x.7)`
      - Mask layer line and space checks must be done on all layers (checked with s.x rules)
      - :drc_flag:`NC`
      - 
+     - 
    * - :drc_rule:`(x.8)`
      - Use of areaid "core" layer ("coreid") must be approved by technology
      - :drc_flag:`NC`
      - 
+     - 
    * - :drc_rule:`(x.9)`
      - Shapes on maskAdd or maskDrop layers ("serifs") are allowed in core only. Exempted are: 
          - cfom md/mp inside "advSeal_6um* OR cuPillarAdvSeal_6um*" pcell 
          - diff rings around the die at min total L>1000 um and W=0.3 um, and PMM/PDMM inside areaid:sl
      - 
      - 
+     - 
    * - :drc_rule:`(x.9)`
      - Shapes on maskAdd or maskDrop layers ("serifs") are allowed in core only. PMM/PDMM inside areaid:sl are excluded.
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(x.10)`
      - Res purpose layer for (diff, poly) cannot overlap licon1
      - 
      - 
+     - 
    * - :drc_rule:`(x.11)`
      - Metal fuses are drawn in met2
      - :drc_flag:`LVS`
      - N/A
+     - N/A
    * - :drc_rule:`(x.11)`
      - Metal fuses are drawn in met3
      - :drc_flag:`LVS`
      - N/A
+     - N/A
    * - :drc_rule:`(x.11)`
      - Metal fuses are drawn in met4
      - :drc_flag:`LVS`
      - 
+     - 
    * - :drc_rule:`(x.\n12a\n12b\n12c)`
      - To comply with the minimum spacing requirement for layer X in the frame:
          - Spacing of :drc_tag:`areaid.mt` to any non-ID layer
@@ -214,63 +236,78 @@
          - Rules exempted for cells with name "*_buildspace"
      - :drc_flag:`F`
      - 
+     - 
    * - :drc_rule:`(x.12d)`
      - Spacing of :drc_tag:`areaid.mt` to huge_metX (Exempt met3.dg)
      - :drc_flag:`F`
      - N/A
+     - N/A
    * - :drc_rule:`(x.12d)`
      - Spacing of :drc_tag:`areaid.mt` to huge_metX (Exempt met5.dg)
      - :drc_flag:`F`
      - 
+     - 
    * - :drc_rule:`(x.12e)`
      - Enclosure of huge_metX by :drc_tag:`areaid.mt` (Exempt met3.dg)
      - :drc_flag:`F`
      - N/A
+     - N/A
    * - :drc_rule:`(x.12e)`
      - Enclosure of huge_metX by :drc_tag:`areaid.mt` (Exempt met5.dg)
      - :drc_flag:`F`
      - 
+     - 
    * - :drc_rule:`(x.13)`
      - Spacing between features located across areaid:ce is checked by …
      - 
      - 
+     - 
    * - :drc_rule:`(x.14)`
      - Width of features straddling areaid:ce is checked by …
      - 
      - 
+     - 
    * - :drc_rule:`(x.15a)`
      - Drawn compatible, mask, and waffle-drop layers are allowed only inside areaid:mt (i.e., etest modules), or inside areaid:sl (i.e., between the outer and inner areaid:sl edges, but not in the die) or inside areaid:ft (i.e., frame, blankings). Exception: FOM/P1M/Metal waffle drop are allowed inside the die
      - :drc_flag:`P`
      - 
+     - 
    * - :drc_rule:`(x.15b)`
      - Rule X.15a exempted for cpmm.dg inside cellnames "PadPLfp", "padPLhp", "padPLstg" and "padPLwlbi" (for the SKY130di-5r-gsmc flow)
      - :drc_flag:`EXEMPT`
      - 
+     - 
    * - :drc_rule:`(x.16)`
      - Die must not overlap :drc_tag:`areaid.mt` (rule waived for test chips and exempted for cellnames "*tech_CD_*", "*_techCD_*", "lazX_*" or "lazY_*" )
      - 
      - 
+     - 
    * - :drc_rule:`(x.17)`
      - All labels must be within the "drawing" polygons of the layer; This check is enabled by using switch "floating_labels"; Identifies floating labels which appear as warnings in LVS. Using this check would enable cleaner LVS run; Not a gate for tapeout
      - 
      - 
+     - 
    * - :drc_rule:`(x.18)`
      - | Use redundant mcon, via, via2, via3 and via4 (Locations where additional vias/contacts can be added to existing single vias/contacts will be identified by this rule).
        | Single via under :drc_tag:`areaid.core` and :drc_tag:`areaid.standarc` are excluded from the single via check
      - :drc_flag:`RR`
      - 
+     - 
    * - :drc_rule:`(x.19)`
      - Lower left corner of the seal ring should be at origin i.e (0,0)
      - 
      - 
+     - 
    * - :drc_rule:`(x.20)`
      - Min spacing between pins on the same layer (center to center); Check enabled by switch "IP_block"
      - 
      - 
+     - 
    * - :drc_rule:`(x.21)`
      - prunde.dg is allowed only inside :drc_tag:`areaid.mt` or :drc_tag:`areaid.sc`
      - 
      - 
+     - 
    * - :drc_rule:`(x.22)`
      - | No floating interconnects (poly, li1, met1-met5) or capm allowed; Rule flags interconnects with no path to poly, difftap or metal pins. Exempt floating layers can be excluded using poly_float, li1_float, m1_float, m2_float, m3_float, m4_float and m5_float text labels. Also flags an error if these text labels are placed on connected layers (not floating) and if the labels are not over the appropriate metal layer.  
        | If floating interconnects need to be connected at a higher level (Parent IP or Full chip), such floating interconnects can be exempted using poly_tie, li1_tie, m1_tie, m2_tie, m3_tie, m4_tie and m5_tie text labels.
@@ -281,55 +318,68 @@
        The 'notPublicCell' switch will deactivate this rule
      - :drc_flag:`RC`
      - 
+     - 
    * - :drc_rule:`(x.23a)`
      - :drc_tag:`areaid.sl` must not overlap diff
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(x.23b)`
      - diff cannot straddle :drc_tag:`areaid.sl`
      - 
      - 
+     - 
    * - :drc_rule:`(x.23c)`
      - :drc_tag:`areaid.sl` must not overlap tap, poly, li1 and metX
      - 
      - 
+     - 
    * - :drc_rule:`(x.23d)`
      - :drc_tag:`areaid.sl` must not overlap tap, poly
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(x.23e)`
      - areaid:sl must not overlap li1 and metX for pcell "advSeal_6um"
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(x.23f)`
      - areaid:SubstrateCut (:drc_tag:`areaid.st`, local_sub) must not straddle p+ tap
      - :drc_flag:`RR`
      - 
+     - 
    * - :drc_rule:`(x.24)`
      - condiode label must be in iso_pwell
      - 
      - 
+     - 
    * - :drc_rule:`(x.25)`
      - pnp.dg must be only within cell name "s8rf_pnp", "s8rf_pnp5x" or "s8tesd_iref_pnp", "stk14ecx_*"
      - 
      - 
+     - 
    * - :drc_rule:`(x.26)`
      - "advSeal_6um" pcell must overlap diff
      - 
      - 
+     - 
    * - :drc_rule:`(x.27)`
      - | If the sealring is present, then partnum is required.  To exempt the requirement, place text.dg saying "partnum_not_necessary".
        | "partnum*block" pcell should be used instead of "partnum*" pcells
      - :drc_flag:`RR`
      - N/A
+     - N/A
    * - :drc_rule:`(x.28)`
      - Min width of :drc_tag:`areaid.sl`
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(x.29)`
      - nfet must be enclosed by dnwell. Rule is checked when switch nfet_in_dnwell is turned on.
      - 
      - 
+     - 
 
 
 .. figure:: periphery/p018-x_dotdash.svg
@@ -344,52 +394,63 @@
 .. list-table:: Function: Define deep nwell for isolating pwell and noise immunity
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(dnwell.2)`
      - Min width of deep nwell
      - 
      - 3.000
+     - µm
    * - :drc_rule:`(dnwell.3)`
      - Min spacing between deep nwells. Rule exempt inside UHVI.
      - 
      - 6.300
+     - µm
    * - :drc_rule:`(dnwell.3a)`
      - Min spacing between deep nwells on same net inside UHVI.
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(dnwell.3b)`
      - Min spacing between deep-nwells inside UHVI and deep-nwell outside UHVI
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(dnwell.3c)`
      - Min spacing between deep-nwells inside UHVI and nwell outsideUHVI
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(dnwell.3d)`
      - Min spacing between deep-nwells inside UHVI on different nets
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(dnwell.4)`
      - Dnwell can not overlap pnp:dg
      - 
      - 
+     - 
    * - :drc_rule:`(dnwell.5)`
      - P+_diff can not straddle Dnwell
      - 
      - 
+     - 
    * - :drc_rule:`(dnwell.6)`
      - RF NMOS must be enclosed by deep nwell (RF FETs are listed in $DESIGN/config/tech/model_set/calibre/fixed_layout_model_map of corresponding techs)
      - 
      - 
+     - 
    * - :drc_rule:`(dnwell.7)`
      - Dnwell can not straddle areaid:substratecut
      - 
      - 
+     - 
 
 
 .. figure:: periphery/p020-dnwell_dotdash.svg
@@ -404,51 +465,61 @@
 .. list-table:: Function: Define nwell implant regions
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(nwell.1)`
      - Width of nwell
      - 
      - 0.840
+     - µm
    * - :drc_rule:`(nwell.2a)`
      - Spacing between two n-wells
      - 
      - 1.270
+     - µm
    * - :drc_rule:`(nwell.2b)`
      - Manual merge wells if less than minimum
      - 
      - 
+     - 
    * - :drc_rule:`(nwell.4)`
      - All n-wells will contain metal-contacted tap  (rule checks only for licon on tap) . Rule exempted from high voltage cells inside UHVI
      - 
      - 
+     - 
    * - :drc_rule:`(nwell.5)`
      - Deep nwell must be enclosed by nwell by atleast... Exempted inside UHVI or :drc_tag:`areaid.lw`
        Nwells can merge over deep nwell if spacing too small (as in rule nwell.2)
      - :drc_flag:`TC`
      - 0.400
+     - µm
    * - :drc_rule:`(nwell.5a)`
      - min enclosure of nwell by dnwell inside UHVI
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(nwell.5b)`
      - nwell inside UHVI must not be on the same net as nwell outside UHVI
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(nwell.6)`
      - Min enclosure of nwell hole by deep nwell outside UHVI
      - :drc_flag:`TC`
      - 1.030
+     - µm
    * - :drc_rule:`(nwell.7)`
      - Min spacing between nwell and deep nwell on separate nets
        Spacing between nwell and deep nwell on the same net is set by the sum of the rules nwell.2 and nwell.5. By default, DRC run on a cell checks for the separate-net spacing, when nwell and deep nwell nets are separate within the cell hierarchy and are joined in the upper hierarchy. To allow net names to be joined and make the same-net rule applicable in this case, the "joinNets" switch should be turned on.
        waffle_chip
      - :drc_flag:`TC`
      - 4.500
+     - µm
 
 
 .. figure:: periphery/p021-nwell_dotdash.svg
@@ -463,32 +534,38 @@
 .. list-table:: Function: Define p-well block
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(pwbm.1)`
      - Min width of pwbm.dg
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(pwbm.2)`
      - Min spacing between two pwbm.dg inside UHVI
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(pwbm.3)`
      - Min enclosure of dnwell:dg by pwbm.dg inside UHVI (exempt pwbm hole inside dnwell)
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(pwbm.4)`
      - dnwell inside UHVI must be enclosed by pwbm (exempt pwbm hole inside dnwell)
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(pwbm.5)`
      - Min Space between two pwbm holes inside UHVI
      - 
      - N/A
+     - N/A
 
 
 .. figure:: periphery/p022-pwbm_dotdash.svg
@@ -503,36 +580,43 @@
 .. list-table:: Function: Defines Pwdem (FIXME)
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(pwdem.1)`
      - Min width of pwdem.dg
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(pwdem.2)`
      - Min spacing between two pwdem.dg inside UHVI on same net
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(pwdem.3)`
      - Min enclosure of pwdem:dg by pwbm.dg inside UHVI
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(pwdem.4)`
      - pwdem.dg must be enclosed by UHVI
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(pwdem.5)`
      - pwdem.dg inside UHVI must be enclosed by deep nwell
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(pwdem.6)`
      - Min enclosure of pwdem:dg by deep nwell inside UHVI
      - 
      - N/A
+     - N/A
 
 
 .. figure:: periphery/p022-pwdem_dotdash.svg
@@ -547,36 +631,43 @@
 .. list-table:: Function: Define Vt adjust implant region for high Vt LV PMOS; 
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(hvtp.1)`
      - Min width of hvtp
      - 
      - 0.380
+     - µm
    * - :drc_rule:`(hvtp.2)`
      - Min spacing between hvtp to hvtp
      - 
      - 0.380
+     - µm
    * - :drc_rule:`(hvtp.3)`
      - Min enclosure of pfet by hvtp
      - :drc_flag:`P`
      - 0.180
+     - µm
    * - :drc_rule:`(hvtp.4)`
      - Min spacing between pfet and hvtp
      - :drc_flag:`P`
      - 0.180
+     - µm
    * - :drc_rule:`(hvtp.5)`
-     - Min area of hvtp (um^2)
+     - Min area of hvtp
      - 
      - 0.265
+     - µm²
    * - :drc_rule:`(hvtp.6)`
-     - Min area of hvtp Holes (um^2)
+     - Min area of hvtp Holes
      - 
      - 0.265
+     - µm²
 
 
 .. figure:: periphery/p023-hvtp_dotdash.svg
@@ -591,24 +682,28 @@
 .. list-table:: Function: Define low VT adjust implant region for pmedlvtrf; 
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(hvtr.1)`
      - Min width of hvtr
      - 
      - 0.380
+     - µm
    * - :drc_rule:`(hvtr.2)`
      - Min spacing between hvtp to hvtr
      - 
      - 0.380
+     - µm
    * - :drc_rule:`(hvtr.3)`
      - Min enclosure of pfet by hvtr
      - :drc_flag:`P`
      - 0.180
+     - µm
 
 
 
@@ -618,52 +713,63 @@
 .. list-table:: Function: Define regions to block Vt adjust implant for low Vt LV PMOS/NMOS, SONOS FETs and Native NMOS
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(lvtn.1a)`
      - Min width of lvtn
      - 
      - 0.380
+     - µm
    * - :drc_rule:`(lvtn.2)`
      - Min space lvtn to lvtn
      - 
      - 0.380
+     - µm
    * - :drc_rule:`(lvtn.3a)`
      - Min spacing of lvtn to gate. Rule exempted inside UHVI.
      - :drc_flag:`P`
      - 0.180
+     - µm
    * - :drc_rule:`(lvtn.3b)`
      - Min spacing of lvtn to pfet along the S/D direction
      - :drc_flag:`P`
      - 0.235
+     - µm
    * - :drc_rule:`(lvtn.4b)`
      - Min enclosure of gate by lvtn. Rule exempted inside UHVI.
      - :drc_flag:`P`
      - 0.180
+     - µm
    * - :drc_rule:`(lvtn.9)`
      - Min spacing, no overlap, between lvtn and hvtp
      - 
      - 0.380
+     - µm
    * - :drc_rule:`(lvtn.10)`
      - Min enclosure of lvtn by (nwell not overlapping Var_channel) (exclude coincident edges)
      - 
      - 0.380
+     - µm
    * - :drc_rule:`(lvtn.12)`
      - Min spacing between lvtn and (nwell inside :drc_tag:`areaid.ce`)
      - 
      - 0.380
+     - µm
    * - :drc_rule:`(lvtn.13)`
-     - Min area of lvtn (um^2)
+     - Min area of lvtn
      - 
      - 0.265
+     - µm²
    * - :drc_rule:`(lvtn.14)`
-     - Min area of lvtn Holes (um^2)
+     - Min area of lvtn Holes
      - 
      - 0.265
+     - µm²
 
 
 .. figure:: periphery/p024-lvtn_dotdash.svg
@@ -678,56 +784,68 @@
 .. list-table:: Function: Define Vt adjust implant region for LV NMOS in the core of NVSRAM
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(ncm.X.2)`
      - Ncm overlapping areaid:ce is checked for core rules only
      - 
      - 
+     - 
    * - :drc_rule:`(ncm.X.3)`
      - Ncm overlapping core cannot overlap N+diff in periphery
      - :drc_flag:`TC`
      - 
+     - 
    * - :drc_rule:`(ncm.1)`
      - Width of ncm
      - 
      - 0.380
+     - µm
    * - :drc_rule:`(ncm.2a)`
      - Spacing of ncm to ncm
      - 
      - 0.380
+     - µm
    * - :drc_rule:`(ncm.2b)`
      - Manual merge ncm if space is below minimum
      - 
      - 
+     - 
    * - :drc_rule:`(ncm.3)`
      - Min enclosure of P+diff by Ncm
      - :drc_flag:`P`
      - 0.180
+     - µm
    * - :drc_rule:`(ncm.4)`
      - Min enclosure of P+diff within (areaid:ed AndNot areaid:de) by Ncm
      - :drc_flag:`P`
      - 0.180
+     - µm
    * - :drc_rule:`(ncm.5)`
      - Min space, no overlap, between ncm and (LVTN_gate) OR (diff containing lvtn)
      - :drc_flag:`P`
      - 0.230
+     - µm
    * - :drc_rule:`(ncm.6)`
      - Min space, no overlap, between ncm and nfet
      - :drc_flag:`P`
      - 0.200
+     - µm
    * - :drc_rule:`(ncm.7)`
-     - Min area of ncm (um^2)
+     - Min area of ncm
      - 
      - 0.265
+     - µm²
    * - :drc_rule:`(ncm.8)`
-     - Min area of ncm Holes (um^2)
+     - Min area of ncm Holes
      - 
      - 0.265
+     - µm²
 
 
 .. figure:: periphery/p025-ncm_dotdash.svg
@@ -742,72 +860,88 @@
 .. list-table:: Function: Defines active regions and contacts to substrate
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(difftap.1)`
      - Width of diff or tap
      - :drc_flag:`P`
      - 0.150
+     - µm
    * - :drc_rule:`(difftap.2)`
      - Minimum channel width (Diff And Poly) except for FETs inside :drc_tag:`areaid.sc`: Rule exempted in the SP8* flows only, for the cells listed in rule difftap.2a
      - :drc_flag:`P`
      - 0.420
+     - µm
    * - :drc_rule:`(difftap.2a)`
      - Minimum channel width (Diff And Poly) for cell names "s8cell_ee_plus_sseln_a", "s8cell_ee_plus_sseln_b", "s8cell_ee_plus_sselp_a", "s8cell_ee_plus_sselp_b" , "s8fpls_pl8", "s8fpls_rdrv4" , "s8fpls_rdrv4f" and "s8fpls_rdrv8"
      - :drc_flag:`P`
      - NA
+     - µm
    * - :drc_rule:`(difftap.2b)`
      - Minimum channel width (Diff And Poly) for FETs inside :drc_tag:`areaid.sc`
      - :drc_flag:`P`
      - 0.360
+     - µm
    * - :drc_rule:`(difftap.3)`
      - Spacing of diff to diff, tap to tap, or non-abutting diff to tap
      - 
      - 0.270
+     - µm
    * - :drc_rule:`(difftap.4)`
      - Min tap bound by one diffusion
      - 
      - 0.290
+     - 
    * - :drc_rule:`(difftap.5)`
      - Min tap bound by two diffusions
      - :drc_flag:`P`
      - 0.400
+     - 
    * - :drc_rule:`(difftap.6)`
      - Diff and tap are not allowed to extend beyond their abutting edge
      - 
      - 
+     - 
    * - :drc_rule:`(difftap.7)`
      - Spacing of diff/tap abutting edge to a non-conciding diff or tap edge
      - :drc_flag:`NE`
      - 0.130
+     - µm
    * - :drc_rule:`(difftap.8)`
      - Enclosure of (p+) diffusion by N-well. Rule exempted inside UHVI.
      - :drc_flag:`DE` :drc_flag:`NE` :drc_flag:`P`
      - 0.180
+     - µm
    * - :drc_rule:`(difftap.9)`
      - Spacing of (n+) diffusion to N-well outside UHVI
      - :drc_flag:`DE` :drc_flag:`NE` :drc_flag:`P`
      - 0.340
+     - µm
    * - :drc_rule:`(difftap.10)`
      - Enclosure of (n+)  tap by N-well. Rule exempted inside UHVI.
      - :drc_flag:`NE` :drc_flag:`P`
      - 0.180
+     - µm
    * - :drc_rule:`(difftap.11)`
      - Spacing of (p+) tap to  N-well. Rule exempted inside UHVI.
      - 
      - 0.130
+     - µm
    * - :drc_rule:`(difftap.12)`
      - ESD_nwell_tap is considered shorted to the abutting diff
      - :drc_flag:`NC`
      - 
+     - 
    * - :drc_rule:`(difftap.13)`
      - Diffusion or the RF FETS in Table H5 is defined by Ldiff and Wdiff.
      - 
      - 
+     - 
 
 
 .. figure:: periphery/p026-difftap_dotdash.svg
@@ -822,44 +956,53 @@
 .. list-table:: Function: Defines SONOS FETs 
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(tunm.1)`
      - Min width of tunm
      - 
      - 0.410
+     - µm
    * - :drc_rule:`(tunm.2)`
      - Min spacing of tunm to tunm
      - 
      - 0.500
+     - µm
    * - :drc_rule:`(tunm.3)`
      - Extension of tunm beyond (poly and diff)
      - 
      - 0.095
+     - 
    * - :drc_rule:`(tunm.4)`
      - Min spacing of tunm to (poly and diff) outside tunm
      - 
      - 0.095
+     - µm
    * - :drc_rule:`(tunm.5)`
      - (poly and diff) may not straddle tunm
      - 
      - 
+     - 
    * - :drc_rule:`(tunm.6a)`
      - Tunm outside deep n-well is not allowed
      - :drc_flag:`TC`
      - 
+     - 
    * - :drc_rule:`(tunm.7)`
      - Min tunm area
      - 
      - 0.672
+     - µm²
    * - :drc_rule:`(tunm.8)`
      - tunm must be enclosed by :drc_tag:`areaid.ce`
      - 
      - 
+     - 
 
 
 .. figure:: periphery/p027-tunm_dotdash.svg
@@ -874,80 +1017,98 @@
 .. list-table:: Function: Defines FET gates, interconnects and resistors
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(poly.X.1)`
      - All FETs would be checked for W/Ls as documented in spec 001-02735  (Exempt FETs that are pruned; exempt for W/L's inside :drc_tag:`areaid.sc` and inside cell name scs8*decap* and listed in the MRGA as a decap only W/L)
      - 
      - 
+     - 
    * - :drc_rule:`(poly.X.1a)`
      - Min & max dummy_poly L is equal to min L allowed for corresponding device type (exempt rule for dummy_poly in cells listed on Table H3)
      - 
      - 
+     - 
    * - :drc_rule:`(poly.1a)`
      - Width of poly
      - 
      - 0.150
+     - µm
    * - :drc_rule:`(poly.1b)`
      - Min channel length (poly width) for pfet overlapping lvtn (exempt rule for dummy_poly in cells listed on Table H3)
      - 
      - 0.350
+     - µm
    * - :drc_rule:`(poly.2)`
      - Spacing of poly to poly except for poly.c2 and poly.c3; Exempt cell: sr_bltd_eq where it is same as poly.c2
      - 
      - 0.210
+     - µm
    * - :drc_rule:`(poly.3)`
      - Min poly resistor width
      - 
      - 0.330
+     - µm
    * - :drc_rule:`(poly.4)`
      - Spacing of poly on field to diff (parallel edges only)
      - :drc_flag:`P`
      - 0.075
+     - µm
    * - :drc_rule:`(poly.5)`
      - Spacing of poly on field to tap
      - :drc_flag:`P`
      - 0.055
+     - µm
    * - :drc_rule:`(poly.6)`
      - Spacing of poly on diff to abutting tap (min source)
      - :drc_flag:`P`
      - 0.300
+     - µm
    * - :drc_rule:`(poly.7)`
      - Extension of diff beyond poly (min drain)
      - :drc_flag:`P`
      - 0.250
+     - 
    * - :drc_rule:`(poly.8)`
      - Extension of poly beyond diffusion (endcap)
      - :drc_flag:`P`
      - 0.130
+     - 
    * - :drc_rule:`(poly.9)`
      - Poly resistor spacing to poly or spacing (no overlap) to diff/tap
      - 
      - 0.480
+     - µm
    * - :drc_rule:`(poly.10)`
      - Poly can't overlap inner corners of diff
      - 
      - 
+     - 
    * - :drc_rule:`(poly.11)`
      - No 90 deg turns of poly on diff
      - 
      - 
+     - 
    * - :drc_rule:`(poly.12)`
      - (Poly NOT (nwell NOT hvi)) may not overlap tap; Rule exempted for cell name "s8fgvr_n_fg2" and gated_npn and inside UHVI.
      - :drc_flag:`P`
      - 
+     - 
    * - :drc_rule:`(poly.15)`
      - Poly must not overlap diff:rs
      - 
      - 
+     - 
    * - :drc_rule:`(poly.16)`
      - Inside RF FETs defined in Table H5, poly cannot overlap poly across multiple adjacent instances
      - 
      - 
+     - 
 
 
 .. figure:: periphery/p028-poly_dotdash.svg
@@ -962,92 +1123,113 @@
 .. list-table:: Function: Defines p+ poly resistors
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(rpm.1a)`
      - Min width of rpm
      - 
      - 1.270
+     - µm
    * - :drc_rule:`(rpm.1b)`
      - Min/Max prec_resistor width xhrpoly_0p35
      - 
      - 0.350
+     - µm
    * - :drc_rule:`(rpm.1c)`
      - Min/Max prec_resistor width xhrpoly_0p69
      - 
      - 0.690
+     - µm
    * - :drc_rule:`(rpm.1d)`
      - Min/Max prec_resistor width xhrpoly_1p41
      - 
      - 1.410
+     - µm
    * - :drc_rule:`(rpm.1e)`
      - Min/Max prec_resistor width xhrpoly_2p85
      - 
      - 2.850
+     - µm
    * - :drc_rule:`(rpm.1f)`
      - Min/Max prec_resistor width xhrpoly_5p73
      - 
      - 5.730
+     - µm
    * - :drc_rule:`(rpm.1g)`
      - Only 1 licon is allowed in xhrpoly_0p35 prec_resistor_terminal
      - 
      - 
+     - 
    * - :drc_rule:`(rpm.1h)`
      - Only 1 licon is allowed in xhrpoly_0p69 prec_resistor_terminal
      - 
      - 
+     - 
    * - :drc_rule:`(rpm.1i)`
      - Only 2 licons are allowed in xhrpoly_1p41 prec_resistor_terminal
      - 
      - 
+     - 
    * - :drc_rule:`(rpm.1j)`
      - Only 4 licons are allowed in xhrpoly_2p85 prec_resistor_terminal
      - 
      - 
+     - 
    * - :drc_rule:`(rpm.1k)`
      - Only 8 licons are allowed in xhrpoly_5p73 prec_resistor_terminal
      - 
      - 
+     - 
    * - :drc_rule:`(rpm.2)`
      - Min spacing of rpm to rpm
      - 
      - 0.840
+     - µm
    * - :drc_rule:`(rpm.3)`
      - rpm must enclose prec_resistor by atleast
      - 
      - 0.200
+     - 
    * - :drc_rule:`(rpm.4)`
      - prec_resistor must be enclosed by psdm by atleast
      - 
      - 0.110
+     - µm
    * - :drc_rule:`(rpm.5)`
      - prec_resistor must be enclosed by npc by atleast
      - 
      - 0.095
+     - µm
    * - :drc_rule:`(rpm.6)`
      - Min spacing, no overlap, of rpm and nsdm
      - 
      - 0.200
+     - µm
    * - :drc_rule:`(rpm.7)`
      - Min spacing between rpm and poly
      - 
      - 0.200
+     - µm
    * - :drc_rule:`(rpm.8)`
      - poly must not straddle rpm
      - 
      - 
+     - 
    * - :drc_rule:`(rpm.9)`
      - Min space, no overlap, between prec_resistor and hvntm
      - 
      - 0.185
+     - µm
    * - :drc_rule:`(rpm.10)`
      - Min spacing of rpm to pwbm
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(rpm.11)`
      - | rpm should not overlap or straddle pwbm except cells
        | s8usbpdv2_csa_top
@@ -1056,6 +1238,7 @@
        | s8usbpdv2_20sbu_sw_300ma_ovp
      - 
      - N/A
+     - N/A
 
 
 .. figure:: periphery/p029-rpm_dotdash.svg
@@ -1070,44 +1253,53 @@
 .. list-table:: Function: Defines varactors
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(varac.1)`
      - Min channel length (poly width) of Var_channel
      - 
      - 0.180
+     - µm
    * - :drc_rule:`(varac.2)`
      - Min channel width (tap width) of Var_channel
      - 
      - 1.000
+     - µm
    * - :drc_rule:`(varac.3)`
      - Min spacing between hvtp to Var_channel
      - 
      - 0.180
+     - µm
    * - :drc_rule:`(varac.4)`
      - Min spacing of licon on tap to Var_channel
      - 
      - 0.250
+     - µm
    * - :drc_rule:`(varac.5)`
      - Min enclosure of poly overlapping Var_channel by nwell
      - 
      - 0.150
+     - µm
    * - :drc_rule:`(varac.6)`
      - Min spacing between VaracTap and difftap
      - 
      - 0.270
+     - µm
    * - :drc_rule:`(varac.7)`
      - Nwell overlapping Var_channel must not overlap P+ diff
      - 
      - 
+     - 
    * - :drc_rule:`(varac.8)`
      - Min enclosure of Var_channel by hvtp
      - 
      - 0.255
+     - µm
 
 
 .. figure:: periphery/p030-varac_dotdash.svg
@@ -1122,56 +1314,68 @@
 .. list-table:: Function: Photo diode for sensing light
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(photo.1)`
      - Rules dnwell.3 and nwell.5 are exempted for photoDiode
      - 
      - 
+     - 
    * - :drc_rule:`(photo.2)`
      - Min/Max width of photoDiode
      - 
      - 3.000
+     - µm
    * - :drc_rule:`(photo.3)`
      - Min spacing between photoDiode
      - 
      - 5.000
+     - µm
    * - :drc_rule:`(photo.4)`
      - Min spacing between photoDiode and deep nwell
      - 
      - 5.300
+     - µm
    * - :drc_rule:`(photo.5)`
      - photoDiode edges must be coincident with :drc_tag:`areaid.po`
      - 
      - 
+     - 
    * - :drc_rule:`(photo.6)`
      - photoDiode must be enclosed by dnwell ring
      - 
      - 
+     - 
    * - :drc_rule:`(photo.7)`
      - photoDiode must be enclosed by p+ tap ring
      - 
      - 
+     - 
    * - :drc_rule:`(photo.8)`
      - Min/Max width of nwell inside photoDiode
      - 
      - 0.840
+     - µm
    * - :drc_rule:`(photo.9)`
      - Min/Max enclosure of nwell by photoDiode
      - 
      - 1.080
+     - µm
    * - :drc_rule:`(photo.10)`
      - Min/Max width of tap inside photoDiode
      - 
      - 0.410
+     - µm
    * - :drc_rule:`(photo.11)`
      - Min/Max enclosure of tap by nwell inside photoDiode
      - 
      - 0.215
+     - µm
 
 
 .. figure:: periphery/p031-photo_dotdash.svg
@@ -1186,32 +1390,38 @@
 .. list-table:: Function: Defines nitride openings to contact poly and Li1
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(npc.1)`
      - Min width of NPC
      - 
      - 0.270
+     - µm
    * - :drc_rule:`(npc.2)`
      - Min spacing of NPC to NPC
      - 
      - 0.270
+     - µm
    * - :drc_rule:`(npc.3)`
      - Manual merge if less than minimum
      - 
      - 
+     - 
    * - :drc_rule:`(npc.4)`
      - Spacing (no overlap) of NPC to Gate
      - 
      - 0.090
+     - µm
    * - :drc_rule:`(npc.5)`
      - Max enclosure of poly overlapping slotted_licon by npcm (merge between adjacent short edges of the slotted_licons if space < min)
      - 
      - 0.095
+     - µm
 
 
 .. figure:: periphery/p032-npc_dotdash.svg
@@ -1226,44 +1436,53 @@
 .. list-table:: Function: Defines opening for N+/P+ implants
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(n/ psd.1)`
      - Width of nsdm(psdm)
      - :drc_flag:`P`
      - 0.380
+     - µm
    * - :drc_rule:`(n/ psd.2)`
      - Spacing of nsdm(psdm) to nsdm(psdm)
      - :drc_flag:`P`
      - 0.380
+     - µm
    * - :drc_rule:`(n/ psd.3)`
      - Manual merge if less than minimum
      - 
      - 
+     - 
    * - :drc_rule:`(n/ psd.5a)`
      - Enclosure of diff by nsdm(psdm), except for butting edge
      - 
      - 0.125
+     - µm
    * - :drc_rule:`(n/ psd.5b)`
      - Enclosure of tap by nsdm(psdm), except for butting edge
      - :drc_flag:`P`
      - 0.125
+     - µm
    * - :drc_rule:`(n/ psd.6)`
      - Enclosure of diff/tap butting edge by nsdm (psdm)
      - 
      - 0.000
+     - µm
    * - :drc_rule:`(n/ psd.7)`
      - Spacing of NSDM/PSDM to opposite implant diff or tap (for non-abutting diff/tap edges)
      - 
      - 0.130
+     - µm
    * - :drc_rule:`(n/ psd.8)`
      - Nsdm and psdm cannot overlap diff/tap regions of opposite doping
      - :drc_flag:`DE`
      - 
+     - 
    * - :drc_rule:`(n/ psd.9)`
      - Diff and tap must be enclosed by their corresponding implant layers. Rule exempted for
          - diff inside "advSeal_6um* OR cuPillarAdvSeal_6um*" pcell for SKY130P*/SP8P*/SKY130DI-5R-CSMC flows
@@ -1272,18 +1491,22 @@
          - :drc_tag:`areaid.zer`.
      - :drc_flag:`DE`
      - 
+     - 
    * - :drc_rule:`(n/ psd.10a)`
-     - Min area of Nsdm (um^2)
+     - Min area of Nsdm
      - 
      - 0.265
+     - µm²
    * - :drc_rule:`(n/ psd.10b)`
-     - Min area of Psdm (um^2)
+     - Min area of Psdm
      - 
      - 0.255
+     - µm²
    * - :drc_rule:`(n/ psd.11)`
-     - Min area of n/psdmHoles (um^2)
+     - Min area of n/psdmHoles
      - 
      - 0.265
+     - µm²
 
 
 .. figure:: periphery/p032-n_psd_dotdash.svg
@@ -1298,137 +1521,169 @@
 .. list-table:: Function: Defines contacts between poly/diff/tap and Li1
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(licon.1)`
      - Min and max L and W of licon (exempt licons inside prec_resistor)
      - 
      - 0.170
+     - µm
    * - :drc_rule:`(licon.1b)`
      - Min and max width of licon inside prec_resistor
      - 
      - 0.190
+     - µm
    * - :drc_rule:`(licon.1c)`
      - Min and max length of licon inside prec_resistor
      - 
      - 2.000
+     - µm
    * - :drc_rule:`(licon.2)`
      - Spacing of licon to licon
      - :drc_flag:`P`
      - 0.170
+     - µm
    * - :drc_rule:`(licon.2b)`
      - Min spacing between two slotted_licon (when the both the edges are 0.19um in length)
      - 
      - 0.350
+     - µm
    * - :drc_rule:`(licon.2c)`
      - Min spacing between two slotted_licon (except for rule licon.2b)
      - 
      - 0.510
+     - µm
    * - :drc_rule:`(licon.2d)`
      - Min spacing between a slotted_licon and 0.17um square licon
      - 
      - 0.510
+     - µm
    * - :drc_rule:`(licon.3)`
      - Only min. square licons are allowed except die seal ring where licons are (licon CD)*L
      - 
      - 0.170 *L
+     - 
    * - :drc_rule:`(licon.4)`
      - Licon1 must overlap li1 and (poly or diff or tap)
      - 
      - 
+     - 
    * - :drc_rule:`(licon.5a)`
      - Enclosure of licon by diff
      - :drc_flag:`P`
      - 0.040
+     - µm
    * - :drc_rule:`(licon.5b)`
      - Min space between tap_licon and diff-abutting tap edge
      - :drc_flag:`P`
      - 0.060
+     - µm
    * - :drc_rule:`(licon.5c)`
      - Enclosure of licon by diff on one of two adjacent sides
      - :drc_flag:`P`
      - 0.060
+     - µm
    * - :drc_rule:`(licon.6)`
      - Licon cannot straddle tap
      - :drc_flag:`P`
      - 
+     - 
    * - :drc_rule:`(licon.7)`
      - Enclosure of licon by one of two adjacent edges of isolated tap
      - :drc_flag:`P`
      - 0.120
+     - µm
    * - :drc_rule:`(licon.8)`
      - Enclosure of poly_licon by poly
      - :drc_flag:`P`
      - 0.050
+     - µm
    * - :drc_rule:`(licon.8a)`
      - Enclosure of poly_licon by poly on one of two adjacent sides
      - :drc_flag:`P`
      - 0.080
+     - µm
    * - :drc_rule:`(licon.9)`
      - Spacing, no overlap, between poly_licon and psdm; In SKY130DIA/SKY130TMA/SKY130PIR-10 flows, the rule is checked only between (poly_licon outside rpm) and psdm
      - :drc_flag:`P`
      - 0.110
+     - µm
    * - :drc_rule:`(licon.10)`
      - Spacing of licon on (tap AND (nwell NOT hvi)) to Var_channel
      - :drc_flag:`P`
      - 0.250
+     - µm
    * - :drc_rule:`(licon.11)`
      - Spacing of licon on diff or tap to poly on diff (except for all FETs inside :drc_tag:`areaid.sc` and except s8spf-10r flow for 0.5um phv inside cell names "s8fs_gwdlvx4", "s8fs_gwdlvx8", "s8fs_hvrsw_x4", "s8fs_hvrsw8", "s8fs_hvrsw264", and "s8fs_hvrsw520" and for 0.15um nshort inside cell names "s8fs_rdecdrv", "s8fs_rdec8", "s8fs_rdec32", "s8fs_rdec264", "s8fs_rdec520")
      - :drc_flag:`P`
      - 0.055
+     - µm
    * - :drc_rule:`(licon.11a)`
      - Spacing of licon on diff or tap to poly on diff (for all FETs inside :drc_tag:`areaid.sc` except 0.15um phighvt)
      - :drc_flag:`P`
      - 0.050
+     - µm
    * - :drc_rule:`(licon.11b)`
      - Spacing of licon on diff or tap to poly on diff (for 0.15um phighvt inside :drc_tag:`areaid.sc`)
      - :drc_flag:`P`
      - 0.050
+     - µm
    * - :drc_rule:`(licon.11c)`
      - Spacing of licon on diff or tap to poly on diff (for 0.5um phv inside cell names "s8fs_gwdlvx4", "s8fs_gwdlvx8", "s8fs_hvrsw_x4", "s8fs_hvrsw8", "s8fs_hvrsw264", and "s8fs_hvrsw520")
      - :drc_flag:`P`
      - 0.040
+     - µm
    * - :drc_rule:`(licon.11d)`
      - Spacing of licon on diff or tap to poly on diff (for 0.15um nshort inside cell names "s8fs_rdecdrv", "s8fs_rdec8", "s8fs_rdec32", "s8fs_rdec264", "s8fs_rdec520")
      - :drc_flag:`P`
      - 0.045
+     - µm
    * - :drc_rule:`(licon.12)`
      - Max SD width without licon
      - :drc_flag:`NC`
      - 5.700
+     - µm
    * - :drc_rule:`(licon.13)`
      - Spacing (no overlap) of NPC to licon on diff or tap
      - :drc_flag:`P`
      - 0.090
+     - µm
    * - :drc_rule:`(licon.14)`
      - Spacing of poly_licon to diff or tap
      - :drc_flag:`P`
      - 0.190
+     - µm
    * - :drc_rule:`(licon.15)`
      - poly_licon must be enclosed by npc by…
      - :drc_flag:`P`
      - 0.100
+     - µm
    * - :drc_rule:`(licon.16)`
      - | Every source_diff and every tap must enclose at least one licon1, including the diff/tap straddling areaid:ce. 
        | Rule exempted inside UHVI.
      - :drc_flag:`P`
      - 
+     - 
    * - :drc_rule:`(licon.17)`
      - Licons may not overlap both poly and (diff or tap)
      - 
      - 
+     - 
    * - :drc_rule:`(licon.18)`
      - Npc must enclose poly_licon
      - 
      - 
+     - 
    * - :drc_rule:`(licon.19)`
      - poly of the HV varactor must not interact with licon
      - :drc_flag:`P`
      - 
+     - 
 
 
 .. figure:: periphery/p034-licon_dotdash.svg
@@ -1443,44 +1698,53 @@
 .. list-table:: Function: Defines local interconnect to diff/tap and poly
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(li.1.-)`
      - Width of LI (except for li.1a)
      - :drc_flag:`P`
      - 0.170
+     - µm
    * - :drc_rule:`(li.1a.-)`
      - Width of LI inside of cells with name s8rf2_xcmvpp_hd5_*
      - :drc_flag:`P`
      - 0.140
+     - µm
    * - :drc_rule:`(li.2.-)`
      - Max ratio of length to width of LI without licon or mcon
      - :drc_flag:`NC`
      - 10.000
+     - µm
    * - :drc_rule:`(li.3.-)`
      - Spacing of LI to LI (except for li.3a)
      - :drc_flag:`P`
      - 0.170
+     - µm
    * - :drc_rule:`(li.3a.-)`
      - Spacing of LI to LI inside cells with names s8rf2_xcmvpp_hd5_*
      - :drc_flag:`P`
      - 0.140
+     - µm
    * - :drc_rule:`(li.5.-)`
      - Enclosure of licon by one of two adjacent LI sides
      - :drc_flag:`P`
      - 0.080
+     - µm
    * - :drc_rule:`(li.6.-)`
      - Min area of LI
      - :drc_flag:`P`
      - 0.0561
+     - µm²
    * - :drc_rule:`(li.7.-)`
      - Min LI resistor width (rule exempted within :drc_tag:`areaid.ed`; Inside :drc_tag:`areaid.ed`, min width of the li resistor is determined by rule li.1)
      - 
      - 0.290
+     - µm
 
 
 .. figure:: periphery/p035-li_dotdash_dotdash.svg
@@ -1495,40 +1759,48 @@
 .. list-table:: Function: Defines contact between Li1 and met1
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(ct.1)`
      - Min and max L and W of mcon
      - :drc_flag:`DNF`
      - 0.170
+     - µm
    * - :drc_rule:`(ct.2)`
      - Spacing of mcon to mcon
      - :drc_flag:`DNF`
      - 0.190
+     - µm
    * - :drc_rule:`(ct.3)`
      - Only min. square mcons are allowed except die seal ring where mcons are…
      - 
      - 0.170*L
+     - 
    * - :drc_rule:`(ct.4)`
      - Mcon must be enclosed by LI by at least …
      - :drc_flag:`P`
      - 0.000
+     - µm
    * - :drc_rule:`(ct.irdrop.1)`
      - For 1 <= n <= 10 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.2
+     - µm
    * - :drc_rule:`(ct.irdrop.2)`
      - For 11 <= n <= 100 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.3
+     - µm
    * - :drc_rule:`(ct.irdrop.3)`
      - For n > 100 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.7
+     - µm
 
 
 .. figure:: periphery/p035-ct_dotdash.svg
@@ -1543,60 +1815,73 @@
 .. list-table:: Function: Defines MIM capacitor
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(capm.1)`
      - Min width of capm
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(capm.2a)`
      - Min spacing of capm to capm
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(capm.2b)`
      - Minimum spacing of capacitor bottom_plate to bottom plate
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(capm.3)`
      - Minimum enclosure of capm (top_plate) by met2
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(capm.4)`
      - Min enclosure of via2 by capm
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(capm.5)`
      - Min spacing between capm and via2
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(capm.6)`
      - Maximum Aspect Ratio (Length/Width)
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(capm.7)`
      - Only rectangular capacitors are allowed
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(capm.8)`
      - Min space, no overlap, between via and capm
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(capm.10)`
      - capm must not straddle nwell, diff, tap, poly, li1 and met1 (Rule exempted for capm overlapping capm_2t.dg)
      - :drc_flag:`TC`
      - N/A
+     - N/A
    * - :drc_rule:`(capm.11)`
      - Min spacing between capm to (met2 not overlapping capm)
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(capm.12)`
      - Max area of capm (um^2)
      - 
      - N/A
+     - N/A
 
 
 .. figure:: periphery/p036-capm_dotdash.svg
@@ -1611,84 +1896,103 @@
 .. list-table:: Function: Defines VPP capacitor
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(vpp.1)`
      - Min width of capacitor:dg
      - 
      - 1.430
+     - µm
    * - :drc_rule:`(vpp.1b)`
      - Max width of capacitor:dg; Rule not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5 and vpp_with_noLi
      - 
      - 11.350
+     - µm
    * - :drc_rule:`(vpp.1c)`
      - Min/Max width of cell name "s8rf_xcmvpp1p8x1p8_m3shield "
      - 
      - 3.880
+     - µm
    * - :drc_rule:`(vpp.3)`
      - capacitor:dg must not overlap (tap or diff or poly); (one exception: Poly is allowed to overlap  vpp_with_Met3Shield and vpp_with_Met5PolyShield); (not applicable for vpp_over_Moscap or "s8rf2_xcmvppx4_2xnhvnative10x4" or vpp_with_LiShield)
      - 
      - 
+     - 
    * - :drc_rule:`(vpp.4)`
      - capacitor:dg must not straddle (nwell or dnwell)
      - 
      - 
+     - 
    * - :drc_rule:`(vpp.5)`
-     - Min spacing between (capacitor:dg edge and (poly or li1 or met1 or met2)) to (poly or li1 or met1 or met2) on separate nets (Exempt area of the error shape less than 2.25 (um^2) and run length less than 2.0um); Rule not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5 and vpp_with_noLi
+     - Min spacing between (capacitor:dg edge and (poly or li1 or met1 or met2)) to (poly or li1 or met1 or met2) on separate nets (Exempt area of the error shape less than 2.25 µm² and run length less than 2.0um); Rule not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5 and vpp_with_noLi
      - 
      - 1.500
+     - µm
    * - :drc_rule:`(vpp.5a)`
      - Max pattern density of met3.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5)
      - 
      - 0.25
+     - \-
    * - :drc_rule:`(vpp.5b)`
      - Max pattern density of met4.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_Met5 and vpp_over_MOSCAP)
      - 
      - 0.3
+     - \-
    * - :drc_rule:`(vpp.5c)`
      - Max pattern density of met5.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_Met5 and vpp_over_MOSCAP and vpp_with_noLi); (one exception: rules does apply to cell "s8rf2_xcmvpp11p5x11p7_m1m4" and "s8rf2_xcmvpp_hd5_atlas*")
      - 
      - 0.4
+     - \-
    * - :drc_rule:`(vpp.8)`
      - Min enclosure of capacitor:dg by nwell
      - 
      - 1.500
+     - µm
    * - :drc_rule:`(vpp.9)`
      - Min spacing of capacitor:dg to nwell (not applicable for vpp_over_MOSCAP)
      - 
      - 1.500
+     - µm
    * - :drc_rule:`(vpp.10)`
      - vpp capacitors must not overlap; Rule checks for capacitor.dg overlapping more than one pwell pin
      - 
      - 
+     - 
    * - :drc_rule:`(vpp.11)`
      - Min pattern density of (poly and diff) over capacitor.dg; (vpp_over_Moscap only)
      - 
      - 0.87
+     - \-
    * - :drc_rule:`(vpp.12a)`
      - Number of met4 shapes inside capacitor.dg of cell "s8rf2_xcmvpp8p6x7p9_m3_lim5shield"  must overlap with size 2.01 x 2.01 (no other met4 shapes allowed)
      - 
      - 9.00
+     - µm
    * - :drc_rule:`(vpp.12b)`
      - Number of met4 shapes inside capacitor.dg of cell "s8rf2_xcmvpp11p5x11p7_m3_lim5shield"  must overlap with size 2.01 x 2.01 (no other met4 shapes allowed)
      - 
      - 16.00
+     - µm
    * - :drc_rule:`(vpp.12c)`
      - Number of met4 shapes inside capacitor.dg of cell "s8rf2_xcmvpp4p4x4p6_m3_lim5shield"  must overlap with size 1.5 x 1.5 (no other met4 shapes allowed)
      - 
      - 4.00
+     - µm
    * - :drc_rule:`(vpp.13)`
      - Min space of met1 to met1inside VPP capacitor
      - :drc_flag:`CU`
      - 0.160
+     - µm
    * - :drc_rule:`(vpp.14)`
      - Min space of met2 to met2 inside VPP capacitor
      - :drc_flag:`CU`
      - 0.160
+     - µm
 
 
 .. figure:: periphery/p037-vpp_dotdash.svg
@@ -1703,12 +2007,13 @@
 .. list-table:: Function: Defines first level of metal interconnects, buses etc;
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(m1.-)`
      - | Algorithm should flag errors, for met1, if ANY of the following is true:
        | An entire 700x700 window is covered by cmm1 waffleDrop, and metX PD < 70% for same window.
@@ -1720,78 +2025,97 @@
        | Exclude cells whose area is below 40Kum2. NOTE: Required for IP, Recommended for Chip-level.
      - :drc_flag:`RC`
      - 
+     - 
    * - :drc_rule:`(m1.1)`
      - Width of metal1
      - 
      - 0.140
+     - µm
    * - :drc_rule:`(m1.2)`
      - Spacing of metal1 to metal1
      - 
      - 0.140
+     - µm
    * - :drc_rule:`(m1.3a)`
-     - Min. spacing of features attached to or extending from huge_met1 for a distance of up to  0.280 um to metal1 (rule not checked over non-huge met1 features)
+     - Min. spacing of features attached to or extending from huge_met1 for a distance of up to  0.280 µm to metal1 (rule not checked over non-huge met1 features)
      - 
      - 0.280
+     - µm
    * - :drc_rule:`(m1.3b)`
      - Min. spacing of huge_met1 to metal1 excluding features checked by m1.3a
      - 
      - 0.280
+     - µm
    * - :drc_rule:`(m1.4)`
      - Mcon must be enclosed by Met1 by at least …(Rule exempted for cell names documented in rule m1.4a)
      - :drc_flag:`P`
      - 0.030
+     - µm
    * - :drc_rule:`(m1.4a)`
      - Mcon must be enclosed by Met1 by at least (for cell names "s8cell_ee_plus_sseln_a", "s8cell_ee_plus_sseln_b", "s8cell_ee_plus_sselp_a", "s8cell_ee_plus_sselp_b", "s8fpls_pl8", and "s8fs_cmux4_fm")
      - :drc_flag:`P`
      - 0.005
+     - µm
    * - :drc_rule:`(m1.5)`
      - Mcon must be enclosed by Met1 on one of two adjacent sides by at least …
      - :drc_flag:`P` :drc_flag:`AL`
      - 0.060
+     - µm
    * - :drc_rule:`(m1.6)`
-     - Min metal 1 area [um2]
+     - Min metal 1 area
      - 
      - 0.083
+     - µm²
    * - :drc_rule:`(m1.7)`
-     - Min area of metal1 holes [um2]
+     - Min area of metal1 holes
      - 
      - 0.140
+     - µm²
    * - :drc_rule:`(m1.pd.1)`
      - Min MM1_oxide_Pattern_density
      - :drc_flag:`RR` :drc_flag:`AL`
      - 0.7
+     - \-
    * - :drc_rule:`(m1.pd.2a)`
      - Rule m1.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …
      - :drc_flag:`A` :drc_flag:`AL`
      - 700
+     - µm
    * - :drc_rule:`(m1.pd.2b)`
      - Rule m1.pd.1 has to be checked by dividing the chip into steps of …
      - :drc_flag:`A` :drc_flag:`AL`
      - 70
+     - 
    * - :drc_rule:`(m1.11)`
      - Max width of metal1after slotting
      - :drc_flag:`CU` :drc_flag:`NC`
      - 4.000
+     - µm
    * - :drc_rule:`(m1.12)`
      - Add slots and remove vias and contacts if met1 wider than…..
      - :drc_flag:`CU`
      - 3.200
+     - 
    * - :drc_rule:`(m1.13)`
      - Max pattern density (PD) of met1
      - :drc_flag:`CU`
      - 0.77
+     - \-
    * - :drc_rule:`(m1.14)`
      - Met1 PD window size
      - :drc_flag:`CU`
      - 50.000
+     - µm
    * - :drc_rule:`(m1.14a)`
      - Met1 PD window step
      - :drc_flag:`CU`
      - 25.000
+     - µm
    * - :drc_rule:`(m1.15)`
      - Mcon must be enclosed by met1 on one of two adjacent sides by at least …
      - :drc_flag:`CU`
      - 0.030
+     - µm
 
 
 .. figure:: periphery/p038-m1_dotdash.svg
@@ -1806,88 +2130,108 @@
 .. list-table:: Function: Defines contact between met1  and met2
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(via.1a)`
      - Min and max L and W of via outside :drc_tag:`areaid.mt`
      - :drc_flag:`AL`
      - 0.150
+     - µm
    * - :drc_rule:`(via.1b)`
      - Three sizes of square Vias allowed inside areaid:mt: 0.150um, 0.230um and 0.280um
      - :drc_flag:`AL`
      - 
+     - 
    * - :drc_rule:`(via.2)`
      - Spacing of via to via
      - :drc_flag:`AL`
      - 0.170
+     - µm
    * - :drc_rule:`(via.3)`
      - Only min. square vias are allowed except die seal ring where vias are (Via CD)*L
      - 
      - 0.2*L
+     - 
    * - :drc_rule:`(via.4a)`
-     - 0.150 um Via must be enclosed by Met1 by at least …
+     - 0.150 µm Via must be enclosed by Met1 by at least …
      - 
      - 0.055
+     - µm
    * - :drc_rule:`(via.4b)`
-     - Inside :drc_tag:`areaid.mt`, 0.230 um Via must be enclosed by met1 by atleast
+     - Inside :drc_tag:`areaid.mt`, 0.230 µm Via must be enclosed by met1 by atleast
      - :drc_flag:`AL`
      - 0.030
+     - µm
    * - :drc_rule:`(via.4c)`
-     - Inside :drc_tag:`areaid.mt`, 0.280 um Via must be enclosed by met1 by atleast
+     - Inside :drc_tag:`areaid.mt`, 0.280 µm Via must be enclosed by met1 by atleast
      - :drc_flag:`AL`
      - 0.000
+     - µm
    * - :drc_rule:`(via.5a)`
-     - 0.150 um Via must be enclosed by Met1 on one of two adjacent sides by at least …
+     - 0.150 µm Via must be enclosed by Met1 on one of two adjacent sides by at least …
      - 
      - 0.085
+     - µm
    * - :drc_rule:`(via.5b)`
-     - Inside :drc_tag:`areaid.mt`, 0.230 um Via must be enclosed by met1 on one of two adjacent sides by at least …
+     - Inside :drc_tag:`areaid.mt`, 0.230 µm Via must be enclosed by met1 on one of two adjacent sides by at least …
      - :drc_flag:`AL`
      - 0.060
+     - µm
    * - :drc_rule:`(via.5c)`
-     - Inside :drc_tag:`areaid.mt`, 0.280 um Via must be enclosed by met1 on one of two adjacent sides by at least …
+     - Inside :drc_tag:`areaid.mt`, 0.280 µm Via must be enclosed by met1 on one of two adjacent sides by at least …
      - :drc_flag:`AL`
      - 0.000
+     - µm
    * - :drc_rule:`(via.11)`
      - Min and max L and W of via outside :drc_tag:`areaid.mt`
      - :drc_flag:`CU`
      - 0.180
+     - µm
    * - :drc_rule:`(via.12)`
      - Min spacing between vias
      - :drc_flag:`CU`
      - 0.130
+     - µm
    * - :drc_rule:`(via.13)`
      - Max of 5 vias within …
      - :drc_flag:`CU`
      - 0.350
+     - µm
    * - :drc_rule:`(via.14)`
-     - 0.180 um Via must be enclosed by parallel edges of Met1 by at least …
+     - 0.180 µm Via must be enclosed by parallel edges of Met1 by at least …
      - :drc_flag:`CU`
      - 0.040
+     - µm
    * - :drc_rule:`(via.irdrop.1)`
      - For 1 <= n <= 2 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.0
+     - µm
    * - :drc_rule:`(via.irdrop.2)`
      - For 3 <= n <= 15 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.6
+     - µm
    * - :drc_rule:`(via.irdrop.3)`
      - For 16 <= n <= 30 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.8
+     - µm
    * - :drc_rule:`(via.irdrop.4)`
      - For n > 30 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.9
+     - µm
    * - :drc_rule:`(via.14a)`
-     - 0.180 um Via must be enclosed by 45 deg edges of Met1 by at least …
+     - 0.180 µm Via must be enclosed by 45 deg edges of Met1 by at least …
      - :drc_flag:`CU`
      - 0.037
+     - deg µm
 
 
 .. figure:: periphery/p039-via_dotdash.svg
@@ -1902,12 +2246,13 @@
 .. list-table:: Function: Defines second level of metal interconnects, buses etc
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(m2.-)`
      - | Algorithm should flag errors, for met2, if ANY of the following is true:
        | An entire 700x700 window is covered by cmm2 waffleDrop, and metX PD < 70% for same window.
@@ -1919,78 +2264,97 @@
        | Exclude cells whose area is below 40Kum2. Required for IP, Recommended for Chip-level.
      - :drc_flag:`RC`
      - 
+     - 
    * - :drc_rule:`(m2.1)`
      - Width of metal 2
      - 
      - 0.140
+     - µm
    * - :drc_rule:`(m2.2)`
      - Spacing of metal 2 to metal 2
      - 
      - 0.140
+     - µm
    * - :drc_rule:`(m2.3a)`
-     - Min. spacing of features attached to or extending from huge_met2 for a distance of up to  0.280 um to metal2 (rule not checked over non-huge met2 features)
+     - Min. spacing of features attached to or extending from huge_met2 for a distance of up to  0.280 µm to metal2 (rule not checked over non-huge met2 features)
      - 
      - 0.280
+     - µm
    * - :drc_rule:`(m2.3b)`
      - Min. spacing of huge_met2 to metal2 excluding features checked by m2.3a
      - 
      - 0.280
+     - µm
    * - :drc_rule:`(m2.3c)`
      - Min spacing between floating_met2 with AR_met2_A >= 0.05 and AR_met2_B =< 0.032, outside areaid:sc must be greater than
      - :drc_flag:`RR`
      - 0.145
+     - µm
    * - :drc_rule:`(m2.4)`
      - Via must be enclosed by Met2 by at least …
      - :drc_flag:`P` :drc_flag:`AL`
      - 0.055
+     - µm
    * - :drc_rule:`(m2.5)`
      - Via must be enclosed by Met2 on one of two adjacent sides by at least …
      - :drc_flag:`AL`
      - 0.085
+     - µm
    * - :drc_rule:`(m2.6)`
-     - Min metal2 area [um2]
+     - Min metal2 area
      - 
      - 0.0676
+     - µm²
    * - :drc_rule:`(m2.7)`
-     - Min area of metal2 holes [um2]
+     - Min area of metal2 holes
      - 
      - 0.140
+     - µm²
    * - :drc_rule:`(m2.pd.1)`
      - Min MM2_oxide_Pattern_density
      - :drc_flag:`RR`
      - 0.7
+     - \-
    * - :drc_rule:`(m2.pd.2a)`
      - Rule m2.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …
      - :drc_flag:`A`
      - 700
+     - µm
    * - :drc_rule:`(m2.pd.2b)`
      - Rule m2.pd.1 has to be checked by dividing the chip into steps of …
      - :drc_flag:`A`
      - 70
+     - 
    * - :drc_rule:`(m2.11)`
      - Max width of metal2
      - :drc_flag:`CU`
      - 4.000
+     - µm
    * - :drc_rule:`(m2.12)`
      - Add slots and remove vias and contacts if met2 wider than…..
      - :drc_flag:`CU`
      - 3.200
+     - 
    * - :drc_rule:`(m2.13)`
      - Max pattern density (PD) of metal2
      - :drc_flag:`CU`
      - 0.77
+     - \-
    * - :drc_rule:`(m2.14)`
      - Met2 PD window size
      - :drc_flag:`CU`
      - 50.000
+     - µm
    * - :drc_rule:`(m2.14a)`
      - Met2 PD window step
      - :drc_flag:`CU`
      - 25.000
+     - µm
    * - :drc_rule:`(m2.15)`
      - Via must be enclosed by met2 by at least…
      - :drc_flag:`CU`
      - 0.040
+     - µm
 
 
 .. figure:: periphery/p040-m2_dotdash.svg
@@ -2005,92 +2369,113 @@
 .. list-table:: Function: Via2 connects met2 to met3 in the SKY130T*/SKY130P*/SP8Q/SP8P* flows and met2/capm to met3 in the SKY130DI* flow.
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(via2.X.1)`
      - Via2 connects met2 to met3 in the SKY130T*/SKY130P*/SP8Q/SP8P* flow and met2/capm to met3 in the SKY130DI* flow.
      - 
      - 
+     - 
    * - :drc_rule:`(via2.1a)`
      - Min and max L and W of via2 (except for rule via2.1b/1c/1d/1e/1f)
      - :drc_flag:`AL`
      - 0.200
+     - µm
    * - :drc_rule:`(via2.1b)`
      - Three sizes of square Vias allowed inside areaid:mt: 0.280um, 1.2 um and 1.5 um
      - :drc_flag:`AL`
      - N/A
+     - N/A
    * - :drc_rule:`(via2.1c)`
      - Two sizes of square Vias allowed inside areaid:mt: 1.2 um and 1.5 um
      - :drc_flag:`AL`
      - N/A
+     - N/A
    * - :drc_rule:`(via2.1d)`
      - Four sizes of square Vias allowed inside areaid:mt: 0.2um, 0.280um, 1.2 um and 1.5 um
      - :drc_flag:`AL`
      - 
+     - 
    * - :drc_rule:`(via2.1e)`
      - Three sizes of square Vias allowed inside areaid:mt: 0.8um, 1.2 um and 1.5 um
      - :drc_flag:`AL`
      - N/A
+     - N/A
    * - :drc_rule:`(via2.1f)`
      - Two sizes of square Vias allowed outside areaid:mt: 0.8um and 1.2 um
      - :drc_flag:`AL`
      - N/A
+     - N/A
    * - :drc_rule:`(via2.2)`
      - Spacing of via2 to via2
      - :drc_flag:`AL`
      - 0.200
+     - µm
    * - :drc_rule:`(via2.3)`
      - Only min. square via2s are allowed except die seal ring where via2s are (Via2 CD)*L
      - :drc_flag:`AL`
      - 0.2*L
+     - 
    * - :drc_rule:`(via2.4)`
      - Via2 must be enclosed by Met2 by at least …
      - :drc_flag:`AL`
      - 0.040
+     - µm
    * - :drc_rule:`(via2.4a)`
-     - Inside :drc_tag:`areaid.mt`, 1.5 um Via2 must be enclosed by met2 by atleast
+     - Inside :drc_tag:`areaid.mt`, 1.5 µm Via2 must be enclosed by met2 by atleast
      - 
      - 0.140
+     - µm
    * - :drc_rule:`(via2.5)`
      - Via2 must be enclosed by Met2 on one of two adjacent sides by at least …
      - :drc_flag:`AL`
      - 0.085
+     - µm
    * - :drc_rule:`(via2.11)`
      - Min and max L and W of via2
      - :drc_flag:`CU`
      - 0.210
+     - µm
    * - :drc_rule:`(via2.12)`
      - Min spacing between via2's
      - :drc_flag:`CU`
      - 0.180
+     - µm
    * - :drc_rule:`(via2.13)`
      - Min spacing between via2 rows
      - :drc_flag:`CU`
      - 0.200
+     - µm
    * - :drc_rule:`(via2.14)`
      - Via2 must be enclosed by met2 by atleast
      - :drc_flag:`CU`
      - 0.035
+     - µm
    * - :drc_rule:`(via2.irdrop.1)`
      - For 1 <= n <= 2 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.0
+     - µm
    * - :drc_rule:`(via2.irdrop.2)`
      - For 3 <= n <= 4 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.6
+     - µm
    * - :drc_rule:`(via2.irdrop.3)`
      - For 5 <= n <= 30 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.79
+     - µm
    * - :drc_rule:`(via2.irdrop.4)`
      - For n > 30 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.9
+     - µm
 
 
 .. figure:: periphery/p041-via2_dotdash.svg
@@ -2105,12 +2490,13 @@
 .. list-table:: Function: Defines third level of metal interconnects, buses etc
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(m3.-)`
      - | Algorithm should flag errors, for met3, if ANY of the following is true:
        | An entire 700x700 window is covered by cmm3 waffleDrop, and metX PD < 70% for same window.
@@ -2122,86 +2508,107 @@
        | Exclude cells whose area is below 40Kum2. NOTE: Required for IP, Recommended for Chip-level.
      - :drc_flag:`RC`
      - 
+     - 
    * - :drc_rule:`(m3.1)`
      - Width of metal 3
      - 
      - 0.300
+     - µm
    * - :drc_rule:`(m3.2)`
      - Spacing of metal 3 to metal 3
      - 
      - 0.300
+     - µm
    * - :drc_rule:`(m3.3a)`
      - Min. spacing of features attached to or extending from huge_met3 for a distance of up to 0.480 um to metal3  (rule not checked over non-huge met3 features)
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(m3.3b)`
      - Min. spacing of huge_met3 to metal3 excluding features checked by m3.3a
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(m3.3c)`
-     - Min. spacing of features attached to or extending from huge_met3 for a distance of up to 0.400 um to metal3  (rule not checked over non-huge met3 features)
+     - Min. spacing of features attached to or extending from huge_met3 for a distance of up to 0.400 µm to metal3  (rule not checked over non-huge met3 features)
      - 
      - 0.400
+     - µm
    * - :drc_rule:`(m3.3d)`
      - Min. spacing of huge_met3 to metal3 excluding features checked by m3.3a
      - 
      - 0.400
+     - µm
    * - :drc_rule:`(m3.4)`
      - Via2 must be enclosed by Met3 by at least …
      - :drc_flag:`AL`
      - 0.065
+     - µm
    * - :drc_rule:`(m3.5)`
      - Via2 must be enclosed by Met3 on one of two adjacent sides by at least …
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(m3.5a)`
      - Via2 must be enclosed by Met3 on all sides by at least …(Rule not checked on a layout when it satisfies both rules m3.4 and m3.5)
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(m3.6)`
      - Min area of metal3
      - 
      - 0.240
+     - µm²
    * - :drc_rule:`(m3.7)`
-     - Min area of metal3 holes [um2]
+     - Min area of metal3 holes
      - :drc_flag:`CU`
      - 0.200
+     - µm²
    * - :drc_rule:`(m3.pd.1)`
      - Min MM3_oxide_Pattern_density
      - :drc_flag:`RR`
      - 0.7
+     - \-
    * - :drc_rule:`(m3.pd.2a)`
      - Rule m3.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …
      - :drc_flag:`A`
      - 700
+     - µm
    * - :drc_rule:`(m3.pd.2b)`
      - Rule m3.pd.1 has to be checked by dividing the chip into steps of …
      - :drc_flag:`A`
      - 70
+     - 
    * - :drc_rule:`(m3.11)`
      - Max width of metal3
      - :drc_flag:`CU`
      - 4.000
+     - µm
    * - :drc_rule:`(m3.12)`
      - Add slots and remove vias and contacts if wider than…..
      - :drc_flag:`CU`
      - 3.200
+     - 
    * - :drc_rule:`(m3.13)`
      - Max pattern density (PD) of metal3
      - :drc_flag:`CU`
      - 0.77
+     - \-
    * - :drc_rule:`(m3.14)`
      - Met3 PD window size
      - :drc_flag:`CU`
      - 50.000
+     - µm
    * - :drc_rule:`(m3.14a)`
      - Met3 PD window step
      - :drc_flag:`CU`
      - 25.000
+     - µm
    * - :drc_rule:`(m3.15)`
      - Via2 must be enclosed by met3 by at least…
      - :drc_flag:`CU`
      - 0.060
+     - µm
 
 
 .. figure:: periphery/p042-m3_dotdash.svg
@@ -2216,68 +2623,83 @@
 .. list-table:: Function: Via3 connects met3 to met4 in the SKY130Q*/SKY130P*/SP8Q/SP8P* flow 
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(via3.1)`
      - Min and max L and W of via3 (except for rule via3.1a)
      - :drc_flag:`AL`
      - 0.200
+     - µm
    * - :drc_rule:`(via3.1a)`
      - Two sizes of square via3 allowed inside :drc_tag:`areaid.mt`: 0.200um and 0.800um
      - :drc_flag:`AL`
      - 
+     - 
    * - :drc_rule:`(via3.2)`
      - Spacing of via3 to via3
      - :drc_flag:`AL`
      - 0.200
+     - µm
    * - :drc_rule:`(via3.3)`
      - Only min. square via3s are allowed except die seal ring where via3s are (Via3 CD)*L
      - 
      - 0.2*L
+     - 
    * - :drc_rule:`(via3.4)`
      - Via3 must be enclosed by Met3 by at least …
      - :drc_flag:`AL`
      - 0.060
+     - µm
    * - :drc_rule:`(via3.5)`
      - Via3 must be enclosed by Met3 on one of two adjacent sides by at least …
      - :drc_flag:`AL`
      - 0.090
+     - µm
    * - :drc_rule:`(via3.11)`
      - Min and max L and W of via3
      - :drc_flag:`CU`
      - 0.210
+     - µm
    * - :drc_rule:`(via3.12)`
      - Min spacing between via2's
      - :drc_flag:`CU`
      - 0.180
+     - µm
    * - :drc_rule:`(via3.13)`
      - Via3 must be enclosed by Met3 by at least …
      - :drc_flag:`CU`
      - 0.055
+     - µm
    * - :drc_rule:`(via3.14)`
      - Min spacing between via3 rows
      - :drc_flag:`CU`
      - 0.350
+     - µm
    * - :drc_rule:`(via3.irdrop.1)`
      - For 1 <= n <= 2 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.0
+     - µm
    * - :drc_rule:`(via3.irdrop.2)`
      - For 3 <= n <= 15 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.6
+     - µm
    * - :drc_rule:`(via3.irdrop.3)`
      - For 16 <= n <= 30 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.8
+     - µm
    * - :drc_rule:`(via3.irdrop.4)`
      - For n > 30 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.9
+     - µm
 
 
 
@@ -2287,32 +2709,38 @@
 .. list-table:: Function: Defines Nitride Seal Mask (FIXME)
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(nsm.1)`
      - Min. width of nsm
      - 
      - 3.000
+     - µm
    * - :drc_rule:`(nsm.2)`
      - Min. spacing of nsm to nsm
      - 
      - 4.000
+     - µm
    * - :drc_rule:`(nsm.3)`
      - Min spacing, no overlap, between NSM_keepout to diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5). Exempt the following from the check: (a) cell name "nikon*" and (b) diff ring inside :drc_tag:`areaid.sl`
      - :drc_flag:`AL`
      - 1.000
+     - µm
    * - :drc_rule:`(nsm.3a)`
      - Min enclosure of diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5) by :drc_tag:`areaid.ft`. Exempt the following from the check: (a) cell name "s8Fab_crntic*"  (b)  blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)
      - 
      - 3.000
+     - µm
    * - :drc_rule:`(nsm.3b)`
      - Min spacing between :drc_tag:`areaid.dt` to diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5). Exempt the following from the check: (a) blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)
      - 
      - 3.000
+     - µm
 
 
 
@@ -2322,28 +2750,33 @@
 .. list-table:: Function: Defines third level of metal interconnects, buses and inductor; top_indmMetal is met3 for SKY130D* flows; Similarly top_padVia is Via2 for SKY130D*
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(indm.1)`
      - Min width of top_indmMetal
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(indm.2)`
      - Min spacing between two top_indmMetal
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(indm.3)`
      - top_padVia must  be enclosed by top_indmMetal by atleast
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(indm.4)`
      - Min area of top_indmMetal
      - 
      - N/A
+     - N/A
 
 
 .. figure:: periphery/p043-indm_dotdash.svg
@@ -2358,12 +2791,13 @@
 .. list-table:: Function: Defines Fourth level of metal interconnects;
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(m4.-)`
      - | Algorithm should flag errors, for met4, if ANY of the following is true:
        | An entire 700x700 window is covered by cmm4 waffleDrop, and metX PD < 70% for same window.
@@ -2375,78 +2809,97 @@
        | Exclude cells whose area is below 40Kum2. Required for IP, Recommended for Chip-level.
      - :drc_flag:`RC`
      - 
+     - 
    * - :drc_rule:`(m4.1)`
      - Min width of met4
      - 
      - 0.300
+     - µm
    * - :drc_rule:`(m4.2)`
      - Min spacing between two met4
      - 
      - 0.300
+     - µm
    * - :drc_rule:`(m4.3)`
      - via3 must  be enclosed by met4 by atleast
      - :drc_flag:`AL`
      - 0.065
+     - µm
    * - :drc_rule:`(m4.4)`
      - Min area of met4 (rule exempted for probe pads which are exactly 1.42um by 1.42um)
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(m4.4a)`
      - Min area of met4
      - 
      - 0.240
+     - µm²
    * - :drc_rule:`(m4.5a)`
-     - Min. spacing of features attached to or extending from huge_met4 for a distance of up to  0.400 um to metal4 (rule not checked over non-huge met4 features)
+     - Min. spacing of features attached to or extending from huge_met4 for a distance of up to  0.400 µm to metal4 (rule not checked over non-huge met4 features)
      - 
      - 0.400
+     - µm
    * - :drc_rule:`(m4.5b)`
      - Min. spacing of huge_met4 to metal4 excluding features checked by m4.5a
      - 
      - 0.400
+     - µm
    * - :drc_rule:`(m4.7)`
-     - Min area of meta4 holes [um2]
+     - Min area of meta4 holes
      - :drc_flag:`CU`
      - 0.200
+     - µm²
    * - :drc_rule:`(m4.pd.1)`
      - Min MM4_oxide_Pattern_density
      - :drc_flag:`RR`
      - 0.7
+     - \-
    * - :drc_rule:`(m4.pd.2a)`
      - Rule m4.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …
      - :drc_flag:`A`
      - 700
+     - µm
    * - :drc_rule:`(m4.pd.2b)`
      - Rule m4.pd.1 has to be checked by dividing the chip into steps of …
      - :drc_flag:`A`
      - 70
+     - 
    * - :drc_rule:`(m4.11)`
      - Max width of metal4
      - :drc_flag:`CU`
      - 10.000
+     - µm
    * - :drc_rule:`(m4.12)`
      - Add slots and remove vias and contacts if wider than…..
      - :drc_flag:`CU`
      - 10.000
+     - 
    * - :drc_rule:`(m4.13)`
      - Max pattern density (PD) of metal4; met4 overlapping pdm areas are excluded from the check
      - :drc_flag:`CU`
      - 0.77
+     - \-
    * - :drc_rule:`(m4.14)`
      - Met4 PD window size
      - :drc_flag:`CU`
      - 50.000
+     - µm
    * - :drc_rule:`(m4.14a)`
      - Met4 PD window step
      - :drc_flag:`CU`
      - 25.000
+     - µm
    * - :drc_rule:`(m4.15)`
      - Via3 must be enclosed by met4 by at least…
      - :drc_flag:`CU`
      - 0.060
+     - µm
    * - :drc_rule:`(m4.16)`
      - Min enclosure of pad by met4
      - :drc_flag:`CU`
      - 0.850
+     - µm
 
 
 .. figure:: periphery/p044-m4_dotdash.svg
@@ -2461,44 +2914,53 @@
 .. list-table:: Function: Via4 connects met4 to met5 in the SKY130P*/SP8P* flow 
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(via4.1)`
      - Min and max L and W of via4
      - 
      - 0.800
+     - µm
    * - :drc_rule:`(via4.2)`
      - Spacing of via4 to via4
      - 
      - 0.800
+     - µm
    * - :drc_rule:`(via4.3)`
      - Only min. square via4s are allowed except die seal ring where via4s are (Via4 CD)*L
      - 
      - 0.8*L
+     - 
    * - :drc_rule:`(via4.4)`
      - Via4 must be enclosed by Met4 by at least …
      - 
      - 0.190
+     - µm
    * - :drc_rule:`(via4.irdrop.1)`
      - For 1 <= n <= 4 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.0
+     - µm
    * - :drc_rule:`(via4.irdrop.2)`
      - For 5 <= n <= 10 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.2
+     - µm
    * - :drc_rule:`(via4.irdrop.3)`
      - For 11 <= n <= 100 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.5
+     - µm
    * - :drc_rule:`(via4.irdrop.4)`
      - For n > 100 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.8
+     - µm
 
 
 
@@ -2508,28 +2970,33 @@
 .. list-table:: Function: Defines Fifth level of metal interconnects;
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(m5.1)`
      - Min width of met5
      - 
      - 1.600
+     - µm
    * - :drc_rule:`(m5.2)`
      - Min spacing between two met5
      - 
      - 1.600
+     - µm
    * - :drc_rule:`(m5.3)`
      - via4 must  be enclosed by met5 by atleast
      - 
      - 0.310
+     - µm
    * - :drc_rule:`(m5.4)`
      - Min area of met5 (For all flows except SKY130PIR*/SKY130PF*, the rule is exempted for probe pads which are exactly 1.42um by 1.42um)
      - 
      - 4.000
+     - µm²
 
 
 
@@ -2539,20 +3006,23 @@
 .. list-table:: Function: Opens the passivation
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(pad.2)`
      - Min spacing of pad:dg to pad:dg
      - 
      - 1.270
+     - µm
    * - :drc_rule:`(pad.3)`
      - Max area of hugePad NOT top_metal
      - 
      - 30000
+     - µm²
 
 
 
@@ -2562,36 +3032,43 @@
 .. list-table:: Function: Defines the Cu Inductor. Connects to met5 through the pad opening
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(rdl.1)`
      - Min width of rdl
      - 
      - 10
+     - µm
    * - :drc_rule:`(rdl.2)`
      - Min spacing between two rdl
      - 
      - 10
+     - µm
    * - :drc_rule:`(rdl.3)`
      - Min enclosure of pad by rdl, except rdl interacting with bump
      - 
      - 10.750
+     - µm
    * - :drc_rule:`(rdl.4)`
      - Min spacing between rdl and outer edge of the seal ring
      - 
      - 15.000
+     - µm
    * - :drc_rule:`(rdl.5)`
      - (rdl OR ccu1m.mk) must not overlap :drc_tag:`areaid.ft`. Exempt the following from the check: (a)  blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)
      - 
      - 
+     - 
    * - :drc_rule:`(rdl.6)`
      - Min spacing of rdl to pad, except rdl interacting with bump
      - 
      - 19.660
+     - µm
 
 
 
@@ -2608,108 +3085,133 @@
 .. list-table:: Function: Defines metal fuses
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(mf.1)`
      - Min. and max width of fuse
      - 
      - 0.800
+     - µm
    * - :drc_rule:`(mf.2)`
      - Length of fuse
      - 
      - 7.200
+     - µm
    * - :drc_rule:`(mf.3)`
      - Spacing between centers of adjacent fuses
      - 
      - 2.760
+     - µm
    * - :drc_rule:`(mf.4)`
      - Spacing between center of fuse and fuse_metal (fuse shields are exempted)
      - 
      - 3.300
+     - µm
    * - :drc_rule:`(mf.5)`
      - Max. extension of fuse_metal beyond fuse boundary
      - 
      - 0.830
+     - 
    * - :drc_rule:`(mf.6)`
      - Spacing (no overlapping) between fuse center and Metal1
      - 
      - 3.300
+     - µm
    * - :drc_rule:`(mf.7)`
      - Spacing (no overlapping) between fuse center and LI
      - 
      - 3.300
+     - µm
    * - :drc_rule:`(mf.8)`
      - Spacing (no overlapping) between fuse center and poly
      - 
      - 2.660
+     - µm
    * - :drc_rule:`(mf.9)`
      - Spacing (no overlapping) between fuse center and tap
      - 
      - 2.640
+     - µm
    * - :drc_rule:`(mf.10)`
      - Spacing (no overlapping) between fuse center and diff
      - 
      - 3.250
+     - µm
    * - :drc_rule:`(mf.11)`
      - Spacing (no overlapping) between fuse center and nwell
      - 
      - 3.320
+     - µm
    * - :drc_rule:`(mf.12)`
      - Size of  fuse_shield
      - 
      - 0.5x2.4
+     - µm
    * - :drc_rule:`(mf.13)`
      - Min. spacing of center of fuse to fuse_shield
      - 
      - 2.200
+     - µm
    * - :drc_rule:`(mf.14)`
      - Max. spacing of center of fuse to fuse_shield
      - 
      - 3.300
+     - µm
    * - :drc_rule:`(mf.15)`
      - Fuse_shields are only placed between periphery metal (i.e., without fuse:dg) and non-isolated edges of fuse as defined by mf.16
      - 
      - 
+     - 
    * - :drc_rule:`(mf.16)`
      - The edge of a fuse is considered non-isolated if wider than or equal to mf.2 and spaced to fuse_metal by less than …
      - 
      - 4.000
+     - 
    * - :drc_rule:`(mf.17)`
      - Offset between fuse_shields center and fuse center
      - :drc_flag:`NC`
      - 0.000
+     - 
    * - :drc_rule:`(mf.18)`
      - Min and max space between fuse_shield and fuse_metal (opposite edges). Rule checked within 1 gridpoint.
      - 
      - 0.600
+     - µm
    * - :drc_rule:`(mf.19)`
      - Spacing (no overlapping) between fuse center and Metal2
      - 
      - 3.300
+     - µm
    * - :drc_rule:`(mf.20)`
      - Only one fuse per metal line allowed
      - 
      - 
+     - 
    * - :drc_rule:`(mf.21)`
      - Min spacing , no overlap, between metal3 and fuse center
      - 
      - 3.300
+     - µm
    * - :drc_rule:`(mf.22)`
      - Min spacing between fuse_contact to fuse_contact
      - 
      - 1.960
+     - µm
    * - :drc_rule:`(mf.23)`
      - Spacing (no overlapping) between fuse center and Metal4
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(mf.24)`
      - Spacing (no overlapping) between fuse center and Metal5
      - 
      - 3.300
+     - µm
 
 
 .. figure:: periphery/p046-mf_dotdash.svg
@@ -2724,32 +3226,38 @@
 .. list-table:: Function: Defines thick oxide for high voltage devices
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(hvi.1)`
      - Min width of Hvi
      - :drc_flag:`P`
      - 0.600
+     - µm
    * - :drc_rule:`(hvi.2a)`
      - Min spacing of Hvi to Hvi
      - :drc_flag:`P`
      - 0.700
+     - µm
    * - :drc_rule:`(hvi.2b)`
      - Manual merge if space is below minimum
      - 
      - 
+     - 
    * - :drc_rule:`(hvi.4)`
      - Hvi must not overlap tunm
      - 
      - 
+     - 
    * - :drc_rule:`(hvi.5)`
      - Min space between hvi and nwell (exclude coincident edges)
      - 
      - 0.700
+     - µm
 
 
 .. figure:: periphery/p047-hvi_dotdash.svg
@@ -2764,28 +3272,33 @@
 .. list-table:: Function: Defines rules for HV nwell; All nwell connected to voltages greater than 1.8V must be enclosed by hvi; Nets connected to LV nwell or nwell overlapping hvi but connected to LV voltages (i.e 1.8V) should be tagged "lv_net" using text.dg; This tag should be only on Li layer
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(hvnwell.8)`
      - Min space between HV_nwell  and any nwell on different nets
      - 
      - 2.000
+     - µm
    * - :drc_rule:`(hvnwell.9)`
      - (Nwell overlapping hvi) must be enclosed by hvi
      - 
      - 
+     - 
    * - :drc_rule:`(hvnwell.10)`
      - LVnwell and HnWell should not be on the same net (for the purposes of this check, short the connectivity through resistors); Exempt HnWell with li nets tagged "lv_net" using text.dg and Hnwell connected to nwell overlapping :drc_tag:`areaid.hl`
      - :drc_flag:`TC`
      - 
+     - 
    * - :drc_rule:`(hvnwell.11)`
      - Nwell connected to the nets mentioned in the "Power_Net_Hv" field of the latcup GUI must be enclosed by hvi (exempt nwell inside :drc_tag:`areaid.hl`). Also for the purposes of this check, short the connectivity through resistors. The rule will be checked in the latchup run and exempted for cells "s8tsg5_tx_ibias_gen" and "s8bbcnv_psoc3p_top_18",  "rainier_top, indus_top*", "rainier_top, manas_top, ccg3_top"
      - 
      - 
+     - 
 
 
 .. figure:: periphery/p047-hvnwell_dotdash.svg
@@ -2800,72 +3313,88 @@
 .. list-table:: Function: Defines rules for HV diff/tap
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(hvdifftap.14)`
      - Min width of diff inside Hvi, except HV Pdiff resistors (difftap.14a)
      - :drc_flag:`P`
      - 0.290
+     - µm
    * - :drc_rule:`(hvdifftap.14a)`
      - Min width of diff inside Hvi, HV Pdiff resistors only
      - :drc_flag:`P`
      - 0.150
+     - µm
    * - :drc_rule:`(hvdifftap.15a)`
      - Min space of Hdiff to Hdiff
      - :drc_flag:`P`
      - 0.300
+     - µm
    * - :drc_rule:`(hvdifftap.15b)`
      - Min space of n+diff to non-abutting p+tap inside Hvi
      - :drc_flag:`P`
      - 0.370
+     - µm
    * - :drc_rule:`(hvdifftap.16)`
      - Min width tap butting diff on one or two sides inside Hvi (rule exempted inside UHVI)
      - 
      - 0.700
+     - µm
    * - :drc_rule:`(hvdifftap.17)`
      - P+ Hdiff or Pdiff inside areaid:hvnwell must be enclosed by Hv_nwell by at least ….[Rule exempted inside UHVI]
      - :drc_flag:`DE` :drc_flag:`NE`
      - 0.330
+     - µm
    * - :drc_rule:`(hvdifftap.18)`
      - Spacing of N+ diff to HV_nwell (rule exempted inside UHVI)
      - :drc_flag:`DE` :drc_flag:`NE`
      - 0.430
+     - µm
    * - :drc_rule:`(hvdifftap.19)`
      - N+ Htap must be enclosed by Hv_nwell by at least …Rule exempted inside UHVI.
      - :drc_flag:`NE`
      - 0.330
+     - µm
    * - :drc_rule:`(hvdifftap.20)`
      - Spacing of P+ tap to HV_nwell (Exempted for p+tap butting pwell.rs; rule exempted inside UHVI)
      - 
      - 0.430
+     - µm
    * - :drc_rule:`(hvdifftap.21)`
      - Diff or tap cannot straddle Hvi
      - :drc_flag:`P`
      - 
+     - 
    * - :drc_rule:`(hvdifftap.22)`
      - Min enclosure of Hdiff or Htap by Hvi. Rule exempted inside UHVI.
      - :drc_flag:`P`
      - 0.180
+     - µm
    * - :drc_rule:`(hvdifftap.23)`
      - Space between diff or tap outside Hvi and Hvi
      - :drc_flag:`P`
      - 0.180
+     - µm
    * - :drc_rule:`(hvdifftap.24)`
      - Spacing of nwell to N+ Hdiff (rule exempted inside UHVI)
      - :drc_flag:`DE` :drc_flag:`NE`
      - 0.430
+     - µm
    * - :drc_rule:`(hvdifftap.25)`
      - Min space of N+ Hdiff inside HVI across non-abutting P+_tap
      - :drc_flag:`NC`
      - 1.070
+     - µm
    * - :drc_rule:`(hvdifftap.26)`
      - Min spacing between pwbm to difftap outside UHVI
      - 
      - N/A
+     - N/A
 
 
 .. figure:: periphery/p048-hvdifftap_dotdash.svg
@@ -2880,20 +3409,23 @@
 .. list-table:: Function: Defines rules for HV poly
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(hvpoly.13)`
      - Min width of poly over diff inside Hvi
      - :drc_flag:`P`
      - 0.500
+     - µm
    * - :drc_rule:`(hvpoly.14)`
      - (poly and diff) cannot straddle Hvi
      - 
      - 
+     - 
 
 
 .. figure:: periphery/p049-hvpoly_dotdash.svg
@@ -2908,56 +3440,68 @@
 .. list-table:: Function: Defines tip implants for the HV NMOS
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
-   * - :drc_rule:`(hvntm.X.1 )`
+     - Unit
+   * - :drc_rule:`(hvntm.X.1)`
      - Hvntm can be drawn inside HVI. Drawn layer will be OR-ed with the CL and rechecked for CLDRC
      - 
      - 
+     - 
    * - :drc_rule:`(hvntm.1)`
      - Width of hvntm
      - :drc_flag:`P`
      - 0.700
+     - µm
    * - :drc_rule:`(hvntm.2)`
      - Spacing of hvntm to hvntm
      - :drc_flag:`P`
      - 0.700
+     - µm
    * - :drc_rule:`(hvntm.3)`
      - Min. enclosure of (n+_diff inside Hvi) but not overlapping :drc_tag:`areaid.ce` by hvntm
      - :drc_flag:`P`
      - 0.185
+     - µm
    * - :drc_rule:`(hvntm.4)`
      - Space, no overlap, between n+_diff outside Hvi and hvntm
      - :drc_flag:`P`
      - 0.185
+     - µm
    * - :drc_rule:`(hvntm.5)`
      - Space, no overlap, between p+_diff  and hvntm
      - :drc_flag:`P` :drc_flag:`DE`
      - 0.185
+     - µm
    * - :drc_rule:`(hvntm.6a)`
      - Space, no overlap, between p+_tap and hvntm (except along the diff-butting edge)
      - :drc_flag:`P`
      - 0.185
+     - µm
    * - :drc_rule:`(hvntm.6b)`
      - Space, no overlap, between p+_tap and hvntm along the diff-butting edge
      - :drc_flag:`P`
      - 0.000
+     - µm
    * - :drc_rule:`(hvntm.7)`
      - hvntm must enclose ESD_nwell_tap inside hvi by atleast
      - :drc_flag:`P`
      - 0.000
+     - 
    * - :drc_rule:`(hvntm.9)`
      - Hvntm must not overlap :drc_tag:`areaid.ce`
      - 
      - 
+     - 
    * - :drc_rule:`(hvntm.10)`
      - Hvntm must overlap hvi
      - 
      - 
+     - 
 
 
 .. figure:: periphery/p049-hvntm_dotdash.svg
@@ -2972,72 +3516,88 @@
 .. list-table:: Function: Defines rules for the 16V Drain extended NMOS devices
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(denmos.1)`
      - Min width of de_nFet_gate
      - 
      - 1.055
+     - µm
    * - :drc_rule:`(denmos.2)`
      - Min width of de_nFet_source not overlapping poly
      - 
      - 0.280
+     - µm
    * - :drc_rule:`(denmos.3)`
      - Min width of de_nFet_source overlapping poly
      - 
      - 0.925
+     - µm
    * - :drc_rule:`(denmos.4)`
      - Min width of the de_nFet_drain
      - 
      - 0.170
+     - µm
    * - :drc_rule:`(denmos.5)`
      - Min/Max extension of de_nFet_source over nwell
      - 
      - 0.225
+     - 
    * - :drc_rule:`(denmos.6)`
      - Min/Max spacing between de_nFet_drain and de_nFet_source
      - 
      - 1.585
+     - µm
    * - :drc_rule:`(denmos.7)`
      - Min channel width for de_nFet_gate
      - 
      - 5.000
+     - µm
    * - :drc_rule:`(denmos.8)`
      - 90 degree angles are not permitted for nwell overlapping de_nFET_drain
      - 
      - 
+     - 
    * - :drc_rule:`(denmos.9a)`
-     - All bevels on nwell are 45 degree, 0.43 um from corners
+     - All bevels on nwell are 45 degree, 0.43 µm from corners
      - :drc_flag:`NC`
      - 
+     - µm
    * - :drc_rule:`(denmos.9b)`
-     - All bevels on de_nFet_drain are 45 degree, 0.05 um from corners
+     - All bevels on de_nFet_drain are 45 degree, 0.05 µm from corners
      - :drc_flag:`NC`
      - 
+     - µm
    * - :drc_rule:`(denmos.10)`
      - Min enclosure of de_nFet_drain by nwell
      - 
      - 0.660
+     - µm
    * - :drc_rule:`(denmos.11)`
      - Min spacing between p+ tap and (nwell overlapping de_nFet_drain)
      - 
      - 0.860
+     - µm
    * - :drc_rule:`(denmos.12)`
      - Min spacing between nwells overlapping de_nFET_drain
      - 
      - 2.400
+     - µm
    * - :drc_rule:`(denmos.13)`
      - de_nFet_source must be enclosed by nsdm by
      - 
      - 0.130
+     - µm
    * - :drc_rule:`(denmos.14)`
      - nvhv FETs must be enclosed by :drc_tag:`areaid.mt`
      - 
      - N/A
+     - N/A
 
 
 .. figure:: periphery/p050-denmos_dotdash.svg
@@ -3052,68 +3612,83 @@
 .. list-table:: Function: Defines rules for the 16V Drain extended NMOS devices
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(depmos.1)`
      - Min width of de_pFet_gate
      - 
      - 1.050
+     - µm
    * - :drc_rule:`(depmos.2)`
      - Min width of de_pFet_source not overlapping poly
      - 
      - 0.280
+     - µm
    * - :drc_rule:`(depmos.3)`
      - Min width of de_pFet_source overlapping poly
      - 
      - 0.920
+     - µm
    * - :drc_rule:`(depmos.4)`
      - Min width of the de_pFet_drain
      - 
      - 0.170
+     - µm
    * - :drc_rule:`(depmos.5)`
      - Min/Max extension of de_pFet_source beyond nwell
      - 
      - 0.260
+     - 
    * - :drc_rule:`(depmos.6)`
      - Min/Max spacing between de_pFet_drain and de_pFet_source
      - 
      - 1.190
+     - µm
    * - :drc_rule:`(depmos.7)`
      - Min channel width for de_pFet_gate
      - 
      - 5.000
+     - µm
    * - :drc_rule:`(depmos.8)`
      - 90 degree angles are not permitted for nwell hole overlapping de_pFET_drain
      - 
      - 
+     - 
    * - :drc_rule:`(depmos.9a)`
-     - All bevels on nwell hole are 45 degree, 0.43 um from corners
+     - All bevels on nwell hole are 45 degree, 0.43 µm from corners
      - :drc_flag:`NC`
      - 
+     - µm
    * - :drc_rule:`(depmos.9b)`
-     - All bevels on de_pFet_drain are 45 degree, 0.05 um from corners
+     - All bevels on de_pFet_drain are 45 degree, 0.05 µm from corners
      - :drc_flag:`NC`
      - 
+     - µm
    * - :drc_rule:`(depmos.10)`
      - Min enclosure of de_pFet_drain by nwell hole
      - 
      - 0.860
+     - µm
    * - :drc_rule:`(depmos.11)`
      - Min spacing between n+ tap and (nwell hole enclosing de_pFET_drain)
      - 
      - 0.660
+     - µm
    * - :drc_rule:`(depmos.12)`
      - de_pFet_source must be enclosed by psdm by
      - 
      - 0.130
+     - µm
    * - :drc_rule:`(depmos.13)`
      - pvhv fets( except those with W/L = 5.0/0.66) must be enclosed by :drc_tag:`areaid.mt`
      - 
      - N/A
+     - N/A
 
 
 .. figure:: periphery/p051-depmos_dotdash.svg
@@ -3128,44 +3703,53 @@
 .. list-table:: Function: Defines rules :drc_tag:`areaid.en`
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(extd.1)`
      - Difftap cannot straddle areaid:en
      - 
      - 
+     - 
    * - :drc_rule:`(extd.2)`
      - DiffTap must have 2 or 3 coincident edges with areaid:en if enclosed by areaid:en
      - 
      - 
+     - 
    * - :drc_rule:`(extd.3)`
      - Poly must not be entirely overlapping difftap in areaid:en
      - 
      - 
+     - 
    * - :drc_rule:`(extd.4)`
      - Only cell name "s8rf_n20vhv1*" is a valid cell name for n20vhv1 device  (Check in LVS as invalid device)
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(extd.5)`
      - Only cell name "s8rf_n20vhviso1" is a valid cell name for n20vhviso1 device  (Check in LVS as invalid device)
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(extd.6)`
      - Only cell name "s8rf_p20vhv1" is a valid cell name for p20vhv1 device  (Check in LVS as invalid device)
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(extd.7)`
      - Only cell name "s8rf_n20nativevhv1*" is a valid cell name for n20nativevhv1 device  (Check in LVS as invalid device)
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(extd.8)`
      - Only cell name "s8rf_n20zvtvhv1*" is a valid cell name for n20zvtvhv1 device  (Check in LVS as invalid device)
      - 
      - N/A
+     - N/A
 
 
 .. figure:: periphery/p052-extd_dotdash.svg
@@ -3185,88 +3769,108 @@
 .. list-table:: Function: Defines High Voltage Rules (FIXME)
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(hv.X.1)`
      - High voltage source/drain regions must be tagged by diff:hv
      - 
      - 
+     - 
    * - :drc_rule:`(hv.X.3)`
      - High voltage poly can be drawn over multiple diff regions that are ALL reverse-biased by at least 300 mV (existence of reverse-bias is not checked by the CAD flow).  It can also be drawn over multiple diffs when all sources and all drain are shorted together. In these case, the high voltage poly can be tagged with the text:dg label with a value “hv_bb”.  Exceptions to this use of the hv_bb label must be approved by technology.  Under certain bias conditions, high voltage poly tagged with hv_bb can cross an nwell boundary. The poly of the drain extended device crosses nwell by construction and can be tagged with the "hv_bb" label. Use of the hv_bb label on high voltage poly crossing an nwell boundary must be approved by technology. All high voltage poly tagged with hv_bb will not be checked to hv.poly.1, hv.poly.2, hv.poly.3 and hv.poly.4.
      - 
      - 
+     - 
    * - :drc_rule:`(hv.X.4)`
      - Any piece of layout that is shorted to hv_source/drain becomes a high voltage feature.
      - 
      - 
+     - 
    * - :drc_rule:`(hv.X.5)`
      - In cases where an hv poly gate abuts only low voltage source and drain, the poly gate can be tagged with the text:dg label with a value "hv_lv".  In this case, the "hv_lv" tagged poly gate and its extensions will not be checked to hv.poly.6, but is checked by rules in the poly.-.- section.  The use of the hv_lv label must be approved by technology.
      - 
      - 
+     - 
    * - :drc_rule:`(hv.X.6)`
      - Nwell biased at voltages >= 7.2V must be tagged with text "shv_nwell"
      - :drc_flag:`NC`
      - 
+     - 
    * - :drc_rule:`(hv.nwell.1)`
      - Min spacing of nwell tagged with text "shv_nwell" to any nwell on different nets
      - 
      - 2.500
+     - µm
    * - :drc_rule:`(hv.diff.1a)`
      - Minimum hv_source/drain spacing to diff for edges of hv_source/drain and diff not butting tap
      - 
      - 0.300
+     - µm
    * - :drc_rule:`(hv.diff.1b)`
      - Minimum spacing of (n+/p+ diff resistors and diodes) connected to hv_source/drain to diff
      - 
      - 0.300
+     - µm
    * - :drc_rule:`(hv.diff.2)`
      - Minimum spacing of nwell connected to hv_source/drain to n+ diff
      - :drc_flag:`DE`
      - 0.430
+     - µm
    * - :drc_rule:`(hv.diff.3a)`
      - Minimum n+ hv_source/drain spacing to nwell
      - 
      - 0.550
+     - µm
    * - :drc_rule:`(hv.diff.3b)`
      - Minimum spacing of (n+ diff resistors and diodes) connected to hv_source/drain to nwell
      - 
      - 0.550
+     - µm
    * - :drc_rule:`(hv.poly.1)`
      - Hv poly feature hvPoly (including hv poly resistors) can be drawn over only one diff region and is not allowed to cross nwell boundary except (1) as allowed in rule .X.3 and (2) nwell hole boundary in depmos
      - 
      - 
+     - 
    * - :drc_rule:`(hv.poly.2)`
      - Min spacing of hvPoly (including hv poly resistor) on field to diff (diff butting hvPoly are excluded)
      - 
      - 0.300
+     - µm
    * - :drc_rule:`(hv.poly.3)`
      - Min spacing of hvPoly (including hv poly resistor) on field to n-well (exempt poly stradding nwell in a denmos/depmos)
      - 
      - 0.550
+     - µm
    * - :drc_rule:`(hv.poly.4)`
      - Enclosure of hvPoly (including hv poly resistor) on field by n-well (exempt poly stradding nwell in a denmos/depmos)
      - 
      - 0.300
+     - µm
    * - :drc_rule:`(hv.poly.6a)`
      - Min extension of poly beyond hvFET_gate (exempt poly extending beyond diff along the S/D direction in a denmos/depmos)
      - 
      - 0.160
+     - 
    * - :drc_rule:`(hv.poly.6b)`
      - Extension of hv poly beyond FET_gate (including hvFET_gate; exempt poly extending beyond diff along the S/D direction in a denmos/depmos)
      - 
      - 0.160
+     - 
    * - :drc_rule:`(hv.poly.7)`
      - Minimum overlap of hv poly ring_FET and diff
      - 
      - 
+     - 
    * - :drc_rule:`(hv.poly.8)`
      - Any poly gate abutting hv_source/drain becomes a hvFET_gate
      - 
      - 
+     - 
 
 
 .. figure:: periphery/p054-hv_dotdash_dotdash.svg
@@ -3281,68 +3885,83 @@
 .. list-table:: Function: Identify nets working between 12-16V
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(vhvi.vhv.1)`
      - Terminals operating at nominal 12V (maximum 16V) bias must be tagged as Very-High-Voltage (VHV) using vhvi:dg layer
      - :drc_flag:`NC`
      - 
+     - 
    * - :drc_rule:`(vhvi.vhv.2)`
      - A source or drain of a drain-extended device can be tagged by vhvi:dg. A device with either source or drain (not both) tagged with vhvi:dg serves as a VHV propagation stopper
      - :drc_flag:`NC`
      - 
+     - 
    * - :drc_rule:`(vhvi.vhv.3)`
      - Any feature connected to VHVSourceDrain becomes a very-high-voltage feature
      - :drc_flag:`NC`
      - 
+     - 
    * - :drc_rule:`(vhvi.vhv.4)`
      - Any feature connected to VHVPoly becomes a very-high-voltage feature
      - :drc_flag:`NC`
      - 
+     - 
    * - :drc_rule:`(vhvi.vhv.5)`
      - Diffusion that is not a part of a drain-extended device (i.e., diff not areaid:en) must not be on the same net as VHVSourceDrain. Only diffusion inside :drc_tag:`areaid.ed` and LV diffusion tagged with vhvi:dg are exempted.
      - 
      - 
+     - 
    * - :drc_rule:`(vhvi.vhv.6)`
      - Poly resistor can act as a VHV propagation stopper. For this, it should be tagged with text "vhv_block"
      - :drc_flag:`NC`
      - 
+     - 
    * - :drc_rule:`(vhvi.1.-)`
      - Min width of vhvi:dg
      - 
      - 0.020
+     - µm
    * - :drc_rule:`(vhvi.2.-)`
      - Vhvi:dg cannot overlap areaid:ce
      - 
      - 
+     - 
    * - :drc_rule:`(vhvi.3.-)`
      - VHVGate must overlap hvi:dg
      - 
      - 
+     - 
    * - :drc_rule:`(vhvi.4.-)`
      - Poly connected to the same net as a VHVSourceDrain must be tagged with vhvi:dg layer
      - 
      - 
+     - 
    * - :drc_rule:`(vhvi.5.-)`
      - Vhvi:dg cannot straddle VHVSourceDrain
      - 
      - 
+     - 
    * - :drc_rule:`(vhvi.6.-)`
      - Vhvi:dg overlapping VHVSourceDrain must not overlap poly
      - 
      - 
+     - 
    * - :drc_rule:`(vhvi.7.-)`
      - Vhvi:dg cannot straddle VHVPoly
      - 
      - 
+     - 
    * - :drc_rule:`(vhvi.8.-)`
      - Min space between nwell tagged with vhvi:dg and deep nwell, nwell, or n+diff on a separate net (except for n+diff overlapping nwell tagged with vhvi:dg).
      - 
      - 11.240
+     - µm
 
 
 
@@ -3352,52 +3971,63 @@
 .. list-table:: Function: Identify nets working between 20V
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(uhvi.1.-)`
      - diff/tap can not straddle UHVI
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(uhvi.2.-)`
      - poly can not straddle UHVI
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(uhvi.3.-)`
      - pwbm.dg must be enclosed by UHVI (exempt inside :drc_tag:`areaid.lw`)
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(uhvi.4.-)`
      - dnw.dg can not straddle UHVI
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(uhvi.5.-)`
      - UHVI must enclose :drc_tag:`areaid.ext`
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(uhvi.6.-)`
      - UHVI must enclose dnwell
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(uhvi.7.-)`
      - natfet.dg must be enclosed by UHVI layer by at least
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(uhvi.8.-)`
      - Minimum width of natfet.dg
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(uhvi.9.-)`
      - Minimum Space spacing of natfet.dg
      - 
      - N/A
+     - N/A
    * - :drc_rule:`(uhvi.10.-)`
      - natfet.dg layer is not allowed
      - 
      - N/A
+     - N/A
 
 
 
@@ -3407,24 +4037,28 @@
 .. list-table:: Function: Identify dnwdiodehv_Psub(BV~60V)
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(ulvt-.1)`
      - :drc_tag:`areaid.low_vt` must enclose dnw for the UHV dnw-psub diode texted "condiodeHvPsub"
      - 
      - NA
+     - 
    * - :drc_rule:`(ulvt-.2)`
      - :drc_tag:`areaid.low_vt` must enclose pwbm.dg for the UHV dnw-psub diode texted "condiodeHvPsub"
      - 
      - NA
+     - 
    * - :drc_rule:`(ulvt-.3)`
      - :drc_tag:`areaid.low_vt` can not straddle UHVI
      - 
      - NA
+     - 
 
 
 
@@ -3434,60 +4068,73 @@
 .. list-table:: Function: Identify pwell resistors
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(pwres.1.-)`
      - Pwell resistor has to be enclosed by the res layer
      - :drc_flag:`NC`
      - 
+     - 
    * - :drc_rule:`(pwres.2.-)`
      - Min/Max width of pwell resistor
      - 
      - 2.650
+     - µm
    * - :drc_rule:`(pwres.3.-)`
      - Min length of pwell resistor
      - 
      - 26.500
+     - µm
    * - :drc_rule:`(pwres.4.-)`
      - Max length of pwell resistor
      - 
      - 265.00
+     - µm
    * - :drc_rule:`(pwres.5.-)`
      - Min/Max spacing of tap inside the pwell resistor to nwell
      - 
      - 0.220
+     - µm
    * - :drc_rule:`(pwres.6.-)`
      - Min/Max width of tap inside the pwell resistor
      - 
      - 0.530
+     - µm
    * - :drc_rule:`(pwres.7a.-)`
      - Every pwres_terminal must enclose 12 licon1
      - 
      - 
+     - 
    * - :drc_rule:`(pwres.7b.-)`
      - Every pwres_terminal must enclose 12 mcons if routed through metal1
      - 
      - 
+     - 
    * - :drc_rule:`(pwres.8.-)`
      - Diff or poly is not allowed in the pwell resistor.
      - 
      - 
+     - 
    * - :drc_rule:`(pwres.9.-)`
      - Nwell surrounding the pwell resistor must have a full ring of contacted tap strapped with metal.
      - 
      - 
+     - 
    * - :drc_rule:`(pwres.10.-)`
      - The res layer must abut pwres_terminal on opposite and parallel edges
      - 
      - 
+     - 
    * - :drc_rule:`(pwres.11.-)`
      - The res layer must abut nwell on opposite and parallel edges not checked in Rule pwres.10
      - 
      - 
+     - 
 
 
 .. figure:: periphery/p056-pwres_dotdash_dotdash.svg
@@ -3502,20 +4149,23 @@
 .. list-table:: Function: Identify RF diodes; Used for RCX
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - :drc_rule:`Name`
      - Description
      - :drc_flag:`Flags`
      - Value
+     - Unit
    * - :drc_rule:`(rfdiode.1.-)`
      - Only 90 degrees allowed for :drc_tag:`areaid.re`
      - 
      - 
+     - 
    * - :drc_rule:`(rfdiode.2.-)`
      - :drc_tag:`areaid.re` must be coincident with nwell for the rf nwell diode
      - 
      - 
+     - 
    * - :drc_rule:`(rfdiode.3.-)`
      - :drc_tag:`areaid.re` must be coincident with innwer edge of the nwell ring for the rf pwell-deep nwell diode
        Allowed PNP layout
@@ -3524,6 +4174,7 @@
        Layout: npnpar1x1
      - 
      - 
+     - 
 
 
 .. figure:: periphery/p057-rfdiode_dotdash_dotdash.svg
diff --git a/docs/rules/periphery/p018-x_dotdash.csv b/docs/rules/periphery/p018-x_dotdash.csv
index cd22507..12da3ec 100644
--- a/docs/rules/periphery/p018-x_dotdash.csv
+++ b/docs/rules/periphery/p018-x_dotdash.csv
@@ -1,52 +1,65 @@
-Name,Description,Flags,Value
-(x.1a),"p1m.md (OPC), DECA and AMKOR layers (pi1.dg, pmm.dg, rdl.dg, pi2.dg, ubm.dg, bump.dg) and mask data for p1m, met1, via, met2 must be on a grid of [mm]",,0.001
-(x.1b),Data for SKY130 layout and mask on all layers except those mentioned in 1a must be on a grid of [mm] (except inside Seal ring),,0.005
-(x.2),Angles permitted on: diff,,N/A
-(x.2),"Angles permitted on: diff except for:\n- diff inside ""advSeal_6um* OR cuPillarAdvSeal_6um*"" pcell, \n- diff rings around the die at min total L>1000 um and W=0.3 um",,n x 90
-(x.2),"Angles permitted on: tap (except inside :drc_tag:`areaid.en`), poly (except for ESD flare gates or gated_npn), li1(periphery), licon1, capm, mcon, via, via2. Anchors are exempted.",,n x 90
-(x.2),Angles permitted on: via3 and via4. Anchors are exempted.,,n x 90
-(x.2a),Analog circuits identified by :drc_tag:`areaid.analog` to use rectangular diff and tap geometries only; that are not to be merged into more complex shapes (T's or L's),,
-(x.2c),"45 degree angles allowed on diff, tap inside UHVI",,
-(x.3),Angles permitted on all other layers and in the seal ring for all the layers,,
-(x.3a),"Angles permitted on all other layers except WLCSP layers (pmm, rdl, pmm2, ubm and bump)",,n x 45
-(x.4),Electrical DR cover layout guidelines for electromigration,NC,
-(x.5),"All ""pin""polygons must be within the ""drawing"" polygons of the layer",AL,
-(x.6),All intra-layer separation checks will include a notch check,,
-(x.7),Mask layer line and space checks must be done on all layers (checked with s.x rules),NC,
-(x.8),"Use of areaid ""core"" layer (""coreid"") must be approved by technology",NC,
-(x.9),"Shapes on maskAdd or maskDrop layers (""serifs"") are allowed in core only. Exempted are: \n- cfom md/mp inside ""advSeal_6um* OR cuPillarAdvSeal_6um*"" pcell \n- diff rings around the die at min total L>1000 um and W=0.3 um, and PMM/PDMM inside areaid:sl",,
-(x.9),"Shapes on maskAdd or maskDrop layers (""serifs"") are allowed in core only. PMM/PDMM inside areaid:sl are excluded.",,N/A
-(x.10),"Res purpose layer for (diff, poly) cannot overlap licon1",,
-(x.11),Metal fuses are drawn in met2,LVS,N/A
-(x.11),Metal fuses are drawn in met3,LVS,N/A
-(x.11),Metal fuses are drawn in met4,LVS,
-(x.\n12a\n12b\n12c),"To comply with the minimum spacing requirement for layer X in the frame:\n- Spacing of :drc_tag:`areaid.mt` to any non-ID layer\n- Enclosure of any non-ID layer by :drc_tag:`areaid.mt`\n- Rules exempted for cells with name ""*_buildspace""",F,
-(x.12d),- Spacing of :drc_tag:`areaid.mt` to huge_metX (Exempt met3.dg),F,N/A
-(x.12d),- Spacing of :drc_tag:`areaid.mt` to huge_metX (Exempt met5.dg),F,
-(x.12e),- Enclosure of huge_metX by :drc_tag:`areaid.mt` (Exempt met3.dg),F,N/A
-(x.12e),- Enclosure of huge_metX by :drc_tag:`areaid.mt` (Exempt met5.dg),F,
-(x.13),Spacing between features located across areaid:ce is checked by …,,
-(x.14),Width of features straddling areaid:ce is checked by …,,
-(x.15a),"Drawn compatible, mask, and waffle-drop layers are allowed only inside areaid:mt (i.e., etest modules), or inside areaid:sl (i.e., between the outer and inner areaid:sl edges, but not in the die) or inside areaid:ft (i.e., frame, blankings). Exception: FOM/P1M/Metal waffle drop are allowed inside the die",P,
-(x.15b),"Rule X.15a exempted for cpmm.dg inside cellnames ""PadPLfp"", ""padPLhp"", ""padPLstg"" and ""padPLwlbi"" (for the SKY130di-5r-gsmc flow)",EXEMPT,
-(x.16),"Die must not overlap :drc_tag:`areaid.mt` (rule waived for test chips and exempted for cellnames ""*tech_CD_*"", ""*_techCD_*"", ""lazX_*"" or ""lazY_*"" )",,
-(x.17),"All labels must be within the ""drawing"" polygons of the layer; This check is enabled by using switch ""floating_labels""; Identifies floating labels which appear as warnings in LVS. Using this check would enable cleaner LVS run; Not a gate for tapeout",,
-(x.18),"Use redundant mcon, via, via2, via3 and via4 (Locations where additional vias/contacts can be added to existing single vias/contacts will be identified by this rule).\nSingle via under :drc_tag:`areaid.core` and :drc_tag:`areaid.standarc` are excluded from the single via check",RR,
-(x.19),"Lower left corner of the seal ring should be at origin i.e (0,0)",,
-(x.20),"Min spacing between pins on the same layer (center to center); Check enabled by switch ""IP_block""",,
-(x.21),prunde.dg is allowed only inside :drc_tag:`areaid.mt` or :drc_tag:`areaid.sc`,,
-(x.22),"No floating interconnects (poly, li1, met1-met5) or capm allowed; Rule flags interconnects with no path to poly, difftap or metal pins. Exempt floating layers can be excluded using poly_float, li1_float, m1_float, m2_float, m3_float, m4_float and m5_float text labels. Also flags an error if these text labels are placed on connected layers (not floating) and if the labels are not over the appropriate metal layer.  \nIf floating interconnects need to be connected at a higher level (Parent IP or Full chip), such floating interconnects can be exempted using poly_tie, li1_tie, m1_tie, m2_tie, m3_tie, m4_tie and m5_tie text labels.\nIt is the responsibility of the IP owner and chip/product owner to communicate and agree to the node each of these texted lines is connected to, if there is any risk to how a line is tied, and to what node.\nOnly metals outside :drc_tag:`areaid.stdcell` are checked.\n
+Name,Description,Flags,Value,Unit
+(x.1a),"p1m.md (OPC), DECA and AMKOR layers (pi1.dg, pmm.dg, rdl.dg, pi2.dg, ubm.dg, bump.dg) and mask data for p1m, met1, via, met2 must be on a grid of mm",,0.001,mm
+(x.1b),Data for SKY130 layout and mask on all layers except those mentioned in 1a must be on a grid of mm (except inside Seal ring),,0.005,mm
+(x.2),Angles permitted on: diff,,N/A,N/A
+(x.2),"Angles permitted on: diff except for:
+  - diff inside ""advSeal_6µm* OR cuPillarAdvSeal_6µm*"" pcell, 
+  - diff rings around the die at min total L>1000 µm and W=0.3 µm",,n x 90,deg
+(x.2),"Angles permitted on: tap (except inside :drc_tag:`areaid.en`), poly (except for ESD flare gates or gated_npn), li1(periphery), licon1, capm, mcon, via, via2. Anchors are exempted.",,n x 90,deg
+(x.2),Angles permitted on: via3 and via4. Anchors are exempted.,,n x 90,deg
+(x.2a),Analog circuits identified by :drc_tag:`areaid.analog` to use rectangular diff and tap geometries only; that are not to be merged into more complex shapes (T's or L's),,,
+(x.2c),"45 degree angles allowed on diff, tap inside UHVI",,,
+(x.3),Angles permitted on all other layers and in the seal ring for all the layers,,,
+(x.3a),"Angles permitted on all other layers except WLCSP layers (pmm, rdl, pmm2, ubm and bump)",,n x 45,deg
+(x.4),Electrical DR cover layout guidelines for electromigration,NC,,
+(x.5),"All ""pin""polygons must be within the ""drawing"" polygons of the layer",AL,,
+(x.6),All intra-layer separation checks will include a notch check,,,
+(x.7),Mask layer line and space checks must be done on all layers (checked with s.x rules),NC,,
+(x.8),"Use of areaid ""core"" layer (""coreid"") must be approved by technology",NC,,
+(x.9),"Shapes on maskAdd or maskDrop layers (""serifs"") are allowed in core only. Exempted are: 
+  - cfom md/mp inside ""advSeal_6um* OR cuPillarAdvSeal_6um*"" pcell 
+  - diff rings around the die at min total L>1000 um and W=0.3 um, and PMM/PDMM inside areaid:sl",,,
+(x.9),"Shapes on maskAdd or maskDrop layers (""serifs"") are allowed in core only. PMM/PDMM inside areaid:sl are excluded.",,N/A,N/A
+(x.10),"Res purpose layer for (diff, poly) cannot overlap licon1",,,
+(x.11),Metal fuses are drawn in met2,LVS,N/A,N/A
+(x.11),Metal fuses are drawn in met3,LVS,N/A,N/A
+(x.11),Metal fuses are drawn in met4,LVS,,
+(x.\n12a\n12b\n12c),"To comply with the minimum spacing requirement for layer X in the frame:
+  - Spacing of :drc_tag:`areaid.mt` to any non-ID layer
+  - Enclosure of any non-ID layer by :drc_tag:`areaid.mt`
+  - Rules exempted for cells with name ""*_buildspace""",F,,
+(x.12d),Spacing of :drc_tag:`areaid.mt` to huge_metX (Exempt met3.dg),F,N/A,N/A
+(x.12d),Spacing of :drc_tag:`areaid.mt` to huge_metX (Exempt met5.dg),F,,
+(x.12e),Enclosure of huge_metX by :drc_tag:`areaid.mt` (Exempt met3.dg),F,N/A,N/A
+(x.12e),Enclosure of huge_metX by :drc_tag:`areaid.mt` (Exempt met5.dg),F,,
+(x.13),Spacing between features located across areaid:ce is checked by …,,,
+(x.14),Width of features straddling areaid:ce is checked by …,,,
+(x.15a),"Drawn compatible, mask, and waffle-drop layers are allowed only inside areaid:mt (i.e., etest modules), or inside areaid:sl (i.e., between the outer and inner areaid:sl edges, but not in the die) or inside areaid:ft (i.e., frame, blankings). Exception: FOM/P1M/Metal waffle drop are allowed inside the die",P,,
+(x.15b),"Rule X.15a exempted for cpmm.dg inside cellnames ""PadPLfp"", ""padPLhp"", ""padPLstg"" and ""padPLwlbi"" (for the SKY130di-5r-gsmc flow)",EXEMPT,,
+(x.16),"Die must not overlap :drc_tag:`areaid.mt` (rule waived for test chips and exempted for cellnames ""*tech_CD_*"", ""*_techCD_*"", ""lazX_*"" or ""lazY_*"" )",,,
+(x.17),"All labels must be within the ""drawing"" polygons of the layer; This check is enabled by using switch ""floating_labels""; Identifies floating labels which appear as warnings in LVS. Using this check would enable cleaner LVS run; Not a gate for tapeout",,,
+(x.18),"| Use redundant mcon, via, via2, via3 and via4 (Locations where additional vias/contacts can be added to existing single vias/contacts will be identified by this rule).
+| Single via under :drc_tag:`areaid.core` and :drc_tag:`areaid.standarc` are excluded from the single via check",RR,,
+(x.19),"Lower left corner of the seal ring should be at origin i.e (0,0)",,,
+(x.20),"Min spacing between pins on the same layer (center to center); Check enabled by switch ""IP_block""",,,
+(x.21),prunde.dg is allowed only inside :drc_tag:`areaid.mt` or :drc_tag:`areaid.sc`,,,
+(x.22),"| No floating interconnects (poly, li1, met1-met5) or capm allowed; Rule flags interconnects with no path to poly, difftap or metal pins. Exempt floating layers can be excluded using poly_float, li1_float, m1_float, m2_float, m3_float, m4_float and m5_float text labels. Also flags an error if these text labels are placed on connected layers (not floating) and if the labels are not over the appropriate metal layer.  
+| If floating interconnects need to be connected at a higher level (Parent IP or Full chip), such floating interconnects can be exempted using poly_tie, li1_tie, m1_tie, m2_tie, m3_tie, m4_tie and m5_tie text labels.
+| It is the responsibility of the IP owner and chip/product owner to communicate and agree to the node each of these texted lines is connected to, if there is any risk to how a line is tied, and to what node.
+| Only metals outside :drc_tag:`areaid.stdcell` are checked.
+| 
 The following are exempt from x.22 violations: _techCD_ , inductor.dg, modulecut, capacitors and s8blerf
-The 'notPublicCell' switch will deactivate this rule",RC,
-(x.23a),:drc_tag:`areaid.sl` must not overlap diff,,N/A
-(x.23b),diff cannot straddle :drc_tag:`areaid.sl`,,
-(x.23c),":drc_tag:`areaid.sl` must not overlap tap, poly, li1 and metX",,
-(x.23d),":drc_tag:`areaid.sl` must not overlap tap, poly",,N/A
-(x.23e),"areaid:sl must not overlap li1 and metX for pcell ""advSeal_6um""",,N/A
-(x.23f),"areaid:SubstrateCut (:drc_tag:`areaid.st`, local_sub) must not straddle p+ tap",RR,
-(x.24),condiode label must be in iso_pwell,,
-(x.25),"pnp.dg must be only within cell name ""s8rf_pnp"", ""s8rf_pnp5x"" or ""s8tesd_iref_pnp"", ""stk14ecx_*""",,
-(x.26),"""advSeal_6um"" pcell must overlap diff",,
-(x.27),"If the sealring is present, then partnum is required.  To exempt the requirement, place text.dg saying ""partnum_not_necessary"".\n""partnum*block"" pcell should be used instead of ""partnum*"" pcells",RR,N/A
-(x.28),Min width of :drc_tag:`areaid.sl`,,N/A
-(x.29),nfet must be enclosed by dnwell. Rule is checked when switch nfet_in_dnwell is turned on.,,
+The 'notPublicCell' switch will deactivate this rule",RC,,
+(x.23a),:drc_tag:`areaid.sl` must not overlap diff,,N/A,N/A
+(x.23b),diff cannot straddle :drc_tag:`areaid.sl`,,,
+(x.23c),":drc_tag:`areaid.sl` must not overlap tap, poly, li1 and metX",,,
+(x.23d),":drc_tag:`areaid.sl` must not overlap tap, poly",,N/A,N/A
+(x.23e),"areaid:sl must not overlap li1 and metX for pcell ""advSeal_6um""",,N/A,N/A
+(x.23f),"areaid:SubstrateCut (:drc_tag:`areaid.st`, local_sub) must not straddle p+ tap",RR,,
+(x.24),condiode label must be in iso_pwell,,,
+(x.25),"pnp.dg must be only within cell name ""s8rf_pnp"", ""s8rf_pnp5x"" or ""s8tesd_iref_pnp"", ""stk14ecx_*""",,,
+(x.26),"""advSeal_6um"" pcell must overlap diff",,,
+(x.27),"| If the sealring is present, then partnum is required.  To exempt the requirement, place text.dg saying ""partnum_not_necessary"".
+| ""partnum*block"" pcell should be used instead of ""partnum*"" pcells",RR,N/A,N/A
+(x.28),Min width of :drc_tag:`areaid.sl`,,N/A,N/A
+(x.29),nfet must be enclosed by dnwell. Rule is checked when switch nfet_in_dnwell is turned on.,,,
diff --git a/docs/rules/periphery/p020-dnwell_dotdash.csv b/docs/rules/periphery/p020-dnwell_dotdash.csv
index d87b1d6..b537658 100644
--- a/docs/rules/periphery/p020-dnwell_dotdash.csv
+++ b/docs/rules/periphery/p020-dnwell_dotdash.csv
@@ -1,11 +1,11 @@
-Name,Description,Flags,Value
-(dnwell.2),Min width of deep nwell,,3.000
-(dnwell.3),Min spacing between deep nwells. Rule exempt inside UHVI.,,6.300
-(dnwell.3a),Min spacing between deep nwells on same net inside UHVI.,,N/A
-(dnwell.3b),Min spacing between deep-nwells inside UHVI and deep-nwell outside UHVI,,N/A
-(dnwell.3c),Min spacing between deep-nwells inside UHVI and nwell outsideUHVI,,N/A
-(dnwell.3d),Min spacing between deep-nwells inside UHVI on different nets,,N/A
-(dnwell.4),Dnwell can not overlap pnp:dg,,
-(dnwell.5),P+_diff can not straddle Dnwell,,
-(dnwell.6),RF NMOS must be enclosed by deep nwell (RF FETs are listed in $DESIGN/config/tech/model_set/calibre/fixed_layout_model_map of corresponding techs),,
-(dnwell.7),Dnwell can not straddle areaid:substratecut,,
+Name,Description,Flags,Value,Unit
+(dnwell.2),Min width of deep nwell,,3.000,µm
+(dnwell.3),Min spacing between deep nwells. Rule exempt inside UHVI.,,6.300,µm
+(dnwell.3a),Min spacing between deep nwells on same net inside UHVI.,,N/A,N/A
+(dnwell.3b),Min spacing between deep-nwells inside UHVI and deep-nwell outside UHVI,,N/A,N/A
+(dnwell.3c),Min spacing between deep-nwells inside UHVI and nwell outsideUHVI,,N/A,N/A
+(dnwell.3d),Min spacing between deep-nwells inside UHVI on different nets,,N/A,N/A
+(dnwell.4),Dnwell can not overlap pnp:dg,,,
+(dnwell.5),P+_diff can not straddle Dnwell,,,
+(dnwell.6),RF NMOS must be enclosed by deep nwell (RF FETs are listed in $DESIGN/config/tech/model_set/calibre/fixed_layout_model_map of corresponding techs),,,
+(dnwell.7),Dnwell can not straddle areaid:substratecut,,,
diff --git a/docs/rules/periphery/p021-nwell_dotdash.csv b/docs/rules/periphery/p021-nwell_dotdash.csv
index 12bece3..136e250 100644
--- a/docs/rules/periphery/p021-nwell_dotdash.csv
+++ b/docs/rules/periphery/p021-nwell_dotdash.csv
@@ -1,13 +1,13 @@
-Name,Description,Flags,Value
-(nwell.1),Width of nwell,,0.840
-(nwell.2a),Spacing between two n-wells,,1.270
-(nwell.2b),Manual merge wells if less than minimum,,
-(nwell.4),All n-wells will contain metal-contacted tap  (rule checks only for licon on tap) . Rule exempted from high voltage cells inside UHVI,,
+Name,Description,Flags,Value,Unit
+(nwell.1),Width of nwell,,0.840,µm
+(nwell.2a),Spacing between two n-wells,,1.270,µm
+(nwell.2b),Manual merge wells if less than minimum,,,
+(nwell.4),All n-wells will contain metal-contacted tap  (rule checks only for licon on tap) . Rule exempted from high voltage cells inside UHVI,,,
 (nwell.5),"Deep nwell must be enclosed by nwell by atleast... Exempted inside UHVI or :drc_tag:`areaid.lw`
-Nwells can merge over deep nwell if spacing too small (as in rule nwell.2)",TC,0.400
-(nwell.5a),min enclosure of nwell by dnwell inside UHVI,,N/A
-(nwell.5b),nwell inside UHVI must not be on the same net as nwell outside UHVI,,N/A
-(nwell.6),Min enclosure of nwell hole by deep nwell outside UHVI,TC,1.030
+Nwells can merge over deep nwell if spacing too small (as in rule nwell.2)",TC,0.400,µm
+(nwell.5a),min enclosure of nwell by dnwell inside UHVI,,N/A,N/A
+(nwell.5b),nwell inside UHVI must not be on the same net as nwell outside UHVI,,N/A,N/A
+(nwell.6),Min enclosure of nwell hole by deep nwell outside UHVI,TC,1.030,µm
 (nwell.7),"Min spacing between nwell and deep nwell on separate nets
 Spacing between nwell and deep nwell on the same net is set by the sum of the rules nwell.2 and nwell.5. By default, DRC run on a cell checks for the separate-net spacing, when nwell and deep nwell nets are separate within the cell hierarchy and are joined in the upper hierarchy. To allow net names to be joined and make the same-net rule applicable in this case, the ""joinNets"" switch should be turned on.
-waffle_chip",TC,4.500
+waffle_chip",TC,4.500,µm
diff --git a/docs/rules/periphery/p022-pwbm_dotdash.csv b/docs/rules/periphery/p022-pwbm_dotdash.csv
index cbbf5da..bce812d 100644
--- a/docs/rules/periphery/p022-pwbm_dotdash.csv
+++ b/docs/rules/periphery/p022-pwbm_dotdash.csv
@@ -1,6 +1,6 @@
-Name,Description,Flags,Value
-(pwbm.1),Min width of pwbm.dg,,N/A
-(pwbm.2),Min spacing between two pwbm.dg inside UHVI,,N/A
-(pwbm.3),Min enclosure of dnwell:dg by pwbm.dg inside UHVI (exempt pwbm hole inside dnwell),,N/A
-(pwbm.4),dnwell inside UHVI must be enclosed by pwbm (exempt pwbm hole inside dnwell),,N/A
-(pwbm.5),Min Space between two pwbm holes inside UHVI,,N/A
+Name,Description,Flags,Value,Unit
+(pwbm.1),Min width of pwbm.dg,,N/A,N/A
+(pwbm.2),Min spacing between two pwbm.dg inside UHVI,,N/A,N/A
+(pwbm.3),Min enclosure of dnwell:dg by pwbm.dg inside UHVI (exempt pwbm hole inside dnwell),,N/A,N/A
+(pwbm.4),dnwell inside UHVI must be enclosed by pwbm (exempt pwbm hole inside dnwell),,N/A,N/A
+(pwbm.5),Min Space between two pwbm holes inside UHVI,,N/A,N/A
diff --git a/docs/rules/periphery/p022-pwdem_dotdash.csv b/docs/rules/periphery/p022-pwdem_dotdash.csv
index 7f181a9..e657786 100644
--- a/docs/rules/periphery/p022-pwdem_dotdash.csv
+++ b/docs/rules/periphery/p022-pwdem_dotdash.csv
@@ -1,7 +1,7 @@
-Name,Description,Flags,Value
-(pwdem.1),Min width of pwdem.dg,,N/A
-(pwdem.2),Min spacing between two pwdem.dg inside UHVI on same net,,N/A
-(pwdem.3),Min enclosure of pwdem:dg by pwbm.dg inside UHVI,,N/A
-(pwdem.4),pwdem.dg must be enclosed by UHVI,,N/A
-(pwdem.5),pwdem.dg inside UHVI must be enclosed by deep nwell,,N/A
-(pwdem.6),Min enclosure of pwdem:dg by deep nwell inside UHVI,,N/A
+Name,Description,Flags,Value,Unit
+(pwdem.1),Min width of pwdem.dg,,N/A,N/A
+(pwdem.2),Min spacing between two pwdem.dg inside UHVI on same net,,N/A,N/A
+(pwdem.3),Min enclosure of pwdem:dg by pwbm.dg inside UHVI,,N/A,N/A
+(pwdem.4),pwdem.dg must be enclosed by UHVI,,N/A,N/A
+(pwdem.5),pwdem.dg inside UHVI must be enclosed by deep nwell,,N/A,N/A
+(pwdem.6),Min enclosure of pwdem:dg by deep nwell inside UHVI,,N/A,N/A
diff --git a/docs/rules/periphery/p023-hvtp_dotdash.csv b/docs/rules/periphery/p023-hvtp_dotdash.csv
index 1290173..341e2a2 100644
--- a/docs/rules/periphery/p023-hvtp_dotdash.csv
+++ b/docs/rules/periphery/p023-hvtp_dotdash.csv
@@ -1,7 +1,7 @@
-Name,Description,Flags,Value
-(hvtp.1),Min width of hvtp,,0.380
-(hvtp.2),Min spacing between hvtp to hvtp,,0.380
-(hvtp.3),Min enclosure of pfet by hvtp,P,0.180
-(hvtp.4),Min spacing between pfet and hvtp,P,0.180
-(hvtp.5),Min area of hvtp (um^2),,0.265
-(hvtp.6),Min area of hvtp Holes (um^2),,0.265
+Name,Description,Flags,Value,Unit
+(hvtp.1),Min width of hvtp,,0.380,µm
+(hvtp.2),Min spacing between hvtp to hvtp,,0.380,µm
+(hvtp.3),Min enclosure of pfet by hvtp,P,0.180,µm
+(hvtp.4),Min spacing between pfet and hvtp,P,0.180,µm
+(hvtp.5),Min area of hvtp,,0.265,µm²
+(hvtp.6),Min area of hvtp Holes,,0.265,µm²
diff --git a/docs/rules/periphery/p024-hvtr_dotdash.csv b/docs/rules/periphery/p024-hvtr_dotdash.csv
index 98b5bc4..ac0d962 100644
--- a/docs/rules/periphery/p024-hvtr_dotdash.csv
+++ b/docs/rules/periphery/p024-hvtr_dotdash.csv
@@ -1,4 +1,4 @@
-Name,Description,Flags,Value
-(hvtr.1),Min width of hvtr,,0.380
-(hvtr.2),Min spacing between hvtp to hvtr,,0.380
-(hvtr.3),Min enclosure of pfet by hvtr,P,0.180
+Name,Description,Flags,Value,Unit
+(hvtr.1),Min width of hvtr,,0.380,µm
+(hvtr.2),Min spacing between hvtp to hvtr,,0.380,µm
+(hvtr.3),Min enclosure of pfet by hvtr,P,0.180,µm
diff --git a/docs/rules/periphery/p024-lvtn_dotdash.csv b/docs/rules/periphery/p024-lvtn_dotdash.csv
index ac4693d..37dd940 100644
--- a/docs/rules/periphery/p024-lvtn_dotdash.csv
+++ b/docs/rules/periphery/p024-lvtn_dotdash.csv
@@ -1,11 +1,11 @@
-Name,Description,Flags,Value
-(lvtn.1a),Min width of lvtn,,0.380
-(lvtn.2),Min space lvtn to lvtn,,0.380
-(lvtn.3a),Min spacing of lvtn to gate. Rule exempted inside UHVI.,P,0.180
-(lvtn.3b),Min spacing of lvtn to pfet along the S/D direction,P,0.235
-(lvtn.4b),Min enclosure of gate by lvtn. Rule exempted inside UHVI.,P,0.180
-(lvtn.9),"Min spacing, no overlap, between lvtn and hvtp",,0.380
-(lvtn.10),Min enclosure of lvtn by (nwell not overlapping Var_channel) (exclude coincident edges),,0.380
-(lvtn.12),Min spacing between lvtn and (nwell inside :drc_tag:`areaid.ce`),,0.380
-(lvtn.13),Min area of lvtn (um^2),,0.265
-(lvtn.14),Min area of lvtn Holes (um^2),,0.265
+Name,Description,Flags,Value,Unit
+(lvtn.1a),Min width of lvtn,,0.380,µm
+(lvtn.2),Min space lvtn to lvtn,,0.380,µm
+(lvtn.3a),Min spacing of lvtn to gate. Rule exempted inside UHVI.,P,0.180,µm
+(lvtn.3b),Min spacing of lvtn to pfet along the S/D direction,P,0.235,µm
+(lvtn.4b),Min enclosure of gate by lvtn. Rule exempted inside UHVI.,P,0.180,µm
+(lvtn.9),"Min spacing, no overlap, between lvtn and hvtp",,0.380,µm
+(lvtn.10),Min enclosure of lvtn by (nwell not overlapping Var_channel) (exclude coincident edges),,0.380,µm
+(lvtn.12),Min spacing between lvtn and (nwell inside :drc_tag:`areaid.ce`),,0.380,µm
+(lvtn.13),Min area of lvtn,,0.265,µm²
+(lvtn.14),Min area of lvtn Holes,,0.265,µm²
diff --git a/docs/rules/periphery/p025-ncm_dotdash.csv b/docs/rules/periphery/p025-ncm_dotdash.csv
index 4493c40..e59cb84 100644
--- a/docs/rules/periphery/p025-ncm_dotdash.csv
+++ b/docs/rules/periphery/p025-ncm_dotdash.csv
@@ -1,12 +1,12 @@
-Name,Description,Flags,Value
-(ncm.X.2),Ncm overlapping areaid:ce is checked for core rules only,,
-(ncm.X.3),Ncm overlapping core cannot overlap N+diff in periphery,TC,
-(ncm.1),Width of ncm,,0.380
-(ncm.2a),Spacing of ncm to ncm,,0.380
-(ncm.2b),Manual merge ncm if space is below minimum,,
-(ncm.3),Min enclosure of P+diff by Ncm,P,0.180
-(ncm.4),Min enclosure of P+diff within (areaid:ed AndNot areaid:de) by Ncm,P,0.180
-(ncm.5),"Min space, no overlap, between ncm and (LVTN_gate) OR (diff containing lvtn)",P,0.230
-(ncm.6),"Min space, no overlap, between ncm and nfet",P,0.200
-(ncm.7),Min area of ncm (um^2),,0.265
-(ncm.8),Min area of ncm Holes (um^2),,0.265
+Name,Description,Flags,Value,Unit
+(ncm.X.2),Ncm overlapping areaid:ce is checked for core rules only,,,
+(ncm.X.3),Ncm overlapping core cannot overlap N+diff in periphery,TC,,
+(ncm.1),Width of ncm,,0.380,µm
+(ncm.2a),Spacing of ncm to ncm,,0.380,µm
+(ncm.2b),Manual merge ncm if space is below minimum,,,
+(ncm.3),Min enclosure of P+diff by Ncm,P,0.180,µm
+(ncm.4),Min enclosure of P+diff within (areaid:ed AndNot areaid:de) by Ncm,P,0.180,µm
+(ncm.5),"Min space, no overlap, between ncm and (LVTN_gate) OR (diff containing lvtn)",P,0.230,µm
+(ncm.6),"Min space, no overlap, between ncm and nfet",P,0.200,µm
+(ncm.7),Min area of ncm,,0.265,µm²
+(ncm.8),Min area of ncm Holes,,0.265,µm²
diff --git a/docs/rules/periphery/p026-difftap_dotdash.csv b/docs/rules/periphery/p026-difftap_dotdash.csv
index 664bbca..408fd9b 100644
--- a/docs/rules/periphery/p026-difftap_dotdash.csv
+++ b/docs/rules/periphery/p026-difftap_dotdash.csv
@@ -1,16 +1,16 @@
-Name,Description,Flags,Value
-(difftap.1),Width of diff or tap,P,0.150
-(difftap.2),"Minimum channel width (Diff And Poly) except for FETs inside :drc_tag:`areaid.sc`: Rule exempted in the SP8* flows only, for the cells listed in rule difftap.2a",P,0.420
-(difftap.2a),"Minimum channel width (Diff And Poly) for cell names ""s8cell_ee_plus_sseln_a"", ""s8cell_ee_plus_sseln_b"", ""s8cell_ee_plus_sselp_a"", ""s8cell_ee_plus_sselp_b"" , ""s8fpls_pl8"", ""s8fpls_rdrv4"" , ""s8fpls_rdrv4f"" and ""s8fpls_rdrv8""",P,NA
-(difftap.2b),Minimum channel width (Diff And Poly) for FETs inside :drc_tag:`areaid.sc`,P,0.360
-(difftap.3),"Spacing of diff to diff, tap to tap, or non-abutting diff to tap",,0.270
-(difftap.4),Min tap bound by one diffusion,,0.290
-(difftap.5),Min tap bound by two diffusions,P,0.400
-(difftap.6),Diff and tap are not allowed to extend beyond their abutting edge,,
-(difftap.7),Spacing of diff/tap abutting edge to a non-conciding diff or tap edge,NE,0.130
-(difftap.8),Enclosure of (p+) diffusion by N-well. Rule exempted inside UHVI.,DE NE P,0.180
-(difftap.9),Spacing of (n+) diffusion to N-well outside UHVI,DE NE P,0.340
-(difftap.10),Enclosure of (n+)  tap by N-well. Rule exempted inside UHVI.,NE P,0.180
-(difftap.11),Spacing of (p+) tap to  N-well. Rule exempted inside UHVI.,,0.130
-(difftap.12),ESD_nwell_tap is considered shorted to the abutting diff,NC,
-(difftap.13),Diffusion or the RF FETS in Table H5 is defined by Ldiff and Wdiff.,,
+Name,Description,Flags,Value,Unit
+(difftap.1),Width of diff or tap,P,0.150,µm
+(difftap.2),"Minimum channel width (Diff And Poly) except for FETs inside :drc_tag:`areaid.sc`: Rule exempted in the SP8* flows only, for the cells listed in rule difftap.2a",P,0.420,µm
+(difftap.2a),"Minimum channel width (Diff And Poly) for cell names ""s8cell_ee_plus_sseln_a"", ""s8cell_ee_plus_sseln_b"", ""s8cell_ee_plus_sselp_a"", ""s8cell_ee_plus_sselp_b"" , ""s8fpls_pl8"", ""s8fpls_rdrv4"" , ""s8fpls_rdrv4f"" and ""s8fpls_rdrv8""",P,NA,µm
+(difftap.2b),Minimum channel width (Diff And Poly) for FETs inside :drc_tag:`areaid.sc`,P,0.360,µm
+(difftap.3),"Spacing of diff to diff, tap to tap, or non-abutting diff to tap",,0.270,µm
+(difftap.4),Min tap bound by one diffusion,,0.290,
+(difftap.5),Min tap bound by two diffusions,P,0.400,
+(difftap.6),Diff and tap are not allowed to extend beyond their abutting edge,,,
+(difftap.7),Spacing of diff/tap abutting edge to a non-conciding diff or tap edge,NE,0.130,µm
+(difftap.8),Enclosure of (p+) diffusion by N-well. Rule exempted inside UHVI.,DE NE P,0.180,µm
+(difftap.9),Spacing of (n+) diffusion to N-well outside UHVI,DE NE P,0.340,µm
+(difftap.10),Enclosure of (n+)  tap by N-well. Rule exempted inside UHVI.,NE P,0.180,µm
+(difftap.11),Spacing of (p+) tap to  N-well. Rule exempted inside UHVI.,,0.130,µm
+(difftap.12),ESD_nwell_tap is considered shorted to the abutting diff,NC,,
+(difftap.13),Diffusion or the RF FETS in Table H5 is defined by Ldiff and Wdiff.,,,
diff --git a/docs/rules/periphery/p027-tunm_dotdash.csv b/docs/rules/periphery/p027-tunm_dotdash.csv
index 06f5e7a..627ce78 100644
--- a/docs/rules/periphery/p027-tunm_dotdash.csv
+++ b/docs/rules/periphery/p027-tunm_dotdash.csv
@@ -1,9 +1,9 @@
-Name,Description,Flags,Value
-(tunm.1),Min width of tunm,,0.410
-(tunm.2),Min spacing of tunm to tunm,,0.500
-(tunm.3),Extension of tunm beyond (poly and diff),,0.095
-(tunm.4),Min spacing of tunm to (poly and diff) outside tunm,,0.095
-(tunm.5),(poly and diff) may not straddle tunm,,
-(tunm.6a),Tunm outside deep n-well is not allowed,TC,
-(tunm.7),Min tunm area,,0.672
-(tunm.8),tunm must be enclosed by :drc_tag:`areaid.ce`,,
+Name,Description,Flags,Value,Unit
+(tunm.1),Min width of tunm,,0.410,µm
+(tunm.2),Min spacing of tunm to tunm,,0.500,µm
+(tunm.3),Extension of tunm beyond (poly and diff),,0.095,
+(tunm.4),Min spacing of tunm to (poly and diff) outside tunm,,0.095,µm
+(tunm.5),(poly and diff) may not straddle tunm,,,
+(tunm.6a),Tunm outside deep n-well is not allowed,TC,,
+(tunm.7),Min tunm area,,0.672,µm²
+(tunm.8),tunm must be enclosed by :drc_tag:`areaid.ce`,,,
diff --git a/docs/rules/periphery/p028-poly_dotdash.csv b/docs/rules/periphery/p028-poly_dotdash.csv
index 9f04c28..224fef5 100644
--- a/docs/rules/periphery/p028-poly_dotdash.csv
+++ b/docs/rules/periphery/p028-poly_dotdash.csv
@@ -1,18 +1,18 @@
-Name,Description,Flags,Value
-(poly.X.1),All FETs would be checked for W/Ls as documented in spec 001-02735  (Exempt FETs that are pruned; exempt for W/L's inside :drc_tag:`areaid.sc` and inside cell name scs8*decap* and listed in the MRGA as a decap only W/L),,
-(poly.X.1a),Min & max dummy_poly L is equal to min L allowed for corresponding device type (exempt rule for dummy_poly in cells listed on Table H3),,
-(poly.1a),Width of poly,,0.150
-(poly.1b),Min channel length (poly width) for pfet overlapping lvtn (exempt rule for dummy_poly in cells listed on Table H3),,0.350
-(poly.2),Spacing of poly to poly except for poly.c2 and poly.c3; Exempt cell: sr_bltd_eq where it is same as poly.c2,,0.210
-(poly.3),Min poly resistor width,,0.330
-(poly.4),Spacing of poly on field to diff (parallel edges only),P,0.075
-(poly.5),Spacing of poly on field to tap,P,0.055
-(poly.6),Spacing of poly on diff to abutting tap (min source),P,0.300
-(poly.7),Extension of diff beyond poly (min drain),P,0.250
-(poly.8),Extension of poly beyond diffusion (endcap),P,0.130
-(poly.9),Poly resistor spacing to poly or spacing (no overlap) to diff/tap,,0.480
-(poly.10),Poly can't overlap inner corners of diff,,
-(poly.11),No 90 deg turns of poly on diff,,
-(poly.12),"(Poly NOT (nwell NOT hvi)) may not overlap tap; Rule exempted for cell name ""s8fgvr_n_fg2"" and gated_npn and inside UHVI.",P,
-(poly.15),Poly must not overlap diff:rs,,
-(poly.16),"Inside RF FETs defined in Table H5, poly cannot overlap poly across multiple adjacent instances",,
+Name,Description,Flags,Value,Unit
+(poly.X.1),All FETs would be checked for W/Ls as documented in spec 001-02735  (Exempt FETs that are pruned; exempt for W/L's inside :drc_tag:`areaid.sc` and inside cell name scs8*decap* and listed in the MRGA as a decap only W/L),,,
+(poly.X.1a),Min & max dummy_poly L is equal to min L allowed for corresponding device type (exempt rule for dummy_poly in cells listed on Table H3),,,
+(poly.1a),Width of poly,,0.150,µm
+(poly.1b),Min channel length (poly width) for pfet overlapping lvtn (exempt rule for dummy_poly in cells listed on Table H3),,0.350,µm
+(poly.2),Spacing of poly to poly except for poly.c2 and poly.c3; Exempt cell: sr_bltd_eq where it is same as poly.c2,,0.210,µm
+(poly.3),Min poly resistor width,,0.330,µm
+(poly.4),Spacing of poly on field to diff (parallel edges only),P,0.075,µm
+(poly.5),Spacing of poly on field to tap,P,0.055,µm
+(poly.6),Spacing of poly on diff to abutting tap (min source),P,0.300,µm
+(poly.7),Extension of diff beyond poly (min drain),P,0.250,
+(poly.8),Extension of poly beyond diffusion (endcap),P,0.130,
+(poly.9),Poly resistor spacing to poly or spacing (no overlap) to diff/tap,,0.480,µm
+(poly.10),Poly can't overlap inner corners of diff,,,
+(poly.11),No 90 deg turns of poly on diff,,,
+(poly.12),"(Poly NOT (nwell NOT hvi)) may not overlap tap; Rule exempted for cell name ""s8fgvr_n_fg2"" and gated_npn and inside UHVI.",P,,
+(poly.15),Poly must not overlap diff:rs,,,
+(poly.16),"Inside RF FETs defined in Table H5, poly cannot overlap poly across multiple adjacent instances",,,
diff --git a/docs/rules/periphery/p029-rpm_dotdash.csv b/docs/rules/periphery/p029-rpm_dotdash.csv
index ce67a05..46bedd2 100644
--- a/docs/rules/periphery/p029-rpm_dotdash.csv
+++ b/docs/rules/periphery/p029-rpm_dotdash.csv
@@ -1,22 +1,26 @@
-Name,Description,Flags,Value
-(rpm.1a),Min width of rpm,,1.270
-(rpm.1b),Min/Max prec_resistor width xhrpoly_0p35,,0.350
-(rpm.1c),Min/Max prec_resistor width xhrpoly_0p69,,0.690
-(rpm.1d),Min/Max prec_resistor width xhrpoly_1p41,,1.410
-(rpm.1e),Min/Max prec_resistor width xhrpoly_2p85,,2.850
-(rpm.1f),Min/Max prec_resistor width xhrpoly_5p73,,5.730
-(rpm.1g),Only 1 licon is allowed in xhrpoly_0p35 prec_resistor_terminal,,
-(rpm.1h),Only 1 licon is allowed in xhrpoly_0p69 prec_resistor_terminal,,
-(rpm.1i),Only 2 licons are allowed in xhrpoly_1p41 prec_resistor_terminal,,
-(rpm.1j),Only 4 licons are allowed in xhrpoly_2p85 prec_resistor_terminal,,
-(rpm.1k),Only 8 licons are allowed in xhrpoly_5p73 prec_resistor_terminal,,
-(rpm.2),Min spacing of rpm to rpm,,0.840
-(rpm.3),rpm must enclose prec_resistor by atleast,,0.200
-(rpm.4),prec_resistor must be enclosed by psdm by atleast,,0.110
-(rpm.5),prec_resistor must be enclosed by npc by atleast,,0.095
-(rpm.6),"Min spacing, no overlap, of rpm and nsdm",,0.200
-(rpm.7),Min spacing between rpm and poly,,0.200
-(rpm.8),poly must not straddle rpm,,
-(rpm.9),"Min space, no overlap, between prec_resistor and hvntm",,0.185
-(rpm.10),Min spacing of rpm to pwbm,,N/A
-(rpm.11),rpm should not overlap or straddle pwbm except cells\ns8usbpdv2_csa_top\ns8usbpdv2_20vconn_sw_300ma_ovp_ngate_unit\ns8usbpdv2_20vconn_sw_300ma_ovp\ns8usbpdv2_20sbu_sw_300ma_ovp,,N/A
+Name,Description,Flags,Value,Unit
+(rpm.1a),Min width of rpm,,1.270,µm
+(rpm.1b),Min/Max prec_resistor width xhrpoly_0p35,,0.350,µm
+(rpm.1c),Min/Max prec_resistor width xhrpoly_0p69,,0.690,µm
+(rpm.1d),Min/Max prec_resistor width xhrpoly_1p41,,1.410,µm
+(rpm.1e),Min/Max prec_resistor width xhrpoly_2p85,,2.850,µm
+(rpm.1f),Min/Max prec_resistor width xhrpoly_5p73,,5.730,µm
+(rpm.1g),Only 1 licon is allowed in xhrpoly_0p35 prec_resistor_terminal,,,
+(rpm.1h),Only 1 licon is allowed in xhrpoly_0p69 prec_resistor_terminal,,,
+(rpm.1i),Only 2 licons are allowed in xhrpoly_1p41 prec_resistor_terminal,,,
+(rpm.1j),Only 4 licons are allowed in xhrpoly_2p85 prec_resistor_terminal,,,
+(rpm.1k),Only 8 licons are allowed in xhrpoly_5p73 prec_resistor_terminal,,,
+(rpm.2),Min spacing of rpm to rpm,,0.840,µm
+(rpm.3),rpm must enclose prec_resistor by atleast,,0.200,
+(rpm.4),prec_resistor must be enclosed by psdm by atleast,,0.110,µm
+(rpm.5),prec_resistor must be enclosed by npc by atleast,,0.095,µm
+(rpm.6),"Min spacing, no overlap, of rpm and nsdm",,0.200,µm
+(rpm.7),Min spacing between rpm and poly,,0.200,µm
+(rpm.8),poly must not straddle rpm,,,
+(rpm.9),"Min space, no overlap, between prec_resistor and hvntm",,0.185,µm
+(rpm.10),Min spacing of rpm to pwbm,,N/A,N/A
+(rpm.11),"| rpm should not overlap or straddle pwbm except cells
+| s8usbpdv2_csa_top
+| s8usbpdv2_20vconn_sw_300ma_ovp_ngate_unit
+| s8usbpdv2_20vconn_sw_300ma_ovp
+| s8usbpdv2_20sbu_sw_300ma_ovp",,N/A,N/A
diff --git a/docs/rules/periphery/p030-varac_dotdash.csv b/docs/rules/periphery/p030-varac_dotdash.csv
index 57bcd5d..469f67a 100644
--- a/docs/rules/periphery/p030-varac_dotdash.csv
+++ b/docs/rules/periphery/p030-varac_dotdash.csv
@@ -1,9 +1,9 @@
-Name,Description,Flags,Value
-(varac.1),Min channel length (poly width) of Var_channel,,0.180
-(varac.2),Min channel width (tap width) of Var_channel,,1.000
-(varac.3),Min spacing between hvtp to Var_channel,,0.180
-(varac.4),Min spacing of licon on tap to Var_channel,,0.250
-(varac.5),Min enclosure of poly overlapping Var_channel by nwell,,0.150
-(varac.6),Min spacing between VaracTap and difftap,,0.270
-(varac.7),Nwell overlapping Var_channel must not overlap P+ diff,,
-(varac.8),Min enclosure of Var_channel by hvtp,,0.255
+Name,Description,Flags,Value,Unit
+(varac.1),Min channel length (poly width) of Var_channel,,0.180,µm
+(varac.2),Min channel width (tap width) of Var_channel,,1.000,µm
+(varac.3),Min spacing between hvtp to Var_channel,,0.180,µm
+(varac.4),Min spacing of licon on tap to Var_channel,,0.250,µm
+(varac.5),Min enclosure of poly overlapping Var_channel by nwell,,0.150,µm
+(varac.6),Min spacing between VaracTap and difftap,,0.270,µm
+(varac.7),Nwell overlapping Var_channel must not overlap P+ diff,,,
+(varac.8),Min enclosure of Var_channel by hvtp,,0.255,µm
diff --git a/docs/rules/periphery/p031-photo_dotdash.csv b/docs/rules/periphery/p031-photo_dotdash.csv
index 3813d11..4912b21 100644
--- a/docs/rules/periphery/p031-photo_dotdash.csv
+++ b/docs/rules/periphery/p031-photo_dotdash.csv
@@ -1,12 +1,12 @@
-Name,Description,Flags,Value
-(photo.1),Rules dnwell.3 and nwell.5 are exempted for photoDiode,,
-(photo.2),Min/Max width of photoDiode,,3.000
-(photo.3),Min spacing between photoDiode,,5.000
-(photo.4),Min spacing between photoDiode and deep nwell,,5.300
-(photo.5),photoDiode edges must be coincident with :drc_tag:`areaid.po`,,
-(photo.6),photoDiode must be enclosed by dnwell ring,,
-(photo.7),photoDiode must be enclosed by p+ tap ring,,
-(photo.8),Min/Max width of nwell inside photoDiode,,0.840
-(photo.9),Min/Max enclosure of nwell by photoDiode,,1.080
-(photo.10),Min/Max width of tap inside photoDiode,,0.410
-(photo.11),Min/Max enclosure of tap by nwell inside photoDiode,,0.215
+Name,Description,Flags,Value,Unit
+(photo.1),Rules dnwell.3 and nwell.5 are exempted for photoDiode,,,
+(photo.2),Min/Max width of photoDiode,,3.000,µm
+(photo.3),Min spacing between photoDiode,,5.000,µm
+(photo.4),Min spacing between photoDiode and deep nwell,,5.300,µm
+(photo.5),photoDiode edges must be coincident with :drc_tag:`areaid.po`,,,
+(photo.6),photoDiode must be enclosed by dnwell ring,,,
+(photo.7),photoDiode must be enclosed by p+ tap ring,,,
+(photo.8),Min/Max width of nwell inside photoDiode,,0.840,µm
+(photo.9),Min/Max enclosure of nwell by photoDiode,,1.080,µm
+(photo.10),Min/Max width of tap inside photoDiode,,0.410,µm
+(photo.11),Min/Max enclosure of tap by nwell inside photoDiode,,0.215,µm
diff --git a/docs/rules/periphery/p032-n_psd_dotdash.csv b/docs/rules/periphery/p032-n_psd_dotdash.csv
index a5e9488..efbb570 100644
--- a/docs/rules/periphery/p032-n_psd_dotdash.csv
+++ b/docs/rules/periphery/p032-n_psd_dotdash.csv
@@ -1,13 +1,17 @@
-Name,Description,Flags,Value
-(n/ psd.1),Width of nsdm(psdm),P,0.380
-(n/ psd.2),Spacing of nsdm(psdm) to nsdm(psdm),P,0.380
-(n/ psd.3),Manual merge if less than minimum,,
-(n/ psd.5a),"Enclosure of diff by nsdm(psdm), except for butting edge",,0.125
-(n/ psd.5b),"Enclosure of tap by nsdm(psdm), except for butting edge",P,0.125
-(n/ psd.6),Enclosure of diff/tap butting edge by nsdm (psdm),,0.000
-(n/ psd.7),Spacing of NSDM/PSDM to opposite implant diff or tap (for non-abutting diff/tap edges),,0.130
-(n/ psd.8),Nsdm and psdm cannot overlap diff/tap regions of opposite doping,DE,
-(n/ psd.9),"Diff and tap must be enclosed by their corresponding implant layers. Rule exempted for\n- diff inside ""advSeal_6um* OR cuPillarAdvSeal_6um*"" pcell for SKY130P*/SP8P*/SKY130DI-5R-CSMC flows\n- diff rings around the die at min total L>1000 um and W=0.3 um\n- gated_npn \n- :drc_tag:`areaid.zer`.",DE,
-(n/ psd.10a),Min area of Nsdm (um^2),,0.265
-(n/ psd.10b),Min area of Psdm (um^2),,0.255
-(n/ psd.11),Min area of n/psdmHoles (um^2),,0.265
+Name,Description,Flags,Value,Unit
+(n/ psd.1),Width of nsdm(psdm),P,0.380,µm
+(n/ psd.2),Spacing of nsdm(psdm) to nsdm(psdm),P,0.380,µm
+(n/ psd.3),Manual merge if less than minimum,,,
+(n/ psd.5a),"Enclosure of diff by nsdm(psdm), except for butting edge",,0.125,µm
+(n/ psd.5b),"Enclosure of tap by nsdm(psdm), except for butting edge",P,0.125,µm
+(n/ psd.6),Enclosure of diff/tap butting edge by nsdm (psdm),,0.000,µm
+(n/ psd.7),Spacing of NSDM/PSDM to opposite implant diff or tap (for non-abutting diff/tap edges),,0.130,µm
+(n/ psd.8),Nsdm and psdm cannot overlap diff/tap regions of opposite doping,DE,,
+(n/ psd.9),"Diff and tap must be enclosed by their corresponding implant layers. Rule exempted for
+  - diff inside ""advSeal_6um* OR cuPillarAdvSeal_6um*"" pcell for SKY130P*/SP8P*/SKY130DI-5R-CSMC flows
+  - diff rings around the die at min total L>1000 um and W=0.3 um
+  - gated_npn 
+  - :drc_tag:`areaid.zer`.",DE,,
+(n/ psd.10a),Min area of Nsdm,,0.265,µm²
+(n/ psd.10b),Min area of Psdm,,0.255,µm²
+(n/ psd.11),Min area of n/psdmHoles,,0.265,µm²
diff --git a/docs/rules/periphery/p032-npc_dotdash.csv b/docs/rules/periphery/p032-npc_dotdash.csv
index c6e5b82..65262c4 100644
--- a/docs/rules/periphery/p032-npc_dotdash.csv
+++ b/docs/rules/periphery/p032-npc_dotdash.csv
@@ -1,6 +1,6 @@
-Name,Description,Flags,Value
-(npc.1),Min width of NPC,,0.270
-(npc.2),Min spacing of NPC to NPC,,0.270
-(npc.3),Manual merge if less than minimum,,
-(npc.4),Spacing (no overlap) of NPC to Gate,,0.090
-(npc.5),Max enclosure of poly overlapping slotted_licon by npcm (merge between adjacent short edges of the slotted_licons if space < min),,0.095
+Name,Description,Flags,Value,Unit
+(npc.1),Min width of NPC,,0.270,µm
+(npc.2),Min spacing of NPC to NPC,,0.270,µm
+(npc.3),Manual merge if less than minimum,,,
+(npc.4),Spacing (no overlap) of NPC to Gate,,0.090,µm
+(npc.5),Max enclosure of poly overlapping slotted_licon by npcm (merge between adjacent short edges of the slotted_licons if space < min),,0.095,µm
diff --git a/docs/rules/periphery/p034-licon_dotdash.csv b/docs/rules/periphery/p034-licon_dotdash.csv
index 519ce9d..01c0124 100644
--- a/docs/rules/periphery/p034-licon_dotdash.csv
+++ b/docs/rules/periphery/p034-licon_dotdash.csv
@@ -1,32 +1,33 @@
-Name,Description,Flags,Value
-(licon.1),Min and max L and W of licon (exempt licons inside prec_resistor),,0.170
-(licon.1b),Min and max width of licon inside prec_resistor,,0.190
-(licon.1c),Min and max length of licon inside prec_resistor,,2.000
-(licon.2),Spacing of licon to licon,P,0.170
-(licon.2b),Min spacing between two slotted_licon (when the both the edges are 0.19um in length),,0.350
-(licon.2c),Min spacing between two slotted_licon (except for rule licon.2b),,0.510
-(licon.2d),Min spacing between a slotted_licon and 0.17um square licon,,0.510
-(licon.3),Only min. square licons are allowed except die seal ring where licons are (licon CD)*L,,0.170 *L
-(licon.4),Licon1 must overlap li1 and (poly or diff or tap),,
-(licon.5a),Enclosure of licon by diff,P,0.040
-(licon.5b),Min space between tap_licon and diff-abutting tap edge,P,0.060
-(licon.5c),Enclosure of licon by diff on one of two adjacent sides,P,0.060
-(licon.6),Licon cannot straddle tap,P,
-(licon.7),Enclosure of licon by one of two adjacent edges of isolated tap,P,0.120
-(licon.8),Enclosure of poly_licon by poly,P,0.050
-(licon.8a),Enclosure of poly_licon by poly on one of two adjacent sides,P,0.080
-(licon.9),"Spacing, no overlap, between poly_licon and psdm; In SKY130DIA/SKY130TMA/SKY130PIR-10 flows, the rule is checked only between (poly_licon outside rpm) and psdm",P,0.110
-(licon.10),Spacing of licon on (tap AND (nwell NOT hvi)) to Var_channel,P,0.250
-(licon.11),"Spacing of licon on diff or tap to poly on diff (except for all FETs inside :drc_tag:`areaid.sc` and except s8spf-10r flow for 0.5um phv inside cell names ""s8fs_gwdlvx4"", ""s8fs_gwdlvx8"", ""s8fs_hvrsw_x4"", ""s8fs_hvrsw8"", ""s8fs_hvrsw264"", and ""s8fs_hvrsw520"" and for 0.15um nshort inside cell names ""s8fs_rdecdrv"", ""s8fs_rdec8"", ""s8fs_rdec32"", ""s8fs_rdec264"", ""s8fs_rdec520"")",P,0.055
-(licon.11a),Spacing of licon on diff or tap to poly on diff (for all FETs inside :drc_tag:`areaid.sc` except 0.15um phighvt),P,0.050
-(licon.11b),Spacing of licon on diff or tap to poly on diff (for 0.15um phighvt inside :drc_tag:`areaid.sc`),P,0.050
-(licon.11c),"Spacing of licon on diff or tap to poly on diff (for 0.5um phv inside cell names ""s8fs_gwdlvx4"", ""s8fs_gwdlvx8"", ""s8fs_hvrsw_x4"", ""s8fs_hvrsw8"", ""s8fs_hvrsw264"", and ""s8fs_hvrsw520"")",P,0.040
-(licon.11d),"Spacing of licon on diff or tap to poly on diff (for 0.15um nshort inside cell names ""s8fs_rdecdrv"", ""s8fs_rdec8"", ""s8fs_rdec32"", ""s8fs_rdec264"", ""s8fs_rdec520"")",P,0.045
-(licon.12),Max SD width without licon,NC,5.700
-(licon.13),Spacing (no overlap) of NPC to licon on diff or tap,P,0.090
-(licon.14),Spacing of poly_licon to diff or tap,P,0.190
-(licon.15),poly_licon must be enclosed by npc by…,P,0.100
-(licon.16),"Every source_diff and every tap must enclose at least one licon1, including the diff/tap straddling areaid:ce. \nRule exempted inside UHVI.",P,
-(licon.17),Licons may not overlap both poly and (diff or tap),,
-(licon.18),Npc must enclose poly_licon,,
-(licon.19),poly of the HV varactor must not interact with licon,P,
+Name,Description,Flags,Value,Unit
+(licon.1),Min and max L and W of licon (exempt licons inside prec_resistor),,0.170,µm
+(licon.1b),Min and max width of licon inside prec_resistor,,0.190,µm
+(licon.1c),Min and max length of licon inside prec_resistor,,2.000,µm
+(licon.2),Spacing of licon to licon,P,0.170,µm
+(licon.2b),Min spacing between two slotted_licon (when the both the edges are 0.19um in length),,0.350,µm
+(licon.2c),Min spacing between two slotted_licon (except for rule licon.2b),,0.510,µm
+(licon.2d),Min spacing between a slotted_licon and 0.17um square licon,,0.510,µm
+(licon.3),Only min. square licons are allowed except die seal ring where licons are (licon CD)*L,,0.170 *L,
+(licon.4),Licon1 must overlap li1 and (poly or diff or tap),,,
+(licon.5a),Enclosure of licon by diff,P,0.040,µm
+(licon.5b),Min space between tap_licon and diff-abutting tap edge,P,0.060,µm
+(licon.5c),Enclosure of licon by diff on one of two adjacent sides,P,0.060,µm
+(licon.6),Licon cannot straddle tap,P,,
+(licon.7),Enclosure of licon by one of two adjacent edges of isolated tap,P,0.120,µm
+(licon.8),Enclosure of poly_licon by poly,P,0.050,µm
+(licon.8a),Enclosure of poly_licon by poly on one of two adjacent sides,P,0.080,µm
+(licon.9),"Spacing, no overlap, between poly_licon and psdm; In SKY130DIA/SKY130TMA/SKY130PIR-10 flows, the rule is checked only between (poly_licon outside rpm) and psdm",P,0.110,µm
+(licon.10),Spacing of licon on (tap AND (nwell NOT hvi)) to Var_channel,P,0.250,µm
+(licon.11),"Spacing of licon on diff or tap to poly on diff (except for all FETs inside :drc_tag:`areaid.sc` and except s8spf-10r flow for 0.5um phv inside cell names ""s8fs_gwdlvx4"", ""s8fs_gwdlvx8"", ""s8fs_hvrsw_x4"", ""s8fs_hvrsw8"", ""s8fs_hvrsw264"", and ""s8fs_hvrsw520"" and for 0.15um nshort inside cell names ""s8fs_rdecdrv"", ""s8fs_rdec8"", ""s8fs_rdec32"", ""s8fs_rdec264"", ""s8fs_rdec520"")",P,0.055,µm
+(licon.11a),Spacing of licon on diff or tap to poly on diff (for all FETs inside :drc_tag:`areaid.sc` except 0.15um phighvt),P,0.050,µm
+(licon.11b),Spacing of licon on diff or tap to poly on diff (for 0.15um phighvt inside :drc_tag:`areaid.sc`),P,0.050,µm
+(licon.11c),"Spacing of licon on diff or tap to poly on diff (for 0.5um phv inside cell names ""s8fs_gwdlvx4"", ""s8fs_gwdlvx8"", ""s8fs_hvrsw_x4"", ""s8fs_hvrsw8"", ""s8fs_hvrsw264"", and ""s8fs_hvrsw520"")",P,0.040,µm
+(licon.11d),"Spacing of licon on diff or tap to poly on diff (for 0.15um nshort inside cell names ""s8fs_rdecdrv"", ""s8fs_rdec8"", ""s8fs_rdec32"", ""s8fs_rdec264"", ""s8fs_rdec520"")",P,0.045,µm
+(licon.12),Max SD width without licon,NC,5.700,µm
+(licon.13),Spacing (no overlap) of NPC to licon on diff or tap,P,0.090,µm
+(licon.14),Spacing of poly_licon to diff or tap,P,0.190,µm
+(licon.15),poly_licon must be enclosed by npc by…,P,0.100,µm
+(licon.16),"| Every source_diff and every tap must enclose at least one licon1, including the diff/tap straddling areaid:ce. 
+| Rule exempted inside UHVI.",P,,
+(licon.17),Licons may not overlap both poly and (diff or tap),,,
+(licon.18),Npc must enclose poly_licon,,,
+(licon.19),poly of the HV varactor must not interact with licon,P,,
diff --git a/docs/rules/periphery/p035-ct_dotdash.csv b/docs/rules/periphery/p035-ct_dotdash.csv
index 3beb869..c8c9696 100644
--- a/docs/rules/periphery/p035-ct_dotdash.csv
+++ b/docs/rules/periphery/p035-ct_dotdash.csv
@@ -1,8 +1,8 @@
-Name,Description,Flags,Value
-(ct.1),Min and max L and W of mcon,DNF,0.170
-(ct.2),Spacing of mcon to mcon,DNF,0.190
-(ct.3),Only min. square mcons are allowed except die seal ring where mcons are…,,0.170*L
-(ct.4),Mcon must be enclosed by LI by at least …,P,0.000
-(ct.irdrop.1),"For 1 <= n <= 10 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.2
-(ct.irdrop.2),"For 11 <= n <= 100 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.3
-(ct.irdrop.3),"For n > 100 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.7
+Name,Description,Flags,Value,Unit
+(ct.1),Min and max L and W of mcon,DNF,0.170,µm
+(ct.2),Spacing of mcon to mcon,DNF,0.190,µm
+(ct.3),Only min. square mcons are allowed except die seal ring where mcons are…,,0.170*L,
+(ct.4),Mcon must be enclosed by LI by at least …,P,0.000,µm
+(ct.irdrop.1),"For 1 <= n <= 10 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.2,µm
+(ct.irdrop.2),"For 11 <= n <= 100 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.3,µm
+(ct.irdrop.3),"For n > 100 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.7,µm
diff --git a/docs/rules/periphery/p035-li_dotdash_dotdash.csv b/docs/rules/periphery/p035-li_dotdash_dotdash.csv
index 77fcfb3..de222fc 100644
--- a/docs/rules/periphery/p035-li_dotdash_dotdash.csv
+++ b/docs/rules/periphery/p035-li_dotdash_dotdash.csv
@@ -1,9 +1,9 @@
-Name,Description,Flags,Value
-(li.1.-),Width of LI (except for li.1a),P,0.170
-(li.1a.-),Width of LI inside of cells with name s8rf2_xcmvpp_hd5_*,P,0.140
-(li.2.-),Max ratio of length to width of LI without licon or mcon,NC,10.000
-(li.3.-),Spacing of LI to LI (except for li.3a),P,0.170
-(li.3a.-),Spacing of LI to LI inside cells with names s8rf2_xcmvpp_hd5_*,P,0.140
-(li.5.-),Enclosure of licon by one of two adjacent LI sides,P,0.080
-(li.6.-),Min area of LI,P,0.0561
-(li.7.-),"Min LI resistor width (rule exempted within :drc_tag:`areaid.ed`; Inside :drc_tag:`areaid.ed`, min width of the li resistor is determined by rule li.1)",,0.290
+Name,Description,Flags,Value,Unit
+(li.1.-),Width of LI (except for li.1a),P,0.170,µm
+(li.1a.-),Width of LI inside of cells with name s8rf2_xcmvpp_hd5_*,P,0.140,µm
+(li.2.-),Max ratio of length to width of LI without licon or mcon,NC,10.000,µm
+(li.3.-),Spacing of LI to LI (except for li.3a),P,0.170,µm
+(li.3a.-),Spacing of LI to LI inside cells with names s8rf2_xcmvpp_hd5_*,P,0.140,µm
+(li.5.-),Enclosure of licon by one of two adjacent LI sides,P,0.080,µm
+(li.6.-),Min area of LI,P,0.0561,µm²
+(li.7.-),"Min LI resistor width (rule exempted within :drc_tag:`areaid.ed`; Inside :drc_tag:`areaid.ed`, min width of the li resistor is determined by rule li.1)",,0.290,µm
diff --git a/docs/rules/periphery/p036-capm_dotdash.csv b/docs/rules/periphery/p036-capm_dotdash.csv
index 8960a83..7261f43 100644
--- a/docs/rules/periphery/p036-capm_dotdash.csv
+++ b/docs/rules/periphery/p036-capm_dotdash.csv
@@ -1,13 +1,13 @@
-Name,Description,Flags,Value
-(capm.1),Min width of capm,,N/A
-(capm.2a),Min spacing of capm to capm,,N/A
-(capm.2b),Minimum spacing of capacitor bottom_plate to bottom plate,,N/A
-(capm.3),Minimum enclosure of capm (top_plate) by met2,,N/A
-(capm.4),Min enclosure of via2 by capm,,N/A
-(capm.5),Min spacing between capm and via2,,N/A
-(capm.6),Maximum Aspect Ratio (Length/Width),,N/A
-(capm.7),Only rectangular capacitors are allowed,,N/A
-(capm.8),"Min space, no overlap, between via and capm",,N/A
-(capm.10),"capm must not straddle nwell, diff, tap, poly, li1 and met1 (Rule exempted for capm overlapping capm_2t.dg)",TC,N/A
-(capm.11),Min spacing between capm to (met2 not overlapping capm),,N/A
-(capm.12),Max area of capm (um^2),,N/A
+Name,Description,Flags,Value,Unit
+(capm.1),Min width of capm,,N/A,N/A
+(capm.2a),Min spacing of capm to capm,,N/A,N/A
+(capm.2b),Minimum spacing of capacitor bottom_plate to bottom plate,,N/A,N/A
+(capm.3),Minimum enclosure of capm (top_plate) by met2,,N/A,N/A
+(capm.4),Min enclosure of via2 by capm,,N/A,N/A
+(capm.5),Min spacing between capm and via2,,N/A,N/A
+(capm.6),Maximum Aspect Ratio (Length/Width),,N/A,N/A
+(capm.7),Only rectangular capacitors are allowed,,N/A,N/A
+(capm.8),"Min space, no overlap, between via and capm",,N/A,N/A
+(capm.10),"capm must not straddle nwell, diff, tap, poly, li1 and met1 (Rule exempted for capm overlapping capm_2t.dg)",TC,N/A,N/A
+(capm.11),Min spacing between capm to (met2 not overlapping capm),,N/A,N/A
+(capm.12),Max area of capm (um^2),,N/A,N/A
diff --git a/docs/rules/periphery/p037-vpp_dotdash.csv b/docs/rules/periphery/p037-vpp_dotdash.csv
index a9c9ea0..f772569 100644
--- a/docs/rules/periphery/p037-vpp_dotdash.csv
+++ b/docs/rules/periphery/p037-vpp_dotdash.csv
@@ -1,19 +1,19 @@
-Name,Description,Flags,Value
-(vpp.1),Min width of capacitor:dg,,1.430
-(vpp.1b),Max width of capacitor:dg; Rule not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5 and vpp_with_noLi,,11.350
-(vpp.1c),"Min/Max width of cell name ""s8rf_xcmvpp1p8x1p8_m3shield """,,3.880
-(vpp.3),"capacitor:dg must not overlap (tap or diff or poly); (one exception: Poly is allowed to overlap  vpp_with_Met3Shield and vpp_with_Met5PolyShield); (not applicable for vpp_over_Moscap or ""s8rf2_xcmvppx4_2xnhvnative10x4"" or vpp_with_LiShield)",,
-(vpp.4),capacitor:dg must not straddle (nwell or dnwell),,
-(vpp.5),Min spacing between (capacitor:dg edge and (poly or li1 or met1 or met2)) to (poly or li1 or met1 or met2) on separate nets (Exempt area of the error shape less than 2.25 (um^2) and run length less than 2.0um); Rule not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5 and vpp_with_noLi,,1.500
-(vpp.5a),Max pattern density of met3.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5),,0.25
-(vpp.5b),Max pattern density of met4.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_Met5 and vpp_over_MOSCAP),,0.3
-(vpp.5c),"Max pattern density of met5.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_Met5 and vpp_over_MOSCAP and vpp_with_noLi); (one exception: rules does apply to cell ""s8rf2_xcmvpp11p5x11p7_m1m4"" and ""s8rf2_xcmvpp_hd5_atlas*"")",,0.4
-(vpp.8),Min enclosure of capacitor:dg by nwell,,1.500
-(vpp.9),Min spacing of capacitor:dg to nwell (not applicable for vpp_over_MOSCAP),,1.500
-(vpp.10),vpp capacitors must not overlap; Rule checks for capacitor.dg overlapping more than one pwell pin,,
-(vpp.11),Min pattern density of (poly and diff) over capacitor.dg; (vpp_over_Moscap only),,0.87
-(vpp.12a),"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp8p6x7p9_m3_lim5shield""  must overlap with size 2.01 x 2.01 (no other met4 shapes allowed)",,9.00
-(vpp.12b),"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp11p5x11p7_m3_lim5shield""  must overlap with size 2.01 x 2.01 (no other met4 shapes allowed)",,16.00
-(vpp.12c),"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp4p4x4p6_m3_lim5shield""  must overlap with size 1.5 x 1.5 (no other met4 shapes allowed)",,4.00
-(vpp.13),Min space of met1 to met1inside VPP capacitor,CU,0.160
-(vpp.14),Min space of met2 to met2 inside VPP capacitor,CU,0.160
+Name,Description,Flags,Value,Unit
+(vpp.1),Min width of capacitor:dg,,1.430,µm
+(vpp.1b),Max width of capacitor:dg; Rule not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5 and vpp_with_noLi,,11.350,µm
+(vpp.1c),"Min/Max width of cell name ""s8rf_xcmvpp1p8x1p8_m3shield """,,3.880,µm
+(vpp.3),"capacitor:dg must not overlap (tap or diff or poly); (one exception: Poly is allowed to overlap  vpp_with_Met3Shield and vpp_with_Met5PolyShield); (not applicable for vpp_over_Moscap or ""s8rf2_xcmvppx4_2xnhvnative10x4"" or vpp_with_LiShield)",,,
+(vpp.4),capacitor:dg must not straddle (nwell or dnwell),,,
+(vpp.5),Min spacing between (capacitor:dg edge and (poly or li1 or met1 or met2)) to (poly or li1 or met1 or met2) on separate nets (Exempt area of the error shape less than 2.25 µm² and run length less than 2.0um); Rule not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5 and vpp_with_noLi,,1.500,µm
+(vpp.5a),Max pattern density of met3.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5),,0.25,\-
+(vpp.5b),Max pattern density of met4.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_Met5 and vpp_over_MOSCAP),,0.3,\-
+(vpp.5c),"Max pattern density of met5.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_Met5 and vpp_over_MOSCAP and vpp_with_noLi); (one exception: rules does apply to cell ""s8rf2_xcmvpp11p5x11p7_m1m4"" and ""s8rf2_xcmvpp_hd5_atlas*"")",,0.4,\-
+(vpp.8),Min enclosure of capacitor:dg by nwell,,1.500,µm
+(vpp.9),Min spacing of capacitor:dg to nwell (not applicable for vpp_over_MOSCAP),,1.500,µm
+(vpp.10),vpp capacitors must not overlap; Rule checks for capacitor.dg overlapping more than one pwell pin,,,
+(vpp.11),Min pattern density of (poly and diff) over capacitor.dg; (vpp_over_Moscap only),,0.87,\-
+(vpp.12a),"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp8p6x7p9_m3_lim5shield""  must overlap with size 2.01 x 2.01 (no other met4 shapes allowed)",,9.00,µm
+(vpp.12b),"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp11p5x11p7_m3_lim5shield""  must overlap with size 2.01 x 2.01 (no other met4 shapes allowed)",,16.00,µm
+(vpp.12c),"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp4p4x4p6_m3_lim5shield""  must overlap with size 1.5 x 1.5 (no other met4 shapes allowed)",,4.00,µm
+(vpp.13),Min space of met1 to met1inside VPP capacitor,CU,0.160,µm
+(vpp.14),Min space of met2 to met2 inside VPP capacitor,CU,0.160,µm
diff --git a/docs/rules/periphery/p038-m1_dotdash.csv b/docs/rules/periphery/p038-m1_dotdash.csv
index 18257df..321c2ff 100644
--- a/docs/rules/periphery/p038-m1_dotdash.csv
+++ b/docs/rules/periphery/p038-m1_dotdash.csv
@@ -1,20 +1,27 @@
-Name,Description,Flags,Value
-(m1.-),"Algorithm should flag errors, for met1, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm1 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. NOTE: Required for IP, Recommended for Chip-level.",RC,
-(m1.1),Width of metal1,,0.140
-(m1.2),Spacing of metal1 to metal1,,0.140
-(m1.3a),Min. spacing of features attached to or extending from huge_met1 for a distance of up to  0.280 um to metal1 (rule not checked over non-huge met1 features),,0.280
-(m1.3b),Min. spacing of huge_met1 to metal1 excluding features checked by m1.3a,,0.280
-(m1.4),Mcon must be enclosed by Met1 by at least …(Rule exempted for cell names documented in rule m1.4a),P,0.030
-(m1.4a),"Mcon must be enclosed by Met1 by at least (for cell names ""s8cell_ee_plus_sseln_a"", ""s8cell_ee_plus_sseln_b"", ""s8cell_ee_plus_sselp_a"", ""s8cell_ee_plus_sselp_b"", ""s8fpls_pl8"", and ""s8fs_cmux4_fm"")",P,0.005
-(m1.5),Mcon must be enclosed by Met1 on one of two adjacent sides by at least …,P AL,0.060
-(m1.6),Min metal 1 area [um2],,0.083
-(m1.7),Min area of metal1 holes [um2],,0.140
-(m1.pd.1),Min MM1_oxide_Pattern_density,RR AL,0.7
-(m1.pd.2a),Rule m1.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A AL,700
-(m1.pd.2b),Rule m1.pd.1 has to be checked by dividing the chip into steps of …,A AL,70
-(m1.11),Max width of metal1after slotting,CU NC,4.000
-(m1.12),Add slots and remove vias and contacts if met1 wider than…..,CU,3.200
-(m1.13),Max pattern density (PD) of met1,CU,0.77
-(m1.14),Met1 PD window size,CU,50.000
-(m1.14a),Met1 PD window step,CU,25.000
-(m1.15),Mcon must be enclosed by met1 on one of two adjacent sides by at least …,CU,0.030
+Name,Description,Flags,Value,Unit
+(m1.-),"| Algorithm should flag errors, for met1, if ANY of the following is true:
+| An entire 700x700 window is covered by cmm1 waffleDrop, and metX PD < 70% for same window.
+| 80-100% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 65% for same window.
+| 60-80% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 60% for same window.
+| 50-60% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 50% for same window.
+| 40-50% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 40% for same window.
+| 30-40% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 30% for same window.
+| Exclude cells whose area is below 40Kum2. NOTE: Required for IP, Recommended for Chip-level.",RC,,
+(m1.1),Width of metal1,,0.140,µm
+(m1.2),Spacing of metal1 to metal1,,0.140,µm
+(m1.3a),Min. spacing of features attached to or extending from huge_met1 for a distance of up to  0.280 µm to metal1 (rule not checked over non-huge met1 features),,0.280,µm
+(m1.3b),Min. spacing of huge_met1 to metal1 excluding features checked by m1.3a,,0.280,µm
+(m1.4),Mcon must be enclosed by Met1 by at least …(Rule exempted for cell names documented in rule m1.4a),P,0.030,µm
+(m1.4a),"Mcon must be enclosed by Met1 by at least (for cell names ""s8cell_ee_plus_sseln_a"", ""s8cell_ee_plus_sseln_b"", ""s8cell_ee_plus_sselp_a"", ""s8cell_ee_plus_sselp_b"", ""s8fpls_pl8"", and ""s8fs_cmux4_fm"")",P,0.005,µm
+(m1.5),Mcon must be enclosed by Met1 on one of two adjacent sides by at least …,P AL,0.060,µm
+(m1.6),Min metal 1 area,,0.083,µm²
+(m1.7),Min area of metal1 holes,,0.140,µm²
+(m1.pd.1),Min MM1_oxide_Pattern_density,RR AL,0.7,\-
+(m1.pd.2a),Rule m1.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A AL,700,µm
+(m1.pd.2b),Rule m1.pd.1 has to be checked by dividing the chip into steps of …,A AL,70,
+(m1.11),Max width of metal1after slotting,CU NC,4.000,µm
+(m1.12),Add slots and remove vias and contacts if met1 wider than…..,CU,3.200,
+(m1.13),Max pattern density (PD) of met1,CU,0.77,\-
+(m1.14),Met1 PD window size,CU,50.000,µm
+(m1.14a),Met1 PD window step,CU,25.000,µm
+(m1.15),Mcon must be enclosed by met1 on one of two adjacent sides by at least …,CU,0.030,µm
diff --git a/docs/rules/periphery/p039-via_dotdash.csv b/docs/rules/periphery/p039-via_dotdash.csv
index e03e2e8..9f2e232 100644
--- a/docs/rules/periphery/p039-via_dotdash.csv
+++ b/docs/rules/periphery/p039-via_dotdash.csv
@@ -1,20 +1,20 @@
-Name,Description,Flags,Value
-(via.1a),Min and max L and W of via outside :drc_tag:`areaid.mt`,AL,0.150
-(via.1b),"Three sizes of square Vias allowed inside areaid:mt: 0.150um, 0.230um and 0.280um",AL,
-(via.2),Spacing of via to via,AL,0.170
-(via.3),Only min. square vias are allowed except die seal ring where vias are (Via CD)*L,,0.2*L
-(via.4a),0.150 um Via must be enclosed by Met1 by at least …,,0.055
-(via.4b),"Inside :drc_tag:`areaid.mt`, 0.230 um Via must be enclosed by met1 by atleast",AL,0.030
-(via.4c),"Inside :drc_tag:`areaid.mt`, 0.280 um Via must be enclosed by met1 by atleast",AL,0.000
-(via.5a),0.150 um Via must be enclosed by Met1 on one of two adjacent sides by at least …,,0.085
-(via.5b),"Inside :drc_tag:`areaid.mt`, 0.230 um Via must be enclosed by met1 on one of two adjacent sides by at least …",AL,0.060
-(via.5c),"Inside :drc_tag:`areaid.mt`, 0.280 um Via must be enclosed by met1 on one of two adjacent sides by at least …",AL,0.000
-(via.11),Min and max L and W of via outside :drc_tag:`areaid.mt`,CU,0.180
-(via.12),Min spacing between vias,CU,0.130
-(via.13),Max of 5 vias within …,CU,0.350
-(via.14),0.180 um Via must be enclosed by parallel edges of Met1 by at least …,CU,0.040
-(via.irdrop.1),"For 1 <= n <= 2 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.0
-(via.irdrop.2),"For 3 <= n <= 15 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.6
-(via.irdrop.3),"For 16 <= n <= 30 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.8
-(via.irdrop.4),"For n > 30 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.9
-(via.14a),0.180 um Via must be enclosed by 45 deg edges of Met1 by at least …,CU,0.037
+Name,Description,Flags,Value,Unit
+(via.1a),Min and max L and W of via outside :drc_tag:`areaid.mt`,AL,0.150,µm
+(via.1b),"Three sizes of square Vias allowed inside areaid:mt: 0.150um, 0.230um and 0.280um",AL,,
+(via.2),Spacing of via to via,AL,0.170,µm
+(via.3),Only min. square vias are allowed except die seal ring where vias are (Via CD)*L,,0.2*L,
+(via.4a),0.150 µm Via must be enclosed by Met1 by at least …,,0.055,µm
+(via.4b),"Inside :drc_tag:`areaid.mt`, 0.230 µm Via must be enclosed by met1 by atleast",AL,0.030,µm
+(via.4c),"Inside :drc_tag:`areaid.mt`, 0.280 µm Via must be enclosed by met1 by atleast",AL,0.000,µm
+(via.5a),0.150 µm Via must be enclosed by Met1 on one of two adjacent sides by at least …,,0.085,µm
+(via.5b),"Inside :drc_tag:`areaid.mt`, 0.230 µm Via must be enclosed by met1 on one of two adjacent sides by at least …",AL,0.060,µm
+(via.5c),"Inside :drc_tag:`areaid.mt`, 0.280 µm Via must be enclosed by met1 on one of two adjacent sides by at least …",AL,0.000,µm
+(via.11),Min and max L and W of via outside :drc_tag:`areaid.mt`,CU,0.180,µm
+(via.12),Min spacing between vias,CU,0.130,µm
+(via.13),Max of 5 vias within …,CU,0.350,µm
+(via.14),0.180 µm Via must be enclosed by parallel edges of Met1 by at least …,CU,0.040,µm
+(via.irdrop.1),"For 1 <= n <= 2 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.0,µm
+(via.irdrop.2),"For 3 <= n <= 15 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.6,µm
+(via.irdrop.3),"For 16 <= n <= 30 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.8,µm
+(via.irdrop.4),"For n > 30 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.9,µm
+(via.14a),0.180 µm Via must be enclosed by 45 deg edges of Met1 by at least …,CU,0.037,deg µm
diff --git a/docs/rules/periphery/p040-m2_dotdash.csv b/docs/rules/periphery/p040-m2_dotdash.csv
index 4304769..cbf83ef 100644
--- a/docs/rules/periphery/p040-m2_dotdash.csv
+++ b/docs/rules/periphery/p040-m2_dotdash.csv
@@ -1,20 +1,27 @@
-Name,Description,Flags,Value
-(m2.-),"Algorithm should flag errors, for met2, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm2 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. Required for IP, Recommended for Chip-level.",RC,
-(m2.1),Width of metal 2,,0.140
-(m2.2),Spacing of metal 2 to metal 2,,0.140
-(m2.3a),Min. spacing of features attached to or extending from huge_met2 for a distance of up to  0.280 um to metal2 (rule not checked over non-huge met2 features),,0.280
-(m2.3b),Min. spacing of huge_met2 to metal2 excluding features checked by m2.3a,,0.280
-(m2.3c),"Min spacing between floating_met2 with AR_met2_A >= 0.05 and AR_met2_B =< 0.032, outside areaid:sc must be greater than",RR,0.145
-(m2.4),Via must be enclosed by Met2 by at least …,P AL,0.055
-(m2.5),Via must be enclosed by Met2 on one of two adjacent sides by at least …,AL,0.085
-(m2.6),Min metal2 area [um2],,0.0676
-(m2.7),Min area of metal2 holes [um2],,0.140
-(m2.pd.1),Min MM2_oxide_Pattern_density,RR,0.7
-(m2.pd.2a),Rule m2.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700
-(m2.pd.2b),Rule m2.pd.1 has to be checked by dividing the chip into steps of …,A,70
-(m2.11),Max width of metal2,CU,4.000
-(m2.12),Add slots and remove vias and contacts if met2 wider than…..,CU,3.200
-(m2.13),Max pattern density (PD) of metal2,CU,0.77
-(m2.14),Met2 PD window size,CU,50.000
-(m2.14a),Met2 PD window step,CU,25.000
-(m2.15),Via must be enclosed by met2 by at least…,CU,0.040
+Name,Description,Flags,Value,Unit
+(m2.-),"| Algorithm should flag errors, for met2, if ANY of the following is true:
+| An entire 700x700 window is covered by cmm2 waffleDrop, and metX PD < 70% for same window.
+| 80-100% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 65% for same window.
+| 60-80% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 60% for same window.
+| 50-60% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 50% for same window.
+| 40-50% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 40% for same window.
+| 30-40% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 30% for same window.
+| Exclude cells whose area is below 40Kum2. Required for IP, Recommended for Chip-level.",RC,,
+(m2.1),Width of metal 2,,0.140,µm
+(m2.2),Spacing of metal 2 to metal 2,,0.140,µm
+(m2.3a),Min. spacing of features attached to or extending from huge_met2 for a distance of up to  0.280 µm to metal2 (rule not checked over non-huge met2 features),,0.280,µm
+(m2.3b),Min. spacing of huge_met2 to metal2 excluding features checked by m2.3a,,0.280,µm
+(m2.3c),"Min spacing between floating_met2 with AR_met2_A >= 0.05 and AR_met2_B =< 0.032, outside areaid:sc must be greater than",RR,0.145,µm
+(m2.4),Via must be enclosed by Met2 by at least …,P AL,0.055,µm
+(m2.5),Via must be enclosed by Met2 on one of two adjacent sides by at least …,AL,0.085,µm
+(m2.6),Min metal2 area,,0.0676,µm²
+(m2.7),Min area of metal2 holes,,0.140,µm²
+(m2.pd.1),Min MM2_oxide_Pattern_density,RR,0.7,\-
+(m2.pd.2a),Rule m2.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700,µm
+(m2.pd.2b),Rule m2.pd.1 has to be checked by dividing the chip into steps of …,A,70,
+(m2.11),Max width of metal2,CU,4.000,µm
+(m2.12),Add slots and remove vias and contacts if met2 wider than…..,CU,3.200,
+(m2.13),Max pattern density (PD) of metal2,CU,0.77,\-
+(m2.14),Met2 PD window size,CU,50.000,µm
+(m2.14a),Met2 PD window step,CU,25.000,µm
+(m2.15),Via must be enclosed by met2 by at least…,CU,0.040,µm
diff --git a/docs/rules/periphery/p041-via2_dotdash.csv b/docs/rules/periphery/p041-via2_dotdash.csv
index 47ecc00..18afe0a 100644
--- a/docs/rules/periphery/p041-via2_dotdash.csv
+++ b/docs/rules/periphery/p041-via2_dotdash.csv
@@ -1,21 +1,21 @@
-Name,Description,Flags,Value
-(via2.X.1),Via2 connects met2 to met3 in the SKY130T*/SKY130P*/SP8Q/SP8P* flow and met2/capm to met3 in the SKY130DI* flow.,,
-(via2.1a),Min and max L and W of via2 (except for rule via2.1b/1c/1d/1e/1f),AL,0.200
-(via2.1b),"Three sizes of square Vias allowed inside areaid:mt: 0.280um, 1.2 um and 1.5 um",AL,N/A
-(via2.1c),Two sizes of square Vias allowed inside areaid:mt: 1.2 um and 1.5 um,AL,N/A
-(via2.1d),"Four sizes of square Vias allowed inside areaid:mt: 0.2um, 0.280um, 1.2 um and 1.5 um",AL,
-(via2.1e),"Three sizes of square Vias allowed inside areaid:mt: 0.8um, 1.2 um and 1.5 um",AL,N/A
-(via2.1f),Two sizes of square Vias allowed outside areaid:mt: 0.8um and 1.2 um,AL,N/A
-(via2.2),Spacing of via2 to via2,AL,0.200
-(via2.3),Only min. square via2s are allowed except die seal ring where via2s are (Via2 CD)*L,AL,0.2*L
-(via2.4),Via2 must be enclosed by Met2 by at least …,AL,0.040
-(via2.4a),"Inside :drc_tag:`areaid.mt`, 1.5 um Via2 must be enclosed by met2 by atleast",,0.140
-(via2.5),Via2 must be enclosed by Met2 on one of two adjacent sides by at least …,AL,0.085
-(via2.11),Min and max L and W of via2,CU,0.210
-(via2.12),Min spacing between via2's,CU,0.180
-(via2.13),Min spacing between via2 rows,CU,0.200
-(via2.14),Via2 must be enclosed by met2 by atleast,CU,0.035
-(via2.irdrop.1),"For 1 <= n <= 2 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.0
-(via2.irdrop.2),"For 3 <= n <= 4 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.6
-(via2.irdrop.3),"For 5 <= n <= 30 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.79
-(via2.irdrop.4),"For n > 30 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.9
+Name,Description,Flags,Value,Unit
+(via2.X.1),Via2 connects met2 to met3 in the SKY130T*/SKY130P*/SP8Q/SP8P* flow and met2/capm to met3 in the SKY130DI* flow.,,,
+(via2.1a),Min and max L and W of via2 (except for rule via2.1b/1c/1d/1e/1f),AL,0.200,µm
+(via2.1b),"Three sizes of square Vias allowed inside areaid:mt: 0.280um, 1.2 um and 1.5 um",AL,N/A,N/A
+(via2.1c),Two sizes of square Vias allowed inside areaid:mt: 1.2 um and 1.5 um,AL,N/A,N/A
+(via2.1d),"Four sizes of square Vias allowed inside areaid:mt: 0.2um, 0.280um, 1.2 um and 1.5 um",AL,,
+(via2.1e),"Three sizes of square Vias allowed inside areaid:mt: 0.8um, 1.2 um and 1.5 um",AL,N/A,N/A
+(via2.1f),Two sizes of square Vias allowed outside areaid:mt: 0.8um and 1.2 um,AL,N/A,N/A
+(via2.2),Spacing of via2 to via2,AL,0.200,µm
+(via2.3),Only min. square via2s are allowed except die seal ring where via2s are (Via2 CD)*L,AL,0.2*L,
+(via2.4),Via2 must be enclosed by Met2 by at least …,AL,0.040,µm
+(via2.4a),"Inside :drc_tag:`areaid.mt`, 1.5 µm Via2 must be enclosed by met2 by atleast",,0.140,µm
+(via2.5),Via2 must be enclosed by Met2 on one of two adjacent sides by at least …,AL,0.085,µm
+(via2.11),Min and max L and W of via2,CU,0.210,µm
+(via2.12),Min spacing between via2's,CU,0.180,µm
+(via2.13),Min spacing between via2 rows,CU,0.200,µm
+(via2.14),Via2 must be enclosed by met2 by atleast,CU,0.035,µm
+(via2.irdrop.1),"For 1 <= n <= 2 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.0,µm
+(via2.irdrop.2),"For 3 <= n <= 4 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.6,µm
+(via2.irdrop.3),"For 5 <= n <= 30 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.79,µm
+(via2.irdrop.4),"For n > 30 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.9,µm
diff --git a/docs/rules/periphery/p042-m3_dotdash.csv b/docs/rules/periphery/p042-m3_dotdash.csv
index 307b931..2a30266 100644
--- a/docs/rules/periphery/p042-m3_dotdash.csv
+++ b/docs/rules/periphery/p042-m3_dotdash.csv
@@ -1,22 +1,29 @@
-Name,Description,Flags,Value
-(m3.-),"Algorithm should flag errors, for met3, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm3 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. NOTE: Required for IP, Recommended for Chip-level.",RC,
-(m3.1),Width of metal 3,,0.300
-(m3.2),Spacing of metal 3 to metal 3,,0.300
-(m3.3a),Min. spacing of features attached to or extending from huge_met3 for a distance of up to 0.480 um to metal3  (rule not checked over non-huge met3 features),,N/A
-(m3.3b),Min. spacing of huge_met3 to metal3 excluding features checked by m3.3a,,N/A
-(m3.3c),Min. spacing of features attached to or extending from huge_met3 for a distance of up to 0.400 um to metal3  (rule not checked over non-huge met3 features),,0.400
-(m3.3d),Min. spacing of huge_met3 to metal3 excluding features checked by m3.3a,,0.400
-(m3.4),Via2 must be enclosed by Met3 by at least …,AL,0.065
-(m3.5),Via2 must be enclosed by Met3 on one of two adjacent sides by at least …,,N/A
-(m3.5a),Via2 must be enclosed by Met3 on all sides by at least …(Rule not checked on a layout when it satisfies both rules m3.4 and m3.5),,N/A
-(m3.6),Min area of metal3,,0.240
-(m3.7),Min area of metal3 holes [um2],CU,0.200
-(m3.pd.1),Min MM3_oxide_Pattern_density,RR,0.7
-(m3.pd.2a),Rule m3.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700
-(m3.pd.2b),Rule m3.pd.1 has to be checked by dividing the chip into steps of …,A,70
-(m3.11),Max width of metal3,CU,4.000
-(m3.12),Add slots and remove vias and contacts if wider than…..,CU,3.200
-(m3.13),Max pattern density (PD) of metal3,CU,0.77
-(m3.14),Met3 PD window size,CU,50.000
-(m3.14a),Met3 PD window step,CU,25.000
-(m3.15),Via2 must be enclosed by met3 by at least…,CU,0.060
+Name,Description,Flags,Value,Unit
+(m3.-),"| Algorithm should flag errors, for met3, if ANY of the following is true:
+| An entire 700x700 window is covered by cmm3 waffleDrop, and metX PD < 70% for same window.
+| 80-100% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 65% for same window.
+| 60-80% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 60% for same window.
+| 50-60% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 50% for same window.
+| 40-50% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 40% for same window.
+| 30-40% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 30% for same window.
+| Exclude cells whose area is below 40Kum2. NOTE: Required for IP, Recommended for Chip-level.",RC,,
+(m3.1),Width of metal 3,,0.300,µm
+(m3.2),Spacing of metal 3 to metal 3,,0.300,µm
+(m3.3a),Min. spacing of features attached to or extending from huge_met3 for a distance of up to 0.480 um to metal3  (rule not checked over non-huge met3 features),,N/A,N/A
+(m3.3b),Min. spacing of huge_met3 to metal3 excluding features checked by m3.3a,,N/A,N/A
+(m3.3c),Min. spacing of features attached to or extending from huge_met3 for a distance of up to 0.400 µm to metal3  (rule not checked over non-huge met3 features),,0.400,µm
+(m3.3d),Min. spacing of huge_met3 to metal3 excluding features checked by m3.3a,,0.400,µm
+(m3.4),Via2 must be enclosed by Met3 by at least …,AL,0.065,µm
+(m3.5),Via2 must be enclosed by Met3 on one of two adjacent sides by at least …,,N/A,N/A
+(m3.5a),Via2 must be enclosed by Met3 on all sides by at least …(Rule not checked on a layout when it satisfies both rules m3.4 and m3.5),,N/A,N/A
+(m3.6),Min area of metal3,,0.240,µm²
+(m3.7),Min area of metal3 holes,CU,0.200,µm²
+(m3.pd.1),Min MM3_oxide_Pattern_density,RR,0.7,\-
+(m3.pd.2a),Rule m3.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700,µm
+(m3.pd.2b),Rule m3.pd.1 has to be checked by dividing the chip into steps of …,A,70,
+(m3.11),Max width of metal3,CU,4.000,µm
+(m3.12),Add slots and remove vias and contacts if wider than…..,CU,3.200,
+(m3.13),Max pattern density (PD) of metal3,CU,0.77,\-
+(m3.14),Met3 PD window size,CU,50.000,µm
+(m3.14a),Met3 PD window step,CU,25.000,µm
+(m3.15),Via2 must be enclosed by met3 by at least…,CU,0.060,µm
diff --git a/docs/rules/periphery/p042-via3_dotdash.csv b/docs/rules/periphery/p042-via3_dotdash.csv
index 3488b8b..67eecd8 100644
--- a/docs/rules/periphery/p042-via3_dotdash.csv
+++ b/docs/rules/periphery/p042-via3_dotdash.csv
@@ -1,15 +1,15 @@
-Name,Description,Flags,Value
-(via3.1),Min and max L and W of via3 (except for rule via3.1a),AL,0.200
-(via3.1a),Two sizes of square via3 allowed inside :drc_tag:`areaid.mt`: 0.200um and 0.800um,AL,
-(via3.2),Spacing of via3 to via3,AL,0.200
-(via3.3),Only min. square via3s are allowed except die seal ring where via3s are (Via3 CD)*L,,0.2*L
-(via3.4),Via3 must be enclosed by Met3 by at least …,AL,0.060
-(via3.5),Via3 must be enclosed by Met3 on one of two adjacent sides by at least …,AL,0.090
-(via3.11),Min and max L and W of via3,CU,0.210
-(via3.12),Min spacing between via2's,CU,0.180
-(via3.13),Via3 must be enclosed by Met3 by at least …,CU,0.055
-(via3.14),Min spacing between via3 rows,CU,0.350
-(via3.irdrop.1),"For 1 <= n <= 2 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.0
-(via3.irdrop.2),"For 3 <= n <= 15 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.6
-(via3.irdrop.3),"For 16 <= n <= 30 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.8
-(via3.irdrop.4),"For n > 30 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.9
+Name,Description,Flags,Value,Unit
+(via3.1),Min and max L and W of via3 (except for rule via3.1a),AL,0.200,µm
+(via3.1a),Two sizes of square via3 allowed inside :drc_tag:`areaid.mt`: 0.200um and 0.800um,AL,,
+(via3.2),Spacing of via3 to via3,AL,0.200,µm
+(via3.3),Only min. square via3s are allowed except die seal ring where via3s are (Via3 CD)*L,,0.2*L,
+(via3.4),Via3 must be enclosed by Met3 by at least …,AL,0.060,µm
+(via3.5),Via3 must be enclosed by Met3 on one of two adjacent sides by at least …,AL,0.090,µm
+(via3.11),Min and max L and W of via3,CU,0.210,µm
+(via3.12),Min spacing between via2's,CU,0.180,µm
+(via3.13),Via3 must be enclosed by Met3 by at least …,CU,0.055,µm
+(via3.14),Min spacing between via3 rows,CU,0.350,µm
+(via3.irdrop.1),"For 1 <= n <= 2 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.0,µm
+(via3.irdrop.2),"For 3 <= n <= 15 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.6,µm
+(via3.irdrop.3),"For 16 <= n <= 30 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.8,µm
+(via3.irdrop.4),"For n > 30 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.9,µm
diff --git a/docs/rules/periphery/p043-indm_dotdash.csv b/docs/rules/periphery/p043-indm_dotdash.csv
index cecef25..ac543bd 100644
--- a/docs/rules/periphery/p043-indm_dotdash.csv
+++ b/docs/rules/periphery/p043-indm_dotdash.csv
@@ -1,5 +1,5 @@
-Name,Description,Flags,Value
-(indm.1),Min width of top_indmMetal,,N/A
-(indm.2),Min spacing between two top_indmMetal,,N/A
-(indm.3),top_padVia must  be enclosed by top_indmMetal by atleast,,N/A
-(indm.4),Min area of top_indmMetal,,N/A
+Name,Description,Flags,Value,Unit
+(indm.1),Min width of top_indmMetal,,N/A,N/A
+(indm.2),Min spacing between two top_indmMetal,,N/A,N/A
+(indm.3),top_padVia must  be enclosed by top_indmMetal by atleast,,N/A,N/A
+(indm.4),Min area of top_indmMetal,,N/A,N/A
diff --git a/docs/rules/periphery/p043-nsm_dotdash.csv b/docs/rules/periphery/p043-nsm_dotdash.csv
index df82f45..cd68216 100644
--- a/docs/rules/periphery/p043-nsm_dotdash.csv
+++ b/docs/rules/periphery/p043-nsm_dotdash.csv
@@ -1,6 +1,6 @@
-Name,Description,Flags,Value
-(nsm.1),Min. width of nsm,,3.000
-(nsm.2),Min. spacing of nsm to nsm,,4.000
-(nsm.3),"Min spacing, no overlap, between NSM_keepout to diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5). Exempt the following from the check: (a) cell name ""nikon*"" and (b) diff ring inside :drc_tag:`areaid.sl`",AL,1.000
-(nsm.3a),"Min enclosure of diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5) by :drc_tag:`areaid.ft`. Exempt the following from the check: (a) cell name ""s8Fab_crntic*""  (b)  blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)",,3.000
-(nsm.3b),"Min spacing between :drc_tag:`areaid.dt` to diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5). Exempt the following from the check: (a) blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)",,3.000
+Name,Description,Flags,Value,Unit
+(nsm.1),Min. width of nsm,,3.000,µm
+(nsm.2),Min. spacing of nsm to nsm,,4.000,µm
+(nsm.3),"Min spacing, no overlap, between NSM_keepout to diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5). Exempt the following from the check: (a) cell name ""nikon*"" and (b) diff ring inside :drc_tag:`areaid.sl`",AL,1.000,µm
+(nsm.3a),"Min enclosure of diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5) by :drc_tag:`areaid.ft`. Exempt the following from the check: (a) cell name ""s8Fab_crntic*""  (b)  blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)",,3.000,µm
+(nsm.3b),"Min spacing between :drc_tag:`areaid.dt` to diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5). Exempt the following from the check: (a) blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)",,3.000,µm
diff --git a/docs/rules/periphery/p044-m4_dotdash.csv b/docs/rules/periphery/p044-m4_dotdash.csv
index d36b918..087e99d 100644
--- a/docs/rules/periphery/p044-m4_dotdash.csv
+++ b/docs/rules/periphery/p044-m4_dotdash.csv
@@ -1,20 +1,27 @@
-Name,Description,Flags,Value
-(m4.-),"Algorithm should flag errors, for met4, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm4 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. Required for IP, Recommended for Chip-level.",RC,
-(m4.1),Min width of met4,,0.300
-(m4.2),Min spacing between two met4,,0.300
-(m4.3),via3 must  be enclosed by met4 by atleast,AL,0.065
-(m4.4),Min area of met4 (rule exempted for probe pads which are exactly 1.42um by 1.42um),,N/A
-(m4.4a),Min area of met4,,0.240
-(m4.5a),Min. spacing of features attached to or extending from huge_met4 for a distance of up to  0.400 um to metal4 (rule not checked over non-huge met4 features),,0.400
-(m4.5b),Min. spacing of huge_met4 to metal4 excluding features checked by m4.5a,,0.400
-(m4.7),Min area of meta4 holes [um2],CU,0.200
-(m4.pd.1),Min MM4_oxide_Pattern_density,RR,0.7
-(m4.pd.2a),Rule m4.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700
-(m4.pd.2b),Rule m4.pd.1 has to be checked by dividing the chip into steps of …,A,70
-(m4.11),Max width of metal4,CU,10.000
-(m4.12),Add slots and remove vias and contacts if wider than…..,CU,10.000
-(m4.13),Max pattern density (PD) of metal4; met4 overlapping pdm areas are excluded from the check,CU,0.77
-(m4.14),Met4 PD window size,CU,50.000
-(m4.14a),Met4 PD window step,CU,25.000
-(m4.15),Via3 must be enclosed by met4 by at least…,CU,0.060
-(m4.16),Min enclosure of pad by met4,CU,0.850
+Name,Description,Flags,Value,Unit
+(m4.-),"| Algorithm should flag errors, for met4, if ANY of the following is true:
+| An entire 700x700 window is covered by cmm4 waffleDrop, and metX PD < 70% for same window.
+| 80-100% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 65% for same window.
+| 60-80% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 60% for same window.
+| 50-60% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 50% for same window.
+| 40-50% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 40% for same window.
+| 30-40% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 30% for same window.
+| Exclude cells whose area is below 40Kum2. Required for IP, Recommended for Chip-level.",RC,,
+(m4.1),Min width of met4,,0.300,µm
+(m4.2),Min spacing between two met4,,0.300,µm
+(m4.3),via3 must  be enclosed by met4 by atleast,AL,0.065,µm
+(m4.4),Min area of met4 (rule exempted for probe pads which are exactly 1.42um by 1.42um),,N/A,N/A
+(m4.4a),Min area of met4,,0.240,µm²
+(m4.5a),Min. spacing of features attached to or extending from huge_met4 for a distance of up to  0.400 µm to metal4 (rule not checked over non-huge met4 features),,0.400,µm
+(m4.5b),Min. spacing of huge_met4 to metal4 excluding features checked by m4.5a,,0.400,µm
+(m4.7),Min area of meta4 holes,CU,0.200,µm²
+(m4.pd.1),Min MM4_oxide_Pattern_density,RR,0.7,\-
+(m4.pd.2a),Rule m4.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700,µm
+(m4.pd.2b),Rule m4.pd.1 has to be checked by dividing the chip into steps of …,A,70,
+(m4.11),Max width of metal4,CU,10.000,µm
+(m4.12),Add slots and remove vias and contacts if wider than…..,CU,10.000,
+(m4.13),Max pattern density (PD) of metal4; met4 overlapping pdm areas are excluded from the check,CU,0.77,\-
+(m4.14),Met4 PD window size,CU,50.000,µm
+(m4.14a),Met4 PD window step,CU,25.000,µm
+(m4.15),Via3 must be enclosed by met4 by at least…,CU,0.060,µm
+(m4.16),Min enclosure of pad by met4,CU,0.850,µm
diff --git a/docs/rules/periphery/p044-m5_dotdash.csv b/docs/rules/periphery/p044-m5_dotdash.csv
index 6cdb44e..bcc9a74 100644
--- a/docs/rules/periphery/p044-m5_dotdash.csv
+++ b/docs/rules/periphery/p044-m5_dotdash.csv
@@ -1,5 +1,5 @@
-Name,Description,Flags,Value
-(m5.1),Min width of met5,,1.600
-(m5.2),Min spacing between two met5,,1.600
-(m5.3),via4 must  be enclosed by met5 by atleast,,0.310
-(m5.4),"Min area of met5 (For all flows except SKY130PIR*/SKY130PF*, the rule is exempted for probe pads which are exactly 1.42um by 1.42um)",,4.000
+Name,Description,Flags,Value,Unit
+(m5.1),Min width of met5,,1.600,µm
+(m5.2),Min spacing between two met5,,1.600,µm
+(m5.3),via4 must  be enclosed by met5 by atleast,,0.310,µm
+(m5.4),"Min area of met5 (For all flows except SKY130PIR*/SKY130PF*, the rule is exempted for probe pads which are exactly 1.42um by 1.42um)",,4.000,µm²
diff --git a/docs/rules/periphery/p044-via4_dotdash.csv b/docs/rules/periphery/p044-via4_dotdash.csv
index 2b82f7e..4b49c3d 100644
--- a/docs/rules/periphery/p044-via4_dotdash.csv
+++ b/docs/rules/periphery/p044-via4_dotdash.csv
@@ -1,9 +1,9 @@
-Name,Description,Flags,Value
-(via4.1),Min and max L and W of via4,,0.800
-(via4.2),Spacing of via4 to via4,,0.800
-(via4.3),Only min. square via4s are allowed except die seal ring where via4s are (Via4 CD)*L,,0.8*L
-(via4.4),Via4 must be enclosed by Met4 by at least …,,0.190
-(via4.irdrop.1),"For 1 <= n <= 4 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.0
-(via4.irdrop.2),"For 5 <= n <= 10 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.2
-(via4.irdrop.3),"For 11 <= n <= 100 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.5
-(via4.irdrop.4),"For n > 100 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.8
+Name,Description,Flags,Value,Unit
+(via4.1),Min and max L and W of via4,,0.800,µm
+(via4.2),Spacing of via4 to via4,,0.800,µm
+(via4.3),Only min. square via4s are allowed except die seal ring where via4s are (Via4 CD)*L,,0.8*L,
+(via4.4),Via4 must be enclosed by Met4 by at least …,,0.190,µm
+(via4.irdrop.1),"For 1 <= n <= 4 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.0,µm
+(via4.irdrop.2),"For 5 <= n <= 10 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.2,µm
+(via4.irdrop.3),"For 11 <= n <= 100 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.5,µm
+(via4.irdrop.4),"For n > 100 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.8,µm
diff --git a/docs/rules/periphery/p045-pad_dotdash.csv b/docs/rules/periphery/p045-pad_dotdash.csv
index f47d603..51dd837 100644
--- a/docs/rules/periphery/p045-pad_dotdash.csv
+++ b/docs/rules/periphery/p045-pad_dotdash.csv
@@ -1,3 +1,3 @@
-Name,Description,Flags,Value
-(pad.2),Min spacing of pad:dg to pad:dg,,1.270
-(pad.3),Max area of hugePad NOT top_metal,,30000
+Name,Description,Flags,Value,Unit
+(pad.2),Min spacing of pad:dg to pad:dg,,1.270,µm
+(pad.3),Max area of hugePad NOT top_metal,,30000,µm²
diff --git a/docs/rules/periphery/p045-rdl_dotdash.csv b/docs/rules/periphery/p045-rdl_dotdash.csv
index 1e36463..60ffe46 100644
--- a/docs/rules/periphery/p045-rdl_dotdash.csv
+++ b/docs/rules/periphery/p045-rdl_dotdash.csv
@@ -1,7 +1,7 @@
-Name,Description,Flags,Value
-(rdl.1),Min width of rdl,,10
-(rdl.2),Min spacing between two rdl,,10
-(rdl.3),"Min enclosure of pad by rdl, except rdl interacting with bump",,10.750
-(rdl.4),Min spacing between rdl and outer edge of the seal ring,,15.000
-(rdl.5),(rdl OR ccu1m.mk) must not overlap :drc_tag:`areaid.ft`. Exempt the following from the check: (a)  blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption),,
-(rdl.6),"Min spacing of rdl to pad, except rdl interacting with bump",,19.660
+Name,Description,Flags,Value,Unit
+(rdl.1),Min width of rdl,,10,µm
+(rdl.2),Min spacing between two rdl,,10,µm
+(rdl.3),"Min enclosure of pad by rdl, except rdl interacting with bump",,10.750,µm
+(rdl.4),Min spacing between rdl and outer edge of the seal ring,,15.000,µm
+(rdl.5),(rdl OR ccu1m.mk) must not overlap :drc_tag:`areaid.ft`. Exempt the following from the check: (a)  blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption),,,
+(rdl.6),"Min spacing of rdl to pad, except rdl interacting with bump",,19.660,µm
diff --git a/docs/rules/periphery/p046-mf_dotdash.csv b/docs/rules/periphery/p046-mf_dotdash.csv
index 41272d2..29cdc6d 100644
--- a/docs/rules/periphery/p046-mf_dotdash.csv
+++ b/docs/rules/periphery/p046-mf_dotdash.csv
@@ -1,25 +1,25 @@
-Name,Description,Flags,Value
-(mf.1),Min. and max width of fuse,,0.800
-(mf.2),Length of fuse,,7.200
-(mf.3),Spacing between centers of adjacent fuses,,2.760
-(mf.4),Spacing between center of fuse and fuse_metal (fuse shields are exempted),,3.300
-(mf.5),Max. extension of fuse_metal beyond fuse boundary,,0.830
-(mf.6),Spacing (no overlapping) between fuse center and Metal1,,3.300
-(mf.7),Spacing (no overlapping) between fuse center and LI,,3.300
-(mf.8),Spacing (no overlapping) between fuse center and poly,,2.660
-(mf.9),Spacing (no overlapping) between fuse center and tap,,2.640
-(mf.10),Spacing (no overlapping) between fuse center and diff,,3.250
-(mf.11),Spacing (no overlapping) between fuse center and nwell,,3.320
-(mf.12),Size of  fuse_shield,,0.5x2.4
-(mf.13),Min. spacing of center of fuse to fuse_shield,,2.200
-(mf.14),Max. spacing of center of fuse to fuse_shield,,3.300
-(mf.15),"Fuse_shields are only placed between periphery metal (i.e., without fuse:dg) and non-isolated edges of fuse as defined by mf.16",,
-(mf.16),The edge of a fuse is considered non-isolated if wider than or equal to mf.2 and spaced to fuse_metal by less than …,,4.000
-(mf.17),Offset between fuse_shields center and fuse center,NC,0.000
-(mf.18),Min and max space between fuse_shield and fuse_metal (opposite edges). Rule checked within 1 gridpoint.,,0.600
-(mf.19),Spacing (no overlapping) between fuse center and Metal2,,3.300
-(mf.20),Only one fuse per metal line allowed,,
-(mf.21),"Min spacing , no overlap, between metal3 and fuse center",,3.300
-(mf.22),Min spacing between fuse_contact to fuse_contact,,1.960
-(mf.23),Spacing (no overlapping) between fuse center and Metal4,,N/A
-(mf.24),Spacing (no overlapping) between fuse center and Metal5,,3.300
+Name,Description,Flags,Value,Unit
+(mf.1),Min. and max width of fuse,,0.800,µm
+(mf.2),Length of fuse,,7.200,µm
+(mf.3),Spacing between centers of adjacent fuses,,2.760,µm
+(mf.4),Spacing between center of fuse and fuse_metal (fuse shields are exempted),,3.300,µm
+(mf.5),Max. extension of fuse_metal beyond fuse boundary,,0.830,
+(mf.6),Spacing (no overlapping) between fuse center and Metal1,,3.300,µm
+(mf.7),Spacing (no overlapping) between fuse center and LI,,3.300,µm
+(mf.8),Spacing (no overlapping) between fuse center and poly,,2.660,µm
+(mf.9),Spacing (no overlapping) between fuse center and tap,,2.640,µm
+(mf.10),Spacing (no overlapping) between fuse center and diff,,3.250,µm
+(mf.11),Spacing (no overlapping) between fuse center and nwell,,3.320,µm
+(mf.12),Size of  fuse_shield,,0.5x2.4,µm
+(mf.13),Min. spacing of center of fuse to fuse_shield,,2.200,µm
+(mf.14),Max. spacing of center of fuse to fuse_shield,,3.300,µm
+(mf.15),"Fuse_shields are only placed between periphery metal (i.e., without fuse:dg) and non-isolated edges of fuse as defined by mf.16",,,
+(mf.16),The edge of a fuse is considered non-isolated if wider than or equal to mf.2 and spaced to fuse_metal by less than …,,4.000,
+(mf.17),Offset between fuse_shields center and fuse center,NC,0.000,
+(mf.18),Min and max space between fuse_shield and fuse_metal (opposite edges). Rule checked within 1 gridpoint.,,0.600,µm
+(mf.19),Spacing (no overlapping) between fuse center and Metal2,,3.300,µm
+(mf.20),Only one fuse per metal line allowed,,,
+(mf.21),"Min spacing , no overlap, between metal3 and fuse center",,3.300,µm
+(mf.22),Min spacing between fuse_contact to fuse_contact,,1.960,µm
+(mf.23),Spacing (no overlapping) between fuse center and Metal4,,N/A,N/A
+(mf.24),Spacing (no overlapping) between fuse center and Metal5,,3.300,µm
diff --git a/docs/rules/periphery/p047-hvi_dotdash.csv b/docs/rules/periphery/p047-hvi_dotdash.csv
index 858bbf1..d460a13 100644
--- a/docs/rules/periphery/p047-hvi_dotdash.csv
+++ b/docs/rules/periphery/p047-hvi_dotdash.csv
@@ -1,6 +1,6 @@
-Name,Description,Flags,Value
-(hvi.1),Min width of Hvi,P,0.600
-(hvi.2a),Min spacing of Hvi to Hvi,P,0.700
-(hvi.2b),Manual merge if space is below minimum,,
-(hvi.4),Hvi must not overlap tunm,,
-(hvi.5),Min space between hvi and nwell (exclude coincident edges),,0.700
+Name,Description,Flags,Value,Unit
+(hvi.1),Min width of Hvi,P,0.600,µm
+(hvi.2a),Min spacing of Hvi to Hvi,P,0.700,µm
+(hvi.2b),Manual merge if space is below minimum,,,
+(hvi.4),Hvi must not overlap tunm,,,
+(hvi.5),Min space between hvi and nwell (exclude coincident edges),,0.700,µm
diff --git a/docs/rules/periphery/p047-hvnwell_dotdash.csv b/docs/rules/periphery/p047-hvnwell_dotdash.csv
index 7288fd9..8f59308 100644
--- a/docs/rules/periphery/p047-hvnwell_dotdash.csv
+++ b/docs/rules/periphery/p047-hvnwell_dotdash.csv
@@ -1,5 +1,5 @@
-Name,Description,Flags,Value
-(hvnwell.8),Min space between HV_nwell  and any nwell on different nets,,2.000
-(hvnwell.9),(Nwell overlapping hvi) must be enclosed by hvi,,
-(hvnwell.10),"LVnwell and HnWell should not be on the same net (for the purposes of this check, short the connectivity through resistors); Exempt HnWell with li nets tagged ""lv_net"" using text.dg and Hnwell connected to nwell overlapping :drc_tag:`areaid.hl`",TC,
-(hvnwell.11),"Nwell connected to the nets mentioned in the ""Power_Net_Hv"" field of the latcup GUI must be enclosed by hvi (exempt nwell inside :drc_tag:`areaid.hl`). Also for the purposes of this check, short the connectivity through resistors. The rule will be checked in the latchup run and exempted for cells ""s8tsg5_tx_ibias_gen"" and ""s8bbcnv_psoc3p_top_18"",  ""rainier_top, indus_top*"", ""rainier_top, manas_top, ccg3_top""",,
+Name,Description,Flags,Value,Unit
+(hvnwell.8),Min space between HV_nwell  and any nwell on different nets,,2.000,µm
+(hvnwell.9),(Nwell overlapping hvi) must be enclosed by hvi,,,
+(hvnwell.10),"LVnwell and HnWell should not be on the same net (for the purposes of this check, short the connectivity through resistors); Exempt HnWell with li nets tagged ""lv_net"" using text.dg and Hnwell connected to nwell overlapping :drc_tag:`areaid.hl`",TC,,
+(hvnwell.11),"Nwell connected to the nets mentioned in the ""Power_Net_Hv"" field of the latcup GUI must be enclosed by hvi (exempt nwell inside :drc_tag:`areaid.hl`). Also for the purposes of this check, short the connectivity through resistors. The rule will be checked in the latchup run and exempted for cells ""s8tsg5_tx_ibias_gen"" and ""s8bbcnv_psoc3p_top_18"",  ""rainier_top, indus_top*"", ""rainier_top, manas_top, ccg3_top""",,,
diff --git a/docs/rules/periphery/p048-hvdifftap_dotdash.csv b/docs/rules/periphery/p048-hvdifftap_dotdash.csv
index f9f0068..8013ce4 100644
--- a/docs/rules/periphery/p048-hvdifftap_dotdash.csv
+++ b/docs/rules/periphery/p048-hvdifftap_dotdash.csv
@@ -1,16 +1,16 @@
-Name,Description,Flags,Value
-(hvdifftap.14),"Min width of diff inside Hvi, except HV Pdiff resistors (difftap.14a)",P,0.290
-(hvdifftap.14a),"Min width of diff inside Hvi, HV Pdiff resistors only",P,0.150
-(hvdifftap.15a),Min space of Hdiff to Hdiff,P,0.300
-(hvdifftap.15b),Min space of n+diff to non-abutting p+tap inside Hvi,P,0.370
-(hvdifftap.16),Min width tap butting diff on one or two sides inside Hvi (rule exempted inside UHVI),,0.700
-(hvdifftap.17),P+ Hdiff or Pdiff inside areaid:hvnwell must be enclosed by Hv_nwell by at least ….[Rule exempted inside UHVI],DE NE,0.330
-(hvdifftap.18),Spacing of N+ diff to HV_nwell (rule exempted inside UHVI),DE NE,0.430
-(hvdifftap.19),N+ Htap must be enclosed by Hv_nwell by at least …Rule exempted inside UHVI.,NE,0.330
-(hvdifftap.20),Spacing of P+ tap to HV_nwell (Exempted for p+tap butting pwell.rs; rule exempted inside UHVI),,0.430
-(hvdifftap.21),Diff or tap cannot straddle Hvi,P,
-(hvdifftap.22),Min enclosure of Hdiff or Htap by Hvi. Rule exempted inside UHVI.,P,0.180
-(hvdifftap.23),Space between diff or tap outside Hvi and Hvi,P,0.180
-(hvdifftap.24),Spacing of nwell to N+ Hdiff (rule exempted inside UHVI),DE NE,0.430
-(hvdifftap.25),Min space of N+ Hdiff inside HVI across non-abutting P+_tap,NC,1.070
-(hvdifftap.26),Min spacing between pwbm to difftap outside UHVI,,N/A
+Name,Description,Flags,Value,Unit
+(hvdifftap.14),"Min width of diff inside Hvi, except HV Pdiff resistors (difftap.14a)",P,0.290,µm
+(hvdifftap.14a),"Min width of diff inside Hvi, HV Pdiff resistors only",P,0.150,µm
+(hvdifftap.15a),Min space of Hdiff to Hdiff,P,0.300,µm
+(hvdifftap.15b),Min space of n+diff to non-abutting p+tap inside Hvi,P,0.370,µm
+(hvdifftap.16),Min width tap butting diff on one or two sides inside Hvi (rule exempted inside UHVI),,0.700,µm
+(hvdifftap.17),P+ Hdiff or Pdiff inside areaid:hvnwell must be enclosed by Hv_nwell by at least ….[Rule exempted inside UHVI],DE NE,0.330,µm
+(hvdifftap.18),Spacing of N+ diff to HV_nwell (rule exempted inside UHVI),DE NE,0.430,µm
+(hvdifftap.19),N+ Htap must be enclosed by Hv_nwell by at least …Rule exempted inside UHVI.,NE,0.330,µm
+(hvdifftap.20),Spacing of P+ tap to HV_nwell (Exempted for p+tap butting pwell.rs; rule exempted inside UHVI),,0.430,µm
+(hvdifftap.21),Diff or tap cannot straddle Hvi,P,,
+(hvdifftap.22),Min enclosure of Hdiff or Htap by Hvi. Rule exempted inside UHVI.,P,0.180,µm
+(hvdifftap.23),Space between diff or tap outside Hvi and Hvi,P,0.180,µm
+(hvdifftap.24),Spacing of nwell to N+ Hdiff (rule exempted inside UHVI),DE NE,0.430,µm
+(hvdifftap.25),Min space of N+ Hdiff inside HVI across non-abutting P+_tap,NC,1.070,µm
+(hvdifftap.26),Min spacing between pwbm to difftap outside UHVI,,N/A,N/A
diff --git a/docs/rules/periphery/p049-hvntm_dotdash.csv b/docs/rules/periphery/p049-hvntm_dotdash.csv
index 0824cc4..9708a99 100644
--- a/docs/rules/periphery/p049-hvntm_dotdash.csv
+++ b/docs/rules/periphery/p049-hvntm_dotdash.csv
@@ -1,12 +1,12 @@
-Name,Description,Flags,Value
-(hvntm.X.1 ),Hvntm can be drawn inside HVI. Drawn layer will be OR-ed with the CL and rechecked for CLDRC,,
-(hvntm.1),Width of hvntm,P,0.700
-(hvntm.2),Spacing of hvntm to hvntm,P,0.700
-(hvntm.3),Min. enclosure of (n+_diff inside Hvi) but not overlapping :drc_tag:`areaid.ce` by hvntm,P,0.185
-(hvntm.4),"Space, no overlap, between n+_diff outside Hvi and hvntm",P,0.185
-(hvntm.5),"Space, no overlap, between p+_diff  and hvntm",P DE,0.185
-(hvntm.6a),"Space, no overlap, between p+_tap and hvntm (except along the diff-butting edge)",P,0.185
-(hvntm.6b),"Space, no overlap, between p+_tap and hvntm along the diff-butting edge",P,0.000
-(hvntm.7),hvntm must enclose ESD_nwell_tap inside hvi by atleast,P,0.000
-(hvntm.9),Hvntm must not overlap :drc_tag:`areaid.ce`,,
-(hvntm.10),Hvntm must overlap hvi,,
+Name,Description,Flags,Value,Unit
+(hvntm.X.1),Hvntm can be drawn inside HVI. Drawn layer will be OR-ed with the CL and rechecked for CLDRC,,,
+(hvntm.1),Width of hvntm,P,0.700,µm
+(hvntm.2),Spacing of hvntm to hvntm,P,0.700,µm
+(hvntm.3),Min. enclosure of (n+_diff inside Hvi) but not overlapping :drc_tag:`areaid.ce` by hvntm,P,0.185,µm
+(hvntm.4),"Space, no overlap, between n+_diff outside Hvi and hvntm",P,0.185,µm
+(hvntm.5),"Space, no overlap, between p+_diff  and hvntm",P DE,0.185,µm
+(hvntm.6a),"Space, no overlap, between p+_tap and hvntm (except along the diff-butting edge)",P,0.185,µm
+(hvntm.6b),"Space, no overlap, between p+_tap and hvntm along the diff-butting edge",P,0.000,µm
+(hvntm.7),hvntm must enclose ESD_nwell_tap inside hvi by atleast,P,0.000,
+(hvntm.9),Hvntm must not overlap :drc_tag:`areaid.ce`,,,
+(hvntm.10),Hvntm must overlap hvi,,,
diff --git a/docs/rules/periphery/p049-hvpoly_dotdash.csv b/docs/rules/periphery/p049-hvpoly_dotdash.csv
index c4dd20b..69fe5eb 100644
--- a/docs/rules/periphery/p049-hvpoly_dotdash.csv
+++ b/docs/rules/periphery/p049-hvpoly_dotdash.csv
@@ -1,3 +1,3 @@
-Name,Description,Flags,Value
-(hvpoly.13),Min width of poly over diff inside Hvi,P,0.500
-(hvpoly.14),(poly and diff) cannot straddle Hvi,,
+Name,Description,Flags,Value,Unit
+(hvpoly.13),Min width of poly over diff inside Hvi,P,0.500,µm
+(hvpoly.14),(poly and diff) cannot straddle Hvi,,,
diff --git a/docs/rules/periphery/p050-denmos_dotdash.csv b/docs/rules/periphery/p050-denmos_dotdash.csv
index e31fd61..8c53323 100644
--- a/docs/rules/periphery/p050-denmos_dotdash.csv
+++ b/docs/rules/periphery/p050-denmos_dotdash.csv
@@ -1,16 +1,16 @@
-Name,Description,Flags,Value
-(denmos.1),Min width of de_nFet_gate,,1.055
-(denmos.2),Min width of de_nFet_source not overlapping poly,,0.280
-(denmos.3),Min width of de_nFet_source overlapping poly,,0.925
-(denmos.4),Min width of the de_nFet_drain,,0.170
-(denmos.5),Min/Max extension of de_nFet_source over nwell,,0.225
-(denmos.6),Min/Max spacing between de_nFet_drain and de_nFet_source,,1.585
-(denmos.7),Min channel width for de_nFet_gate,,5.000
-(denmos.8),90 degree angles are not permitted for nwell overlapping de_nFET_drain,,
-(denmos.9a),"All bevels on nwell are 45 degree, 0.43 um from corners",NC,
-(denmos.9b),"All bevels on de_nFet_drain are 45 degree, 0.05 um from corners",NC,
-(denmos.10),Min enclosure of de_nFet_drain by nwell,,0.660
-(denmos.11),Min spacing between p+ tap and (nwell overlapping de_nFet_drain),,0.860
-(denmos.12),Min spacing between nwells overlapping de_nFET_drain,,2.400
-(denmos.13),de_nFet_source must be enclosed by nsdm by,,0.130
-(denmos.14),nvhv FETs must be enclosed by :drc_tag:`areaid.mt`,,N/A
+Name,Description,Flags,Value,Unit
+(denmos.1),Min width of de_nFet_gate,,1.055,µm
+(denmos.2),Min width of de_nFet_source not overlapping poly,,0.280,µm
+(denmos.3),Min width of de_nFet_source overlapping poly,,0.925,µm
+(denmos.4),Min width of the de_nFet_drain,,0.170,µm
+(denmos.5),Min/Max extension of de_nFet_source over nwell,,0.225,
+(denmos.6),Min/Max spacing between de_nFet_drain and de_nFet_source,,1.585,µm
+(denmos.7),Min channel width for de_nFet_gate,,5.000,µm
+(denmos.8),90 degree angles are not permitted for nwell overlapping de_nFET_drain,,,
+(denmos.9a),"All bevels on nwell are 45 degree, 0.43 µm from corners",NC,,µm
+(denmos.9b),"All bevels on de_nFet_drain are 45 degree, 0.05 µm from corners",NC,,µm
+(denmos.10),Min enclosure of de_nFet_drain by nwell,,0.660,µm
+(denmos.11),Min spacing between p+ tap and (nwell overlapping de_nFet_drain),,0.860,µm
+(denmos.12),Min spacing between nwells overlapping de_nFET_drain,,2.400,µm
+(denmos.13),de_nFet_source must be enclosed by nsdm by,,0.130,µm
+(denmos.14),nvhv FETs must be enclosed by :drc_tag:`areaid.mt`,,N/A,N/A
diff --git a/docs/rules/periphery/p051-depmos_dotdash.csv b/docs/rules/periphery/p051-depmos_dotdash.csv
index d573fbf..28e3049 100644
--- a/docs/rules/periphery/p051-depmos_dotdash.csv
+++ b/docs/rules/periphery/p051-depmos_dotdash.csv
@@ -1,15 +1,15 @@
-Name,Description,Flags,Value
-(depmos.1),Min width of de_pFet_gate,,1.050
-(depmos.2),Min width of de_pFet_source not overlapping poly,,0.280
-(depmos.3),Min width of de_pFet_source overlapping poly,,0.920
-(depmos.4),Min width of the de_pFet_drain,,0.170
-(depmos.5),Min/Max extension of de_pFet_source beyond nwell,,0.260
-(depmos.6),Min/Max spacing between de_pFet_drain and de_pFet_source,,1.190
-(depmos.7),Min channel width for de_pFet_gate,,5.000
-(depmos.8),90 degree angles are not permitted for nwell hole overlapping de_pFET_drain,,
-(depmos.9a),"All bevels on nwell hole are 45 degree, 0.43 um from corners",NC,
-(depmos.9b),"All bevels on de_pFet_drain are 45 degree, 0.05 um from corners",NC,
-(depmos.10),Min enclosure of de_pFet_drain by nwell hole,,0.860
-(depmos.11),Min spacing between n+ tap and (nwell hole enclosing de_pFET_drain),,0.660
-(depmos.12),de_pFet_source must be enclosed by psdm by,,0.130
-(depmos.13),pvhv fets( except those with W/L = 5.0/0.66) must be enclosed by :drc_tag:`areaid.mt`,,N/A
+Name,Description,Flags,Value,Unit
+(depmos.1),Min width of de_pFet_gate,,1.050,µm
+(depmos.2),Min width of de_pFet_source not overlapping poly,,0.280,µm
+(depmos.3),Min width of de_pFet_source overlapping poly,,0.920,µm
+(depmos.4),Min width of the de_pFet_drain,,0.170,µm
+(depmos.5),Min/Max extension of de_pFet_source beyond nwell,,0.260,
+(depmos.6),Min/Max spacing between de_pFet_drain and de_pFet_source,,1.190,µm
+(depmos.7),Min channel width for de_pFet_gate,,5.000,µm
+(depmos.8),90 degree angles are not permitted for nwell hole overlapping de_pFET_drain,,,
+(depmos.9a),"All bevels on nwell hole are 45 degree, 0.43 µm from corners",NC,,µm
+(depmos.9b),"All bevels on de_pFet_drain are 45 degree, 0.05 µm from corners",NC,,µm
+(depmos.10),Min enclosure of de_pFet_drain by nwell hole,,0.860,µm
+(depmos.11),Min spacing between n+ tap and (nwell hole enclosing de_pFET_drain),,0.660,µm
+(depmos.12),de_pFet_source must be enclosed by psdm by,,0.130,µm
+(depmos.13),pvhv fets( except those with W/L = 5.0/0.66) must be enclosed by :drc_tag:`areaid.mt`,,N/A,N/A
diff --git a/docs/rules/periphery/p052-extd_dotdash.csv b/docs/rules/periphery/p052-extd_dotdash.csv
index b028bfd..a4060ee 100644
--- a/docs/rules/periphery/p052-extd_dotdash.csv
+++ b/docs/rules/periphery/p052-extd_dotdash.csv
@@ -1,9 +1,9 @@
-Name,Description,Flags,Value
-(extd.1),Difftap cannot straddle areaid:en,,
-(extd.2),DiffTap must have 2 or 3 coincident edges with areaid:en if enclosed by areaid:en,,
-(extd.3),Poly must not be entirely overlapping difftap in areaid:en,,
-(extd.4),"Only cell name ""s8rf_n20vhv1*"" is a valid cell name for n20vhv1 device  (Check in LVS as invalid device)",,N/A
-(extd.5),"Only cell name ""s8rf_n20vhviso1"" is a valid cell name for n20vhviso1 device  (Check in LVS as invalid device)",,N/A
-(extd.6),"Only cell name ""s8rf_p20vhv1"" is a valid cell name for p20vhv1 device  (Check in LVS as invalid device)",,N/A
-(extd.7),"Only cell name ""s8rf_n20nativevhv1*"" is a valid cell name for n20nativevhv1 device  (Check in LVS as invalid device)",,N/A
-(extd.8),"Only cell name ""s8rf_n20zvtvhv1*"" is a valid cell name for n20zvtvhv1 device  (Check in LVS as invalid device)",,N/A
+Name,Description,Flags,Value,Unit
+(extd.1),Difftap cannot straddle areaid:en,,,
+(extd.2),DiffTap must have 2 or 3 coincident edges with areaid:en if enclosed by areaid:en,,,
+(extd.3),Poly must not be entirely overlapping difftap in areaid:en,,,
+(extd.4),"Only cell name ""s8rf_n20vhv1*"" is a valid cell name for n20vhv1 device  (Check in LVS as invalid device)",,N/A,N/A
+(extd.5),"Only cell name ""s8rf_n20vhviso1"" is a valid cell name for n20vhviso1 device  (Check in LVS as invalid device)",,N/A,N/A
+(extd.6),"Only cell name ""s8rf_p20vhv1"" is a valid cell name for p20vhv1 device  (Check in LVS as invalid device)",,N/A,N/A
+(extd.7),"Only cell name ""s8rf_n20nativevhv1*"" is a valid cell name for n20nativevhv1 device  (Check in LVS as invalid device)",,N/A,N/A
+(extd.8),"Only cell name ""s8rf_n20zvtvhv1*"" is a valid cell name for n20zvtvhv1 device  (Check in LVS as invalid device)",,N/A,N/A
diff --git a/docs/rules/periphery/p054-hv_dotdash_dotdash.csv b/docs/rules/periphery/p054-hv_dotdash_dotdash.csv
index 03d9d78..3a06ddb 100644
--- a/docs/rules/periphery/p054-hv_dotdash_dotdash.csv
+++ b/docs/rules/periphery/p054-hv_dotdash_dotdash.csv
@@ -1,20 +1,20 @@
-Name,Description,Flags,Value
-(hv.X.1),High voltage source/drain regions must be tagged by diff:hv,,
-(hv.X.3),"High voltage poly can be drawn over multiple diff regions that are ALL reverse-biased by at least 300 mV (existence of reverse-bias is not checked by the CAD flow).  It can also be drawn over multiple diffs when all sources and all drain are shorted together. In these case, the high voltage poly can be tagged with the text:dg label with a value “hv_bb”.  Exceptions to this use of the hv_bb label must be approved by technology.  Under certain bias conditions, high voltage poly tagged with hv_bb can cross an nwell boundary. The poly of the drain extended device crosses nwell by construction and can be tagged with the ""hv_bb"" label. Use of the hv_bb label on high voltage poly crossing an nwell boundary must be approved by technology. All high voltage poly tagged with hv_bb will not be checked to hv.poly.1, hv.poly.2, hv.poly.3 and hv.poly.4.",,
-(hv.X.4),Any piece of layout that is shorted to hv_source/drain becomes a high voltage feature.,,
-(hv.X.5),"In cases where an hv poly gate abuts only low voltage source and drain, the poly gate can be tagged with the text:dg label with a value ""hv_lv"".  In this case, the ""hv_lv"" tagged poly gate and its extensions will not be checked to hv.poly.6, but is checked by rules in the poly.-.- section.  The use of the hv_lv label must be approved by technology.",,
-(hv.X.6),"Nwell biased at voltages >= 7.2V must be tagged with text ""shv_nwell""",NC,
-(hv.nwell.1),"Min spacing of nwell tagged with text ""shv_nwell"" to any nwell on different nets",,2.500
-(hv.diff.1a),Minimum hv_source/drain spacing to diff for edges of hv_source/drain and diff not butting tap,,0.300
-(hv.diff.1b),Minimum spacing of (n+/p+ diff resistors and diodes) connected to hv_source/drain to diff,,0.300
-(hv.diff.2),Minimum spacing of nwell connected to hv_source/drain to n+ diff,DE,0.430
-(hv.diff.3a),Minimum n+ hv_source/drain spacing to nwell,,0.550
-(hv.diff.3b),Minimum spacing of (n+ diff resistors and diodes) connected to hv_source/drain to nwell,,0.550
-(hv.poly.1),Hv poly feature hvPoly (including hv poly resistors) can be drawn over only one diff region and is not allowed to cross nwell boundary except (1) as allowed in rule .X.3 and (2) nwell hole boundary in depmos,,
-(hv.poly.2),Min spacing of hvPoly (including hv poly resistor) on field to diff (diff butting hvPoly are excluded),,0.300
-(hv.poly.3),Min spacing of hvPoly (including hv poly resistor) on field to n-well (exempt poly stradding nwell in a denmos/depmos),,0.550
-(hv.poly.4),Enclosure of hvPoly (including hv poly resistor) on field by n-well (exempt poly stradding nwell in a denmos/depmos),,0.300
-(hv.poly.6a),Min extension of poly beyond hvFET_gate (exempt poly extending beyond diff along the S/D direction in a denmos/depmos),,0.160
-(hv.poly.6b),Extension of hv poly beyond FET_gate (including hvFET_gate; exempt poly extending beyond diff along the S/D direction in a denmos/depmos),,0.160
-(hv.poly.7),Minimum overlap of hv poly ring_FET and diff,,
-(hv.poly.8),Any poly gate abutting hv_source/drain becomes a hvFET_gate,,
+Name,Description,Flags,Value,Unit
+(hv.X.1),High voltage source/drain regions must be tagged by diff:hv,,,
+(hv.X.3),"High voltage poly can be drawn over multiple diff regions that are ALL reverse-biased by at least 300 mV (existence of reverse-bias is not checked by the CAD flow).  It can also be drawn over multiple diffs when all sources and all drain are shorted together. In these case, the high voltage poly can be tagged with the text:dg label with a value “hv_bb”.  Exceptions to this use of the hv_bb label must be approved by technology.  Under certain bias conditions, high voltage poly tagged with hv_bb can cross an nwell boundary. The poly of the drain extended device crosses nwell by construction and can be tagged with the ""hv_bb"" label. Use of the hv_bb label on high voltage poly crossing an nwell boundary must be approved by technology. All high voltage poly tagged with hv_bb will not be checked to hv.poly.1, hv.poly.2, hv.poly.3 and hv.poly.4.",,,
+(hv.X.4),Any piece of layout that is shorted to hv_source/drain becomes a high voltage feature.,,,
+(hv.X.5),"In cases where an hv poly gate abuts only low voltage source and drain, the poly gate can be tagged with the text:dg label with a value ""hv_lv"".  In this case, the ""hv_lv"" tagged poly gate and its extensions will not be checked to hv.poly.6, but is checked by rules in the poly.-.- section.  The use of the hv_lv label must be approved by technology.",,,
+(hv.X.6),"Nwell biased at voltages >= 7.2V must be tagged with text ""shv_nwell""",NC,,
+(hv.nwell.1),"Min spacing of nwell tagged with text ""shv_nwell"" to any nwell on different nets",,2.500,µm
+(hv.diff.1a),Minimum hv_source/drain spacing to diff for edges of hv_source/drain and diff not butting tap,,0.300,µm
+(hv.diff.1b),Minimum spacing of (n+/p+ diff resistors and diodes) connected to hv_source/drain to diff,,0.300,µm
+(hv.diff.2),Minimum spacing of nwell connected to hv_source/drain to n+ diff,DE,0.430,µm
+(hv.diff.3a),Minimum n+ hv_source/drain spacing to nwell,,0.550,µm
+(hv.diff.3b),Minimum spacing of (n+ diff resistors and diodes) connected to hv_source/drain to nwell,,0.550,µm
+(hv.poly.1),Hv poly feature hvPoly (including hv poly resistors) can be drawn over only one diff region and is not allowed to cross nwell boundary except (1) as allowed in rule .X.3 and (2) nwell hole boundary in depmos,,,
+(hv.poly.2),Min spacing of hvPoly (including hv poly resistor) on field to diff (diff butting hvPoly are excluded),,0.300,µm
+(hv.poly.3),Min spacing of hvPoly (including hv poly resistor) on field to n-well (exempt poly stradding nwell in a denmos/depmos),,0.550,µm
+(hv.poly.4),Enclosure of hvPoly (including hv poly resistor) on field by n-well (exempt poly stradding nwell in a denmos/depmos),,0.300,µm
+(hv.poly.6a),Min extension of poly beyond hvFET_gate (exempt poly extending beyond diff along the S/D direction in a denmos/depmos),,0.160,
+(hv.poly.6b),Extension of hv poly beyond FET_gate (including hvFET_gate; exempt poly extending beyond diff along the S/D direction in a denmos/depmos),,0.160,
+(hv.poly.7),Minimum overlap of hv poly ring_FET and diff,,,
+(hv.poly.8),Any poly gate abutting hv_source/drain becomes a hvFET_gate,,,
diff --git a/docs/rules/periphery/p055-uhvi_dotdash_dotdash.csv b/docs/rules/periphery/p055-uhvi_dotdash_dotdash.csv
index b6ed684..3975773 100644
--- a/docs/rules/periphery/p055-uhvi_dotdash_dotdash.csv
+++ b/docs/rules/periphery/p055-uhvi_dotdash_dotdash.csv
@@ -1,11 +1,11 @@
-Name,Description,Flags,Value
-(uhvi.1.-),diff/tap can not straddle UHVI,,N/A
-(uhvi.2.-),poly can not straddle UHVI,,N/A
-(uhvi.3.-),pwbm.dg must be enclosed by UHVI (exempt inside :drc_tag:`areaid.lw`),,N/A
-(uhvi.4.-),dnw.dg can not straddle UHVI,,N/A
-(uhvi.5.-),UHVI must enclose :drc_tag:`areaid.ext`,,N/A
-(uhvi.6.-),UHVI must enclose dnwell,,N/A
-(uhvi.7.-),natfet.dg must be enclosed by UHVI layer by at least,,N/A
-(uhvi.8.-),Minimum width of natfet.dg,,N/A
-(uhvi.9.-),Minimum Space spacing of natfet.dg,,N/A
-(uhvi.10.-),natfet.dg layer is not allowed,,N/A
+Name,Description,Flags,Value,Unit
+(uhvi.1.-),diff/tap can not straddle UHVI,,N/A,N/A
+(uhvi.2.-),poly can not straddle UHVI,,N/A,N/A
+(uhvi.3.-),pwbm.dg must be enclosed by UHVI (exempt inside :drc_tag:`areaid.lw`),,N/A,N/A
+(uhvi.4.-),dnw.dg can not straddle UHVI,,N/A,N/A
+(uhvi.5.-),UHVI must enclose :drc_tag:`areaid.ext`,,N/A,N/A
+(uhvi.6.-),UHVI must enclose dnwell,,N/A,N/A
+(uhvi.7.-),natfet.dg must be enclosed by UHVI layer by at least,,N/A,N/A
+(uhvi.8.-),Minimum width of natfet.dg,,N/A,N/A
+(uhvi.9.-),Minimum Space spacing of natfet.dg,,N/A,N/A
+(uhvi.10.-),natfet.dg layer is not allowed,,N/A,N/A
diff --git a/docs/rules/periphery/p055-ulvt-_dotdash.csv b/docs/rules/periphery/p055-ulvt-_dotdash.csv
index 32f94b0..d59f02f 100644
--- a/docs/rules/periphery/p055-ulvt-_dotdash.csv
+++ b/docs/rules/periphery/p055-ulvt-_dotdash.csv
@@ -1,4 +1,4 @@
-Name,Description,Flags,Value
-(ulvt-.1),":drc_tag:`areaid.low_vt` must enclose dnw for the UHV dnw-psub diode texted ""condiodeHvPsub""",,NA
-(ulvt-.2),":drc_tag:`areaid.low_vt` must enclose pwbm.dg for the UHV dnw-psub diode texted ""condiodeHvPsub""",,NA
-(ulvt-.3),:drc_tag:`areaid.low_vt` can not straddle UHVI,,NA
+Name,Description,Flags,Value,Unit
+(ulvt-.1),":drc_tag:`areaid.low_vt` must enclose dnw for the UHV dnw-psub diode texted ""condiodeHvPsub""",,NA,
+(ulvt-.2),":drc_tag:`areaid.low_vt` must enclose pwbm.dg for the UHV dnw-psub diode texted ""condiodeHvPsub""",,NA,
+(ulvt-.3),:drc_tag:`areaid.low_vt` can not straddle UHVI,,NA,
diff --git a/docs/rules/periphery/p055-vhvi_dotdash_dotdash.csv b/docs/rules/periphery/p055-vhvi_dotdash_dotdash.csv
index fb0a4e5..90ba2e2 100644
--- a/docs/rules/periphery/p055-vhvi_dotdash_dotdash.csv
+++ b/docs/rules/periphery/p055-vhvi_dotdash_dotdash.csv
@@ -1,15 +1,15 @@
-Name,Description,Flags,Value
-(vhvi.vhv.1),Terminals operating at nominal 12V (maximum 16V) bias must be tagged as Very-High-Voltage (VHV) using vhvi:dg layer,NC,
-(vhvi.vhv.2),A source or drain of a drain-extended device can be tagged by vhvi:dg. A device with either source or drain (not both) tagged with vhvi:dg serves as a VHV propagation stopper,NC,
-(vhvi.vhv.3),Any feature connected to VHVSourceDrain becomes a very-high-voltage feature,NC,
-(vhvi.vhv.4),Any feature connected to VHVPoly becomes a very-high-voltage feature,NC,
-(vhvi.vhv.5),"Diffusion that is not a part of a drain-extended device (i.e., diff not areaid:en) must not be on the same net as VHVSourceDrain. Only diffusion inside :drc_tag:`areaid.ed` and LV diffusion tagged with vhvi:dg are exempted.",,
-(vhvi.vhv.6),"Poly resistor can act as a VHV propagation stopper. For this, it should be tagged with text ""vhv_block""",NC,
-(vhvi.1.-),Min width of vhvi:dg,,0.020
-(vhvi.2.-),Vhvi:dg cannot overlap areaid:ce,,
-(vhvi.3.-),VHVGate must overlap hvi:dg,,
-(vhvi.4.-),Poly connected to the same net as a VHVSourceDrain must be tagged with vhvi:dg layer,,
-(vhvi.5.-),Vhvi:dg cannot straddle VHVSourceDrain,,
-(vhvi.6.-),Vhvi:dg overlapping VHVSourceDrain must not overlap poly,,
-(vhvi.7.-),Vhvi:dg cannot straddle VHVPoly,,
-(vhvi.8.-),"Min space between nwell tagged with vhvi:dg and deep nwell, nwell, or n+diff on a separate net (except for n+diff overlapping nwell tagged with vhvi:dg).",,11.240
+Name,Description,Flags,Value,Unit
+(vhvi.vhv.1),Terminals operating at nominal 12V (maximum 16V) bias must be tagged as Very-High-Voltage (VHV) using vhvi:dg layer,NC,,
+(vhvi.vhv.2),A source or drain of a drain-extended device can be tagged by vhvi:dg. A device with either source or drain (not both) tagged with vhvi:dg serves as a VHV propagation stopper,NC,,
+(vhvi.vhv.3),Any feature connected to VHVSourceDrain becomes a very-high-voltage feature,NC,,
+(vhvi.vhv.4),Any feature connected to VHVPoly becomes a very-high-voltage feature,NC,,
+(vhvi.vhv.5),"Diffusion that is not a part of a drain-extended device (i.e., diff not areaid:en) must not be on the same net as VHVSourceDrain. Only diffusion inside :drc_tag:`areaid.ed` and LV diffusion tagged with vhvi:dg are exempted.",,,
+(vhvi.vhv.6),"Poly resistor can act as a VHV propagation stopper. For this, it should be tagged with text ""vhv_block""",NC,,
+(vhvi.1.-),Min width of vhvi:dg,,0.020,µm
+(vhvi.2.-),Vhvi:dg cannot overlap areaid:ce,,,
+(vhvi.3.-),VHVGate must overlap hvi:dg,,,
+(vhvi.4.-),Poly connected to the same net as a VHVSourceDrain must be tagged with vhvi:dg layer,,,
+(vhvi.5.-),Vhvi:dg cannot straddle VHVSourceDrain,,,
+(vhvi.6.-),Vhvi:dg overlapping VHVSourceDrain must not overlap poly,,,
+(vhvi.7.-),Vhvi:dg cannot straddle VHVPoly,,,
+(vhvi.8.-),"Min space between nwell tagged with vhvi:dg and deep nwell, nwell, or n+diff on a separate net (except for n+diff overlapping nwell tagged with vhvi:dg).",,11.240,µm
diff --git a/docs/rules/periphery/p056-pwres_dotdash_dotdash.csv b/docs/rules/periphery/p056-pwres_dotdash_dotdash.csv
index 168c42c..9a2ff55 100644
--- a/docs/rules/periphery/p056-pwres_dotdash_dotdash.csv
+++ b/docs/rules/periphery/p056-pwres_dotdash_dotdash.csv
@@ -1,13 +1,13 @@
-Name,Description,Flags,Value
-(pwres.1.-),Pwell resistor has to be enclosed by the res layer,NC,
-(pwres.2.-),Min/Max width of pwell resistor,,2.650
-(pwres.3.-),Min length of pwell resistor,,26.500
-(pwres.4.-),Max length of pwell resistor,,265.00
-(pwres.5.-),Min/Max spacing of tap inside the pwell resistor to nwell,,0.220
-(pwres.6.-),Min/Max width of tap inside the pwell resistor,,0.530
-(pwres.7a.-),Every pwres_terminal must enclose 12 licon1,,
-(pwres.7b.-),Every pwres_terminal must enclose 12 mcons if routed through metal1,,
-(pwres.8.-),Diff or poly is not allowed in the pwell resistor.,,
-(pwres.9.-),Nwell surrounding the pwell resistor must have a full ring of contacted tap strapped with metal.,,
-(pwres.10.-),The res layer must abut pwres_terminal on opposite and parallel edges,,
-(pwres.11.-),The res layer must abut nwell on opposite and parallel edges not checked in Rule pwres.10,,
+Name,Description,Flags,Value,Unit
+(pwres.1.-),Pwell resistor has to be enclosed by the res layer,NC,,
+(pwres.2.-),Min/Max width of pwell resistor,,2.650,µm
+(pwres.3.-),Min length of pwell resistor,,26.500,µm
+(pwres.4.-),Max length of pwell resistor,,265.00,µm
+(pwres.5.-),Min/Max spacing of tap inside the pwell resistor to nwell,,0.220,µm
+(pwres.6.-),Min/Max width of tap inside the pwell resistor,,0.530,µm
+(pwres.7a.-),Every pwres_terminal must enclose 12 licon1,,,
+(pwres.7b.-),Every pwres_terminal must enclose 12 mcons if routed through metal1,,,
+(pwres.8.-),Diff or poly is not allowed in the pwell resistor.,,,
+(pwres.9.-),Nwell surrounding the pwell resistor must have a full ring of contacted tap strapped with metal.,,,
+(pwres.10.-),The res layer must abut pwres_terminal on opposite and parallel edges,,,
+(pwres.11.-),The res layer must abut nwell on opposite and parallel edges not checked in Rule pwres.10,,,
diff --git a/docs/rules/periphery/p057-rfdiode_dotdash_dotdash.csv b/docs/rules/periphery/p057-rfdiode_dotdash_dotdash.csv
index f45b91f..ebf7e97 100644
--- a/docs/rules/periphery/p057-rfdiode_dotdash_dotdash.csv
+++ b/docs/rules/periphery/p057-rfdiode_dotdash_dotdash.csv
@@ -1,8 +1,8 @@
-Name,Description,Flags,Value
-(rfdiode.1.-),Only 90 degrees allowed for :drc_tag:`areaid.re`,,
-(rfdiode.2.-),:drc_tag:`areaid.re` must be coincident with nwell for the rf nwell diode,,
+Name,Description,Flags,Value,Unit
+(rfdiode.1.-),Only 90 degrees allowed for :drc_tag:`areaid.re`,,,
+(rfdiode.2.-),:drc_tag:`areaid.re` must be coincident with nwell for the rf nwell diode,,,
 (rfdiode.3.-),":drc_tag:`areaid.re` must be coincident with innwer edge of the nwell ring for the rf pwell-deep nwell diode
 Allowed PNP layout
 Layout: pnppar
 Allowed NPN layout
-Layout: npnpar1x1",,
+Layout: npnpar1x1",,,
diff --git a/docs/rules/periphery/periphery-split-csv.py b/docs/rules/periphery/periphery-split-csv.py
index b1a2274..9e632d4 100755
--- a/docs/rules/periphery/periphery-split-csv.py
+++ b/docs/rules/periphery/periphery-split-csv.py
@@ -55,7 +55,7 @@
     description: str = ''
     flags: Tuple[RuleFlags] = field(default_factory=tuple)
     value: str = ''
-
+    unit: str = ''
 
 @dataclass
 class RuleTable:
@@ -219,7 +219,7 @@
         rt.enabled = False
 
     for r in rows:
-        assert len(r) == 4, r
+        assert len(r) == 5, r
 
         if r[0] == 'Use' and r[1] == 'Explanation':
             break
@@ -233,6 +233,7 @@
             r[3] = ''
         rc.flags = tuple(flags)
         rc.value = r[3]
+        rc.unit  = r[4].strip()
         rt.rules.append(rc)
 
     if rule_tables:
@@ -288,14 +289,14 @@
 
 """.format(textwrap.indent(rt.notes, prefix='    ')))
 
-    headers = ('Name', 'Description', 'Flags', 'Value')
-    headers_fmt = (':drc_rule:`Name`', 'Description', ':drc_flag:`Flags`', 'Value')
+    headers = ('Name', 'Description', 'Flags', 'Value', 'Unit')
+    headers_fmt = (':drc_rule:`Name`', 'Description', ':drc_flag:`Flags`', 'Value', 'Unit')
 
     rst.write("""\
 .. list-table:: {rt.description}
    :header-rows: 1
    :stub-columns: 1
-   :widths: 10 75 5 10
+   :widths: 9 73 6 6 6
 
    * - {h}
 """.format(rt=rt,h='\n     - '.join(headers_fmt)))
@@ -308,19 +309,20 @@
         elif '\\n' in r.description: # multi line description
             r.description = '\n'.join( [ '| '+l for l in r.description.split('\\n') ] )
         else:
-            r.description = r.description.lstrip(' -') # one item bullet list to text           
+            r.description = r.description.lstrip(' -') # one item bullet list to text
         d = textwrap.indent(r.description, prefix='       ').strip()
         rst.write("""\
    * - :drc_rule:`{r.name}`
      - {d}
      - {f}
      - {r.value}
+     - {r.unit}
 """.format(r=r, d=d, f=f))
 
     rst.write('\n\n')
 
     with open(rt.csv_fname, 'w', newline='', encoding='utf8') as f:
-        w = csv.DictWriter(f, headers)
+        w = csv.DictWriter(f, headers, lineterminator='\n')
         w.writeheader()
         for r in rt.rules:
             d = {f: getattr(r, f.lower()) for f in headers}
diff --git a/docs/rules/periphery/periphery.csv b/docs/rules/periphery/periphery.csv
index d210225..32234f1 100644
--- a/docs/rules/periphery/periphery.csv
+++ b/docs/rules/periphery/periphery.csv
@@ -5,74 +5,74 @@
 , ,,
 (x.-),General,,
 ,,,
-1a,"p1m.md (OPC), DECA and AMKOR layers (pi1.dg, pmm.dg, rdl.dg, pi2.dg, ubm.dg, bump.dg) and mask data for p1m, met1, via, met2 must be on a grid of [mm]",,0.001
-1b,Data for SKY130 layout and mask on all layers except those mentioned in 1a must be on a grid of [mm] (except inside Seal ring),,0.005
-2,Angles permitted on: diff,,N/A
- ,"Angles permitted on: diff except for:\n- diff inside ""advSeal_6um* OR cuPillarAdvSeal_6um*"" pcell, \n- diff rings around the die at min total L>1000 um and W=0.3 um",,n x 90
- ,"Angles permitted on: tap (except inside :drc_tag:`areaid.en`), poly (except for ESD flare gates or gated_npn), li1(periphery), licon1, capm, mcon, via, via2. Anchors are exempted.",,n x 90
- ,Angles permitted on: via3 and via4. Anchors are exempted.,,n x 90
-2a,Analog circuits identified by :drc_tag:`areaid.analog` to use rectangular diff and tap geometries only; that are not to be merged into more complex shapes (T's or L's) ,,
-2c,"45 degree angles allowed on diff, tap inside UHVI",,
+1a,"p1m.md (OPC), DECA and AMKOR layers (pi1.dg, pmm.dg, rdl.dg, pi2.dg, ubm.dg, bump.dg) and mask data for p1m, met1, via, met2 must be on a grid of mm",,0.001,mm
+1b,Data for SKY130 layout and mask on all layers except those mentioned in 1a must be on a grid of mm (except inside Seal ring),,0.005,mm
+2,Angles permitted on: diff,,N/A,N/A
+ ,"Angles permitted on: diff except for:\n- diff inside ""advSeal_6µm* OR cuPillarAdvSeal_6µm*"" pcell, \n- diff rings around the die at min total L>1000 µm and W=0.3 µm",,n x 90,deg
+ ,"Angles permitted on: tap (except inside :drc_tag:`areaid.en`), poly (except for ESD flare gates or gated_npn), li1(periphery), licon1, capm, mcon, via, via2. Anchors are exempted.",,n x 90,deg
+ ,Angles permitted on: via3 and via4. Anchors are exempted.,,n x 90,deg
+2a,Analog circuits identified by :drc_tag:`areaid.analog` to use rectangular diff and tap geometries only; that are not to be merged into more complex shapes (T's or L's),,,
+2c,"45 degree angles allowed on diff, tap inside UHVI",,,
 ,,,
-3,Angles permitted on all other layers and in the seal ring for all the layers,,
-3a,"Angles permitted on all other layers except WLCSP layers (pmm, rdl, pmm2, ubm and bump)",,n x 45
-4,Electrical DR cover layout guidelines for electromigration,NC,
-5,"All ""pin""polygons must be within the ""drawing"" polygons of the layer",Al,
-6,All intra-layer separation checks will include a notch check,,
-7,Mask layer line and space checks must be done on all layers (checked with s.x rules),NC,
-8,"Use of areaid ""core"" layer (""coreid"") must be approved by technology",NC,
-9,"Shapes on maskAdd or maskDrop layers (""serifs"") are allowed in core only. Exempted are: \n- cfom md/mp inside ""advSeal_6um* OR cuPillarAdvSeal_6um*"" pcell \n- diff rings around the die at min total L>1000 um and W=0.3 um, and PMM/PDMM inside areaid:sl",,
- ,"Shapes on maskAdd or maskDrop layers (""serifs"") are allowed in core only. PMM/PDMM inside areaid:sl are excluded.",,N/A
-10,"Res purpose layer for (diff, poly) cannot overlap licon1",,
-11,Metal fuses are drawn in met2,LVS,N/A
- ,Metal fuses are drawn in met3,LVS,N/A
- ,Metal fuses are drawn in met4,LVS,
-\n12a\n12b\n12c,"To comply with the minimum spacing requirement for layer X in the frame:\n- Spacing of :drc_tag:`areaid.mt` to any non-ID layer\n- Enclosure of any non-ID layer by :drc_tag:`areaid.mt`\n- Rules exempted for cells with name ""*_buildspace""",F,
-12d,- Spacing of :drc_tag:`areaid.mt` to huge_metX (Exempt met3.dg),F,N/A
-12d,- Spacing of :drc_tag:`areaid.mt` to huge_metX (Exempt met5.dg),F,
-12e,- Enclosure of huge_metX by :drc_tag:`areaid.mt` (Exempt met3.dg),F,N/A
-12e,- Enclosure of huge_metX by :drc_tag:`areaid.mt` (Exempt met5.dg),F,
-13,Spacing between features located across areaid:ce is checked by …,,
-14,Width of features straddling areaid:ce is checked by …,,
-15a,"Drawn compatible, mask, and waffle-drop layers are allowed only inside areaid:mt (i.e., etest modules), or inside areaid:sl (i.e., between the outer and inner areaid:sl edges, but not in the die) or inside areaid:ft (i.e., frame, blankings). Exception: FOM/P1M/Metal waffle drop are allowed inside the die",P,
-15b,"Rule X.15a exempted for cpmm.dg inside cellnames ""PadPLfp"", ""padPLhp"", ""padPLstg"" and ""padPLwlbi"" (for the SKY130di-5r-gsmc flow)",Exempt,
-16,"Die must not overlap :drc_tag:`areaid.mt` (rule waived for test chips and exempted for cellnames ""*tech_CD_*"", ""*_techCD_*"", ""lazX_*"" or ""lazY_*"" )",,
-17,"All labels must be within the ""drawing"" polygons of the layer; This check is enabled by using switch ""floating_labels""; Identifies floating labels which appear as warnings in LVS. Using this check would enable cleaner LVS run; Not a gate for tapeout",,
-18,"Use redundant mcon, via, via2, via3 and via4 (Locations where additional vias/contacts can be added to existing single vias/contacts will be identified by this rule).\nSingle via under :drc_tag:`areaid.core` and :drc_tag:`areaid.standarc` are excluded from the single via check",RR,
-19,"Lower left corner of the seal ring should be at origin i.e (0,0)",,
-20,"Min spacing between pins on the same layer (center to center); Check enabled by switch ""IP_block""",,
-21,prunde.dg is allowed only inside :drc_tag:`areaid.mt` or :drc_tag:`areaid.sc`,,
-22,"No floating interconnects (poly, li1, met1-met5) or capm allowed; Rule flags interconnects with no path to poly, difftap or metal pins. Exempt floating layers can be excluded using poly_float, li1_float, m1_float, m2_float, m3_float, m4_float and m5_float text labels. Also flags an error if these text labels are placed on connected layers (not floating) and if the labels are not over the appropriate metal layer.  \nIf floating interconnects need to be connected at a higher level (Parent IP or Full chip), such floating interconnects can be exempted using poly_tie, li1_tie, m1_tie, m2_tie, m3_tie, m4_tie and m5_tie text labels.\nIt is the responsibility of the IP owner and chip/product owner to communicate and agree to the node each of these texted lines is connected to, if there is any risk to how a line is tied, and to what node.\nOnly metals outside :drc_tag:`areaid.stdcell` are checked.\n",RC,
+3,Angles permitted on all other layers and in the seal ring for all the layers,,,
+3a,"Angles permitted on all other layers except WLCSP layers (pmm, rdl, pmm2, ubm and bump)",,n x 45,deg
+4,Electrical DR cover layout guidelines for electromigration,NC,,
+5,"All ""pin""polygons must be within the ""drawing"" polygons of the layer",Al,,
+6,All intra-layer separation checks will include a notch check,,,
+7,Mask layer line and space checks must be done on all layers (checked with s.x rules),NC,,
+8,"Use of areaid ""core"" layer (""coreid"") must be approved by technology",NC,,
+9,"Shapes on maskAdd or maskDrop layers (""serifs"") are allowed in core only. Exempted are: \n- cfom md/mp inside ""advSeal_6um* OR cuPillarAdvSeal_6um*"" pcell \n- diff rings around the die at min total L>1000 um and W=0.3 um, and PMM/PDMM inside areaid:sl",,,
+ ,"Shapes on maskAdd or maskDrop layers (""serifs"") are allowed in core only. PMM/PDMM inside areaid:sl are excluded.",,N/A,N/A
+10,"Res purpose layer for (diff, poly) cannot overlap licon1",,,
+11,Metal fuses are drawn in met2,LVS,N/A,N/A
+ ,Metal fuses are drawn in met3,LVS,N/A,N/A
+ ,Metal fuses are drawn in met4,LVS,,
+\n12a\n12b\n12c,"To comply with the minimum spacing requirement for layer X in the frame:\n- Spacing of :drc_tag:`areaid.mt` to any non-ID layer\n- Enclosure of any non-ID layer by :drc_tag:`areaid.mt`\n- Rules exempted for cells with name ""*_buildspace""",F,,
+12d,- Spacing of :drc_tag:`areaid.mt` to huge_metX (Exempt met3.dg),F,N/A,N/A
+12d,- Spacing of :drc_tag:`areaid.mt` to huge_metX (Exempt met5.dg),F,,
+12e,- Enclosure of huge_metX by :drc_tag:`areaid.mt` (Exempt met3.dg),F,N/A,N/A
+12e,- Enclosure of huge_metX by :drc_tag:`areaid.mt` (Exempt met5.dg),F,,
+13,Spacing between features located across areaid:ce is checked by …,,,
+14,Width of features straddling areaid:ce is checked by …,,,
+15a,"Drawn compatible, mask, and waffle-drop layers are allowed only inside areaid:mt (i.e., etest modules), or inside areaid:sl (i.e., between the outer and inner areaid:sl edges, but not in the die) or inside areaid:ft (i.e., frame, blankings). Exception: FOM/P1M/Metal waffle drop are allowed inside the die",P,,
+15b,"Rule X.15a exempted for cpmm.dg inside cellnames ""PadPLfp"", ""padPLhp"", ""padPLstg"" and ""padPLwlbi"" (for the SKY130di-5r-gsmc flow)",Exempt,,
+16,"Die must not overlap :drc_tag:`areaid.mt` (rule waived for test chips and exempted for cellnames ""*tech_CD_*"", ""*_techCD_*"", ""lazX_*"" or ""lazY_*"" )",,,
+17,"All labels must be within the ""drawing"" polygons of the layer; This check is enabled by using switch ""floating_labels""; Identifies floating labels which appear as warnings in LVS. Using this check would enable cleaner LVS run; Not a gate for tapeout",,,
+18,"Use redundant mcon, via, via2, via3 and via4 (Locations where additional vias/contacts can be added to existing single vias/contacts will be identified by this rule).\nSingle via under :drc_tag:`areaid.core` and :drc_tag:`areaid.standarc` are excluded from the single via check",RR,,
+19,"Lower left corner of the seal ring should be at origin i.e (0,0)",,,
+20,"Min spacing between pins on the same layer (center to center); Check enabled by switch ""IP_block""",,,
+21,prunde.dg is allowed only inside :drc_tag:`areaid.mt` or :drc_tag:`areaid.sc`,,,
+22,"No floating interconnects (poly, li1, met1-met5) or capm allowed; Rule flags interconnects with no path to poly, difftap or metal pins. Exempt floating layers can be excluded using poly_float, li1_float, m1_float, m2_float, m3_float, m4_float and m5_float text labels. Also flags an error if these text labels are placed on connected layers (not floating) and if the labels are not over the appropriate metal layer.  \nIf floating interconnects need to be connected at a higher level (Parent IP or Full chip), such floating interconnects can be exempted using poly_tie, li1_tie, m1_tie, m2_tie, m3_tie, m4_tie and m5_tie text labels.\nIt is the responsibility of the IP owner and chip/product owner to communicate and agree to the node each of these texted lines is connected to, if there is any risk to how a line is tied, and to what node.\nOnly metals outside :drc_tag:`areaid.stdcell` are checked.\n",RC,,
 ,"The following are exempt from x.22 violations: _techCD_ , inductor.dg, modulecut, capacitors and s8blerf",,
 ,The 'notPublicCell' switch will deactivate this rule,,
-23a,:drc_tag:`areaid.sl` must not overlap diff,,N/A
-23b,diff cannot straddle :drc_tag:`areaid.sl`,,
-23c,":drc_tag:`areaid.sl` must not overlap tap, poly, li1 and metX",,
-23d,":drc_tag:`areaid.sl` must not overlap tap, poly",,N/A
-23e,"areaid:sl must not overlap li1 and metX for pcell ""advSeal_6um""",,N/A
-23f,"areaid:SubstrateCut (:drc_tag:`areaid.st`, local_sub) must not straddle p+ tap",RR,
-24,condiode label must be in iso_pwell,,
-25,"pnp.dg must be only within cell name ""s8rf_pnp"", ""s8rf_pnp5x"" or ""s8tesd_iref_pnp"", ""stk14ecx_*""",,
-26,"""advSeal_6um"" pcell must overlap diff",,
-27,"If the sealring is present, then partnum is required.  To exempt the requirement, place text.dg saying ""partnum_not_necessary"".\n""partnum*block"" pcell should be used instead of ""partnum*"" pcells",RR,N/A
-28,Min width of :drc_tag:`areaid.sl`,,N/A
-29,nfet must be enclosed by dnwell. Rule is checked when switch nfet_in_dnwell is turned on.,,
- ,,,
-Use,Explanation,,
-P,Rule applies to periphery only (outside :drc_tag:`areaid.ce`). A corresponding core rule may or may not exist.,,
-NE,Rule not checked for esd_nwell_tap. There are no corresponding rule for esd_nwell_tap.,,
-NC,Rule not checked by DRC. It should be used as a guideline only.,,
-TC,"Rule not checked for cell name ""*_tech_CD_top*""",,
-A,Rule documents a functionality implemented in CL algorithms and may not be checked by DRC.,,
-AD,Rule documents a functionality implemented in CL algorithms and checked by DRC.,,
-DE,Rule not checked for source of Drain Extended device,,
-LVS,Rule handled by LVS,,
-F,"Rule intended for Frame only,  not checked inside Die",,
-DNF,Drawn Not equal Final. The drawn rule does not reflect the final dimension on silicon. See table J for details.,,
-RC,"Recommended rule at the chip level, required rule at the IP level.",,
-RR,Recommended rule at any IP level,,
-Al  Cu,Rules applicable only to Al or Cu BE flows,,
-IR,IR drop check compering Al database and slotted Cu database for the same product (2 gds files) must be clean,Cu,
+23a,:drc_tag:`areaid.sl` must not overlap diff,,N/A,N/A
+23b,diff cannot straddle :drc_tag:`areaid.sl`,,,
+23c,":drc_tag:`areaid.sl` must not overlap tap, poly, li1 and metX",,,
+23d,":drc_tag:`areaid.sl` must not overlap tap, poly",,N/A,N/A
+23e,"areaid:sl must not overlap li1 and metX for pcell ""advSeal_6um""",,N/A,N/A
+23f,"areaid:SubstrateCut (:drc_tag:`areaid.st`, local_sub) must not straddle p+ tap",RR,,
+24,condiode label must be in iso_pwell,,,
+25,"pnp.dg must be only within cell name ""s8rf_pnp"", ""s8rf_pnp5x"" or ""s8tesd_iref_pnp"", ""stk14ecx_*""",,,
+26,"""advSeal_6um"" pcell must overlap diff",,,
+27,"If the sealring is present, then partnum is required.  To exempt the requirement, place text.dg saying ""partnum_not_necessary"".\n""partnum*block"" pcell should be used instead of ""partnum*"" pcells",RR,N/A,N/A
+28,Min width of :drc_tag:`areaid.sl`,,N/A,N/A
+29,nfet must be enclosed by dnwell. Rule is checked when switch nfet_in_dnwell is turned on.,,,
+ ,,,,
+Use,Explanation,,,
+P,Rule applies to periphery only (outside :drc_tag:`areaid.ce`). A corresponding core rule may or may not exist.,,,
+NE,Rule not checked for esd_nwell_tap. There are no corresponding rule for esd_nwell_tap.,,,
+NC,Rule not checked by DRC. It should be used as a guideline only.,,,
+TC,"Rule not checked for cell name ""*_tech_CD_top*""",,,
+A,Rule documents a functionality implemented in CL algorithms and may not be checked by DRC.,,,
+AD,Rule documents a functionality implemented in CL algorithms and checked by DRC.,,,
+DE,Rule not checked for source of Drain Extended device,,,
+LVS,Rule handled by LVS,,,
+F,"Rule intended for Frame only,  not checked inside Die",,,
+DNF,Drawn Not equal Final. The drawn rule does not reflect the final dimension on silicon. See table J for details.,,,
+RC,"Recommended rule at the chip level, required rule at the IP level.",,,
+RR,Recommended rule at any IP level,,,
+Al  Cu,Rules applicable only to Al or Cu BE flows,,,
+IR,IR drop check compering Al database and slotted Cu database for the same product (2 gds files) must be clean,Cu,,
 ,,,
 ,,,
 Note: some rules contain correction factors to compensate possible mask defect and unpredicted process biases,,,
@@ -80,16 +80,16 @@
 (dnwell.-),Deep Nwell,,sky130
 ,Function: Define deep nwell for isolating pwell and noise immunity,,
 ,,,
-2,Min width of deep nwell,,3.000
-3,Min spacing between deep nwells. Rule exempt inside UHVI.,,6.300
-3a,Min spacing between deep nwells on same net inside UHVI.,,N/A
-3b,Min spacing between deep-nwells inside UHVI and deep-nwell outside UHVI,,N/A
-3c,Min spacing between deep-nwells inside UHVI and nwell outsideUHVI,,N/A
-3d,Min spacing between deep-nwells inside UHVI on different nets,,N/A
-4,Dnwell can not overlap pnp:dg,,
-5,P+_diff can not straddle Dnwell ,,
-6,RF NMOS must be enclosed by deep nwell (RF FETs are listed in $DESIGN/config/tech/model_set/calibre/fixed_layout_model_map of corresponding techs),,
-7,Dnwell can not straddle areaid:substratecut,,
+2,Min width of deep nwell,,3.000,µm
+3,Min spacing between deep nwells. Rule exempt inside UHVI.,,6.300,µm
+3a,Min spacing between deep nwells on same net inside UHVI.,,N/A,N/A
+3b,Min spacing between deep-nwells inside UHVI and deep-nwell outside UHVI,,N/A,N/A
+3c,Min spacing between deep-nwells inside UHVI and nwell outsideUHVI,,N/A,N/A
+3d,Min spacing between deep-nwells inside UHVI on different nets,,N/A,N/A
+4,Dnwell can not overlap pnp:dg,,,
+5,P+_diff can not straddle Dnwell,,,
+6,RF NMOS must be enclosed by deep nwell (RF FETs are listed in $DESIGN/config/tech/model_set/calibre/fixed_layout_model_map of corresponding techs),,,
+7,Dnwell can not straddle areaid:substratecut,,,
 ,,,
 ,,,
 ,,,
@@ -117,16 +117,16 @@
 (nwell.-),Nwell,,sky130
 ,Function: Define nwell implant regions,,
 ,,,
-1,Width of nwell,,0.840
-2a,Spacing between two n-wells,,1.270
-2b,Manual merge wells if less than minimum,,
-4,All n-wells will contain metal-contacted tap  (rule checks only for licon on tap) . Rule exempted from high voltage cells inside UHVI,,
-5,Deep nwell must be enclosed by nwell by atleast... Exempted inside UHVI or :drc_tag:`areaid.lw`,TC,0.400
+1,Width of nwell,,0.840,µm
+2a,Spacing between two n-wells,,1.270,µm
+2b,Manual merge wells if less than minimum,,,
+4,All n-wells will contain metal-contacted tap  (rule checks only for licon on tap) . Rule exempted from high voltage cells inside UHVI,,,
+5,Deep nwell must be enclosed by nwell by atleast... Exempted inside UHVI or :drc_tag:`areaid.lw`,TC,0.400,µm
 ,Nwells can merge over deep nwell if spacing too small (as in rule nwell.2),,
-5a,min enclosure of nwell by dnwell inside UHVI,,N/A
-5b,nwell inside UHVI must not be on the same net as nwell outside UHVI,,N/A
-6,Min enclosure of nwell hole by deep nwell outside UHVI,TC,1.030
-7,Min spacing between nwell and deep nwell on separate nets,TC,4.500
+5a,min enclosure of nwell by dnwell inside UHVI,,N/A,N/A
+5b,nwell inside UHVI must not be on the same net as nwell outside UHVI,,N/A,N/A
+6,Min enclosure of nwell hole by deep nwell outside UHVI,TC,1.030,µm
+7,Min spacing between nwell and deep nwell on separate nets,TC,4.500,µm
 ,"Spacing between nwell and deep nwell on the same net is set by the sum of the rules nwell.2 and nwell.5. By default, DRC run on a cell checks for the separate-net spacing, when nwell and deep nwell nets are separate within the cell hierarchy and are joined in the upper hierarchy. To allow net names to be joined and make the same-net rule applicable in this case, the ""joinNets"" switch should be turned on.",,
 ,,,
 ,,,
@@ -155,11 +155,11 @@
 (pwbm.-),Pwbm,,sky130
 ,Function: Define p-well block,,
 ,,,
-1,Min width of pwbm.dg,,N/A
-2,Min spacing between two pwbm.dg inside UHVI,,N/A
-3,Min enclosure of dnwell:dg by pwbm.dg inside UHVI (exempt pwbm hole inside dnwell),,N/A
-4,dnwell inside UHVI must be enclosed by pwbm (exempt pwbm hole inside dnwell),,N/A
-5,Min Space between two pwbm holes inside UHVI,,N/A
+1,Min width of pwbm.dg,,N/A,N/A
+2,Min spacing between two pwbm.dg inside UHVI,,N/A,N/A
+3,Min enclosure of dnwell:dg by pwbm.dg inside UHVI (exempt pwbm hole inside dnwell),,N/A,N/A
+4,dnwell inside UHVI must be enclosed by pwbm (exempt pwbm hole inside dnwell),,N/A,N/A
+5,Min Space between two pwbm holes inside UHVI,,N/A,N/A
 ,,,
 ,,,
 ,,,
@@ -177,12 +177,12 @@
 (pwdem.-),Pwdem,,sky130
 ,,,
 ,,,
-1,Min width of pwdem.dg,,N/A
-2,Min spacing between two pwdem.dg inside UHVI on same net,,N/A
-3,Min enclosure of pwdem:dg by pwbm.dg inside UHVI,,N/A
-4,pwdem.dg must be enclosed by UHVI,,N/A
-5,pwdem.dg inside UHVI must be enclosed by deep nwell,,N/A
-6,Min enclosure of pwdem:dg by deep nwell inside UHVI,,N/A
+1,Min width of pwdem.dg,,N/A,N/A
+2,Min spacing between two pwdem.dg inside UHVI on same net,,N/A,N/A
+3,Min enclosure of pwdem:dg by pwbm.dg inside UHVI,,N/A,N/A
+4,pwdem.dg must be enclosed by UHVI,,N/A,N/A
+5,pwdem.dg inside UHVI must be enclosed by deep nwell,,N/A,N/A
+6,Min enclosure of pwdem:dg by deep nwell inside UHVI,,N/A,N/A
 ,,,
 ,,,
 ,,,
@@ -205,12 +205,12 @@
 (hvtp.-),Hvtp,,sky130
 ,Function: Define Vt adjust implant region for high Vt LV PMOS; ,,
 ,,,
-1,Min width of hvtp,,0.380
-2,Min spacing between hvtp to hvtp,,0.380
-3,Min enclosure of pfet by hvtp,P,0.180
-4,Min spacing between pfet and hvtp,P,0.180
-5,Min area of hvtp (um^2),,0.265
-6,Min area of hvtp Holes (um^2),,0.265
+1,Min width of hvtp,,0.380,µm
+2,Min spacing between hvtp to hvtp,,0.380,µm
+3,Min enclosure of pfet by hvtp,P,0.180,µm
+4,Min spacing between pfet and hvtp,P,0.180,µm
+5,Min area of hvtp ,,0.265,µm²
+6,Min area of hvtp Holes ,,0.265,µm²
 ,,,
 ,,,
 ,,,
@@ -238,24 +238,24 @@
 (hvtr.-),Hvtr,,sky130
 ,Function: Define low VT adjust implant region for pmedlvtrf; ,,
 ,,,
-1,Min width of hvtr,,0.380
-2,Min spacing between hvtp to hvtr,,0.380
-3,Min enclosure of pfet by hvtr,P,0.180
+1,Min width of hvtr,,0.380,µm
+2,Min spacing between hvtp to hvtr,,0.380,µm
+3,Min enclosure of pfet by hvtr,P,0.180,µm
 ,,,
 ,,,
 (lvtn.-),Lvtnm,,sky130
 ,"Function: Define regions to block Vt adjust implant for low Vt LV PMOS/NMOS, SONOS FETs and Native NMOS",,
 ,,,
-1a,Min width of lvtn,,0.380
-2,Min space lvtn to lvtn,,0.380
-3a,Min spacing of lvtn to gate. Rule exempted inside UHVI.,P,0.180
-3b,Min spacing of lvtn to pfet along the S/D direction,P,0.235
-4b,Min enclosure of gate by lvtn. Rule exempted inside UHVI.,P,0.180
-9,"Min spacing, no overlap, between lvtn and hvtp",,0.380
-10,Min enclosure of lvtn by (nwell not overlapping Var_channel) (exclude coincident edges),,0.380
-12,Min spacing between lvtn and (nwell inside :drc_tag:`areaid.ce`),,0.380
-13,Min area of lvtn (um^2),,0.265
-14,Min area of lvtn Holes (um^2),,0.265
+1a,Min width of lvtn,,0.380,µm
+2,Min space lvtn to lvtn,,0.380,µm
+3a,Min spacing of lvtn to gate. Rule exempted inside UHVI.,P,0.180,µm
+3b,Min spacing of lvtn to pfet along the S/D direction,P,0.235,µm
+4b,Min enclosure of gate by lvtn. Rule exempted inside UHVI.,P,0.180,µm
+9,"Min spacing, no overlap, between lvtn and hvtp",,0.380,µm
+10,Min enclosure of lvtn by (nwell not overlapping Var_channel) (exclude coincident edges),,0.380,µm
+12,Min spacing between lvtn and (nwell inside :drc_tag:`areaid.ce`),,0.380,µm
+13,Min area of lvtn ,,0.265,µm²
+14,Min area of lvtn Holes ,,0.265,µm²
 ,,,
 ,,,
 ,,,
@@ -291,17 +291,17 @@
 (ncm.-),Ncm,,sky130
 ,Function: Define Vt adjust implant region for LV NMOS in the core of NVSRAM,,
 ,,,
-X.2,Ncm overlapping areaid:ce is checked for core rules only,,
-X.3,Ncm overlapping core cannot overlap N+diff in periphery,TC,
-1,Width of ncm,,0.380
-2a,Spacing of ncm to ncm,,0.380
-2b,Manual merge ncm if space is below minimum,,
-3,Min enclosure of P+diff by Ncm,P,0.180
-4,Min enclosure of P+diff within (areaid:ed AndNot areaid:de) by Ncm,P,0.180
-5,"Min space, no overlap, between ncm and (LVTN_gate) OR (diff containing lvtn)",P,0.230
-6,"Min space, no overlap, between ncm and nfet",P,0.200
-7,Min area of ncm (um^2),,0.265
-8,Min area of ncm Holes (um^2),,0.265
+X.2,Ncm overlapping areaid:ce is checked for core rules only,,,
+X.3,Ncm overlapping core cannot overlap N+diff in periphery,TC,,
+1,Width of ncm,,0.380,µm
+2a,Spacing of ncm to ncm,,0.380,µm
+2b,Manual merge ncm if space is below minimum,,,
+3,Min enclosure of P+diff by Ncm,P,0.180,µm
+4,Min enclosure of P+diff within (areaid:ed AndNot areaid:de) by Ncm,P,0.180,µm
+5,"Min space, no overlap, between ncm and (LVTN_gate) OR (diff containing lvtn)",P,0.230,µm
+6,"Min space, no overlap, between ncm and nfet",P,0.200,µm
+7,Min area of ncm ,,0.265,µm²
+8,Min area of ncm Holes ,,0.265,µm²
 ,,,
 ,,,
 ,,,
@@ -317,21 +317,21 @@
 (difftap.-),Diff/tap,,sky130
 ,Function: Defines active regions and contacts to substrate,,
 ,,,
-1,Width of diff or tap,P,0.150
-2,"Minimum channel width (Diff And Poly) except for FETs inside :drc_tag:`areaid.sc`: Rule exempted in the SP8* flows only, for the cells listed in rule difftap.2a ",P,0.420
-2a,"Minimum channel width (Diff And Poly) for cell names ""s8cell_ee_plus_sseln_a"", ""s8cell_ee_plus_sseln_b"", ""s8cell_ee_plus_sselp_a"", ""s8cell_ee_plus_sselp_b"" , ""s8fpls_pl8"", ""s8fpls_rdrv4"" , ""s8fpls_rdrv4f"" and ""s8fpls_rdrv8""",P,NA
-2b,Minimum channel width (Diff And Poly) for FETs inside :drc_tag:`areaid.sc`,P,0.360
-3,"Spacing of diff to diff, tap to tap, or non-abutting diff to tap",,0.270
-4,Min tap bound by one diffusion,,0.290
-5,Min tap bound by two diffusions,P,0.400
-6,Diff and tap are not allowed to extend beyond their abutting edge,,
-7,Spacing of diff/tap abutting edge to a non-conciding diff or tap edge,NE,0.130
-8,Enclosure of (p+) diffusion by N-well. Rule exempted inside UHVI.,"DE, NE, P",0.180
-9,Spacing of (n+) diffusion to N-well outside UHVI,"DE, NE, P",0.340
-10,Enclosure of (n+)  tap by N-well. Rule exempted inside UHVI.,"NE, P",0.180
-11,Spacing of (p+) tap to  N-well. Rule exempted inside UHVI.,,0.130
-12,ESD_nwell_tap is considered shorted to the abutting diff,NC,
-13,Diffusion or the RF FETS in Table H5 is defined by Ldiff and Wdiff.,,
+1,Width of diff or tap,P,0.150,µm
+2,"Minimum channel width (Diff And Poly) except for FETs inside :drc_tag:`areaid.sc`: Rule exempted in the SP8* flows only, for the cells listed in rule difftap.2a ",P,0.420,µm
+2a,"Minimum channel width (Diff And Poly) for cell names ""s8cell_ee_plus_sseln_a"", ""s8cell_ee_plus_sseln_b"", ""s8cell_ee_plus_sselp_a"", ""s8cell_ee_plus_sselp_b"" , ""s8fpls_pl8"", ""s8fpls_rdrv4"" , ""s8fpls_rdrv4f"" and ""s8fpls_rdrv8""",P,NA,µm
+2b,Minimum channel width (Diff And Poly) for FETs inside :drc_tag:`areaid.sc`,P,0.360,µm
+3,"Spacing of diff to diff, tap to tap, or non-abutting diff to tap",,0.270,µm
+4,Min tap bound by one diffusion,,0.290,
+5,Min tap bound by two diffusions,P,0.400,
+6,Diff and tap are not allowed to extend beyond their abutting edge,,,
+7,Spacing of diff/tap abutting edge to a non-conciding diff or tap edge,NE,0.130,µm
+8,Enclosure of (p+) diffusion by N-well. Rule exempted inside UHVI.,"DE, NE, P",0.180,µm
+9,Spacing of (n+) diffusion to N-well outside UHVI,"DE, NE, P",0.340,µm
+10,Enclosure of (n+)  tap by N-well. Rule exempted inside UHVI.,"NE, P",0.180,µm
+11,Spacing of (p+) tap to  N-well. Rule exempted inside UHVI.,,0.130,µm
+12,ESD_nwell_tap is considered shorted to the abutting diff,NC,,
+13,Diffusion or the RF FETS in Table H5 is defined by Ldiff and Wdiff.,,,
 ,,,
 ,,,
 ,,,
@@ -359,14 +359,14 @@
 (tunm.-),Tunnel,,sky130
 ,Function: Defines SONOS FETs ,,
 ,,,
-1,Min width of tunm,,0.410
-2,Min spacing of tunm to tunm,,0.500
-3,Extension of tunm beyond (poly and diff),,0.095
-4,Min spacing of tunm to (poly and diff) outside tunm,,0.095
-5,(poly and diff) may not straddle tunm,,
-6a,Tunm outside deep n-well is not allowed,TC,
-7,Min tunm area,,0.672
-8,tunm must be enclosed by :drc_tag:`areaid.ce`,,
+1,Min width of tunm,,0.410,µm
+2,Min spacing of tunm to tunm,,0.500,µm
+3,Extension of tunm beyond (poly and diff),,0.095,
+4,Min spacing of tunm to (poly and diff) outside tunm,,0.095,µm
+5,(poly and diff) may not straddle tunm,,,
+6a,Tunm outside deep n-well is not allowed,TC,,
+7,Min tunm area,,0.672,µm²
+8,tunm must be enclosed by :drc_tag:`areaid.ce`,,,
 ,,,
 ,,,
 ,,,
@@ -395,23 +395,23 @@
 (poly.-),Poly  ,,sky130
 ,"Function: Defines FET gates, interconnects and resistors",,
 ,,,
-X.1,All FETs would be checked for W/Ls as documented in spec 001-02735  (Exempt FETs that are pruned; exempt for W/L's inside :drc_tag:`areaid.sc` and inside cell name scs8*decap* and listed in the MRGA as a decap only W/L),,
-X.1a,Min & max dummy_poly L is equal to min L allowed for corresponding device type (exempt rule for dummy_poly in cells listed on Table H3),,
-1a,Width of poly,,0.150
-1b,Min channel length (poly width) for pfet overlapping lvtn (exempt rule for dummy_poly in cells listed on Table H3),,0.350
-2,Spacing of poly to poly except for poly.c2 and poly.c3; Exempt cell: sr_bltd_eq where it is same as poly.c2,,0.210
-3,Min poly resistor width,,0.330
-4,Spacing of poly on field to diff (parallel edges only),P,0.075
-5,Spacing of poly on field to tap,P,0.055
-6,Spacing of poly on diff to abutting tap (min source),P,0.300
-7,Extension of diff beyond poly (min drain),P,0.250
-8,Extension of poly beyond diffusion (endcap),P,0.130
-9,Poly resistor spacing to poly or spacing (no overlap) to diff/tap,,0.480
-10,Poly can't overlap inner corners of diff,,
-11,No 90 deg turns of poly on diff,,
-12,"(Poly NOT (nwell NOT hvi)) may not overlap tap; Rule exempted for cell name ""s8fgvr_n_fg2"" and gated_npn and inside UHVI.",P,
-15,Poly must not overlap diff:rs,,
-16,"Inside RF FETs defined in Table H5, poly cannot overlap poly across multiple adjacent instances",,
+X.1,All FETs would be checked for W/Ls as documented in spec 001-02735  (Exempt FETs that are pruned; exempt for W/L's inside :drc_tag:`areaid.sc` and inside cell name scs8*decap* and listed in the MRGA as a decap only W/L),,,
+X.1a,Min & max dummy_poly L is equal to min L allowed for corresponding device type (exempt rule for dummy_poly in cells listed on Table H3),,,
+1a,Width of poly,,0.150,µm
+1b,Min channel length (poly width) for pfet overlapping lvtn (exempt rule for dummy_poly in cells listed on Table H3),,0.350,µm
+2,Spacing of poly to poly except for poly.c2 and poly.c3; Exempt cell: sr_bltd_eq where it is same as poly.c2,,0.210,µm
+3,Min poly resistor width,,0.330,µm
+4,Spacing of poly on field to diff (parallel edges only),P,0.075,µm
+5,Spacing of poly on field to tap,P,0.055,µm
+6,Spacing of poly on diff to abutting tap (min source),P,0.300,µm
+7,Extension of diff beyond poly (min drain),P,0.250,
+8,Extension of poly beyond diffusion (endcap),P,0.130,
+9,Poly resistor spacing to poly or spacing (no overlap) to diff/tap,,0.480,µm
+10,Poly can't overlap inner corners of diff,,,
+11,No 90 deg turns of poly on diff,,,
+12,"(Poly NOT (nwell NOT hvi)) may not overlap tap; Rule exempted for cell name ""s8fgvr_n_fg2"" and gated_npn and inside UHVI.",P,,
+15,Poly must not overlap diff:rs,,,
+16,"Inside RF FETs defined in Table H5, poly cannot overlap poly across multiple adjacent instances",,,
 ,,,
 ,,,
 ,,,
@@ -447,27 +447,27 @@
 (rpm.-),P+ Poly resistor,,sky130
 ,Function: Defines p+ poly resistors,,
 ,,,
-1a,Min width of rpm,,1.270
-1b,Min/Max prec_resistor width xhrpoly_0p35,,0.350
-1c,Min/Max prec_resistor width xhrpoly_0p69,,0.690
-1d,Min/Max prec_resistor width xhrpoly_1p41,,1.410
-1e,Min/Max prec_resistor width xhrpoly_2p85,,2.850
-1f,Min/Max prec_resistor width xhrpoly_5p73,,5.730
-1g,Only 1 licon is allowed in xhrpoly_0p35 prec_resistor_terminal,,
-1h,Only 1 licon is allowed in xhrpoly_0p69 prec_resistor_terminal,,
-1i,Only 2 licons are allowed in xhrpoly_1p41 prec_resistor_terminal,,
-1j,Only 4 licons are allowed in xhrpoly_2p85 prec_resistor_terminal,,
-1k,Only 8 licons are allowed in xhrpoly_5p73 prec_resistor_terminal,,
-2,Min spacing of rpm to rpm,,0.840
-3,rpm must enclose prec_resistor by atleast,,0.200
-4,prec_resistor must be enclosed by psdm by atleast,,0.110
-5,prec_resistor must be enclosed by npc by atleast,,0.095
-6,"Min spacing, no overlap, of rpm and nsdm",,0.200
-7,Min spacing between rpm and poly,,0.200
-8,poly must not straddle rpm,,
-9,"Min space, no overlap, between prec_resistor and hvntm",,0.185
-10,Min spacing of rpm to pwbm,,N/A
-11,rpm should not overlap or straddle pwbm except cells\ns8usbpdv2_csa_top\ns8usbpdv2_20vconn_sw_300ma_ovp_ngate_unit\ns8usbpdv2_20vconn_sw_300ma_ovp\ns8usbpdv2_20sbu_sw_300ma_ovp,,N/A
+1a,Min width of rpm,,1.270,µm
+1b,Min/Max prec_resistor width xhrpoly_0p35,,0.350,µm
+1c,Min/Max prec_resistor width xhrpoly_0p69,,0.690,µm
+1d,Min/Max prec_resistor width xhrpoly_1p41,,1.410,µm
+1e,Min/Max prec_resistor width xhrpoly_2p85,,2.850,µm
+1f,Min/Max prec_resistor width xhrpoly_5p73,,5.730,µm
+1g,Only 1 licon is allowed in xhrpoly_0p35 prec_resistor_terminal,,,
+1h,Only 1 licon is allowed in xhrpoly_0p69 prec_resistor_terminal,,,
+1i,Only 2 licons are allowed in xhrpoly_1p41 prec_resistor_terminal,,,
+1j,Only 4 licons are allowed in xhrpoly_2p85 prec_resistor_terminal,,,
+1k,Only 8 licons are allowed in xhrpoly_5p73 prec_resistor_terminal,,,
+2,Min spacing of rpm to rpm,,0.840,µm
+3,rpm must enclose prec_resistor by atleast,,0.200,
+4,prec_resistor must be enclosed by psdm by atleast,,0.110,µm
+5,prec_resistor must be enclosed by npc by atleast,,0.095,µm
+6,"Min spacing, no overlap, of rpm and nsdm",,0.200,µm
+7,Min spacing between rpm and poly,,0.200,µm
+8,poly must not straddle rpm,,,
+9,"Min space, no overlap, between prec_resistor and hvntm",,0.185,µm
+10,Min spacing of rpm to pwbm,,N/A,N/A
+11,rpm should not overlap or straddle pwbm except cells\ns8usbpdv2_csa_top\ns8usbpdv2_20vconn_sw_300ma_ovp_ngate_unit\ns8usbpdv2_20vconn_sw_300ma_ovp\ns8usbpdv2_20sbu_sw_300ma_ovp,,N/A,N/A
 ,,,
 ,,,
 ,,,
@@ -494,14 +494,14 @@
 (varac.-),Varactor,,sky130
 ,Function: Defines varactors,,
 ,,,
-1,Min channel length (poly width) of Var_channel,,0.180
-2,Min channel width (tap width) of Var_channel,,1.000
-3,Min spacing between hvtp to Var_channel,,0.180
-4,Min spacing of licon on tap to Var_channel,,0.250
-5,Min enclosure of poly overlapping Var_channel by nwell,,0.150
-6,Min spacing between VaracTap and difftap,,0.270
-7,Nwell overlapping Var_channel must not overlap P+ diff,,
-8,Min enclosure of Var_channel by hvtp,,0.255
+1,Min channel length (poly width) of Var_channel,,0.180,µm
+2,Min channel width (tap width) of Var_channel,,1.000,µm
+3,Min spacing between hvtp to Var_channel,,0.180,µm
+4,Min spacing of licon on tap to Var_channel,,0.250,µm
+5,Min enclosure of poly overlapping Var_channel by nwell,,0.150,µm
+6,Min spacing between VaracTap and difftap,,0.270,µm
+7,Nwell overlapping Var_channel must not overlap P+ diff,,,
+8,Min enclosure of Var_channel by hvtp,,0.255,µm
 ,,,
 ,,,
 ,,,
@@ -528,17 +528,17 @@
 (photo.-),Photo diode,,sky130
 ,Function: Photo diode for sensing light,,
 ,,,
-1,Rules dnwell.3 and nwell.5 are exempted for photoDiode,,
-2,Min/Max width of photoDiode,,3.000
-3,Min spacing between photoDiode,,5.000
-4,Min spacing between photoDiode and deep nwell,,5.300
-5,photoDiode edges must be coincident with :drc_tag:`areaid.po`,,
-6,photoDiode must be enclosed by dnwell ring,,
-7,photoDiode must be enclosed by p+ tap ring,,
-8,Min/Max width of nwell inside photoDiode,,0.840
-9,Min/Max enclosure of nwell by photoDiode,,1.080
-10,Min/Max width of tap inside photoDiode,,0.410
-11,Min/Max enclosure of tap by nwell inside photoDiode,,0.215
+1,Rules dnwell.3 and nwell.5 are exempted for photoDiode,,,
+2,Min/Max width of photoDiode,,3.000,µm
+3,Min spacing between photoDiode,,5.000,µm
+4,Min spacing between photoDiode and deep nwell,,5.300,µm
+5,photoDiode edges must be coincident with :drc_tag:`areaid.po`,,,
+6,photoDiode must be enclosed by dnwell ring,,,
+7,photoDiode must be enclosed by p+ tap ring,,,
+8,Min/Max width of nwell inside photoDiode,,0.840,µm
+9,Min/Max enclosure of nwell by photoDiode,,1.080,µm
+10,Min/Max width of tap inside photoDiode,,0.410,µm
+11,Min/Max enclosure of tap by nwell inside photoDiode,,0.215,µm
 ,,,
 ,,,
 ,,,
@@ -567,11 +567,11 @@
 (npc.-),Nitride Poly Cut (NPC),,sky130
 ,Function: Defines nitride openings to contact poly and Li1,,
 ,,,
-1,Min width of NPC,,0.270
-2,Min spacing of NPC to NPC,,0.270
-3,Manual merge if less than minimum,,
-4,Spacing (no overlap) of NPC to Gate,,0.090
-5,Max enclosure of poly overlapping slotted_licon by npcm (merge between adjacent short edges of the slotted_licons if space < min),,0.095
+1,Min width of NPC,,0.270,µm
+2,Min spacing of NPC to NPC,,0.270,µm
+3,Manual merge if less than minimum,,,
+4,Spacing (no overlap) of NPC to Gate,,0.090,µm
+5,Max enclosure of poly overlapping slotted_licon by npcm (merge between adjacent short edges of the slotted_licons if space < min),,0.095,µm
 ,,,
 ,,,
 ,,,
@@ -594,18 +594,18 @@
 (n/ psd.-),N+/P+ Source/Drain Implants (Nsdm and Psdm),,sky130
 ,Function: Defines opening for N+/P+ implants,,
 ,,,
-1,Width of nsdm(psdm),P,0.380
-2,Spacing of nsdm(psdm) to nsdm(psdm),P,0.380
-3,Manual merge if less than minimum,,
-5a,"Enclosure of diff by nsdm(psdm), except for butting edge",,0.125
-5b,"Enclosure of tap by nsdm(psdm), except for butting edge",P,0.125
-6,Enclosure of diff/tap butting edge by nsdm (psdm) ,,0.000
-7,Spacing of NSDM/PSDM to opposite implant diff or tap (for non-abutting diff/tap edges),,0.130
-8,Nsdm and psdm cannot overlap diff/tap regions of opposite doping,DE,
-9,"Diff and tap must be enclosed by their corresponding implant layers. Rule exempted for\n- diff inside ""advSeal_6um* OR cuPillarAdvSeal_6um*"" pcell for SKY130P*/SP8P*/SKY130DI-5R-CSMC flows\n- diff rings around the die at min total L>1000 um and W=0.3 um\n- gated_npn \n- :drc_tag:`areaid.zer`.",DE,
-10a,Min area of Nsdm (um^2),,0.265
-10b,Min area of Psdm (um^2),,0.255
-11,Min area of n/psdmHoles (um^2),,0.265
+1,Width of nsdm(psdm),P,0.380,µm
+2,Spacing of nsdm(psdm) to nsdm(psdm),P,0.380,µm
+3,Manual merge if less than minimum,,,
+5a,"Enclosure of diff by nsdm(psdm), except for butting edge",,0.125,µm
+5b,"Enclosure of tap by nsdm(psdm), except for butting edge",P,0.125,µm
+6,Enclosure of diff/tap butting edge by nsdm (psdm),,0.000,µm
+7,Spacing of NSDM/PSDM to opposite implant diff or tap (for non-abutting diff/tap edges),,0.130,µm
+8,Nsdm and psdm cannot overlap diff/tap regions of opposite doping,DE,,
+9,"Diff and tap must be enclosed by their corresponding implant layers. Rule exempted for\n- diff inside ""advSeal_6um* OR cuPillarAdvSeal_6um*"" pcell for SKY130P*/SP8P*/SKY130DI-5R-CSMC flows\n- diff rings around the die at min total L>1000 um and W=0.3 um\n- gated_npn \n- :drc_tag:`areaid.zer`.",DE,,
+10a,Min area of Nsdm ,,0.265,µm²
+10b,Min area of Psdm ,,0.255,µm²
+11,Min area of n/psdmHoles ,,0.265,µm²
 ,,,
 ,,,
 ,,,
@@ -621,37 +621,37 @@
 (licon.-),Local Interconnect Contact (Licon),,sky130
 ,Function: Defines contacts between poly/diff/tap and Li1,,
 , ,,
-1,Min and max L and W of licon (exempt licons inside prec_resistor),,0.170
-1b,Min and max width of licon inside prec_resistor,,0.190
-1c,Min and max length of licon inside prec_resistor,,2.000
-2,Spacing of licon to licon,P,0.170
-2b,Min spacing between two slotted_licon (when the both the edges are 0.19um in length),,0.350
-2c,Min spacing between two slotted_licon (except for rule licon.2b),,0.510
-2d,Min spacing between a slotted_licon and 0.17um square licon,,0.510
-3,Only min. square licons are allowed except die seal ring where licons are (licon CD)*L ,,0.170 *L
-4,Licon1 must overlap li1 and (poly or diff or tap),,
-5a,Enclosure of licon by diff,P,0.040
-5b,Min space between tap_licon and diff-abutting tap edge,P,0.060
-5c,Enclosure of licon by diff on one of two adjacent sides,P,0.060
-6,Licon cannot straddle tap,P,
-7,Enclosure of licon by one of two adjacent edges of isolated tap,P,0.120
-8,Enclosure of poly_licon by poly,P,0.050
-8a,Enclosure of poly_licon by poly on one of two adjacent sides,P,0.080
-9,"Spacing, no overlap, between poly_licon and psdm; In SKY130DIA/SKY130TMA/SKY130PIR-10 flows, the rule is checked only between (poly_licon outside rpm) and psdm",P,0.110
-10,Spacing of licon on (tap AND (nwell NOT hvi)) to Var_channel,P,0.250
-11,"Spacing of licon on diff or tap to poly on diff (except for all FETs inside :drc_tag:`areaid.sc` and except s8spf-10r flow for 0.5um phv inside cell names ""s8fs_gwdlvx4"", ""s8fs_gwdlvx8"", ""s8fs_hvrsw_x4"", ""s8fs_hvrsw8"", ""s8fs_hvrsw264"", and ""s8fs_hvrsw520"" and for 0.15um nshort inside cell names ""s8fs_rdecdrv"", ""s8fs_rdec8"", ""s8fs_rdec32"", ""s8fs_rdec264"", ""s8fs_rdec520"")",P,0.055
-11a,Spacing of licon on diff or tap to poly on diff (for all FETs inside :drc_tag:`areaid.sc` except 0.15um phighvt),P,0.050
-11b,Spacing of licon on diff or tap to poly on diff (for 0.15um phighvt inside :drc_tag:`areaid.sc`),P,0.050
-11c,"Spacing of licon on diff or tap to poly on diff (for 0.5um phv inside cell names ""s8fs_gwdlvx4"", ""s8fs_gwdlvx8"", ""s8fs_hvrsw_x4"", ""s8fs_hvrsw8"", ""s8fs_hvrsw264"", and ""s8fs_hvrsw520"")",P,0.040
-11d,"Spacing of licon on diff or tap to poly on diff (for 0.15um nshort inside cell names ""s8fs_rdecdrv"", ""s8fs_rdec8"", ""s8fs_rdec32"", ""s8fs_rdec264"", ""s8fs_rdec520"")",P,0.045
-12,Max SD width without licon,NC,5.700
-13,Spacing (no overlap) of NPC to licon on diff or tap,P,0.090
-14,Spacing of poly_licon to diff or tap,P,0.190
-15,poly_licon must be enclosed by npc by…,P,0.100
-16,"Every source_diff and every tap must enclose at least one licon1, including the diff/tap straddling areaid:ce. \nRule exempted inside UHVI.",P,
-17,Licons may not overlap both poly and (diff or tap),,
-18,Npc must enclose poly_licon,,
-19,poly of the HV varactor must not interact with licon,P,
+1,Min and max L and W of licon (exempt licons inside prec_resistor),,0.170,µm
+1b,Min and max width of licon inside prec_resistor,,0.190,µm
+1c,Min and max length of licon inside prec_resistor,,2.000,µm
+2,Spacing of licon to licon,P,0.170,µm
+2b,Min spacing between two slotted_licon (when the both the edges are 0.19um in length),,0.350,µm
+2c,Min spacing between two slotted_licon (except for rule licon.2b),,0.510,µm
+2d,Min spacing between a slotted_licon and 0.17um square licon,,0.510,µm
+3,Only min. square licons are allowed except die seal ring where licons are (licon CD)*L,,0.170 *L,
+4,Licon1 must overlap li1 and (poly or diff or tap),,,
+5a,Enclosure of licon by diff,P,0.040,µm
+5b,Min space between tap_licon and diff-abutting tap edge,P,0.060,µm
+5c,Enclosure of licon by diff on one of two adjacent sides,P,0.060,µm
+6,Licon cannot straddle tap,P,,
+7,Enclosure of licon by one of two adjacent edges of isolated tap,P,0.120,µm
+8,Enclosure of poly_licon by poly,P,0.050,µm
+8a,Enclosure of poly_licon by poly on one of two adjacent sides,P,0.080,µm
+9,"Spacing, no overlap, between poly_licon and psdm; In SKY130DIA/SKY130TMA/SKY130PIR-10 flows, the rule is checked only between (poly_licon outside rpm) and psdm",P,0.110,µm
+10,Spacing of licon on (tap AND (nwell NOT hvi)) to Var_channel,P,0.250,µm
+11,"Spacing of licon on diff or tap to poly on diff (except for all FETs inside :drc_tag:`areaid.sc` and except s8spf-10r flow for 0.5um phv inside cell names ""s8fs_gwdlvx4"", ""s8fs_gwdlvx8"", ""s8fs_hvrsw_x4"", ""s8fs_hvrsw8"", ""s8fs_hvrsw264"", and ""s8fs_hvrsw520"" and for 0.15um nshort inside cell names ""s8fs_rdecdrv"", ""s8fs_rdec8"", ""s8fs_rdec32"", ""s8fs_rdec264"", ""s8fs_rdec520"")",P,0.055,µm
+11a,Spacing of licon on diff or tap to poly on diff (for all FETs inside :drc_tag:`areaid.sc` except 0.15um phighvt),P,0.050,µm
+11b,Spacing of licon on diff or tap to poly on diff (for 0.15um phighvt inside :drc_tag:`areaid.sc`),P,0.050,µm
+11c,"Spacing of licon on diff or tap to poly on diff (for 0.5um phv inside cell names ""s8fs_gwdlvx4"", ""s8fs_gwdlvx8"", ""s8fs_hvrsw_x4"", ""s8fs_hvrsw8"", ""s8fs_hvrsw264"", and ""s8fs_hvrsw520"")",P,0.040,µm
+11d,"Spacing of licon on diff or tap to poly on diff (for 0.15um nshort inside cell names ""s8fs_rdecdrv"", ""s8fs_rdec8"", ""s8fs_rdec32"", ""s8fs_rdec264"", ""s8fs_rdec520"")",P,0.045,µm
+12,Max SD width without licon,NC,5.700,µm
+13,Spacing (no overlap) of NPC to licon on diff or tap,P,0.090,µm
+14,Spacing of poly_licon to diff or tap,P,0.190,µm
+15,poly_licon must be enclosed by npc by…,P,0.100,µm
+16,"Every source_diff and every tap must enclose at least one licon1, including the diff/tap straddling areaid:ce. \nRule exempted inside UHVI.",P,,
+17,Licons may not overlap both poly and (diff or tap),,,
+18,Npc must enclose poly_licon,,,
+19,poly of the HV varactor must not interact with licon,P,,
 ,,,
 ,,,
 ,,,
@@ -699,14 +699,14 @@
 (li.-.-),Local Interconnect (LI),,sky130
 ,Function: Defines local interconnect to diff/tap and poly,,
 ,,,
-1,Width of LI (except for li.1a),P,0.170
-1a,Width of LI inside of cells with name s8rf2_xcmvpp_hd5_*,P,0.140
-2,Max ratio of length to width of LI without licon or mcon,NC,10.000
-3,Spacing of LI to LI (except for li.3a),P,0.170
-3a,Spacing of LI to LI inside cells with names s8rf2_xcmvpp_hd5_*,P,0.140
-5,Enclosure of licon by one of two adjacent LI sides,P,0.080
-6,Min area of LI,P,0.0561
-7,"Min LI resistor width (rule exempted within :drc_tag:`areaid.ed`; Inside :drc_tag:`areaid.ed`, min width of the li resistor is determined by rule li.1)",,0.290
+1,Width of LI (except for li.1a),P,0.170,µm
+1a,Width of LI inside of cells with name s8rf2_xcmvpp_hd5_*,P,0.140,µm
+2,Max ratio of length to width of LI without licon or mcon,NC,10.000,µm
+3,Spacing of LI to LI (except for li.3a),P,0.170,µm
+3a,Spacing of LI to LI inside cells with names s8rf2_xcmvpp_hd5_*,P,0.140,µm
+5,Enclosure of licon by one of two adjacent LI sides,P,0.080,µm
+6,Min area of LI,P,0.0561,µm²
+7,"Min LI resistor width (rule exempted within :drc_tag:`areaid.ed`; Inside :drc_tag:`areaid.ed`, min width of the li resistor is determined by rule li.1)",,0.290,µm
 ,,,
 ,,,
 ,,,
@@ -722,13 +722,13 @@
 (ct.-),Metal contact (Mcon),,sky130
 ,Function: Defines contact between Li1 and met1,,
 ,,,
-1,Min and max L and W of mcon,DNF,0.170
-2,Spacing of mcon to mcon,DNF,0.190
-3,Only min. square mcons are allowed except die seal ring where mcons are…,,0.170*L
-4,Mcon must be enclosed by LI by at least …,P,0.000
-irdrop.1,"For 1 <= n <= 10 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.2
-irdrop.2,"For 11 <= n <= 100 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.3
-irdrop.3,"For n > 100 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.7
+1,Min and max L and W of mcon,DNF,0.170,µm
+2,Spacing of mcon to mcon,DNF,0.190,µm
+3,Only min. square mcons are allowed except die seal ring where mcons are…,,0.170*L,
+4,Mcon must be enclosed by LI by at least …,P,0.000,µm
+irdrop.1,"For 1 <= n <= 10 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.2,µm
+irdrop.2,"For 11 <= n <= 100 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.3,µm
+irdrop.3,"For n > 100 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.7,µm
 ,,,
 ,,,
 ,,,
@@ -742,18 +742,18 @@
 (capm.-),MIM Capacitor (Capm),,sky130
 ,Function: Defines MIM capacitor,,
 ,,,
-1,Min width of capm,,N/A
-2a,Min spacing of capm to capm,,N/A
-2b,Minimum spacing of capacitor bottom_plate to bottom plate,,N/A
-3,Minimum enclosure of capm (top_plate) by met2,,N/A
-4,Min enclosure of via2 by capm,,N/A
-5,Min spacing between capm and via2,,N/A
-6,Maximum Aspect Ratio (Length/Width) ,,N/A
-7,Only rectangular capacitors are allowed,,N/A
-8,"Min space, no overlap, between via and capm",,N/A
-10,"capm must not straddle nwell, diff, tap, poly, li1 and met1 (Rule exempted for capm overlapping capm_2t.dg)",TC,N/A
-11,Min spacing between capm to (met2 not overlapping capm),,N/A
-12,Max area of capm (um^2),,N/A
+1,Min width of capm,,N/A,N/A
+2a,Min spacing of capm to capm,,N/A,N/A
+2b,Minimum spacing of capacitor bottom_plate to bottom plate,,N/A,N/A
+3,Minimum enclosure of capm (top_plate) by met2,,N/A,N/A
+4,Min enclosure of via2 by capm,,N/A,N/A
+5,Min spacing between capm and via2,,N/A,N/A
+6,Maximum Aspect Ratio (Length/Width),,N/A,N/A
+7,Only rectangular capacitors are allowed,,N/A,N/A
+8,"Min space, no overlap, between via and capm",,N/A,N/A
+10,"capm must not straddle nwell, diff, tap, poly, li1 and met1 (Rule exempted for capm overlapping capm_2t.dg)",TC,N/A,N/A
+11,Min spacing between capm to (met2 not overlapping capm),,N/A,N/A
+12,Max area of capm (um^2),,N/A,N/A
 ,,,
 ,,,
 ,,,
@@ -781,24 +781,24 @@
 (vpp.-),VPP Capacitor ,,sky130
 ,Function: Defines VPP capacitor,,
 ,,,
-1,Min width of capacitor:dg,,1.430
-1b,Max width of capacitor:dg; Rule not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5 and vpp_with_noLi,,11.350
-1c,"Min/Max width of cell name ""s8rf_xcmvpp1p8x1p8_m3shield """,,3.880
-3,"capacitor:dg must not overlap (tap or diff or poly); (one exception: Poly is allowed to overlap  vpp_with_Met3Shield and vpp_with_Met5PolyShield); (not applicable for vpp_over_Moscap or ""s8rf2_xcmvppx4_2xnhvnative10x4"" or vpp_with_LiShield)",,
-4,capacitor:dg must not straddle (nwell or dnwell),,
-5,Min spacing between (capacitor:dg edge and (poly or li1 or met1 or met2)) to (poly or li1 or met1 or met2) on separate nets (Exempt area of the error shape less than 2.25 (um^2) and run length less than 2.0um); Rule not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5 and vpp_with_noLi,,1.500
-5a,Max pattern density of met3.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5),,0.25
-5b,Max pattern density of met4.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_Met5 and vpp_over_MOSCAP),,0.3
-5c,"Max pattern density of met5.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_Met5 and vpp_over_MOSCAP and vpp_with_noLi); (one exception: rules does apply to cell ""s8rf2_xcmvpp11p5x11p7_m1m4"" and ""s8rf2_xcmvpp_hd5_atlas*"")",,0.4
-8,Min enclosure of capacitor:dg by nwell,,1.500
-9,Min spacing of capacitor:dg to nwell (not applicable for vpp_over_MOSCAP),,1.500
-10,vpp capacitors must not overlap; Rule checks for capacitor.dg overlapping more than one pwell pin,,
-11,Min pattern density of (poly and diff) over capacitor.dg; (vpp_over_Moscap only),,0.87
-12a,"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp8p6x7p9_m3_lim5shield""  must overlap with size 2.01 x 2.01 (no other met4 shapes allowed)",,9.00
-12b,"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp11p5x11p7_m3_lim5shield""  must overlap with size 2.01 x 2.01 (no other met4 shapes allowed)",,16.00
-12c,"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp4p4x4p6_m3_lim5shield""  must overlap with size 1.5 x 1.5 (no other met4 shapes allowed)",,4.00
-13,Min space of met1 to met1inside VPP capacitor,Cu,0.160
-14,Min space of met2 to met2 inside VPP capacitor,Cu,0.160
+1,Min width of capacitor:dg,,1.430,µm
+1b,Max width of capacitor:dg; Rule not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5 and vpp_with_noLi,,11.350,µm
+1c,"Min/Max width of cell name ""s8rf_xcmvpp1p8x1p8_m3shield """,,3.880,µm
+3,"capacitor:dg must not overlap (tap or diff or poly); (one exception: Poly is allowed to overlap  vpp_with_Met3Shield and vpp_with_Met5PolyShield); (not applicable for vpp_over_Moscap or ""s8rf2_xcmvppx4_2xnhvnative10x4"" or vpp_with_LiShield)",,,
+4,capacitor:dg must not straddle (nwell or dnwell),,,
+5,Min spacing between (capacitor:dg edge and (poly or li1 or met1 or met2)) to (poly or li1 or met1 or met2) on separate nets (Exempt area of the error shape less than 2.25 µm² and run length less than 2.0um); Rule not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5 and vpp_with_noLi,,1.500,µm
+5a,Max pattern density of met3.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5),,0.25,\-
+5b,Max pattern density of met4.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_Met5 and vpp_over_MOSCAP),,0.3,\-
+5c,"Max pattern density of met5.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_Met5 and vpp_over_MOSCAP and vpp_with_noLi); (one exception: rules does apply to cell ""s8rf2_xcmvpp11p5x11p7_m1m4"" and ""s8rf2_xcmvpp_hd5_atlas*"")",,0.4,\-
+8,Min enclosure of capacitor:dg by nwell,,1.500,µm
+9,Min spacing of capacitor:dg to nwell (not applicable for vpp_over_MOSCAP),,1.500,µm
+10,vpp capacitors must not overlap; Rule checks for capacitor.dg overlapping more than one pwell pin,,,
+11,Min pattern density of (poly and diff) over capacitor.dg; (vpp_over_Moscap only),,0.87,\-
+12a,"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp8p6x7p9_m3_lim5shield""  must overlap with size 2.01 x 2.01 (no other met4 shapes allowed)",,9.00,µm
+12b,"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp11p5x11p7_m3_lim5shield""  must overlap with size 2.01 x 2.01 (no other met4 shapes allowed)",,16.00,µm
+12c,"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp4p4x4p6_m3_lim5shield""  must overlap with size 1.5 x 1.5 (no other met4 shapes allowed)",,4.00,µm
+13,Min space of met1 to met1inside VPP capacitor,Cu,0.160,µm
+14,Min space of met2 to met2 inside VPP capacitor,Cu,0.160,µm
 ,,,
 ,,,
 ,,,
@@ -825,25 +825,25 @@
 (m1.-),Met1,,sky130
 ,"Function: Defines first level of metal interconnects, buses etc;",,
 ,,,
-.X.1,"Algorithm should flag errors, for met1, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm1 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. NOTE: Required for IP, Recommended for Chip-level.",RC,
-1,Width of metal1,,0.140
-2,Spacing of metal1 to metal1,,0.140
-3a,Min. spacing of features attached to or extending from huge_met1 for a distance of up to  0.280 um to metal1 (rule not checked over non-huge met1 features),,0.280
-3b,Min. spacing of huge_met1 to metal1 excluding features checked by m1.3a,,0.280
-4,Mcon must be enclosed by Met1 by at least …(Rule exempted for cell names documented in rule m1.4a),P,0.030
-4a,"Mcon must be enclosed by Met1 by at least (for cell names ""s8cell_ee_plus_sseln_a"", ""s8cell_ee_plus_sseln_b"", ""s8cell_ee_plus_sselp_a"", ""s8cell_ee_plus_sselp_b"", ""s8fpls_pl8"", and ""s8fs_cmux4_fm"")",P,0.005
-5,Mcon must be enclosed by Met1 on one of two adjacent sides by at least …,"P, Al",0.060
-6,Min metal 1 area [um2],,0.083
-7,Min area of metal1 holes [um2],,0.140
-pd.1,Min MM1_oxide_Pattern_density,"RR, Al",0.7
-pd.2a,Rule m1.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,"A, Al",700
-pd.2b,Rule m1.pd.1 has to be checked by dividing the chip into steps of …,"A, Al",70
-11,Max width of metal1after slotting,"Cu, NC",4.000
-12,Add slots and remove vias and contacts if met1 wider than…..,Cu,3.200
-13,Max pattern density (PD) of met1,Cu,0.77
-14,Met1 PD window size ,Cu,50.000
-14a,Met1 PD window step,Cu,25.000
-15,Mcon must be enclosed by met1 on one of two adjacent sides by at least …,Cu,0.030
+.X.1,"Algorithm should flag errors, for met1, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm1 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. NOTE: Required for IP, Recommended for Chip-level.",RC,,
+1,Width of metal1,,0.140,µm
+2,Spacing of metal1 to metal1,,0.140,µm
+3a,Min. spacing of features attached to or extending from huge_met1 for a distance of up to  0.280 µm to metal1 (rule not checked over non-huge met1 features),,0.280,µm
+3b,Min. spacing of huge_met1 to metal1 excluding features checked by m1.3a,,0.280,µm
+4,Mcon must be enclosed by Met1 by at least …(Rule exempted for cell names documented in rule m1.4a),P,0.030,µm
+4a,"Mcon must be enclosed by Met1 by at least (for cell names ""s8cell_ee_plus_sseln_a"", ""s8cell_ee_plus_sseln_b"", ""s8cell_ee_plus_sselp_a"", ""s8cell_ee_plus_sselp_b"", ""s8fpls_pl8"", and ""s8fs_cmux4_fm"")",P,0.005,µm
+5,Mcon must be enclosed by Met1 on one of two adjacent sides by at least …,"P, Al",0.060,µm
+6,Min metal 1 area ,,0.083,µm²
+7,Min area of metal1 holes ,,0.140,µm²
+pd.1,Min MM1_oxide_Pattern_density,"RR, Al",0.7,\-
+pd.2a,Rule m1.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,"A, Al",700,µm
+pd.2b,Rule m1.pd.1 has to be checked by dividing the chip into steps of …,"A, Al",70,
+11,Max width of metal1after slotting,"Cu, NC",4.000,µm
+12,Add slots and remove vias and contacts if met1 wider than…..,Cu,3.200,
+13,Max pattern density (PD) of met1,Cu,0.77,\-
+14,Met1 PD window size,Cu,50.000,µm
+14a,Met1 PD window step,Cu,25.000,µm
+15,Mcon must be enclosed by met1 on one of two adjacent sides by at least …,Cu,0.030,µm
 ,,,
 ,,,
 ,,,
@@ -873,25 +873,25 @@
 (via.-),Via,,sky130
 ,Function: Defines contact between met1  and met2,,
 ,,,
-1a,Min and max L and W of via outside :drc_tag:`areaid.mt`,Al,0.150
-1b,"Three sizes of square Vias allowed inside areaid:mt: 0.150um, 0.230um and 0.280um",Al,
-2,Spacing of via to via,Al,0.170
-3,Only min. square vias are allowed except die seal ring where vias are (Via CD)*L,,0.2*L
-4a,0.150 um Via must be enclosed by Met1 by at least …,,0.055
-4b,"Inside :drc_tag:`areaid.mt`, 0.230 um Via must be enclosed by met1 by atleast",Al,0.030
-4c,"Inside :drc_tag:`areaid.mt`, 0.280 um Via must be enclosed by met1 by atleast",Al,0.000
-5a,0.150 um Via must be enclosed by Met1 on one of two adjacent sides by at least …,,0.085
-5b,"Inside :drc_tag:`areaid.mt`, 0.230 um Via must be enclosed by met1 on one of two adjacent sides by at least …",Al,0.060
-5c,"Inside :drc_tag:`areaid.mt`, 0.280 um Via must be enclosed by met1 on one of two adjacent sides by at least …",Al,0.000
-11,Min and max L and W of via outside :drc_tag:`areaid.mt`,Cu,0.180
-12,Min spacing between vias,Cu,0.130
-13,Max of 5 vias within …,Cu,0.350
-14,0.180 um Via must be enclosed by parallel edges of Met1 by at least …,Cu,0.040
-irdrop.1,"For 1 <= n <= 2 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.0
-irdrop.2,"For 3 <= n <= 15 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.6
-irdrop.3,"For 16 <= n <= 30 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.8
-irdrop.4,"For n > 30 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.9
-14a,0.180 um Via must be enclosed by 45 deg edges of Met1 by at least …,Cu,0.037
+1a,Min and max L and W of via outside :drc_tag:`areaid.mt`,Al,0.150,µm
+1b,"Three sizes of square Vias allowed inside areaid:mt: 0.150um, 0.230um and 0.280um",Al,,
+2,Spacing of via to via,Al,0.170,µm
+3,Only min. square vias are allowed except die seal ring where vias are (Via CD)*L,,0.2*L,
+4a,0.150 µm Via must be enclosed by Met1 by at least …,,0.055,µm
+4b,"Inside :drc_tag:`areaid.mt`, 0.230 µm Via must be enclosed by met1 by atleast",Al,0.030,µm
+4c,"Inside :drc_tag:`areaid.mt`, 0.280 µm Via must be enclosed by met1 by atleast",Al,0.000,µm
+5a,0.150 µm Via must be enclosed by Met1 on one of two adjacent sides by at least …,,0.085,µm
+5b,"Inside :drc_tag:`areaid.mt`, 0.230 µm Via must be enclosed by met1 on one of two adjacent sides by at least …",Al,0.060,µm
+5c,"Inside :drc_tag:`areaid.mt`, 0.280 µm Via must be enclosed by met1 on one of two adjacent sides by at least …",Al,0.000,µm
+11,Min and max L and W of via outside :drc_tag:`areaid.mt`,Cu,0.180,µm
+12,Min spacing between vias,Cu,0.130,µm
+13,Max of 5 vias within …,Cu,0.350,µm
+14,0.180 µm Via must be enclosed by parallel edges of Met1 by at least …,Cu,0.040,µm
+irdrop.1,"For 1 <= n <= 2 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.0,µm
+irdrop.2,"For 3 <= n <= 15 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.6,µm
+irdrop.3,"For 16 <= n <= 30 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.8,µm
+irdrop.4,"For n > 30 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.9,µm
+14a,0.180 µm Via must be enclosed by 45 deg edges of Met1 by at least …,Cu,0.037,deg µm
 ,,,
 ,,,
 ,,,
@@ -909,25 +909,25 @@
 (m2.-),Metal 2,,sky130
 ,"Function: Defines second level of metal interconnects, buses etc",,
 ,,,
-.X.1,"Algorithm should flag errors, for met2, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm2 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. Required for IP, Recommended for Chip-level.",RC,
-1,Width of metal 2,,0.140
-2,Spacing of metal 2 to metal 2,,0.140
-3a,Min. spacing of features attached to or extending from huge_met2 for a distance of up to  0.280 um to metal2 (rule not checked over non-huge met2 features),,0.280
-3b,Min. spacing of huge_met2 to metal2 excluding features checked by m2.3a,,0.280
-3c,"Min spacing between floating_met2 with AR_met2_A >= 0.05 and AR_met2_B =< 0.032, outside areaid:sc must be greater than",RR,0.145
-4,Via must be enclosed by Met2 by at least … ,"P, Al",0.055
-5,Via must be enclosed by Met2 on one of two adjacent sides by at least …,Al,0.085
-6,Min metal2 area [um2],,0.0676
-7,Min area of metal2 holes [um2],,0.140
-pd.1,Min MM2_oxide_Pattern_density,RR,0.7
-pd.2a,Rule m2.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700
-pd.2b,Rule m2.pd.1 has to be checked by dividing the chip into steps of …,A,70
-11,Max width of metal2,Cu,4.000
-12,Add slots and remove vias and contacts if met2 wider than…..,Cu,3.200
-13,Max pattern density (PD) of metal2,Cu,0.77
-14,Met2 PD window size ,Cu,50.000
-14a,Met2 PD window step,Cu,25.000
-15,Via must be enclosed by met2 by at least…,Cu,0.040
+.X.1,"Algorithm should flag errors, for met2, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm2 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. Required for IP, Recommended for Chip-level.",RC,,
+1,Width of metal 2,,0.140,µm
+2,Spacing of metal 2 to metal 2,,0.140,µm
+3a,Min. spacing of features attached to or extending from huge_met2 for a distance of up to  0.280 µm to metal2 (rule not checked over non-huge met2 features),,0.280,µm
+3b,Min. spacing of huge_met2 to metal2 excluding features checked by m2.3a,,0.280,µm
+3c,"Min spacing between floating_met2 with AR_met2_A >= 0.05 and AR_met2_B =< 0.032, outside areaid:sc must be greater than",RR,0.145,µm
+4,Via must be enclosed by Met2 by at least …,"P, Al",0.055,µm
+5,Via must be enclosed by Met2 on one of two adjacent sides by at least …,Al,0.085,µm
+6,Min metal2 area ,,0.0676,µm²
+7,Min area of metal2 holes ,,0.140,µm²
+pd.1,Min MM2_oxide_Pattern_density,RR,0.7,\-
+pd.2a,Rule m2.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700,µm
+pd.2b,Rule m2.pd.1 has to be checked by dividing the chip into steps of …,A,70,
+11,Max width of metal2,Cu,4.000,µm
+12,Add slots and remove vias and contacts if met2 wider than…..,Cu,3.200,
+13,Max pattern density (PD) of metal2,Cu,0.77,\-
+14,Met2 PD window size,Cu,50.000,µm
+14a,Met2 PD window step,Cu,25.000,µm
+15,Via must be enclosed by met2 by at least…,Cu,0.040,µm
 ,,,
 ,,,
 ,,,
@@ -953,26 +953,26 @@
 (via2.-),Via2,,sky130
 ,Function: Via2 connects met2 to met3 in the SKY130T*/SKY130P*/SP8Q/SP8P* flows and met2/capm to met3 in the SKY130DI* flow.,,
 ,,,
-X.1,Via2 connects met2 to met3 in the SKY130T*/SKY130P*/SP8Q/SP8P* flow and met2/capm to met3 in the SKY130DI* flow. ,,
-1a,Min and max L and W of via2 (except for rule via2.1b/1c/1d/1e/1f),Al,0.200
-1b,"Three sizes of square Vias allowed inside areaid:mt: 0.280um, 1.2 um and 1.5 um",Al,N/A
-1c,Two sizes of square Vias allowed inside areaid:mt: 1.2 um and 1.5 um,Al,N/A
-1d,"Four sizes of square Vias allowed inside areaid:mt: 0.2um, 0.280um, 1.2 um and 1.5 um",Al,
-1e,"Three sizes of square Vias allowed inside areaid:mt: 0.8um, 1.2 um and 1.5 um",Al,N/A
-1f,Two sizes of square Vias allowed outside areaid:mt: 0.8um and 1.2 um,Al,N/A
-2,Spacing of via2 to via2,Al,0.200
-3,Only min. square via2s are allowed except die seal ring where via2s are (Via2 CD)*L,Al,0.2*L
-4,Via2 must be enclosed by Met2 by at least …,Al,0.040
-4a,"Inside :drc_tag:`areaid.mt`, 1.5 um Via2 must be enclosed by met2 by atleast",,0.140
-5,Via2 must be enclosed by Met2 on one of two adjacent sides by at least …,Al,0.085
-11,Min and max L and W of via2,Cu,0.210
-12,Min spacing between via2's,Cu,0.180
-13,Min spacing between via2 rows,Cu,0.200
-14,Via2 must be enclosed by met2 by atleast,Cu,0.035
-irdrop.1,"For 1 <= n <= 2 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.0
-irdrop.2,"For 3 <= n <= 4 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.6
-irdrop.3,"For 5 <= n <= 30 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.79
-irdrop.4,"For n > 30 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.9
+X.1,Via2 connects met2 to met3 in the SKY130T*/SKY130P*/SP8Q/SP8P* flow and met2/capm to met3 in the SKY130DI* flow.,,,
+1a,Min and max L and W of via2 (except for rule via2.1b/1c/1d/1e/1f),Al,0.200,µm
+1b,"Three sizes of square Vias allowed inside areaid:mt: 0.280um, 1.2 um and 1.5 um",Al,N/A,N/A
+1c,Two sizes of square Vias allowed inside areaid:mt: 1.2 um and 1.5 um,Al,N/A,N/A
+1d,"Four sizes of square Vias allowed inside areaid:mt: 0.2um, 0.280um, 1.2 um and 1.5 um",Al,,
+1e,"Three sizes of square Vias allowed inside areaid:mt: 0.8um, 1.2 um and 1.5 um",Al,N/A,N/A
+1f,Two sizes of square Vias allowed outside areaid:mt: 0.8um and 1.2 um,Al,N/A,N/A
+2,Spacing of via2 to via2,Al,0.200,µm
+3,Only min. square via2s are allowed except die seal ring where via2s are (Via2 CD)*L,Al,0.2*L,
+4,Via2 must be enclosed by Met2 by at least …,Al,0.040,µm
+4a,"Inside :drc_tag:`areaid.mt`, 1.5 µm Via2 must be enclosed by met2 by atleast",,0.140,µm
+5,Via2 must be enclosed by Met2 on one of two adjacent sides by at least …,Al,0.085,µm
+11,Min and max L and W of via2,Cu,0.210,µm
+12,Min spacing between via2's,Cu,0.180,µm
+13,Min spacing between via2 rows,Cu,0.200,µm
+14,Via2 must be enclosed by met2 by atleast,Cu,0.035,µm
+irdrop.1,"For 1 <= n <= 2 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.0,µm
+irdrop.2,"For 3 <= n <= 4 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.6,µm
+irdrop.3,"For 5 <= n <= 30 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.79,µm
+irdrop.4,"For n > 30 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.9,µm
 ,,,
 ,,,
 ,,,
@@ -990,27 +990,27 @@
 (m3.-),Metal 3,,sky130
 ,"Function: Defines third level of metal interconnects, buses etc",,
 ,,,
-.X.1,"Algorithm should flag errors, for met3, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm3 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. NOTE: Required for IP, Recommended for Chip-level.",RC,
-1,Width of metal 3,,0.300
-2,Spacing of metal 3 to metal 3,,0.300
-3a,Min. spacing of features attached to or extending from huge_met3 for a distance of up to 0.480 um to metal3  (rule not checked over non-huge met3 features),,N/A
-3b,Min. spacing of huge_met3 to metal3 excluding features checked by m3.3a,,N/A
-3c,Min. spacing of features attached to or extending from huge_met3 for a distance of up to 0.400 um to metal3  (rule not checked over non-huge met3 features),,0.400
-3d,Min. spacing of huge_met3 to metal3 excluding features checked by m3.3a,,0.400
-4,Via2 must be enclosed by Met3 by at least …,Al,0.065
-5,Via2 must be enclosed by Met3 on one of two adjacent sides by at least …,,N/A
-5a,Via2 must be enclosed by Met3 on all sides by at least …(Rule not checked on a layout when it satisfies both rules m3.4 and m3.5),,N/A
-6,Min area of metal3 ,,0.240
-7,Min area of metal3 holes [um2],Cu,0.200
-pd.1,Min MM3_oxide_Pattern_density,RR,0.7
-pd.2a,Rule m3.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700
-pd.2b,Rule m3.pd.1 has to be checked by dividing the chip into steps of …,A,70
-11,Max width of metal3,Cu,4.000
-12,Add slots and remove vias and contacts if wider than…..,Cu,3.200
-13,Max pattern density (PD) of metal3,Cu,0.77
-14,Met3 PD window size ,Cu,50.000
-14a,Met3 PD window step,Cu,25.000
-15,Via2 must be enclosed by met3 by at least…,Cu,0.060
+.X.1,"Algorithm should flag errors, for met3, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm3 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. NOTE: Required for IP, Recommended for Chip-level.",RC,,
+1,Width of metal 3,,0.300,µm
+2,Spacing of metal 3 to metal 3,,0.300,µm
+3a,Min. spacing of features attached to or extending from huge_met3 for a distance of up to 0.480 um to metal3  (rule not checked over non-huge met3 features),,N/A,N/A
+3b,Min. spacing of huge_met3 to metal3 excluding features checked by m3.3a,,N/A,N/A
+3c,Min. spacing of features attached to or extending from huge_met3 for a distance of up to 0.400 µm to metal3  (rule not checked over non-huge met3 features),,0.400,µm
+3d,Min. spacing of huge_met3 to metal3 excluding features checked by m3.3a,,0.400,µm
+4,Via2 must be enclosed by Met3 by at least …,Al,0.065,µm
+5,Via2 must be enclosed by Met3 on one of two adjacent sides by at least …,,N/A,N/A
+5a,Via2 must be enclosed by Met3 on all sides by at least …(Rule not checked on a layout when it satisfies both rules m3.4 and m3.5),,N/A,N/A
+6,Min area of metal3,,0.240,µm²
+7,Min area of metal3 holes ,Cu,0.200,µm²
+pd.1,Min MM3_oxide_Pattern_density,RR,0.7,\-
+pd.2a,Rule m3.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700,µm
+pd.2b,Rule m3.pd.1 has to be checked by dividing the chip into steps of …,A,70,
+11,Max width of metal3,Cu,4.000,µm
+12,Add slots and remove vias and contacts if wider than…..,Cu,3.200,
+13,Max pattern density (PD) of metal3,Cu,0.77,\-
+14,Met3 PD window size,Cu,50.000,µm
+14a,Met3 PD window step,Cu,25.000,µm
+15,Via2 must be enclosed by met3 by at least…,Cu,0.060,µm
 ,,,
 ,,,
 ,,,
@@ -1032,36 +1032,36 @@
 (via3.-),Via3,,sky130
 ,Function: Via3 connects met3 to met4 in the SKY130Q*/SKY130P*/SP8Q/SP8P* flow ,,
 ,,,
-1,Min and max L and W of via3 (except for rule via3.1a),Al,0.200
-1a,Two sizes of square via3 allowed inside :drc_tag:`areaid.mt`: 0.200um and 0.800um,Al,
-2,Spacing of via3 to via3,Al,0.200
-3,Only min. square via3s are allowed except die seal ring where via3s are (Via3 CD)*L,,0.2*L
-4,Via3 must be enclosed by Met3 by at least …,Al,0.060
-5,Via3 must be enclosed by Met3 on one of two adjacent sides by at least …,Al,0.090
-11,Min and max L and W of via3,Cu,0.210
-12,Min spacing between via2's,Cu,0.180
-13,Via3 must be enclosed by Met3 by at least …,Cu,0.055
-14,Min spacing between via3 rows,Cu,0.350
-irdrop.1,"For 1 <= n <= 2 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.0
-irdrop.2,"For 3 <= n <= 15 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.6
-irdrop.3,"For 16 <= n <= 30 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.8
-irdrop.4,"For n > 30 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.9
+1,Min and max L and W of via3 (except for rule via3.1a),Al,0.200,µm
+1a,Two sizes of square via3 allowed inside :drc_tag:`areaid.mt`: 0.200um and 0.800um,Al,,
+2,Spacing of via3 to via3,Al,0.200,µm
+3,Only min. square via3s are allowed except die seal ring where via3s are (Via3 CD)*L,,0.2*L,
+4,Via3 must be enclosed by Met3 by at least …,Al,0.060,µm
+5,Via3 must be enclosed by Met3 on one of two adjacent sides by at least …,Al,0.090,µm
+11,Min and max L and W of via3,Cu,0.210,µm
+12,Min spacing between via2's,Cu,0.180,µm
+13,Via3 must be enclosed by Met3 by at least …,Cu,0.055,µm
+14,Min spacing between via3 rows,Cu,0.350,µm
+irdrop.1,"For 1 <= n <= 2 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.0,µm
+irdrop.2,"For 3 <= n <= 15 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.6,µm
+irdrop.3,"For 16 <= n <= 30 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.8,µm
+irdrop.4,"For n > 30 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.9,µm
 ,,,
 (nsm.-),Nitride Seal Mask,,sky130
 ,,,
-1,Min. width of nsm, ,3.000
-2,Min. spacing of nsm to nsm,,4.000
-3,"Min spacing, no overlap, between NSM_keepout to diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5). Exempt the following from the check: (a) cell name ""nikon*"" and (b) diff ring inside :drc_tag:`areaid.sl` ",Al,1.000
-3a,"Min enclosure of diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5) by :drc_tag:`areaid.ft`. Exempt the following from the check: (a) cell name ""s8Fab_crntic*""  (b)  blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)",,3.000
-3b,"Min spacing between :drc_tag:`areaid.dt` to diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5). Exempt the following from the check: (a) blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)",,3.000
+1,Min. width of nsm,,3.000,µm
+2,Min. spacing of nsm to nsm,,4.000,µm
+3,"Min spacing, no overlap, between NSM_keepout to diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5). Exempt the following from the check: (a) cell name ""nikon*"" and (b) diff ring inside :drc_tag:`areaid.sl` ",Al,1.000,µm
+3a,"Min enclosure of diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5) by :drc_tag:`areaid.ft`. Exempt the following from the check: (a) cell name ""s8Fab_crntic*""  (b)  blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)",,3.000,µm
+3b,"Min spacing between :drc_tag:`areaid.dt` to diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5). Exempt the following from the check: (a) blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)",,3.000,µm
 ,,,
 (indm.-),Inductor metal,,sky130
 ,"Function: Defines third level of metal interconnects, buses and inductor; top_indmMetal is met3 for SKY130D* flows; Similarly top_padVia is Via2 for SKY130D*",,
 ,,,
-1,Min width of top_indmMetal,,N/A
-2,Min spacing between two top_indmMetal,,N/A
-3,top_padVia must  be enclosed by top_indmMetal by atleast,,N/A
-4,Min area of top_indmMetal,,N/A
+1,Min width of top_indmMetal,,N/A,N/A
+2,Min spacing between two top_indmMetal,,N/A,N/A
+3,top_padVia must  be enclosed by top_indmMetal by atleast,,N/A,N/A
+4,Min area of top_indmMetal,,N/A,N/A
 ,,,
 ,,,
 ,,,
@@ -1075,25 +1075,25 @@
 (m4.-),Metal 4,,sky130
 ,Function: Defines Fourth level of metal interconnects;,,
 ,,,
-.X.1,"Algorithm should flag errors, for met4, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm4 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. Required for IP, Recommended for Chip-level.",RC,
-1,Min width of met4,,0.300
-2,Min spacing between two met4,,0.300
-3,via3 must  be enclosed by met4 by atleast,Al,0.065
-4,Min area of met4 (rule exempted for probe pads which are exactly 1.42um by 1.42um),,N/A
-4a,Min area of met4 ,,0.240
-5a,Min. spacing of features attached to or extending from huge_met4 for a distance of up to  0.400 um to metal4 (rule not checked over non-huge met4 features),,0.400
-5b,Min. spacing of huge_met4 to metal4 excluding features checked by m4.5a,,0.400
-7,Min area of meta4 holes [um2],Cu,0.200
-pd.1,Min MM4_oxide_Pattern_density,RR,0.7
-pd.2a,Rule m4.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700
-pd.2b,Rule m4.pd.1 has to be checked by dividing the chip into steps of …,A,70
-11,Max width of metal4,Cu,10.000
-12,Add slots and remove vias and contacts if wider than…..,Cu,10.000
-13,Max pattern density (PD) of metal4; met4 overlapping pdm areas are excluded from the check,Cu,0.77
-14,Met4 PD window size ,Cu,50.000
-14a,Met4 PD window step,Cu,25.000
-15,Via3 must be enclosed by met4 by at least…,Cu,0.060
-16,Min enclosure of pad by met4,Cu,0.850
+.X.1,"Algorithm should flag errors, for met4, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm4 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. Required for IP, Recommended for Chip-level.",RC,,
+1,Min width of met4,,0.300,µm
+2,Min spacing between two met4,,0.300,µm
+3,via3 must  be enclosed by met4 by atleast,Al,0.065,µm
+4,Min area of met4 (rule exempted for probe pads which are exactly 1.42um by 1.42um),,N/A,N/A
+4a,Min area of met4,,0.240,µm²
+5a,Min. spacing of features attached to or extending from huge_met4 for a distance of up to  0.400 µm to metal4 (rule not checked over non-huge met4 features),,0.400,µm
+5b,Min. spacing of huge_met4 to metal4 excluding features checked by m4.5a,,0.400,µm
+7,Min area of meta4 holes ,Cu,0.200,µm²
+pd.1,Min MM4_oxide_Pattern_density,RR,0.7,\-
+pd.2a,Rule m4.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700,µm
+pd.2b,Rule m4.pd.1 has to be checked by dividing the chip into steps of …,A,70,
+11,Max width of metal4,Cu,10.000,µm
+12,Add slots and remove vias and contacts if wider than…..,Cu,10.000,
+13,Max pattern density (PD) of metal4; met4 overlapping pdm areas are excluded from the check,Cu,0.77,\-
+14,Met4 PD window size,Cu,50.000,µm
+14a,Met4 PD window step,Cu,25.000,µm
+15,Via3 must be enclosed by met4 by at least…,Cu,0.060,µm
+16,Min enclosure of pad by met4,Cu,0.850,µm
 ,,,
 ,,,
 ,,,
@@ -1124,67 +1124,67 @@
 (via4.-),Via4,,sky130
 ,Function: Via4 connects met4 to met5 in the SKY130P*/SP8P* flow ,,
 ,,,
-1,Min and max L and W of via4,,0.800
-2,Spacing of via4 to via4,,0.800
-3,Only min. square via4s are allowed except die seal ring where via4s are (Via4 CD)*L,,0.8*L
-4,Via4 must be enclosed by Met4 by at least …,,0.190
-irdrop.1,"For 1 <= n <= 4 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.0
-irdrop.2,"For 5 <= n <= 10 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.2
-irdrop.3,"For 11 <= n <= 100 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.5
-irdrop.4,"For n > 100 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.8
+1,Min and max L and W of via4,,0.800,µm
+2,Spacing of via4 to via4,,0.800,µm
+3,Only min. square via4s are allowed except die seal ring where via4s are (Via4 CD)*L,,0.8*L,
+4,Via4 must be enclosed by Met4 by at least …,,0.190,µm
+irdrop.1,"For 1 <= n <= 4 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.0,µm
+irdrop.2,"For 5 <= n <= 10 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.2,µm
+irdrop.3,"For 11 <= n <= 100 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.5,µm
+irdrop.4,"For n > 100 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.8,µm
 ,,,
 (m5.-),Metal 5,,sky130
 ,Function: Defines Fifth level of metal interconnects;,,
 ,,,
-1,Min width of met5,,1.600
-2,Min spacing between two met5,,1.600
-3,via4 must  be enclosed by met5 by atleast,,0.310
-4,"Min area of met5 (For all flows except SKY130PIR*/SKY130PF*, the rule is exempted for probe pads which are exactly 1.42um by 1.42um)",,4.000
+1,Min width of met5,,1.600,µm
+2,Min spacing between two met5,,1.600,µm
+3,via4 must  be enclosed by met5 by atleast,,0.310,µm
+4,"Min area of met5 (For all flows except SKY130PIR*/SKY130PF*, the rule is exempted for probe pads which are exactly 1.42um by 1.42um)",,4.000,µm²
 ,,,
 (pad.-),Pad,,sky130
 ,Function: Opens the passivation,,
 ,,,
-2,Min spacing of pad:dg to pad:dg,,1.270
-3,Max area of hugePad NOT top_metal ,,30000
+2,Min spacing of pad:dg to pad:dg,,1.270,µm
+3,Max area of hugePad NOT top_metal,,30000,µm²
 ,,,
 (rdl.-),Cu Inductor,,sky130
 ,Function: Defines the Cu Inductor. Connects to met5 through the pad opening,,
 ,,,
-1,Min width of rdl,,10
-2,Min spacing between two rdl,,10
-3,"Min enclosure of pad by rdl, except rdl interacting with bump",,10.750
-4,Min spacing between rdl and outer edge of the seal ring,,15.000
-5,(rdl OR ccu1m.mk) must not overlap :drc_tag:`areaid.ft`. Exempt the following from the check: (a)  blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption),,
-6,"Min spacing of rdl to pad, except rdl interacting with bump",,19.660
+1,Min width of rdl,,10,µm
+2,Min spacing between two rdl,,10,µm
+3,"Min enclosure of pad by rdl, except rdl interacting with bump",,10.750,µm
+4,Min spacing between rdl and outer edge of the seal ring,,15.000,µm
+5,(rdl OR ccu1m.mk) must not overlap :drc_tag:`areaid.ft`. Exempt the following from the check: (a)  blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption),,,
+6,"Min spacing of rdl to pad, except rdl interacting with bump",,19.660,µm
 ,,,
 (mf.-),Metal Fuse,,sky130
 ,Function: Defines metal fuses,,
 ,For SKY130D* and SKY130TM* CADflow use MM2 for Metal Fuse,,
 ,For SP8P*/SKY130P* (PLM) CADflow use MM4 for Metal Fuse,,
-1,Min. and max width of fuse,,0.800
-2,Length of fuse,,7.200
-3,Spacing between centers of adjacent fuses,,2.760
-4,Spacing between center of fuse and fuse_metal (fuse shields are exempted),,3.300
-5,Max. extension of fuse_metal beyond fuse boundary ,,0.830
-6,Spacing (no overlapping) between fuse center and Metal1,,3.300
-7,Spacing (no overlapping) between fuse center and LI,,3.300
-8,Spacing (no overlapping) between fuse center and poly,,2.660
-9,Spacing (no overlapping) between fuse center and tap,,2.640
-10,Spacing (no overlapping) between fuse center and diff,,3.250
-11,Spacing (no overlapping) between fuse center and nwell,,3.320
-12,Size of  fuse_shield, ,0.5x2.4
-13,Min. spacing of center of fuse to fuse_shield,,2.200
-14,Max. spacing of center of fuse to fuse_shield,,3.300
-15,"Fuse_shields are only placed between periphery metal (i.e., without fuse:dg) and non-isolated edges of fuse as defined by mf.16",,
-16,The edge of a fuse is considered non-isolated if wider than or equal to mf.2 and spaced to fuse_metal by less than …,,4.000
-17,Offset between fuse_shields center and fuse center,NC,0.000
-18,Min and max space between fuse_shield and fuse_metal (opposite edges). Rule checked within 1 gridpoint.,,0.600
-19,Spacing (no overlapping) between fuse center and Metal2,,3.300
-20,Only one fuse per metal line allowed,,
-21,"Min spacing , no overlap, between metal3 and fuse center",,3.300
-22,Min spacing between fuse_contact to fuse_contact,,1.960
-23,Spacing (no overlapping) between fuse center and Metal4,,N/A
-24,Spacing (no overlapping) between fuse center and Metal5,,3.300
+1,Min. and max width of fuse,,0.800,µm
+2,Length of fuse,,7.200,µm
+3,Spacing between centers of adjacent fuses,,2.760,µm
+4,Spacing between center of fuse and fuse_metal (fuse shields are exempted),,3.300,µm
+5,Max. extension of fuse_metal beyond fuse boundary,,0.830,
+6,Spacing (no overlapping) between fuse center and Metal1,,3.300,µm
+7,Spacing (no overlapping) between fuse center and LI,,3.300,µm
+8,Spacing (no overlapping) between fuse center and poly,,2.660,µm
+9,Spacing (no overlapping) between fuse center and tap,,2.640,µm
+10,Spacing (no overlapping) between fuse center and diff,,3.250,µm
+11,Spacing (no overlapping) between fuse center and nwell,,3.320,µm
+12,Size of  fuse_shield,,0.5x2.4,µm
+13,Min. spacing of center of fuse to fuse_shield,,2.200,µm
+14,Max. spacing of center of fuse to fuse_shield,,3.300,µm
+15,"Fuse_shields are only placed between periphery metal (i.e., without fuse:dg) and non-isolated edges of fuse as defined by mf.16",,,
+16,The edge of a fuse is considered non-isolated if wider than or equal to mf.2 and spaced to fuse_metal by less than …,,4.000,
+17,Offset between fuse_shields center and fuse center,NC,0.000,
+18,Min and max space between fuse_shield and fuse_metal (opposite edges). Rule checked within 1 gridpoint.,,0.600,µm
+19,Spacing (no overlapping) between fuse center and Metal2,,3.300,µm
+20,Only one fuse per metal line allowed,,,
+21,"Min spacing , no overlap, between metal3 and fuse center",,3.300,µm
+22,Min spacing between fuse_contact to fuse_contact,,1.960,µm
+23,Spacing (no overlapping) between fuse center and Metal4,,N/A,N/A
+24,Spacing (no overlapping) between fuse center and Metal5,,3.300,µm
 ,,,
 ,,,
 ,,,
@@ -1216,16 +1216,16 @@
 ,,,
 ,,,
 ,,,
-Section G2b: Rules for HV devices,,,
+Section G2b: Rules for HV devices,,,,
 ,,,
 (hvi.-),HVI,,sky130
 ,Function: Defines thick oxide for high voltage devices,,
 ,,,
-1,Min width of Hvi,P,0.600
-2a,Min spacing of Hvi to Hvi,P,0.700
-2b,Manual merge if space is below minimum,,
-4,Hvi must not overlap tunm,,
-5,Min space between hvi and nwell (exclude coincident edges),,0.700
+1,Min width of Hvi,P,0.600,µm
+2a,Min spacing of Hvi to Hvi,P,0.700,µm
+2b,Manual merge if space is below minimum,,,
+4,Hvi must not overlap tunm,,,
+5,Min space between hvi and nwell (exclude coincident edges),,0.700,µm
 ,,,
 ,,,
 ,,,
@@ -1240,10 +1240,10 @@
 (nwell.-),High Voltage Nwell,,sky130
 ,"Function: Defines rules for HV nwell; All nwell connected to voltages greater than 1.8V must be enclosed by hvi; Nets connected to LV nwell or nwell overlapping hvi but connected to LV voltages (i.e 1.8V) should be tagged ""lv_net"" using text.dg; This tag should be only on Li layer",,
 ,,,
-8,Min space between HV_nwell  and any nwell on different nets,,2.000
-9,(Nwell overlapping hvi) must be enclosed by hvi,,
-10,"LVnwell and HnWell should not be on the same net (for the purposes of this check, short the connectivity through resistors); Exempt HnWell with li nets tagged ""lv_net"" using text.dg and Hnwell connected to nwell overlapping :drc_tag:`areaid.hl`",TC,
-11,"Nwell connected to the nets mentioned in the ""Power_Net_Hv"" field of the latcup GUI must be enclosed by hvi (exempt nwell inside :drc_tag:`areaid.hl`). Also for the purposes of this check, short the connectivity through resistors. The rule will be checked in the latchup run and exempted for cells ""s8tsg5_tx_ibias_gen"" and ""s8bbcnv_psoc3p_top_18"",  ""rainier_top, indus_top*"", ""rainier_top, manas_top, ccg3_top""",,
+8,Min space between HV_nwell  and any nwell on different nets,,2.000,µm
+9,(Nwell overlapping hvi) must be enclosed by hvi,,,
+10,"LVnwell and HnWell should not be on the same net (for the purposes of this check, short the connectivity through resistors); Exempt HnWell with li nets tagged ""lv_net"" using text.dg and Hnwell connected to nwell overlapping :drc_tag:`areaid.hl`",TC,,
+11,"Nwell connected to the nets mentioned in the ""Power_Net_Hv"" field of the latcup GUI must be enclosed by hvi (exempt nwell inside :drc_tag:`areaid.hl`). Also for the purposes of this check, short the connectivity through resistors. The rule will be checked in the latchup run and exempted for cells ""s8tsg5_tx_ibias_gen"" and ""s8bbcnv_psoc3p_top_18"",  ""rainier_top, indus_top*"", ""rainier_top, manas_top, ccg3_top""",,,
 ,,,
 ,,,
 ,,,
@@ -1261,21 +1261,21 @@
 (difftap.-),High Voltage Diff/Tap,,sky130
 ,Function: Defines rules for HV diff/tap,,
 ,,,
-14,"Min width of diff inside Hvi, except HV Pdiff resistors (difftap.14a)",P,0.290
-14a,"Min width of diff inside Hvi, HV Pdiff resistors only",P,0.150
-15a,Min space of Hdiff to Hdiff ,P,0.300
-15b,Min space of n+diff to non-abutting p+tap inside Hvi,P,0.370
-16,Min width tap butting diff on one or two sides inside Hvi (rule exempted inside UHVI),,0.700
-17,P+ Hdiff or Pdiff inside areaid:hvnwell must be enclosed by Hv_nwell by at least ….[Rule exempted inside UHVI],"DE, NE",0.330
-18,Spacing of N+ diff to HV_nwell (rule exempted inside UHVI),"DE, NE",0.430
-19,N+ Htap must be enclosed by Hv_nwell by at least …Rule exempted inside UHVI.,NE,0.330
-20,Spacing of P+ tap to HV_nwell (Exempted for p+tap butting pwell.rs; rule exempted inside UHVI),,0.430
-21,Diff or tap cannot straddle Hvi ,P,
-22,Min enclosure of Hdiff or Htap by Hvi. Rule exempted inside UHVI.,P,0.180
-23,Space between diff or tap outside Hvi and Hvi,P,0.180
-24,Spacing of nwell to N+ Hdiff (rule exempted inside UHVI),"DE, NE",0.430
-25,Min space of N+ Hdiff inside HVI across non-abutting P+_tap,NC,1.070
-26,Min spacing between pwbm to difftap outside UHVI,,N/A
+14,"Min width of diff inside Hvi, except HV Pdiff resistors (difftap.14a)",P,0.290,µm
+14a,"Min width of diff inside Hvi, HV Pdiff resistors only",P,0.150,µm
+15a,Min space of Hdiff to Hdiff,P,0.300,µm
+15b,Min space of n+diff to non-abutting p+tap inside Hvi,P,0.370,µm
+16,Min width tap butting diff on one or two sides inside Hvi (rule exempted inside UHVI),,0.700,µm
+17,P+ Hdiff or Pdiff inside areaid:hvnwell must be enclosed by Hv_nwell by at least ….[Rule exempted inside UHVI],"DE, NE",0.330,µm
+18,Spacing of N+ diff to HV_nwell (rule exempted inside UHVI),"DE, NE",0.430,µm
+19,N+ Htap must be enclosed by Hv_nwell by at least …Rule exempted inside UHVI.,NE,0.330,µm
+20,Spacing of P+ tap to HV_nwell (Exempted for p+tap butting pwell.rs; rule exempted inside UHVI),,0.430,µm
+21,Diff or tap cannot straddle Hvi,P,,
+22,Min enclosure of Hdiff or Htap by Hvi. Rule exempted inside UHVI.,P,0.180,µm
+23,Space between diff or tap outside Hvi and Hvi,P,0.180,µm
+24,Spacing of nwell to N+ Hdiff (rule exempted inside UHVI),"DE, NE",0.430,µm
+25,Min space of N+ Hdiff inside HVI across non-abutting P+_tap,NC,1.070,µm
+26,Min spacing between pwbm to difftap outside UHVI,,N/A,N/A
 ,,,
 ,,,
 ,,,
@@ -1317,8 +1317,8 @@
 (poly.-),High Voltage Poly,,sky130
 ,Function: Defines rules for HV poly,,
 ,,,
-13,Min width of poly over diff inside Hvi,P,0.500
-14,(poly and diff) cannot straddle Hvi,,
+13,Min width of poly over diff inside Hvi,P,0.500,µm
+14,(poly and diff) cannot straddle Hvi,,,
 ,,,
 ,,,
 ,,,
@@ -1345,17 +1345,17 @@
 (hvntm.-),Hvntm,,sky130
 ,Function: Defines tip implants for the HV NMOS,,
 ,,,
-X.1 ,Hvntm can be drawn inside HVI. Drawn layer will be OR-ed with the CL and rechecked for CLDRC,,
-1,Width of hvntm,P,0.700
-2,Spacing of hvntm to hvntm,P,0.700
-3,Min. enclosure of (n+_diff inside Hvi) but not overlapping :drc_tag:`areaid.ce` by hvntm,P,0.185
-4,"Space, no overlap, between n+_diff outside Hvi and hvntm",P,0.185
-5,"Space, no overlap, between p+_diff  and hvntm","P, DE",0.185
-6a,"Space, no overlap, between p+_tap and hvntm (except along the diff-butting edge)",P,0.185
-6b,"Space, no overlap, between p+_tap and hvntm along the diff-butting edge",P,0.000
-7,hvntm must enclose ESD_nwell_tap inside hvi by atleast,P,0.000
-9,Hvntm must not overlap :drc_tag:`areaid.ce`,,
-10,Hvntm must overlap hvi,,
+X.1,Hvntm can be drawn inside HVI. Drawn layer will be OR-ed with the CL and rechecked for CLDRC,,,
+1,Width of hvntm,P,0.700,µm
+2,Spacing of hvntm to hvntm,P,0.700,µm
+3,Min. enclosure of (n+_diff inside Hvi) but not overlapping :drc_tag:`areaid.ce` by hvntm,P,0.185,µm
+4,"Space, no overlap, between n+_diff outside Hvi and hvntm",P,0.185,µm
+5,"Space, no overlap, between p+_diff  and hvntm","P, DE",0.185,µm
+6a,"Space, no overlap, between p+_tap and hvntm (except along the diff-butting edge)",P,0.185,µm
+6b,"Space, no overlap, between p+_tap and hvntm along the diff-butting edge",P,0.000,µm
+7,hvntm must enclose ESD_nwell_tap inside hvi by atleast,P,0.000,
+9,Hvntm must not overlap :drc_tag:`areaid.ce`,,,
+10,Hvntm must overlap hvi,,,
 ,,,
 ,,,
 ,,,
@@ -1388,21 +1388,21 @@
 (denmos.-),Denmos,,sky130
 ,Function: Defines rules for the 16V Drain extended NMOS devices,,
 ,,,
-1,Min width of de_nFet_gate,,1.055
-2,Min width of de_nFet_source not overlapping poly,,0.280
-3,Min width of de_nFet_source overlapping poly,,0.925
-4,Min width of the de_nFet_drain,,0.170
-5,Min/Max extension of de_nFet_source over nwell,,0.225
-6,Min/Max spacing between de_nFet_drain and de_nFet_source,,1.585
-7,Min channel width for de_nFet_gate,,5.000
-8,90 degree angles are not permitted for nwell overlapping de_nFET_drain,,
-9a,"All bevels on nwell are 45 degree, 0.43 um from corners",,NC
-9b,"All bevels on de_nFet_drain are 45 degree, 0.05 um from corners",,NC
-10,Min enclosure of de_nFet_drain by nwell,,0.660
-11,Min spacing between p+ tap and (nwell overlapping de_nFet_drain),,0.860
-12,Min spacing between nwells overlapping de_nFET_drain,,2.400
-13,de_nFet_source must be enclosed by nsdm by,,0.130
-14,nvhv FETs must be enclosed by :drc_tag:`areaid.mt`,,N/A
+1,Min width of de_nFet_gate,,1.055,µm
+2,Min width of de_nFet_source not overlapping poly,,0.280,µm
+3,Min width of de_nFet_source overlapping poly,,0.925,µm
+4,Min width of the de_nFet_drain,,0.170,µm
+5,Min/Max extension of de_nFet_source over nwell,,0.225,
+6,Min/Max spacing between de_nFet_drain and de_nFet_source,,1.585,µm
+7,Min channel width for de_nFet_gate,,5.000,µm
+8,90 degree angles are not permitted for nwell overlapping de_nFET_drain,,,
+9a,"All bevels on nwell are 45 degree, 0.43 µm from corners",,NC,µm
+9b,"All bevels on de_nFet_drain are 45 degree, 0.05 µm from corners",,NC,µm
+10,Min enclosure of de_nFet_drain by nwell,,0.660,µm
+11,Min spacing between p+ tap and (nwell overlapping de_nFet_drain),,0.860,µm
+12,Min spacing between nwells overlapping de_nFET_drain,,2.400,µm
+13,de_nFet_source must be enclosed by nsdm by,,0.130,µm
+14,nvhv FETs must be enclosed by :drc_tag:`areaid.mt`,,N/A,N/A
 ,,,
 ,,,
 ,,,
@@ -1430,20 +1430,20 @@
 (depmos.-),Depmos,,sky130
 ,Function: Defines rules for the 16V Drain extended NMOS devices,,
 ,,,
-1,Min width of de_pFet_gate,,1.050
-2,Min width of de_pFet_source not overlapping poly,,0.280
-3,Min width of de_pFet_source overlapping poly,,0.920
-4,Min width of the de_pFet_drain,,0.170
-5,Min/Max extension of de_pFet_source beyond nwell,,0.260
-6,Min/Max spacing between de_pFet_drain and de_pFet_source,,1.190
-7,Min channel width for de_pFet_gate,,5.000
-8,90 degree angles are not permitted for nwell hole overlapping de_pFET_drain,,
-9a,"All bevels on nwell hole are 45 degree, 0.43 um from corners",,NC
-9b,"All bevels on de_pFet_drain are 45 degree, 0.05 um from corners",,NC
-10,Min enclosure of de_pFet_drain by nwell hole,,0.860
-11,Min spacing between n+ tap and (nwell hole enclosing de_pFET_drain),,0.660
-12,de_pFet_source must be enclosed by psdm by,,0.130
-13,pvhv fets( except those with W/L = 5.0/0.66) must be enclosed by :drc_tag:`areaid.mt`,,N/A
+1,Min width of de_pFet_gate,,1.050,µm
+2,Min width of de_pFet_source not overlapping poly,,0.280,µm
+3,Min width of de_pFet_source overlapping poly,,0.920,µm
+4,Min width of the de_pFet_drain,,0.170,µm
+5,Min/Max extension of de_pFet_source beyond nwell,,0.260,
+6,Min/Max spacing between de_pFet_drain and de_pFet_source,,1.190,µm
+7,Min channel width for de_pFet_gate,,5.000,µm
+8,90 degree angles are not permitted for nwell hole overlapping de_pFET_drain,,,
+9a,"All bevels on nwell hole are 45 degree, 0.43 µm from corners",,NC,µm
+9b,"All bevels on de_pFet_drain are 45 degree, 0.05 µm from corners",,NC,µm
+10,Min enclosure of de_pFet_drain by nwell hole,,0.860,µm
+11,Min spacing between n+ tap and (nwell hole enclosing de_pFET_drain),,0.660,µm
+12,de_pFet_source must be enclosed by psdm by,,0.130,µm
+13,pvhv fets( except those with W/L = 5.0/0.66) must be enclosed by :drc_tag:`areaid.mt`,,N/A,N/A
 ,,,
 ,,,
 ,,,
@@ -1473,14 +1473,14 @@
 (extd.-),Extended Drain,,sky130
 ,Function: Defines rules :drc_tag:`areaid.en`,,
 ,,,
-1,Difftap cannot straddle areaid:en,,
-2,DiffTap must have 2 or 3 coincident edges with areaid:en if enclosed by areaid:en,,
-3,Poly must not be entirely overlapping difftap in areaid:en,,
-4,"Only cell name ""s8rf_n20vhv1*"" is a valid cell name for n20vhv1 device  (Check in LVS as invalid device)",,N/A
-5,"Only cell name ""s8rf_n20vhviso1"" is a valid cell name for n20vhviso1 device  (Check in LVS as invalid device)",,N/A
-6,"Only cell name ""s8rf_p20vhv1"" is a valid cell name for p20vhv1 device  (Check in LVS as invalid device)",,N/A
-7,"Only cell name ""s8rf_n20nativevhv1*"" is a valid cell name for n20nativevhv1 device  (Check in LVS as invalid device)",,N/A
-8,"Only cell name ""s8rf_n20zvtvhv1*"" is a valid cell name for n20zvtvhv1 device  (Check in LVS as invalid device)",,N/A
+1,Difftap cannot straddle areaid:en,,,
+2,DiffTap must have 2 or 3 coincident edges with areaid:en if enclosed by areaid:en,,,
+3,Poly must not be entirely overlapping difftap in areaid:en,,,
+4,"Only cell name ""s8rf_n20vhv1*"" is a valid cell name for n20vhv1 device  (Check in LVS as invalid device)",,N/A,N/A
+5,"Only cell name ""s8rf_n20vhviso1"" is a valid cell name for n20vhviso1 device  (Check in LVS as invalid device)",,N/A,N/A
+6,"Only cell name ""s8rf_p20vhv1"" is a valid cell name for p20vhv1 device  (Check in LVS as invalid device)",,N/A,N/A
+7,"Only cell name ""s8rf_n20nativevhv1*"" is a valid cell name for n20nativevhv1 device  (Check in LVS as invalid device)",,N/A,N/A
+8,"Only cell name ""s8rf_n20zvtvhv1*"" is a valid cell name for n20zvtvhv1 device  (Check in LVS as invalid device)",,N/A,N/A
 ,,,
 ,,,
 ,,,
@@ -1496,26 +1496,26 @@
 ,,,
 (hv.-.-),High Voltage Rules,,sky130
 ,,,
-Note,High voltage rule apply for an operating voltage range of 5.5 - 12V; Nodes switching between 0 to 5.5V do not need to follow these rules,,
-.X.1,High voltage source/drain regions must be tagged by diff:hv,,
-.X.3,"High voltage poly can be drawn over multiple diff regions that are ALL reverse-biased by at least 300 mV (existence of reverse-bias is not checked by the CAD flow).  It can also be drawn over multiple diffs when all sources and all drain are shorted together. In these case, the high voltage poly can be tagged with the text:dg label with a value “hv_bb”.  Exceptions to this use of the hv_bb label must be approved by technology.  Under certain bias conditions, high voltage poly tagged with hv_bb can cross an nwell boundary. The poly of the drain extended device crosses nwell by construction and can be tagged with the ""hv_bb"" label. Use of the hv_bb label on high voltage poly crossing an nwell boundary must be approved by technology. All high voltage poly tagged with hv_bb will not be checked to hv.poly.1, hv.poly.2, hv.poly.3 and hv.poly.4.",,
-.X.4,Any piece of layout that is shorted to hv_source/drain becomes a high voltage feature.,,
-.X.5,"In cases where an hv poly gate abuts only low voltage source and drain, the poly gate can be tagged with the text:dg label with a value ""hv_lv"".  In this case, the ""hv_lv"" tagged poly gate and its extensions will not be checked to hv.poly.6, but is checked by rules in the poly.-.- section.  The use of the hv_lv label must be approved by technology.",,
-.X.6,"Nwell biased at voltages >= 7.2V must be tagged with text ""shv_nwell""",NC,
-.nwell.1,"Min spacing of nwell tagged with text ""shv_nwell"" to any nwell on different nets",,2.500
-.diff.1a,Minimum hv_source/drain spacing to diff for edges of hv_source/drain and diff not butting tap,,0.300
-.diff.1b,Minimum spacing of (n+/p+ diff resistors and diodes) connected to hv_source/drain to diff,,0.300
-.diff.2,Minimum spacing of nwell connected to hv_source/drain to n+ diff,DE,0.430
-.diff.3a,Minimum n+ hv_source/drain spacing to nwell,,0.550
-.diff.3b,Minimum spacing of (n+ diff resistors and diodes) connected to hv_source/drain to nwell,,0.550
-.poly.1,Hv poly feature hvPoly (including hv poly resistors) can be drawn over only one diff region and is not allowed to cross nwell boundary except (1) as allowed in rule .X.3 and (2) nwell hole boundary in depmos,,
-.poly.2,Min spacing of hvPoly (including hv poly resistor) on field to diff (diff butting hvPoly are excluded),,0.300
-.poly.3,Min spacing of hvPoly (including hv poly resistor) on field to n-well (exempt poly stradding nwell in a denmos/depmos),,0.550
-.poly.4,Enclosure of hvPoly (including hv poly resistor) on field by n-well (exempt poly stradding nwell in a denmos/depmos),,0.300
-.poly.6a,Min extension of poly beyond hvFET_gate (exempt poly extending beyond diff along the S/D direction in a denmos/depmos),,0.160
-.poly.6b,Extension of hv poly beyond FET_gate (including hvFET_gate; exempt poly extending beyond diff along the S/D direction in a denmos/depmos),,0.160
-.poly.7,Minimum overlap of hv poly ring_FET and diff,,
-.poly.8,Any poly gate abutting hv_source/drain becomes a hvFET_gate,,
+Note,High voltage rule apply for an operating voltage range of 5.5 - 12V; Nodes switching between 0 to 5.5V do not need to follow these rules,,,
+.X.1,High voltage source/drain regions must be tagged by diff:hv,,,
+.X.3,"High voltage poly can be drawn over multiple diff regions that are ALL reverse-biased by at least 300 mV (existence of reverse-bias is not checked by the CAD flow).  It can also be drawn over multiple diffs when all sources and all drain are shorted together. In these case, the high voltage poly can be tagged with the text:dg label with a value “hv_bb”.  Exceptions to this use of the hv_bb label must be approved by technology.  Under certain bias conditions, high voltage poly tagged with hv_bb can cross an nwell boundary. The poly of the drain extended device crosses nwell by construction and can be tagged with the ""hv_bb"" label. Use of the hv_bb label on high voltage poly crossing an nwell boundary must be approved by technology. All high voltage poly tagged with hv_bb will not be checked to hv.poly.1, hv.poly.2, hv.poly.3 and hv.poly.4.",,,
+.X.4,Any piece of layout that is shorted to hv_source/drain becomes a high voltage feature.,,,
+.X.5,"In cases where an hv poly gate abuts only low voltage source and drain, the poly gate can be tagged with the text:dg label with a value ""hv_lv"".  In this case, the ""hv_lv"" tagged poly gate and its extensions will not be checked to hv.poly.6, but is checked by rules in the poly.-.- section.  The use of the hv_lv label must be approved by technology.",,,
+.X.6,"Nwell biased at voltages >= 7.2V must be tagged with text ""shv_nwell""",NC,,
+.nwell.1,"Min spacing of nwell tagged with text ""shv_nwell"" to any nwell on different nets",,2.500,µm
+.diff.1a,Minimum hv_source/drain spacing to diff for edges of hv_source/drain and diff not butting tap,,0.300,µm
+.diff.1b,Minimum spacing of (n+/p+ diff resistors and diodes) connected to hv_source/drain to diff,,0.300,µm
+.diff.2,Minimum spacing of nwell connected to hv_source/drain to n+ diff,DE,0.430,µm
+.diff.3a,Minimum n+ hv_source/drain spacing to nwell,,0.550,µm
+.diff.3b,Minimum spacing of (n+ diff resistors and diodes) connected to hv_source/drain to nwell,,0.550,µm
+.poly.1,Hv poly feature hvPoly (including hv poly resistors) can be drawn over only one diff region and is not allowed to cross nwell boundary except (1) as allowed in rule .X.3 and (2) nwell hole boundary in depmos,,,
+.poly.2,Min spacing of hvPoly (including hv poly resistor) on field to diff (diff butting hvPoly are excluded),,0.300,µm
+.poly.3,Min spacing of hvPoly (including hv poly resistor) on field to n-well (exempt poly stradding nwell in a denmos/depmos),,0.550,µm
+.poly.4,Enclosure of hvPoly (including hv poly resistor) on field by n-well (exempt poly stradding nwell in a denmos/depmos),,0.300,µm
+.poly.6a,Min extension of poly beyond hvFET_gate (exempt poly extending beyond diff along the S/D direction in a denmos/depmos),,0.160,
+.poly.6b,Extension of hv poly beyond FET_gate (including hvFET_gate; exempt poly extending beyond diff along the S/D direction in a denmos/depmos),,0.160,
+.poly.7,Minimum overlap of hv poly ring_FET and diff,,,
+.poly.8,Any poly gate abutting hv_source/drain becomes a hvFET_gate,,,
 ,,,
 ,,,
 ,,,
@@ -1579,57 +1579,57 @@
 (vhvi.-.-),VHVI - Very HV ID and Rules,,sky130
 ,Function: Identify nets working between 12-16V,,
 ,,,
-.vhv.1,Terminals operating at nominal 12V (maximum 16V) bias must be tagged as Very-High-Voltage (VHV) using vhvi:dg layer,,NC
-.vhv.2,A source or drain of a drain-extended device can be tagged by vhvi:dg. A device with either source or drain (not both) tagged with vhvi:dg serves as a VHV propagation stopper,,NC
-.vhv.3,Any feature connected to VHVSourceDrain becomes a very-high-voltage feature,,NC
-.vhv.4,Any feature connected to VHVPoly becomes a very-high-voltage feature,,NC
-.vhv.5,"Diffusion that is not a part of a drain-extended device (i.e., diff not areaid:en) must not be on the same net as VHVSourceDrain. Only diffusion inside :drc_tag:`areaid.ed` and LV diffusion tagged with vhvi:dg are exempted.",,
-.vhv.6,"Poly resistor can act as a VHV propagation stopper. For this, it should be tagged with text ""vhv_block""",,NC
-1,Min width of vhvi:dg,,0.020
-2,Vhvi:dg cannot overlap areaid:ce,,
-3,VHVGate must overlap hvi:dg,,
-4,Poly connected to the same net as a VHVSourceDrain must be tagged with vhvi:dg layer,,
-5,Vhvi:dg cannot straddle VHVSourceDrain,,
-6,Vhvi:dg overlapping VHVSourceDrain must not overlap poly,,
-7,Vhvi:dg cannot straddle VHVPoly,,
-8,"Min space between nwell tagged with vhvi:dg and deep nwell, nwell, or n+diff on a separate net (except for n+diff overlapping nwell tagged with vhvi:dg).",,11.240
+.vhv.1,Terminals operating at nominal 12V (maximum 16V) bias must be tagged as Very-High-Voltage (VHV) using vhvi:dg layer,,NC,
+.vhv.2,A source or drain of a drain-extended device can be tagged by vhvi:dg. A device with either source or drain (not both) tagged with vhvi:dg serves as a VHV propagation stopper,,NC,
+.vhv.3,Any feature connected to VHVSourceDrain becomes a very-high-voltage feature,,NC,
+.vhv.4,Any feature connected to VHVPoly becomes a very-high-voltage feature,,NC,
+.vhv.5,"Diffusion that is not a part of a drain-extended device (i.e., diff not areaid:en) must not be on the same net as VHVSourceDrain. Only diffusion inside :drc_tag:`areaid.ed` and LV diffusion tagged with vhvi:dg are exempted.",,,
+.vhv.6,"Poly resistor can act as a VHV propagation stopper. For this, it should be tagged with text ""vhv_block""",,NC,
+1,Min width of vhvi:dg,,0.020,µm
+2,Vhvi:dg cannot overlap areaid:ce,,,
+3,VHVGate must overlap hvi:dg,,,
+4,Poly connected to the same net as a VHVSourceDrain must be tagged with vhvi:dg layer,,,
+5,Vhvi:dg cannot straddle VHVSourceDrain,,,
+6,Vhvi:dg overlapping VHVSourceDrain must not overlap poly,,,
+7,Vhvi:dg cannot straddle VHVPoly,,,
+8,"Min space between nwell tagged with vhvi:dg and deep nwell, nwell, or n+diff on a separate net (except for n+diff overlapping nwell tagged with vhvi:dg).",,11.240,µm
 ,,,
 (uhvi.-.-),UHVI - Ultra HV ID and Rules,,sky130
 ,Function: Identify nets working between 20V,,
 ,,,
-1,diff/tap can not straddle UHVI,,N/A
-2,poly can not straddle UHVI,,N/A
-3,pwbm.dg must be enclosed by UHVI (exempt inside :drc_tag:`areaid.lw`),,N/A
-4,dnw.dg can not straddle UHVI,,N/A
-5,UHVI must enclose :drc_tag:`areaid.ext`,,N/A
-6,UHVI must enclose dnwell,,N/A
-7,natfet.dg must be enclosed by UHVI layer by at least,,N/A
-8,Minimum width of natfet.dg,,N/A
-9,Minimum Space spacing of natfet.dg ,,N/A
-10,natfet.dg layer is not allowed,,N/A
+1,diff/tap can not straddle UHVI,,N/A,N/A
+2,poly can not straddle UHVI,,N/A,N/A
+3,pwbm.dg must be enclosed by UHVI (exempt inside :drc_tag:`areaid.lw`),,N/A,N/A
+4,dnw.dg can not straddle UHVI,,N/A,N/A
+5,UHVI must enclose :drc_tag:`areaid.ext`,,N/A,N/A
+6,UHVI must enclose dnwell,,N/A,N/A
+7,natfet.dg must be enclosed by UHVI layer by at least,,N/A,N/A
+8,Minimum width of natfet.dg,,N/A,N/A
+9,Minimum Space spacing of natfet.dg,,N/A,N/A
+10,natfet.dg layer is not allowed,,N/A,N/A
 , ,,
 (ulvt-.-),:drc_tag:`areaid.low_vt` for UHV Diodes ,,sky130
 ,Function: Identify dnwdiodehv_Psub(BV~60V),,
 ,,,NA
-1,":drc_tag:`areaid.low_vt` must enclose dnw for the UHV dnw-psub diode texted ""condiodeHvPsub""",,NA
-2,":drc_tag:`areaid.low_vt` must enclose pwbm.dg for the UHV dnw-psub diode texted ""condiodeHvPsub""",,NA
-3,:drc_tag:`areaid.low_vt` can not straddle UHVI,,NA
+1,":drc_tag:`areaid.low_vt` must enclose dnw for the UHV dnw-psub diode texted ""condiodeHvPsub""",,NA,
+2,":drc_tag:`areaid.low_vt` must enclose pwbm.dg for the UHV dnw-psub diode texted ""condiodeHvPsub""",,NA,
+3,:drc_tag:`areaid.low_vt` can not straddle UHVI,,NA,
 ,,,
 (pwres.-.-),Pwell resistor,,sky130
 ,Function: Identify pwell resistors,,
 ,,,
-1,Pwell resistor has to be enclosed by the res layer,NC,
-2,Min/Max width of pwell resistor ,,2.650
-3,Min length of pwell resistor,,26.500
-4,Max length of pwell resistor,,265.00
-5,Min/Max spacing of tap inside the pwell resistor to nwell ,,0.220
-6,Min/Max width of tap inside the pwell resistor ,,0.530
-7a,Every pwres_terminal must enclose 12 licon1,,
-7b,Every pwres_terminal must enclose 12 mcons if routed through metal1,,
-8,Diff or poly is not allowed in the pwell resistor.,,
-9,Nwell surrounding the pwell resistor must have a full ring of contacted tap strapped with metal.,,
-10,The res layer must abut pwres_terminal on opposite and parallel edges,,
-11,The res layer must abut nwell on opposite and parallel edges not checked in Rule pwres.10,,
+1,Pwell resistor has to be enclosed by the res layer,NC,,
+2,Min/Max width of pwell resistor,,2.650,µm
+3,Min length of pwell resistor,,26.500,µm
+4,Max length of pwell resistor,,265.00,µm
+5,Min/Max spacing of tap inside the pwell resistor to nwell,,0.220,µm
+6,Min/Max width of tap inside the pwell resistor,,0.530,µm
+7a,Every pwres_terminal must enclose 12 licon1,,,
+7b,Every pwres_terminal must enclose 12 mcons if routed through metal1,,,
+8,Diff or poly is not allowed in the pwell resistor.,,,
+9,Nwell surrounding the pwell resistor must have a full ring of contacted tap strapped with metal.,,,
+10,The res layer must abut pwres_terminal on opposite and parallel edges,,,
+11,The res layer must abut nwell on opposite and parallel edges not checked in Rule pwres.10,,,
 ,,,
 ,,,
 ,,,
@@ -1657,9 +1657,9 @@
 (rfdiode.-.-),Areaid.re for RF Diodes ,,sky130
 ,Function: Identify RF diodes; Used for RCX,,
 ,,,
-1,Only 90 degrees allowed for :drc_tag:`areaid.re`,,
-2,:drc_tag:`areaid.re` must be coincident with nwell for the rf nwell diode,,
-3,:drc_tag:`areaid.re` must be coincident with innwer edge of the nwell ring for the rf pwell-deep nwell diode,,
+1,Only 90 degrees allowed for :drc_tag:`areaid.re`,,,
+2,:drc_tag:`areaid.re` must be coincident with nwell for the rf nwell diode,,,
+3,:drc_tag:`areaid.re` must be coincident with innwer edge of the nwell ring for the rf pwell-deep nwell diode,,,
 ,,,
 ,,,
 ,Allowed PNP layout,,
diff --git a/libraries/sky130_fd_io/latest b/libraries/sky130_fd_io/latest
new file mode 160000
index 0000000..01b1869
--- /dev/null
+++ b/libraries/sky130_fd_io/latest
@@ -0,0 +1 @@
+Subproject commit 01b18699b4102d8e54ad1406b3991ecb652e5aee
diff --git a/libraries/sky130_fd_io/latest/README.rst b/libraries/sky130_fd_io/latest/README.rst
deleted file mode 100644
index 825d502..0000000
--- a/libraries/sky130_fd_io/latest/README.rst
+++ /dev/null
@@ -1,10 +0,0 @@
-:lib:`sky130_fd_io` - SKY130 IO and periphery cells (SkyWater Provided)
-=======================================================================
-
-Initial documentation only release.
-
-.. toctree::
-    :maxdepth: 1
-    :name: sky130-lib-foundry-io-top
-
-    docs/user_guide
diff --git a/libraries/sky130_fd_io/latest/docs/figures/sky130_fd_io__gpio.png b/libraries/sky130_fd_io/latest/docs/figures/sky130_fd_io__gpio.png
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diff --git a/libraries/sky130_fd_io/latest/docs/figures/sky130_fd_io__sio.png b/libraries/sky130_fd_io/latest/docs/figures/sky130_fd_io__sio.png
deleted file mode 100644
index 36eea45..0000000
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diff --git a/libraries/sky130_fd_io/latest/docs/figures/sky130_fd_io__sio_macro.png b/libraries/sky130_fd_io/latest/docs/figures/sky130_fd_io__sio_macro.png
deleted file mode 100644
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diff --git a/libraries/sky130_fd_io/latest/docs/figures/sky130_fd_io__top_amuxsplitv2.png b/libraries/sky130_fd_io/latest/docs/figures/sky130_fd_io__top_amuxsplitv2.png
deleted file mode 100644
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-User Guide for :lib:`sky130_fd_io`
-==================================
-
-Summary
--------
-
-This IP document includes two versions of a General Purpose I/O buffer (:cell:`sky130_fd_io__gpio`) with different feature sets,
-:cell:`sky130_fd_io__sio` macro (pair of Special I/O buffer (:cell:`sky130_fd_io__sio`) + REFerence GENerator (:cell:`sky130_fd_io__refgen`).
-
-The IP also includes;
-
-*  Power, Ground cells (PG pads),
-*  Reset cells (XRES),
-*  Test pads,
-*  Analog pads,
-*  power detector,
-*  overlay cells.
-
-The IP also includes all the relevant ESD clamps, diodes and trigger circuits to complete the I/O ring.
-
-The I/O buffers can be configured as an input buffer, output buffer, or an I/O buffer.
-
-The :cell:`sky130_fd_io__gpio` buffer includes a single-ended input buffer that can be configured for LVTTL, CMOS/I2C operation.
-
-:cell:`sky130_fd_io__gpiov2` has better electrical performance and the Rx can handle 1.8V signaling when the I/O supply is different from 1.8V.
-
-:cell:`sky130_fd_io__gpio_ovtv2` is fully I2C compliant and includes the over-voltage tolerance feature.
-It also has an input buffer that can support selectable trip-point feature along with a reference generator.
-
-The :cell:`sky130_fd_io__sio` buffer can be configured to produce a regulated high output level, and includes a differential input buffer.
-All I/O buffers support multiple drive modes.
-
-The IP supports a power supply range of 1.71V to 5.5V.
-
-Features. Benefits, Tradeoffs, Limitations
-------------------------------------------
-
-*  1.71V-5.5V continuous supply operating range
-*  Rail-based ESD protection for :cell:`sky130_fd_io__gpio*` and :cell:`sky130_fd_io__sio_macro`
-*  I2C compliant :cell:`sky130_fd_io__gpio_ovtv2`
-*  I2C compatible - :cell:`sky130_fd_io__gpiov2`, :cell:`sky130_fd_io__gpio`, :cell:`sky130_fd_io__sio`
-*  CMOS, LPC compliant - :cell:`sky130_fd_io__gpio*`, :cell:`sky130_fd_io__sio`
-*  Low Power modes: Hibernate mode (Latch previous state), Deep Sleep Mode (allows I2C communication), Stop Mode (retains I/O state when LV supply is gone)
-*  Selectable output buffer drive modes (open drain high/low, strong/weak pull up/down, High-Z output) - :cell:`sky130_fd_io__gpio*`, :cell:`sky130_fd_io__sio`
-*  Regulated output high level - :cell:`sky130_fd_io__sio`
-*  Hot swap & over-voltage tolerant - :cell:`sky130_fd_io__sio`, :cell:`sky130_fd_io__gpio_ovtv2`
-*  Selectable output buffer slew rate control - :cell:`sky130_fd_io__sio`, :cell:`sky130_fd_io__gpio*`
-*  Selectable input buffer threshold (LVTTL or CMOS/I2C)- :cell:`sky130_fd_io__gpio*`, :cell:`sky130_fd_io__sio`
-*  Selectable 1.8V signaling (Active Mode) - :cell:`sky130_fd_io__gpiov2`, :cell:`sky130_fd_io__gpio_ovtv2`
-*  Selectable differential input buffer threshold (4 options) - :cell:`sky130_fd_io__sio`
-*  Integrated analog multiplexers (2) - :cell:`sky130_fd_io__gpio*`
-*  IP has multiple Power/Ground pads with HV and LV clamps, diodes, Test pads to enable I/O ring assembly
-*  VDDIO and VDDD power detector
-*  Multiple flavors of XRES cells
-*  For complete set of feature comparison, see :numref:`io features comparison`
-*  AIP/LEDA rules set compliant : 5.0
-
-
-Design Metrics
---------------
-
-
-.. table:: Design Metrics-1
-   :name: design-metrics-1
-
-   +--------------------------------+--------------+------------+
-   | Description                    | Active Mode  | Deep Sleep |
-   +================================+==============+============+
-   | Output: Fmax Freq              | 33MHz        | 33Mhz      |
-   +--------------------------------+--------------+------------+
-   | Output: Fmax Freq              | 33MHz        | 33Mhz      |
-   +--------------------------------+--------------+------------+
-   | SE Input: Fmax Freq            | 66MHz        | 66MHz      |
-   +--------------------------------+--------------+------------+
-   | Number of power domains        | 5                         |
-   +--------------------------------+---------------------------+
-   | Number of power modes          | *  Active                 |
-   |                                | *  Hibernate              |
-   |                                | *  Deep Sleep             |
-   |                                | *  Stop                   |
-   +--------------------------------+---------------------------+
-   | Single-ended Input buffer      | I2C complaint             |
-   | hysteresis (ALL I/O)           |                           |
-   +--------------------------------+---------------------------+
-   | Rise/Fall trip point for       | 0.7V-1.5V                 |
-   | VDDD detector                  |                           |
-   +--------------------------------+---------------------------+
-   | Rise/Fall trip point for       | 0.7V-1.5V                 |
-   | VDDIO detector                 |                           |
-   +--------------------------------+---------------------------+
-   | Simulation Temperature Range   | -40C to 100C              |
-   +--------------------------------+---------------------------+
-   | * Simulation Voltage range I/O | 1.65V-5.5V                |
-   | * Analog Supply                |                           |
-   +--------------------------------+---------------------------+
-   | * Simulation Voltage range I/O | 1.60V-1.95V               |
-   | * LV Digital Supply            |                           |
-   +--------------------------------+---------------------------+
-
-.. table:: Design Metrics-2
-   :name: design-metrics-2
-
-   +---------------------------+------------+-----------+------------+
-   | :cell:`sky130_fd_io__sio` | 2.0V       | 3.3V      | 5.0V       |
-   | Differential Input buffer |            |           |            |
-   +===========================+============+===========+============+
-   | Quiescent current         | 0.23mA     | 0.25mA    | 0.27mA     |
-   +---------------------------+------------+-----------+------------+
-   | ICC @ Fmax                | 0.35mA     | 0.40mA    | 0.50mA     |
-   +---------------------------+------------+-----------+------------+
-   | Voltage trip point (SIO)  | Vinref±200mV                        |
-   +---------------------------+-------------------------------------+
-
-.. table:: Design Metrics-3
-   :name: design-metrics-3
-
-   +-----------------------------------+-------------+-----------+
-   |                                   | ``tt_leak`` | ``leak``  |
-   |                                   | 3.0V, 25C   | 3.0V, 85C |
-   +===================================+=============+===========+
-   | * :cell:`sky130_fd_io__gpio*` ISB | 0.17nA      | 89.63nA   |
-   | * ``enable_h`` = 0                |             |           |
-   +-----------------------------------+-------------+-----------+
-   | * :cell:`sky130_fd_io__sio` ISB   | 0.22nA      | 40.29nA   |
-   | * ``enable_h`` = 0                |             |           |
-   +-----------------------------------+-------------+-----------+
-
-.. table:: Design Metrics-4
-   :name: design-metrics-4
-
-   +----------------------------------------------------+----------------------+
-   | :cell:`sky130_fd_io__gpio*` AMUX switch resistance | *  275 : CSD Range   |
-   |                                                    | *  1000 : Full Range |
-   +----------------------------------------------------+----------------------+
-
-Configuration Options
----------------------
-
-* ALL I/O: Input and Output buffers can be enabled independently
-* ALL I/O: Input buffer trip point select between CMOS/I2C & LVTTL
-* ALL I/O: Configurable for 8 different Output drive modes
-* ALL I/O: Output can be configured for different slew rates
-* ALL I/O: I/O buffer can be configured into low power or low leakage mode using hold state control signals
-* ALL I/O: O/P Buffer can be configured to drive the PAD during deep sleep mode
-* :cell:`sky130_fd_io__sio` output buffer can be cured to be CMOS or Regulated output high level buffer (only in Strong Pull up mode)
-* :cell:`sky130_fd_io__gpiov2`, :cell:`sky130_fd_io__gpio_ovtv2` to handle 1.8V signaling on pad
-* :cell:`sky130_fd_io__gpio_ovtv2` input buffer supports selectable trip point feature
-
-Typical Application
--------------------
-
-The SKY130 IO cells are typically used to build the I/O ring around the chip core.
-In addition to I/O's, Power/Ground cells, ESD clamps, Bond pad etc.
-are also available in this IP.
-I/O's are used to communicate with the external world and acts as the interface/buffer between the chip core and the external system.
-
-Power Performance
------------------
-
-The I/O's support multiple power modes (Hibernate, Deep Sleep, Stop) which are low-power modes, while still retaining the state of the I/O.
-
-FMEA
-----
-
-Rail-Based ESD
-~~~~~~~~~~~~~~
-
-The ESD strategy for M0S8 platform is non-distributed (grouped) rail-based ESD.
-This will be implemented across all pins and the ESD scheme can be fully simulated and easily portable across technologies.
-
-Architecture and Implementation details
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The different components needed to build the I/O ring are - :cell:`sky130_fd_io__gpio` :cell:`sky130_fd_io__sio`, ESD RC Clamps (which sit inside the Power/Ground PADS).
-Each external power domain will be protected with its own ESD RC clamp.
-There will be ESD diodes from each of the derived supplies to the source supply.
-For this purpose, two types of ESD RC clamps will be developed - HV Clamp and LV clamp.
-
-Alternate XRES implementation
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The glitch filter and 5k pull-up resistor in the current :cell:`sky130_fd_io__top_xres_2` are provided as separate cells.
-A PMOS switch is used to disable the pull-up resistor.
-
-.. figure:: figures/sky130_fd_io__top_axresv2.png
-   :name: alternate xres implementation
-   :width: 3.58056in
-   :height: 1.25347in
-
-   Alternate XRES Implementation
-
-
-Critical Requirements Summary
-=============================
-
-Overview of Block Applications
-------------------------------
-
-The Data I/O circuitry is used to communicate with other components in a PC board environment.
-The circuit also has the capability of shifting between core level voltages and I/O level voltages.
-
-The buffers support a power supply range of 1.71V to 5.5V.
-
-Block Architecture Overview
----------------------------
-
-The following sections describe each of the blocks in detail:
-
-.. contents:: :local:
-   :depth: 1
-
-Block Description
-~~~~~~~~~~~~~~~~~
-
-The SKY130 IO cells is a toolkit IP.
-It contains all the cells and primitives required to construct an I/O ring in the SKY130 technology.
-
-Additional details of the cells included can be found in the sections below.
-
-This :lib:`sky130_fd_io` library contained in this document covers different kinds of I/O cells, a general purpose I/O (:cell:`sky130_fd_io__gpio`)
-and a special I/O (:cell:`sky130_fd_io__sio`), a reference generator (:cell:`sky130_fd_io__refgen`) for providing voltage references to the :cell:`sky130_fd_io__sio` and Power and Ground (PG)
-cells that make up the I/O ring.
-
-A single table comparison of all features across different IO's is provided in :numref:`io features comparison`.
-
-.. io-common-features_
-
-I/O\ [1]_ Common Features
-~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The :cell:`sky130_fd_io__gpio` and :cell:`sky130_fd_io__sio` buffers contain the following common features:
-
-.. contents:: :local:
-   :depth: 1
-
-.. [1] I/O (:cell:`sky130_fd_io__gpio`, :cell:`sky130_fd_io__gpiosf`, :cell:`sky130_fd_io__gpiov2`, :cell:`sky130_fd_io__gpio_ovtv2`, SIO).
-
-
-The features that are supported by different I/O's are documented in :numref:`io features comparison` below:
-
-.. table:: Comparison of features across different I/O's provided in this IP
-   :name: io features comparison
-
-   +-------------------+-----------------------------+---------------------------------+------------------------------+----------------------------------+
-   | Feature           | :cell:`sky130_fd_io__gpio*` | :cell:`sky130_fd_io__sio_macro` | :cell:`sky130_fd_io__gpiov2` | :cell:`sky130_fd_io__gpio_ovtv2` |
-   +===================+=============================+=================================+==============================+==================================+
-   | Drive Capability  | 4mA                         | 4mA                             | 4mA                          | 4mA                              |
-   | (Source) [2]_     |                             |                                 |                              |                                  |
-   +-------------------+-----------------------------+---------------------------------+------------------------------+----------------------------------+
-   | Drive Capability  | 4mA [3]_                    | 20mA [5]_                       | 4mA [3]_                     | 10mA [3]_                        |
-   | (Sink)            |                             |                                 |                              |                                  |
-   +-------------------+-----------------------------+---------------------------------+------------------------------+----------------------------------+
-   | Drive Modes       | 8-Modes                     | 8-Modes                         | 8-Modes                      | 8-Modes                          |
-   +-------------------+-----------------------------+---------------------------------+------------------------------+----------------------------------+
-   | Slew Rate Control | Slow/Fast                   | Slow/Fast                       | Slow/Fast                    | Slow/Fast/I2C                    |
-   +-------------------+-----------------------------+---------------------------------+------------------------------+----------------------------------+
-   | Input Buffer      | CMOS/TTL                    | CMOS/TTL                        | CMOS/TTL/1.8V                | CMOS/TTL/1.8V/Selectable         |
-   | trip point        |                             |                                 |                              |                                  |
-   +-------------------+-----------------------------+---------------------------------+------------------------------+----------------------------------+
-   | Over-Voltage      | No                          | Yes                             | No                           | Yes                              |
-   | Tolerance         |                             |                                 |                              |                                  |
-   +-------------------+-----------------------------+---------------------------------+------------------------------+----------------------------------+
-   | Analog Mux        | 2                           | 0 [4]_                          | 2                            | 2                                |
-   +-------------------+-----------------------------+---------------------------------+------------------------------+----------------------------------+
-   | Regulated Output  | No                          | Yes                             | No                           | No                               |
-   +-------------------+-----------------------------+---------------------------------+------------------------------+----------------------------------+
-   | Input buffer type | SE                          | SE+Diff                         | SE                           | SE                               |
-   +-------------------+-----------------------------+---------------------------------+------------------------------+----------------------------------+
-   | I2C Compliance    | Limited [5]_                | Limited [5]_                    | Standard,Fast                | * Standard                       |
-   |                   |                             |                                 |                              | * Fast                           |
-   |                   |                             |                                 |                              | * Fast-Plus [6]_                 |
-   |                   |                             |                                 |                              | * High-Speed                     |
-   +-------------------+-----------------------------+---------------------------------+------------------------------+----------------------------------+
-   | Low-voltage       | No                          | No                              | Yes                          | Yes                              |
-   | DFT support       |                             |                                 |                              |                                  |
-   +-------------------+-----------------------------+---------------------------------+------------------------------+----------------------------------+
-   | Hysteresis [7]_   | 5%                          | 5%                              | 10% [8]_                     | 10% [8]_                         |
-   +-------------------+-----------------------------+---------------------------------+------------------------------+----------------------------------+
-
-.. [2] For 3V range. :cell:`sky130_fd_io__sio` configured in unregulated mode.
-.. [3] VDDIO≥1.71V.
-.. [4] SIO interacts with the analog mux for ADFT of :cell:`sky130_fd_io__refgen`.
-.. [5] Limited - Compliant for limited ranges of Vext, Rext and Cbus.
-.. [6] 20mA support for VDDIO>2.9V.
-.. [7] Input Buffer operating at 48 MHz w hen VCCHIB=1.4V, VDDIO=1.65V
-.. [8] For CMOS mode only.
-
-Eight drive strength modes
-^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The IP includes three static drive mode bits (dm<2:0>).
-These bits are used to configure the output buffer drive strength.
-A default setting for enabling or disabling the input and output buffer is also defined.
-The eight drive strength modes are defined in the following table.
-
-.. table:: Truth table for I/O Drive Strength Modes
-   :name: io drive strength modes
-
-   +-------------+----------+---------+-----------------+----------+----------+---------------------------------+
-   | ``inp_dis`` | ``oe_n`` | dm<2:0> | Pad State       | Input    | Output   | Mode Description                |
-   |             |          |         +--------+--------+ Buffer   | Buffer   |                                 |
-   |             |          |         | out=1  | out=0  |          |          |                                 |
-   +=============+==========+=========+========+========+==========+==========+=================================+
-   | X           | X        | 000     | Hi- Z  | Hi- Z  | Disabled | Disabled | * Input/Output buffers disabled |
-   |             |          |         |        |        | (in=0)   |          | * Analog Input Mode             |
-   +-------------+----------+---------+--------+--------+----------+----------+---------------------------------+
-   | 0           | X        | 001     | Hi- Z  | Hi- Z  | Enabled  | Disabled | Configured as Input only        |
-   +-------------+----------+---------+--------+--------+----------+----------+---------------------------------+
-   | 0           | 0        | 010     | Res 1  | Strong | Enabled  | Enabled  | * Weak pull-up,                 |
-   |             |          |         | (5k)   | 0      | (in=0)   |          | * strong pull-down              |
-   +-------------+----------+---------+--------+--------+----------+----------+---------------------------------+
-   | 0           | 0        | 011     | Strong | Res 0  | Enabled  | Enabled  | * Strong pull-up                |
-   |             |          |         | 1      | (5k)   | (in=0)   |          | * Weak pull-down                |
-   +-------------+----------+---------+--------+--------+----------+----------+---------------------------------+
-   | 0           | 0        | 100     | Hi- Z  | Strong | Enabled  | Enabled  | * Open Drain                    |
-   |             |          |         |        | 0      | (in=0)   |          | * Strong pull-down              |
-   +-------------+----------+---------+--------+--------+----------+----------+---------------------------------+
-   | 0           | 0        | 101     | Strong | Hi- Z  | Enabled  | Enabled  | * Open Drain                    |
-   |             |          |         | 1      |        | (in=0)   |          | * Strong pull-up                |
-   +-------------+----------+---------+--------+--------+----------+----------+---------------------------------+
-   | 0           | 0        | 110     | Strong | Strong | Enabled  | Enabled  | * Strong pull-up                |
-   |             |          |         | 1      | 0      | (in=0)   |          | * Strong pull-down              |
-   +-------------+----------+---------+--------+--------+----------+----------+---------------------------------+
-   | 0           | 0        | 111     | Res 1  | Res 0  | Enabled  | Enabled  | * Weak pull-up                  |
-   |             |          |         | (5k)   | (5k)   | (in=0)   |          | * Weak pull-down                |
-   +-------------+----------+---------+--------+--------+----------+----------+---------------------------------+
-   | 1           | X        | XXX     |        |        | Disabled |          | Input buffer disabled           |
-   +-------------+----------+---------+--------+--------+----------+----------+---------------------------------+
-   | X           | 1        | XXX     | Hi-Z   | Hi-Z   |          | Disabled | Output buffer tri-stated        |
-   +-------------+----------+---------+--------+--------+----------+----------+---------------------------------+
-
-*X = don't care 0/1*
-
-Independent control of input and output buffer enables
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The I/O cells also include separate input disable ``inp_dis`` and output enable ``oe_n`` control signals as shown in :numref:`io drive strength modes`.
-When ``inp_dis`` = 0 the input buffer is enabled and when ``oe_n`` = 0 the output buffer is enabled.
-When these signals are high (logic 1) the corresponding buffers are disabled independent of the state of the drive mode bits dm<2:0>.
-For example, if drive mode 2 (dm<2:0>=010) is selected, the input buffer is enabled by default.
-If ``inp_dis=1`` for this drive mode, the input buffer enable default state will be overridden and the input buffer will be disabled and the input buffer
-output will be driven low.
-
-Input buffer threshold select
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The ``vtrip_sel`` signal alters the input buffer Vil and Vih specifications.
-The Vil and Vih specifications are listed in the following table.
-
-.. table:: I/O Vil & Vih Specifications
-   :name: io vil vih
-
-   +----------+-------------+-------+----------------+-----------------+-----------------+
-   | Prameter | Description | Units | Condition      | ``vtrip_sel=0`` | ``vtrip_sel=1`` |
-   +==========+=============+=======+================+=================+=================+
-   | VIL      | Input Low   | V     | * vddio < 2.7V | 0.3 \* vddio    | * 0.3 \* vddio  |
-   |          | Voltage     |       | * vddio > 2.7V |                 | * 0.8           |
-   +----------+-------------+-------+----------------+-----------------+-----------------+
-   | VIH      | Input High  | V     | * vddio < 2.7V | 0.7 \* vddio    | * 0.7 \* vddio  |
-   |          | Voltage     |       | * vddio > 2.7V |                 | * 2.0           |
-   +----------+-------------+-------+----------------+-----------------+-----------------+
-
-When ``vtrip_sel`` = 0, the input buffer functions as a CMOS input buffer.
-When ``vtrip_sel`` = 1, the input buffer functions as an LVTTL input buffer.
-
-I/O supply and Internal supply level input buffer outputs
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The input buffer produces two outputs, a low voltage output and a high voltage output.
-The low voltage output is produced by level shifting the external ``vddio`` referenced level input to the internal ``vcchib`` level output.
-The high voltage output is produced by not level shifting the external ``vddio`` referenced level input to a buffered internal ``vddio_q`` level output.
-
-Selectable output edge rate control
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The CMOS output buffer includes a slew rate control input signal ``slow``.
-When this signal is activated (slow = 1) the output edge rate will be slower than the default setting (slow = 0).
-
-Hold state mode (latch previous state)
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The I/O cell includes a hold state control signal ``hld_h_n``.
-The purpose of this signal is to place the I/O cell into a low leakage mode while holding the previous state of the input controls, output controls
-and data.
-``hld_h_n`` latches all control signals except ``enable_h``.
-Specific timing constraints between the ``hld_h_n`` input and the other control signals must be satisfied to when entering and exiting the hold state
-mode.
-The Input signals which are latched by ``hld_h_n`` are dm<2:0>, slow, ``vtrip_sel``, ``inp_dis``, out, ``oe_n``.
-The input signals, ``ibuf_sel``, ``vreg_en``, in :cell:`sky130_fd_io__sio` cell are also latched by ``hld_h_n``.
-
-During the hold mode, vccd can either be taken down to 0 or can float.
-During this case, the I/O input buffer would continue to actively drive out as long as there are valid power supplies (vddio, vddio_q and vcchib).
-
-During the hold mode, the O/P can be configured to drive the PAD as described in Feature 9.
-
-I/O Mode Control Override during Power-up
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The :cell:`sky130_fd_io__gpio` includes an I/O mode control override signal ``enable_h`` that is different from the ``oe_n`` signal.
-The signal ``enable_h=0`` forces the output drive mode to Hi-Z.
-The ``enable_h`` signal is intended to be at logic 0 during the chip power-up sequence.
-During the power-up sequence this signal is driven low and the output driver is forced to a known state (Hi-Z).
-This ensures that the output driver does not enter a crow-bar condition.
-
-Before the power-up sequence is completed, and the ``enable_h`` signal is asserted (logic 1), the data inputs and the control signals must be stable to
-ensure that the output driver does not inadvertently enter a crow-bar condition while exiting the power-up sequence.
-
-The ``enable_h`` signal takes priority over the ``hld_h_n`` signal.
-In other words, when the I/O mode control override signal ``enable_h`` is logic 0 and the ``hld_h_n`` control signal is active, the output driver will
-be forced to drive Hi-Z.
-The previous states on the pull-up and pull-down signals will be over written and set to the levels required to force the driver.
-If the ``hld_h_n`` signal remains active after the ``enable_h`` signal transitions from logic 0 to logic 1, the forced condition (Hi-Z) will be held.
-:numref:`mode control override and hold state` describes the ``enable_h``, ``hld_h_n`` functionality.
-
-.. table:: :cell:`sky130_fd_io__gpio` Mode Control Override & Hold State Operation
-   :name: mode control override and hold state
-
-   +--------------+-------------+--------------+--------------+--------------------------------------------------+
-   | ``enable_h`` | ``hld_h_n`` | Previous pad | Current pad  | Notes                                            |
-   |              |             | Output state | Output State |                                                  |
-   +==============+=============+==============+==============+==================================================+
-   | 1            | 0           | 0            | 0            |                                                  |
-   +--------------+-------------+--------------+--------------+--------------------------------------------------+
-   | 1            | 0           | 1            | 1            |                                                  |
-   +--------------+-------------+--------------+--------------+--------------------------------------------------+
-   | 1            | 0           | Hi-Z         | Hi-Z         |                                                  |
-   +--------------+-------------+--------------+--------------+--------------------------------------------------+
-   | 1            | 1           | Table 4.2-1  | Table 4.2-1  |                                                  |
-   +--------------+-------------+--------------+--------------+--------------------------------------------------+
-   | 0            | X           | X            | Hi-Z         | * Input buffer disabled;                         |
-   |              |             |              |              | * Output buffer Hi-Z (configured as dm<2:0>=000) |
-   +--------------+-------------+--------------+--------------+--------------------------------------------------+
-
-Note that there is no latch present on the ``pad`` itself, but the data ``in`` gets latched whenever ``hld_h_n=0``.
-Further whenever ``enable_h=0``, this data level shifter gets forced to a value which determines the ``pad`` current output state.
-
-Pad Access to the Core
-^^^^^^^^^^^^^^^^^^^^^^
-
-The I/O provides pad access to the core.
-``pad_no_esd_h`` is directly connected to the pad.
-``pad_a_esd_0_h`` and ``pad_a_esd_1_h`` is connected to the pad through a 150 ohm ESD resistor.
-
-O/P configuration to drive the PAD in hold mode
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The hold over ride signal (``hld_ovr``, active high, vcchib domain) signals the O/P buffer when to provide the flow-through functionality of the data
-input to the output buffer and output enable in deep sleep mode.
-
-The functionality is defined in :numref:`normal and hold modes`.
-
-.. table:: Functionality during normal and hold modes
-   :name: normal and hold modes
-
-   +-------------+-------------+-----------+-----------+
-   | ``hld_ovr`` | ``hld_h_n`` | in        | ``oe_n``  |
-   +=============+=============+===========+===========+
-   | 0           | 0           | Latched   | Latched   |
-   +-------------+-------------+-----------+-----------+
-   | 0           | 1           | Normal    | Normal    |
-   +-------------+-------------+-----------+-----------+
-   | 1           | 0           | Over-ride | Over-ride |
-   +-------------+-------------+-----------+-----------+
-   | 1           | 1           | Normal    | Normal    |
-   +-------------+-------------+-----------+-----------+
-
-.. note::
-   - Latched means that the input and output enable are latched. This is the same functionality as mentioned in :numref:`io vil vih`.
-   - Normal refers any mode other than Sleep modes
-
-:cell:`sky130_fd_io__gpio` Additional Features
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The block diagram for the :cell:`sky130_fd_io__gpio` is shown in :numref:`sky130_fd_io__top_gpio block diagram`.
-Note: Bus notation dm[3] denotes a 3 bit bus dm[2:0].
-These notations are interchangeably used in the document.
-
-.. figure:: figures/sky130_fd_io__gpio.png
-   :name: sky130_fd_io__top_gpio block diagram
-   :width: 5.69792in
-   :height: 7.07292in
-
-   Block diagram for :cell:`sky130_fd_io__top_gpio`
-
-All :cell:`sky130_fd_io__gpio` provides additional functionality of analog connectivity to the PAD for CSD and other applications as described
-below:
-
-:cell:`sky130_fd_io__gpio` Analog Connectivity Modes
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The M0S8 :cell:`sky130_fd_io__gpio` integrates the AMUXBUS switches to two ``AMUXBUS_A`` and ``AMUXBUS_B`` analog buses.
-These buses are used for both Capsense operation (as described in the CSD chapter), and general analog connectivity for Programmable Analog blocks and
-ADFT.
-
-The analog functionality is controlled using three control signals.
-
--  ``analog_en`` enables the analog functions of the :cell:`sky130_fd_io__gpio` cell
-
--  ``analog_sel`` selects between ``AMUXBUS_A`` and ``AMUXBUS_B``
-
--  ``analog_pol`` selects the function of the ``out`` input, which toggles between AMUXBUS and VSSIO or between VDDIO and AMUXBUS
-
-:numref:`analog functionality` describes the analog functionality as selected by the relevant control signals:
-
-.. table:: Analog functionality by the relevant control signals
-   :name: analog functionality
-
-   +-------------------------------------------------+-------------------------------+-------------------------+
-   |                                                 | Analog Function               | Digital Function        |
-   +---------------+----------------+----------------+---------------+---------------+------------+------------+
-   | ``analog_en`` | ``analog_sel`` | ``analog_pol`` | out=0         | out=1         | Input      | Output     |
-   +===============+================+================+===============+===============+============+============+
-   | 0             | X              | X              | N/C           | N/C           | Unaffected | Unaffected |
-   +---------------+----------------+----------------+---------------+---------------+------------+------------+
-   | 1             | 0              | 0              | Vssio         | ``amuxbus_a`` | Disabled   | Unaffected |
-   +---------------+----------------+----------------+---------------+---------------+------------+------------+
-   | 1             | 0              | 1              | ``amuxbus_a`` | Vddio         | Disabled   | Unaffected |
-   +---------------+----------------+----------------+---------------+---------------+------------+------------+
-   | 1             | 1              | 0              | Vssio         | ``amuxbus_b`` | Disabled   | Unaffected |
-   +---------------+----------------+----------------+---------------+---------------+------------+------------+
-   | 1             | 1              | 1              | ``amuxbus_b`` | Vddio         | Disabled   | Unaffected |
-   +---------------+----------------+----------------+---------------+---------------+------------+------------+
-
-Note that digital output driver can be used concurrent with analog function
-
-Note the following: When the I/O is in an ``analog`` mode, the digital input buffer is disabled, but the output driver is not.
-Both CSD and certain Programmable Analog applications make use of the digital output driver as a driver on analog signals/nodes.
-The output driver performs the function as selected by its dm[3] inputs (which may be either OFF or not).
-
-Note that these modes only concern analog functions ``internal`` to the :cell:`sky130_fd_io__gpio`, i.e.
-using the internal AMUXBUS switches.
-
-*Shielding for Analog Mux busses:* AMUX switches can also be used to source and sink currents from CSD IDAC block to :cell:`sky130_fd_io__gpio` pins.
-The current IDAC for CSD block can be used to supply/ source current through AMUX to any :cell:`sky130_fd_io__gpio` pin.
-The maximum current can be up to 1mA and thus the AMUX layout needs to be designed keeping EM/IR considerations in mind.
-
-*Usage of ``VSSIO_Q`` in AMUX:* The CSD pull-down transistor used in AMUX is the only one that uses the ``vssio_q`` connection to the I/O.
-In case the AMUX is used for CSD operation, ``vssio_q`` can alternatively be connected to VSSA without concerns for noise.
-Care must be taken that VSSIO and ``VSSIO_Q`` should not be shorted at VSSIO pad when used in this configuration.
-
-Changes to Analog Mux for :cell:`sky130_fd_io__gpiov2` and :cell:`sky130_fd_io__gpio_ovtv2`
-*******************************************************************************************
-
-1. The input buffer is no longer disabled inside :cell:`sky130_fd_io__gpiov2` and :cell:`sky130_fd_io__gpio_ovtv2` automatically when analog mux is
-   enabled (``analog_en=1``).
-   This was done to unblock self-testing of I/O cells.
-   The firmware needs to ensure that ``inp_dis=1`` when ``analog_en=1``.
-
-2. Power mode behavior was modified for both :cell:`sky130_fd_io__gpiov2` and :cell:`sky130_fd_io__gpio_ovtv2`.
-   An extra control signal ``enable_vswitch_h`` is added to have better control over the power mode behavior.
-   The following table gives the supplies, control signals and their role:
-
-.. list-table:: Supplies, control signals and their definition
-   :name: supplies control signals
-   :widths: 10 90
-   :header-rows: 1
-
-   * - Signal
-     - I/O-Behavior
-   * - vddio
-     - Digital supply for the I/O-cell. This supply is used to implement all digital input/output functions. It can be connected to the main system digital supply (vddd) or to an independent vddio supply.
-   * - vdda
-     - Analog supply for the I/O-cell. This supply is used to implement the analog switches associated with amuxbus and CSD behavior. This supply is either connected to the global analog supply in the system or tied off to vddio when amuxbus functionality is not used.
-   * - vccd
-     - The main regulated (1.8V) core supply. This supply is the relative supply of most of the configuration/control signals coming into the I/O-cell and is used for level translation only. No I/O circuits are powered using this supply.
-   * - vcchib
-     - The hibernate regulated supply (1.8V). This supply is the relative supply for the I/O data interface (in, out, ``oe_n``) and is also used mainly for level translation only. This supply can also be used as a reference for the :cell:`sky130_fd_io__gpio` input buffer.
-   * - ``enable_h``
-     - The master enable signal to the I/O-cell's digital section. This signal is in the vddio voltage domain. This signal is guaranteed to establish early during the vddio power ramp to enable glitch free operation during power up and down ramps. When asserted (1), this signal guarantees that vddio is valid and that either ``hld_h_n=0`` or all LV control signals are valid.
-   * - ``enable_inp_h``
-     - This signal must be tied off to 0 or 1. Its value controls the power state of the input buffer when ``enable_h=0``. This is a special feature used on 2 I/O-cells to allow for test-mode entry while XRES=0.
-   * - ``enable_vdda_h``
-     - The master enable signal to the I/O-cell's analog section. This signal is guaranteed to establish early during the power ramp to enable glitch free operation during power up and down ramps. It is used to power up/down all vdda powered circuits in the I/O-cell. When asserted (1), this signal guarantees that vdda and vddio are valid, and that either ``hld_h_n=0`` or all LV control signals are valid.
-   * - ``enable_vswitch_h``
-     - A signal that controls the use of the pumped-up vswitch supply. When asserted (1), this signal guarantees that vswitch and vdda and vddio are valid, and that either ``hld_h_n=0`` or all LV control signals are valid.
-   * - ``enable_vddio``
-     - A signal that controls the use of the vcchib supply in some of the I/O circuits. When asserted (1), this signal guarantees that vcchib and all HV supplies are valid, and that either ``hld_h_n=0`` or all LV control signals are valid.
-   * - ``hld_h_n``
-     - This signal controls the iso-latches in the I/O-cell. It transitions low to freeze the state of the I/O-cell such that the active supply can be removed and the IO continues to function as configured.
-   * - ``hld_ovr``
-     - When ``hld_h_n=1`` this signal is ignored, when ``hld_h_n=0`` all control signals including this signal are frozen. The frozen value of this signal determines if the ``out`` and ``oe_n`` are frozen or not.  0: the I/O latches all of its configuration and control inputs as well as out and ``oe_n``. 1: only the configuration and control inputs are latched.  The logic in IOSS makes sure that ``hld_ovr=1`` never occurs when the system goes into STOP mode (which removes vcchib).
-
-
-The normal operational state of the analog mux is when all supplies are present and all qualifiers asserted.
-However, there are many transient and special states that occur during power sequencing and during low power modes.
-
-Input buffer enable during reset (``enable_inp_h``)
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The ``enable_inp_h`` input determines the power on/off state of the digital input buffer when the I/O is disabled; i.e.
-``enable_h`` is ``0``.
-This pin is intended to be tied off to 0 or 1 (using the ``tie_hi_esd`` and ``tie_lo_esd`` signals on the I/O cell), depending on the need to have the
-input buffer enabled while ``enable_h=0``.
-The truth table for ``enable_inp_h`` is given below in :numref:`enable_inp_h truth table`:
-
-.. table:: ``enable_inp_h`` truth table
-   :name: enable_inp_h truth table
-
-   +--------------+------------------+---------------+---------------+
-   | ``enable_h`` | ``enable_inp_h`` | * ``Inp_dis`` | Input Buffer  |
-   |              |                  | * dm[3]       | State         |
-   +==============+==================+===============+===============+
-   | 0            | 0                | X             | Disabled      |
-   +--------------+------------------+---------------+---------------+
-   | 0            | 1                | X             | Enabled       |
-   +--------------+------------------+---------------+---------------+
-   | 1            | X                | Valid         | F(``inp_dis`` |
-   |              |                  |               | , dm[3])      |
-   +--------------+------------------+---------------+---------------+
-
-
-Use of ``enable_inp_h`` at chip level: ``enable_inp_h`` is a hard-tie to either ``tie_hi_esd`` or ``tie_lo_esd`` of the :cell:`sky130_fd_io__gpio` and
-should not be register controlled.
-The ``enable_inp_h`` functionality is used to implement the Power-On-Reset Bypass Mode in SRSSv2: while XRES is asserted, SRSSv2 listens for a magic key
-on the SWD interface.
-This requires that primary SWD interface :cell:`sky130_fd_io__gpio` cells have their input buffers enabled, while XRES is asserted (``enable_inp_h`` is
-``tie_hi_esd``).
-All other :cell:`sky130_fd_io__gpio` cells have their input buffers disabled while XRES is asserted (``enable_inp_h`` is ``tie_lo_esd``).
-
-:cell:`sky130_fd_io__gpiov2` Additional Features
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The block diagram for :cell:`sky130_fd_io__gpiov2` is shown below in :numref:`sky130_fd_io__gpiov2 block diagram`.
-Note: bus notation dm[3] denotes a 3 bit bus dm[2:0].
-These notations are used interchangeably in the document.
-
-.. figure:: figures/sky130_fd_io__top_gpiov2.png
-   :name: sky130_fd_io__gpiov2 block diagram
-   :width: 5.55000in
-   :height: 7.57000in
-
-   :cell:`sky130_fd_io__gpiov2` Block Diagram
-
-:cell:`sky130_fd_io__gpiov2` provides all functionality as the original :cell:`sky130_fd_io__gpio` does.
-In addition, it provides the following extra features:
-
--  Improved hysteresis of 10% across the entire supply range in CMOS mode
-
--  Improved hysteresis of 100mV in LVTTL mode
-
--  Improvements to meet I2C fall time with a certain minimum bus cap. Support only for Standard and Fast I2C modes. :numref:`sky130_fd_io__gpiov2 output buffer` gives the different output buffer configurations.
-
--  Supports 1.8V signaling on PAD independent of vddio.
-
-   1. Full spec support for Vcchib ≥ 1.6
-
-   2. Limited functional support down to Vcchib ≥ 1.4 (Deep-sleep mode). 15Mhz CMOS operation.
-
--  Improvements to the analog mux to support multiple power modes.
-
--  Low-voltage DFT support (Input buffer runs at lower supply voltage than spec'ed)
-
-Following additional pins have been added to support some of the above features:
-
--  ``ib_mode_sel:`` This signal is used select between VDDIO and VCCHIB based thresholds (0=VDDIO, 1=VCCHIB)
-
--  ``enable_vddio:`` This qualifier lets the :cell:`sky130_fd_io__gpio` know that VDDIO is either present (1) or absent (0) in VCCHIB domain. Currently, a skew of 100ns is allowed between ``enable_h`` and ``enable_vddio``
-
--  ``enable_vswitch_h:`` These qualifiers let the :cell:`sky130_fd_io__gpio` know that VSWITCH is either present (1) or absent (0) in VSWITCH domain
-
-Input Buffer selection for :cell:`sky130_fd_io__gpiov2` is explained below in :numref:`sky130_fd_io__gpiov2 input buffer trip point`:
-
-.. table:: Input Buffer Trip point selection for :cell:`sky130_fd_io__gpiov2`
-   :name: sky130_fd_io__gpiov2 input buffer trip point
-
-   +--------+-----------------+---------------+-------------------------+--------------------+
-   | Mode   | ``ib_mode_sel`` | ``vtrip_sel`` | Input Buffer Trip Point | Description        |
-   +========+=================+===============+=========================+====================+
-   | CMOS   | 0               | 0             | 30%/70% of Vddio        | CMOS input buffer  |
-   +--------+-----------------+---------------+-------------------------+--------------------+
-   | TTL    | 0               | 1             | * VIL=0.8V, Vddio>2.7V  | LVTTL input buffer |
-   |        |                 |               | * VIH=2.0V, Vddio>2.7V  |                    |
-   +--------+-----------------+---------------+-------------------------+--------------------+
-   | VCCHIB | 1               | 0/1           | VIH=1.26V, VIL=0.54V    | Supports 1.8V      |
-   |        |                 |               |                         | signaling on PAD   |
-   +--------+-----------------+---------------+-------------------------+--------------------+
-
-.. note::
-    If :cell:`sky130_fd_io__gpiov2` or :cell:`sky130_fd_io__gpio_ovtv2` is used to catch an external interrupt in hibernate mode, then care must be
-    taken to have ``ib_mode_sel`` in logic 0 state before entering low-power modes.
-
-    This is because VCCHIB mode will not work in hibernate mode.
-
-
-.. table:: :cell:`sky130_fd_io__gpiov2` output buffer configurations
-   :name: sky130_fd_io__gpiov2 output buffer
-
-   +---------+----------+------+-------------------+-------------------+---------------------+---------------------------+
-   | dm[3]   | ``oe_n`` | slow | Driver PU         | Driver PU         | Driver PD           | Description               |
-   |         |          |      | (Rise Time Specs) | (Rise Times- Sch) | (Fall Time Specs)   |                           |
-   +=========+==========+======+===================+===================+=====================+===========================+
-   | 000/001 | x        | x    | Disabled          | Disabled          | Disabled            | Tri-state                 |
-   +---------+----------+------+-------------------+-------------------+---------------------+---------------------------+
-   | x       | 1        | x    | Disabled          | Disabled          | Disabled            | Tri-state                 |
-   +---------+----------+------+-------------------+-------------------+---------------------+---------------------------+
-   | 010     | 0        | 0    | Resistive (5K)    |                   | Strong-Fast         | * WPU                     |
-   |         |          |      |                   |                   | (2-12ns)            | * SPD Mode                |
-   |         |          |      |                   |                   |                     | * 25pF load               |
-   +---------+----------+------+-------------------+-------------------+---------------------+---------------------------+
-   | 010     | 0        | 1    | Resistive (5K)    |                   | Strong-Slow         |                           |
-   |         |          |      |                   |                   | (10-60ns)           |                           |
-   +---------+----------+------+-------------------+-------------------+---------------------+---------------------------+
-   | 011     | 0        | 0    | Strong-Fast       |                   | Resistive (5K)      | * SPU                     |
-   |         |          |      | (2-12ns)          |                   |                     | * WPD Mode                |
-   |         |          |      |                   |                   |                     | * 25pF load               |
-   +---------+----------+------+-------------------+-------------------+---------------------+---------------------------+
-   | 011     | 0        | 1    | Strong-Slow       |                   | Resistive (5K)      |                           |
-   |         |          |      | (10-60ns)         |                   |                     |                           |
-   +---------+----------+------+-------------------+-------------------+---------------------+---------------------------+
-   | 100     | 0        | 0    | Open-Drain        |                   | Strong-Fast         | * OPD-PU                  |
-   |         |          |      |                   |                   | (2-12ns)            | * SPD Mode                |
-   |         |          |      |                   |                   |                     | * I2C Standard Mode       |
-   |         |          |      |                   |                   |                     | * I2C FS+ Mode            |
-   +---------+----------+------+-------------------+-------------------+---------------------+---------------------------+
-   | 100     | 0        | 1    | Open-Drain        |                   | I2C Fast Mode       | * I2C Fast Mode           |
-   |         |          |      |                   |                   | (6.22/20ns - 250ns) | * Cbus>200pF              |
-   |         |          |      |                   |                   |                     | * Rext≥1K                 |
-   |         |          |      |                   |                   |                     | * Rext= tr/(0.8463\*Cbus) |
-   +---------+----------+------+-------------------+-------------------+---------------------+---------------------------+
-   | 101     | 0        | 0    | Strong-Fast       |                   | Open-Drain          | * SPU                     |
-   |         |          |      | (2-12ns)          |                   |                     | * OPD-PD Mode             |
-   +---------+----------+------+-------------------+-------------------+---------------------+---------------------------+
-   | 101     | 0        | 1    | Strong-Slow       |                   | Open-Drain          | * WPU                     |
-   |         |          |      | (10-60ns)         |                   |                     | * OPD-PD Mode             |
-   +---------+----------+------+-------------------+-------------------+---------------------+---------------------------+
-   | 110     | 0        | 0    | Strong-Fast       |                   | Strong-Fast         | * SPU                     |
-   |         |          |      | (2-12ns)          |                   | (2-12ns)            | * SPD Mode                |
-   +---------+----------+------+-------------------+-------------------+---------------------+---------------------------+
-   | 110     | 0        | 1    | Strong-Slow       |                   | Strong-Slow         | * SPU                     |
-   |         |          |      | (10-60ns)         |                   | (10-60ns)           | * SPD Mode                |
-   +---------+----------+------+-------------------+-------------------+---------------------+---------------------------+
-   | 111     | 0        | x    | Resistive (5K)    |                   | Resistive (5K)      | * WPU                     |
-   |         |          |      |                   |                   |                     | * WPD Mode                |
-   +---------+----------+------+-------------------+-------------------+---------------------+---------------------------+
-
-
-:cell:`sky130_fd_io__gpio_ovtv2` Additional Features
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-.. figure:: figures/sky130_fd_io__top_gpio_ovtv2.png
-   :name: sky130_fd_io__gpio_ovtv2 block diagram
-   :width: 5.73000in
-   :height: 7.07000in
-
-   :cell:`sky130_fd_io__gpio_ovtv2` Block Diagram
-
-:cell:`sky130_fd_io__gpio_ovtv2` provides all functionality as :cell:`sky130_fd_io__gpiov2` does.
-In addition, it provides the following extra features
-
--  Over-voltage tolerant
-
--  Provides better pull-down drive strength (V:sub:`OL`\ =0.6V @ I\ :sub:`OL`\ =10mA for VDDIO=1.71V)
-
--  Compliance to I2C standard, fast, fast-plus and high-speed modes
-
--  Provides selectable trip points feature. Using an internal reference generator, input buffer trip points can be adjusted over a wide range of value. The max frequency of operation is 66MHz when input signaling is greater than 2.2V. When input signaling is between 1.8V and 2.2V, the max frequency is 33 MHz. The minimum value of input signaling for which full functional specs are met is 1.8v.
-
--  :cell:`sky130_fd_io__gpio_ovtv2` is not critical corner compliant as it uses the MIM cap from :lib:`sky130_fd_pr` library. :cell:`sky130_fd_io__gpio_ovtv2` cannot be placed in corner of the die.
-
-   Following additional pins have been added to support some of the above features:
-
--  ``ib_mode_sel<1:0>:`` Used to configure input buffer trip points. Refer to :numref:`Input Buffer gpio_ovtv2`
-
--  ``hys_trim:`` Used to increase hysteresis feedback for input buffer in ``Ref Mode``. Set to ``1`` for input signaling voltage > 2.2V and ``0`` otherwise.
-
--  ``slew_ctl<1:0>`` : Used to vary slew rate in I2C mode (dm=100). Refer to :numref:`sky130_fd_io__gpio_ovtv2 slew rate control`
-
--  ``enable_vddio_lv:`` This qualifier lets the :cell:`sky130_fd_io__gpio` know that VDDIO is either present (1) or absent (0) in VCCHIB domain
-
--  ``enable_vswitch_h:`` This qualifier lets the :cell:`sky130_fd_io__gpio` know that VSWITCH is either present (1) or absent (0) in VSWITCH domain
-
-Feature: Selectable Trip point feature
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The input buffer in :cell:`sky130_fd_io__gpio_ovtv2` supports the following modes as given in :numref:`Input Buffer gpio_ovtv2` below:
-
-
-.. table:: Input Buffer modes in :cell:`sky130_fd_io__gpio_ovtv2` and their description
-   :name: Input Buffer gpio_ovtv2
-
-   +--------+-----------------+---------------+-----------------------------+-------------------------------------------+
-   | Mode   | ``ib_mode_sel`` | ``vtrip_sel`` | Input Buffer Trip Point     | Description                               |
-   |        | <1:0>           |               |                             |                                           |
-   +========+=================+===============+=============================+===========================================+
-   | CMOS   | 00              | 0             | 30%/70% of Vddio            | CMOS input buffer                         |
-   |        |                 |               |                             |                                           |
-   +--------+-----------------+---------------+--------------+--------------+-------------------------------------------+
-   | TTL    | 00              | 1             | * VIL=0.8V   | * VIH=2.0V   | LVTTL input buffer                        |
-   |        |                 |               | * Vddio>2.7V | * Vddio>2.7V |                                           |
-   +--------+-----------------+---------------+--------------+--------------+-------------------------------------------+
-   | VCCHIB | 01              | 0/1           | * VIH=1.26V                 | Supports 1.8V signalling on PAD           |
-   |        |                 |               | * VIL=0.54V                 |                                           |
-   +--------+-----------------+---------------+-----------------------------+-------------------------------------------+
-   | Ref    | 10/11           | 0/1           | 30%/70% of ``vinref``       | * vinref = VDDIO\*(13n+184)/600           |
-   |        |                 |               |                             | * This feature works in conjunction with: |
-   |        |                 |               |                             | * ::cell:`sky130_fd_io__top_gpiovrefv2`   |
-   |        |                 |               |                             | * ::cell:`sky130_fd_io__top_vrefcapv2`    |
-   +--------+-----------------+---------------+-----------------------------+-------------------------------------------+
-
-.. table:: :cell:`sky130_fd_io__gpio_ovtv2` Slew rate control with slow and ``slew_ctl<1:0>``
-   :name: sky130_fd_io__gpio_ovtv2 slew rate control
-
-   +-------+----------+------+--------------+-------------------+-------------------------------------------+---------------+
-   | dm[3] | ``oe_n`` | slow | ``slew_ctl`` | Driver PU         | Driver PD (Fall Time Specs)               | Description   |
-   |       |          |      | [2]          | (Fall Time Specs) |                                           |               |
-   +=======+==========+======+==============+===================+===========================================+===============+
-   | * 000 | x        | x    | x            | Disabled          | Disabled                                  | Tri-state     |
-   | * 001 |          |      |              |                   |                                           |               |
-   +-------+----------+------+--------------+-------------------+-------------------------------------------+---------------+
-   | x     | 1        | x    | x            | Disabled          | Disabled                                  | Tri-state     |
-   +-------+----------+------+--------------+-------------------+-------------------------------------------+---------------+
-   | 010   | 0        | 0    | x            | Resistive (5K)    | Strong-Fast  (2-12ns)                     | * WPU         |
-   +-------+----------+------+--------------+-------------------+-------------------------------------------+ * SPD Mode    |
-   | 010   | 0        | 1    | x            | Resistive (5K)    | Strong-Slow  (10-60ns)                    | * 25pF load   |
-   +-------+----------+------+--------------+-------------------+-------------------------------------------+---------------+
-   | 011   | 0        | 0    | x            | Strong-Fast       | Resistive (5K)                            | * SPU         |
-   |       |          |      |              | (2-12ns)          |                                           |               |
-   +-------+----------+------+--------------+-------------------+-------------------------------------------+ * WPD Mode    |
-   | 011   | 0        | 1    | x            | Strong-Slow       | Resistive (5K)                            | * 25pF load   |
-   |       |          |      |              | (10-60ns)         |                                           |               |
-   +-------+----------+------+--------------+-------------------+-------------------------------------------+---------------+
-   | 100   | 0        | 0    | x            | Open-Drain        | Strong-Fast  (2-12ns)                     | * OPD-PU      |
-   |       |          |      |              |                   |                                           | * SPD Mode    |
-   +-------+----------+------+--------------+-------------------+-------------------------------------------+---------------+
-   | 100   | 0        | 1    | 11           | Open-Drain        | * HS mode (Vext=<2.8, F=1.7MHz) (10-80ns) | To be used in |
-   |       |          |      |              |                   | * FS+ mode, Vext<=2.8V (20-120ns)         | I2C mode      |
-   |       |          |      +--------------+                   +-------------------------------------------+               |
-   |       |          |      | 01           |                   | * HS mode (Vext>2.8, F=1.7MHz) (10-80ns)  |               |
-   |       |          |      |              |                   | * FS+ mode, Vext>2.8 (20-120ns)           |               |
-   |       |          |      +--------------+                   +-------------------------------------------+               |
-   |       |          |      | 10           |                   | HS mode (Vext<3.3) (20-160ns)             |               |
-   |       |          |      +--------------+                   +-------------------------------------------+               |
-   |       |          |      | 00           |                   | * HS mode (Vext>3.0)                      |               |
-   |       |          |      |              |                   | * FS mode (20-160ns)                      |               |
-   +-------+----------+------+--------------+-------------------+-------------------------------------------+---------------+
-   | 101   | 0        | 0    | x            | Strong-Fast       | Open-Drain                                | * SPU         |
-   |       |          |      |              | (2-12ns)          |                                           | * OPD-PD Mode |
-   +-------+----------+------+--------------+-------------------+-------------------------------------------+---------------+
-   | 101   | 0        | 1    | x            | Strong-Slow       | Open-Drain                                | * WPU         |
-   |       |          |      |              | (10-60ns)         |                                           | * OPD-PD Mode |
-   +-------+----------+------+--------------+-------------------+-------------------------------------------+---------------+
-   | 110   | 0        | 0    | x            | Strong-Fast       | Strong-Fast  (2-12ns)                     | * SPU         |
-   |       |          |      |              | (2-12ns)          |                                           | * SPD Mode    |
-   +-------+----------+------+--------------+-------------------+-------------------------------------------+---------------+
-   | 110   | 0        | 1    | x            | Strong-Slow       | Strong-Slow  (10-60ns)                    | * SPU         |
-   |       |          |      |              | (10-60ns)         |                                           | * SPD Mode    |
-   +-------+----------+------+--------------+-------------------+-------------------------------------------+---------------+
-   | 111   | 0        | x    | x            | Resistive (5K)    | Resistive (5K)                            | * WPU         |
-   |       |          |      |              |                   |                                           | * WPD Mode    |
-   +-------+----------+------+--------------+-------------------+-------------------------------------------+---------------+
-
-:cell:`sky130_fd_io__sio` Additional Features
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The block diagram for Special I/O (:cell:`sky130_fd_io__sio`) macro is shown below in :numref:`sky130_fd_io__sio_macro block diagram`
-
-.. figure:: figures/sky130_fd_io__sio_macro.png
-   :name: sky130_fd_io__sio_macro block diagram
-
-   Block diagram of :cell:`sky130_fd_io__sio_macro`
-
-The :cell:`sky130_fd_io__sio_macro` consists of 2 :cell:`sky130_fd_io__sio` cells (:numref:`sky130_fd_io__top_sio block diagram`) and a Reference generator cell.
-The :cell:`sky130_fd_io__sio` cells are ONLY available as pairs.
-The block diagram of :cell:`sky130_fd_io__sio` is shown below in :numref:`sky130_fd_io__top_sio block diagram`.
-Note that dm[3] denotes a 3 bit bus dm[2:0].
-These notations are used interchangeably in the document.
-
-1. I/O-Cell :cell:`sky130_fd_io__sio`
-
-.. figure:: figures/sky130_fd_io__sio.png
-   :name: sky130_fd_io__top_sio block diagram
-   :width: 5.79167in
-   :height: 6.14583in
-
-   Block diagram for :cell:`sky130_fd_io__top_sio`
-
-The :cell:`sky130_fd_io__sio` provides the following additional features over the :cell:`sky130_fd_io__gpio`:
-
--  Regulated output buffer
-
--  Differential input buffer
-
-The :cell:`sky130_fd_io__sio` cell adds a differential input buffer and a means for controlling or regulating the output buffer output high voltage level (Voh).
-The :cell:`sky130_fd_io__sio` cell has two additional control inputs (``vreg_en``, ``ibuf_sel``), and an input buffer reference voltage (``vinref``), and an output buffer
-reference voltage (``voutref``).
-The added control inputs are used to select the input buffer type (single ended or differential) and output buffer type (CMOS or regulated).
-The input buffer configuration is selected based on the state of the ``ibuf_sel`` control input.
-If this signal is low the standard single ended (:cell:`sky130_fd_io__gpio`) input buffer is selected, otherwise the differential input buffer is
-selected.
-
-The following tables 13 and 14 describe the :cell:`sky130_fd_io__sio` cell configurations based on the added control signals.
-
-.. table:: :cell:`sky130_fd_io__sio` Input Buffer Truth Table
-   :name: sio Input Buffer
-
-   +--------------+--------------+-------------+---------------+------------------+--------------------+
-   | ``ibuf_sel`` | ``Vref_sel`` | ``voh_sel`` | ``vtrip_sel`` | Trip Point       | Description        |
-   |              | [1:0]        | [2:0]       |               | (Vinref)         |                    |
-   +==============+==============+=============+===============+==================+====================+
-   | 0            | X            | X           | 0             | 30% / 70%        | CMOS input buffer  |
-   |              |              |             |               |                  | w/wo Hysteresis    |
-   +--------------+--------------+-------------+---------------+------------------+--------------------+
-   | 0            | X            | X           | 1             | * min (0.8V,30%) | LVTTL input buffer |
-   |              |              |             |               | * min (2.0V,70%) | w/wo Hysteresis    |
-   +--------------+--------------+-------------+---------------+------------------+--------------------+
-   | 1            | 00           | X           | 0             | 50% of vddio     | Differential input |
-   |              |              |             |               |                  | buffer             |
-   +--------------+--------------+-------------+---------------+------------------+--------------------+
-   | 1            | 00           | X           | 1             | 40% of vddio     | Differential input |
-   |              |              |             |               |                  | buffer             |
-   +--------------+--------------+-------------+---------------+------------------+--------------------+
-   | 1            | 01           | 000         | 0             | 0.5 \* Vohref    | Differential input |
-   |              |              |             |               |                  | buffer             |
-   +--------------+--------------+-------------+---------------+------------------+--------------------+
-   | 1            | 01           | 000         | 1             | Vohref           | Differential input |
-   |              |              |             |               | (buffered)       | buffer             |
-   +--------------+--------------+-------------+---------------+------------------+--------------------+
-   | 1            | 10/11        | 000         | 0             | 0.5 \*           | Differential input |
-   |              |              |             |               | ``amuxbus_a/b``  | buffer             |
-   +--------------+--------------+-------------+---------------+------------------+--------------------+
-   | 1            | 10/11        | 000         | 1             | ``amuxbus_a/b``  | Differential input |
-   |              |              |             |               | (buffered)       | buffer             |
-   +--------------+--------------+-------------+---------------+------------------+--------------------+
-
-The ``vreg_en`` control input selects the output buffer configuration.
-If this signal is low the standard CMOS (:cell:`sky130_fd_io__gpio`) output configuration is selected.
-The regulated output configuration is selected ONLY if the dm<2:0> bits are correctly set to the strong pull up configuration.
-If the dm bits are set to any other configuration other than strong pull up, the regulated output buffer will be disabled, and the standard CMOS
-output buffer would take over.
-
-.. table:: :cell:`sky130_fd_io__sio` Output Buffer Truth Table
-   :name: sio Output Buffer
-
-   +-------------+------+--------------+-------------+--------------------+---------------------------------------+
-   | ``Vreg_en`` | slow | ``Vref_seL`` | ``Voh_sel`` | Voutref for o/p    | Description                           |
-   |             |      | [1:0]        | [2:0]       | buffer             |                                       |
-   +=============+======+==============+=============+====================+=======================================+
-   | 0           | 0    | X            | X           | vohref             | * Output driver in CMOS mode          |
-   |             |      |              |             |                    | * Max slew rate                       |
-   +-------------+------+--------------+-------------+--------------------+---------------------------------------+
-   | 0           | 1    | X            | X           | vohref             | * Output driver in CMOS mode          |
-   |             |      |              |             |                    | * Reduced slew rate                   |
-   +-------------+------+--------------+-------------+--------------------+---------------------------------------+
-   | 1           | 0    | 00/01        | [0-7]       | Refer to           | * Output driver in Regulate mode      |
-   |             |      |              |             | :numref:`voh sel` | * VOH is vohref based                 |
-   +-------------+------+--------------+-------------+--------------------+---------------------------------------+
-   | 1           | 0    | 10/11        | [0-7]       | Refer to           | * Output driver in Regulate mode      |
-   |             |      |              |             | :numref:`voh sel` | * VOH  is ``amuxbus_a/b`` based.      |
-   +-------------+------+--------------+-------------+--------------------+---------------------------------------+
-   | 1           | 1    | 00/01        | [0-7]       | Refer to           | * Output driver in Regulate slow mode |
-   |             |      |              |             | :numref:`voh sel` | * VOH is vohref based.                |
-   +-------------+------+--------------+-------------+--------------------+---------------------------------------+
-   | 1           | 1    | 10/11        | [0-7]       | Refer to           | * Output driver in Regulate slow mode |
-   |             |      |              |             | :numref:`voh sel`  | * VOH is ``amuxbus_a/b`` based.       |
-   +-------------+------+--------------+-------------+--------------------+---------------------------------------+
-
-Note: The ``voh_sel[2:0]`` combinations are found in the :numref:`voh sel`
-
-
-Notice that the input buffer and output buffer configurations can be selected independently.
-For example, the standard single-ended input buffer and the regulated output buffer can be selected.
-
-:cell:`sky130_fd_io__refgen` (Reference Generator) Features
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The block diagram of :cell:`sky130_fd_io__refgen` used in :cell:`sky130_fd_io__sio_macro` is shown below in :numref:`sky130_fd_io__refgen block diagram`:
-
-.. figure:: figures/sky130_fd_io__top_refgen.png
-   :name: sky130_fd_io__refgen block diagram
-   :width: 6.50000in
-   :height: 6.25417in
-
-   Block diagram for :cell:`sky130_fd_io__refgen`
-
-The :cell:`sky130_fd_io__refgen` block :cell:`sky130_fd_io__top_refgen` is an opamp connected in negative feedback loop configuration to generate the output
-reference voltage ``voutref``.
-The input to the opamp (vref) can be selected from any of the three input references (vohref, ``amuxbus_a`` or ``amuxbus_b`` ).
-The input reference is selected based on the control input ``vref_sel[1:0]`` (:numref:`io drive strength modes`).
-The voltage voutref is ``voh_out+Vgs`` (diode-connected nFET).
-In the Regulated Output Buffer, the voltage voutref is applied to the gate of a nFET (of the same type as the diode-connected nFET used to generate
-the voutref signal) and the output is the source of that nFET.
-
-Consequently, this configuration compensates for the V\ :sub:`GS` voltage drop of the source follower in the Regulated Output Buffer circuit and
-allows its output to be pulled to the desired V\ :sub:`OH` voltage level, nominally equal to vohref value.
-The actual V\ :sub:`OH` level and its tolerance relative to the vohref voltage depends on the output current load conditions.
-The acceptable variation in V\ :sub:`OH`-vohref tolerance versus output current load is specified in DC Specification tables.
-For a given input reference, vref, the value of voutref can varied by selecting different tap point from the resistive divider in the feedback path
-(:numref:`sky130_fd_io__refgen block diagram`).
-The resistors are not equal in value and are skewed to generate standard voltages (1.2, 1.5, 1.8, 2, 2.5, 3.3, 4.8), when the bandgap voltage (1.2V)
-is connected to vohref.
-This selection is based on the select signals , ``voh_sel[2:0]`` (:numref:`voh sel`).
-The output regulated value ``(voh_out)`` equals ``vref/n``, where n=Rtap/Rtotal (:numref:`voh sel`).
-
-.. table:: Input Reference selection
-   :name: input reference selection
-
-   +--------------+---------------+
-   | ``Vref_sel`` | Ref.Selected  |
-   | [1:0]        |               |
-   +==============+===============+
-   | 00           | Vohref        |
-   +--------------+---------------+
-   | 01           | Vohref        |
-   +--------------+---------------+
-   | 10           | ``amuxbus_a`` |
-   +--------------+---------------+
-   | 11           | ``amuxbus_b`` |
-   +--------------+---------------+
-
-Note: The voltage range for the analog reference inputs ``(vref/amuxbus_a/amuxbus_b)`` is 1.0-4.6V and is dependent on the I/O supply, shown in :numref:`analog reference input` below.
-
-.. table:: Analog Reference Input
-   :name: analog reference input
-
-   +-------------------------+--------------------------------+
-   | I/O Supply (vddio)      | analog input to reference      |
-   |                         | ``(vref/amuxbus_a/amuxbus_b)`` |
-   +=========================+================================+
-   | 1.65V <= vddio < = 3.7V | 1 - (vddio-0.5)                |
-   +-------------------------+--------------------------------+
-   | 3.7V< vddio <= 5.6V     | 1 - (vddio-1)                  |
-   +-------------------------+--------------------------------+
-
-.. table:: V\ :sub:`OH` reference selection
-   :name: voh sel
-
-   +------------------+-----------------+
-   | ``voh_sel[2:0]`` | n = Rtap/Rtotal |
-   +==================+=================+
-   | 000              | 1               |
-   +------------------+-----------------+
-   | 001              | 0.8             |
-   +------------------+-----------------+
-   | 010              | 0.67            |
-   +------------------+-----------------+
-   | 011              | 0.6             |
-   +------------------+-----------------+
-   | 100              | 0.48            |
-   +------------------+-----------------+
-   | 101              | 0.4             |
-   +------------------+-----------------+
-   | 110              | 0.36            |
-   +------------------+-----------------+
-   | 111              | 0.25            |
-   +------------------+-----------------+
-
-
-Note:
-
--  All the ``voh_sel[2:0]`` values cannot be selected for entire reference range (1V-4.6V). The upper value on VOH is limited to ``Vddio_q - 400mV``.
-
--  The resistors are not equal in value and are skewed to generates standard voltages (1.2, 1.5, 1.8, 2, 2.5, 3.3, 4.8), when band-gap voltage (1.2V) is connected to vref.
-
-The input buffer reference ``vinref`` can be derived from four sources: vinref, half of ``voh_out``, and 40% or 50% of the I/O supply voltage ``vcc_io``.
-The ``vinref`` voltage level selected is based on the input buffer voltage trip point select ``vtrip_sel`` and voltage reference select ``vref_sel``
-control inputs.
-
-The truth tables for :cell:`sky130_fd_io__refgen` are shown in :numref:`sky130_fd_io__sio input buffer voltage` and :numref:`sky130_fd_io__refgen truth table`.
-
-Important notes about :cell:`sky130_fd_io__sio` macro:
-
--  Each pair of :cell:`sky130_fd_io__sio`'s share a single RefGen block. This block allows for the generation of a ``regulated mode`` selectable input buffer trip point and output driver level.
-
--  The I/Os retain the ability to disable the input buffer for I/O's with an active analog function. For :cell:`sky130_fd_io__sio`'s not connected to any analog component this input must be tied off.
-
--  The input reference (Vohref) to the RefGen block is assumed to be 1.2V.
-
--  The RefGen block also connects to ``amuxbus_a`` and ``amuxbus_b`` for reference generation. Use case: An external pin as reference voltage.
-
--  Regulated output buffer mode and differential input buffer mode cannot be used in low-power modes where VCCD is unavailable. It is the responsibility of firmware to ensure that the :cell:`sky130_fd_io__sio` is not configured in these modes before entering low-power modes.
-
--  If :cell:`sky130_fd_io__sio_macro` is being used as an I2C pin to drive SDA, the following configuration bits need to be set (CMOS input buffer and open-drain output)—The configuration bits are given w.r.t a single :cell:`sky130_fd_io__sio`
-
-   -  dm<2:0>=100 (To enable the 20mA driver (I2C FS+ mode and input buffer)
-
-   -  ``ibuf_sel=0`` (To enable the SE buffer)
-
-   -  ``inp_dis=0`` (To enable input buffer)
-
-   -  ``vtrip_sel=0`` (To enable CMOS input buffer mode)
-
--  All other control signals are don't care. The refgen can be disabled when :cell:`sky130_fd_io__sio_macro` is used for I2C ``(vreg_en_refgen=0)``
-
-.. table:: Valid :cell:`sky130_fd_io__sio` Differential Input Buffer Reference Voltage
-   :name: sky130_fd_io__sio input buffer voltage
-
-   +--------------+---------------+--------------------+
-   | ``Vref_sel`` | ``vtrip_sel`` | Vinref             |
-   | <1:0>        |               |                    |
-   +==============+===============+====================+
-   | 00           | 0             | 0.5 \* ``vcc_io``  |
-   +--------------+---------------+--------------------+
-   | 00           | 1             | 0.4 \* ``vcc_io``  |
-   +--------------+---------------+--------------------+
-   | 01           | 0             | 0.5 \* ``voh_out`` |
-   +--------------+---------------+--------------------+
-   | 01           | 1             | vref               |
-   +--------------+---------------+--------------------+
-   | 10           | 0             | 0.5 \* ``voh_out`` |
-   +--------------+---------------+--------------------+
-   | 10           | 1             | vref               |
-   +--------------+---------------+--------------------+
-   | 11           | 0             | 0.5 \* ``voh_out`` |
-   +--------------+---------------+--------------------+
-   | 11           | 1             | vref               |
-   +--------------+---------------+--------------------+
-
-.. table:: :cell:`sky130_fd_io__refgen` Truth Table
-   :name: sky130_fd_io__refgen truth table
-
-   +--------+-------------+--------------+--------------+---------+--------+
-   | vohref | ``vreg_en`` | ``ibuf_sel`` | ``vref_sel`` | voutref | vinref |
-   |        |             |              | <1:0>        |         |        |
-   +========+=============+==============+==============+=========+========+
-   | X      | 0           | 0            | X            | Hi-Z    | Hi-Z   |
-   +--------+-------------+--------------+--------------+---------+--------+
-   | 1      | 0           | 1            | 00           | Hi-Z    | 1      |
-   +--------+-------------+--------------+--------------+---------+--------+
-   | 1      | 0           | 1            | 01,10,11     | 1       | 1      |
-   +--------+-------------+--------------+--------------+---------+--------+
-   | 1      | 1           | 0            | 00,01        | 1       | Hi-Z   |
-   +--------+-------------+--------------+--------------+---------+--------+
-   | X      | 1           | 0            | XX           | 1       | Hi-Z   |
-   +--------+-------------+--------------+--------------+---------+--------+
-   | 1      | 1           | 1            | 00,01        | 1       | 1      |
-   +--------+-------------+--------------+--------------+---------+--------+
-   | X      | 1           | 1            | 10,11        | 1       | 1      |
-   +--------+-------------+--------------+--------------+---------+--------+
-
-Use of ``dft_refgen`` for ADFT purpose:
-
--  The :cell:`sky130_fd_io__refgen` block produces two references to be used in the :cell:`sky130_fd_io__sio_macro`. ``vinref`` is the reference to the differential input buffer and ``voutref`` is the reference to the regulated output buffer.
-
--  In order to have 100% ADFT coverage, these two references are bought out to the interface of the :cell:`sky130_fd_io__sio_macro`. By enabling ``dft_refgen``, these two outputs of refgen can be observed on ``vinref_dft`` and ``voutref_dft``. In order to observe these two pins on any :cell:`sky130_fd_io__gpio` pins, these two pins need to be hooked to the analog busses and bought to any :cell:`sky130_fd_io__gpio` pad through the AMUXBUS inside the :cell:`sky130_fd_io__gpio`.
-
-:cell:`sky130_fd_io__gpio_vrefv2` (Reference generator for Selectable trip point input buffer) Features
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-This cell provides a reference (``vinref``) to the selectable trip point buffer in :cell:`sky130_fd_io__gpio_ovtv2`.
-This reference generator is a low-leakage resistive ladder whose tap points are selected based on the signaling required at the
-:cell:`sky130_fd_io__gpio_ovtv2` pad.
-The block diagram is shown below in :numref:`sky130_fd_io__gpio_vrefv2 block diagram`.
-Note ref_sel[5] denotes a 5 bit bus ``ref_sel[4:0].``
-These notations are used interchangeably in the document.
-
-.. figure:: figures/sky130_fd_io__top_gpiovrefv2.png
-   :name: sky130_fd_io__gpio_vrefv2 block diagram
-   :width: 6.07292in
-   :height: 4.31250in
-
-   :cell:`sky130_fd_io__gpio_vrefv2` Block Diagram
-
-The reference selection is based on the signaling range that needs to be at the PAD.
-For this to work, the external signaling range must be lower than VDDIO.
-The tap point selection is based on the formula:
-
-vinref = (13n+184)\*VDDIO/600
-
--  Where vinref represents the input signaling voltage at :cell:`sky130_fd_io__gpio_ovtv2` pad
-
--  VDDIO is the supply voltage to the :cell:`sky130_fd_io__gpio`
-
--  ``n`` is the tap point selection that gives us required vinref. Binary coding of ``n`` is ``ref_sel<4:0>.`` ``n`` should be chosen such that ``vinref`` is greater than 1.8V
-
-   For example:
-
-   -  Need to support 1.8V (vinref) signaling on PAD with VDDIO=5.0V. Plugging these numbers into the equation yields:
-
-      1.8 = (13n+184)\*5.0/600
-
-      n= 2.46
-
-   -  As n=2.46, ``ref_sel<4:0>`` can be selected as either 2 (5'b00010) or 3 (5'b00011). This would give out a reference of ``1.75V`` and ``1.858V`` respectively.
-
-   -  Use a ceiling on ``n`` i.e. if n=2.46, use n=3 instead of n=2.
-
-::cell:`sky130_fd_io__top_vrefcapv2` Features
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-This cell contains a unit capacitance (4pF) that is intended to be placed on the ``vinref`` node that goes to multiple :cell:`sky130_fd_io__gpio_ovtv2`
-cells.
-This is a filter cap used to suppress kick-back noise from the input buffers.
-The usage is shown below in :numref:`sky130_fd_io__top_vrefcapv2 block diagram`:
-
-.. figure:: figures/sky130_fd_io__top_vrefcapv2.png
-   :name: sky130_fd_io__top_vrefcapv2 block diagram
-   :width: 4.64583in
-   :height: 6.32292in
-
-   :cell:`sky130_fd_io__top_vrefcapv2`
-
-:cell:`sky130_fd_io__top_amuxsplitv2` Features
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The amux splitter cell is designed to provide large chips (with large number of :cell:`sky130_fd_io__gpio`'s) to break the analog mux into multiple segments.
-This cell is capable of grounding, disconnecting or feeding through each amuxbus.
-The block diagram is shown below in :numref:`sky130_fd_io__top_amuxsplitv2 block diagram`.
-
-.. figure:: figures/sky130_fd_io__top_amuxsplitv2.png
-   :name: sky130_fd_io__top_amuxsplitv2 block diagram
-   :width: 6.50000in
-   :height: 4.11944in
-
-   Block diagram of :cell:`sky130_fd_io__top_amuxsplitv2`
-
-Each T-switch has 3 control signals coming to control the state of the switches.
-These are expected to be static switches.
-During power-up ``(enable_vdda_h=0)`` and low-power modes ``(hld_vdda_h_n=0),`` the switches of the amux splitter are open.
-
-General guidelines for the T-switch: Break before make logic that needs to be followed when working with the switch control signals.
-For example - when ``amux_a_l`` and ``amux_a_r`` are Independent, the mid-node of the switch needs to be closed to prevent unwanted coupling between the
-two amuxbus's.
-When connecting ``amux_a_l`` and ``amux_a_r`` care must be taken to disconnect the mid-node and then close the right and left switch.
-
-PG pads (ESD)
-~~~~~~~~~~~~~
-
-The I/O library consists of Power (P) and Ground (G) pads that have RC ESD clamps embedded in them.
-There are two types of RC ESD clamps that are present in these PG pads.
-
--  HV clamp- Only one HV (High Voltage) clamp is present underneath the PG pads whose terminals can be connected independently without interfering with the PG connections
-
--  LV clamp- Two LV (Low Voltage) clamps and a B2B (back 2 back) diode can be accommodated underneath the PG pads. The two LV clamps have a total of six terminals that can be tied according to chip-level needs. The B2B however should be connected to the source/body of LV clamp1 and another independent ground node ``(bdy_b2b).``
-
-A layout variant of the HV clamp without pad is :cell:`sky130_fd_io__top_hvclamp_wopadv2`.
-This is a derivative of :cell:`sky130_fd_io__top_hvclamp_wopad` with following changes:
-
--  Vssd pin added: P-substrate connection
-
--  HV clamp gate connection improved.
-
--  HV clamp source/drain connection improved.
-
-Two additional pad cells to be used for power and ground connections added, namely:
-
--  :cell:`sky130_fd_io__top_power_padonlyv2`
-
--  :cell:`sky130_fd_io__top_ground_padonlyv2`
-
-These are only M4/M5 pad structures with a short element.
-They are used to provide pad structure/connection to wopad clamps.
-
-Integration Guidelines
-^^^^^^^^^^^^^^^^^^^^^^
-
-All power and ground pads have the I/O bussing running through them in M5/M4, thereby forming an I/O ring when abutted to each other.
-The power and ground pads can be abutted to either the :cell:`sky130_fd_io__gpio` or the :cell:`sky130_fd_io__sio_macro`.
-
-The Power and Ground pads are designed in such a way that one side of it is full DRC complaint to any :cell:`sky130_fd_io__gpio` or :cell:`sky130_fd_io__sio_macro` that abuts it.
-However due to limited area constraints, the other side cannot be abutted directly to a :cell:`sky130_fd_io__gpio`/:cell:`sky130_fd_io__sio_macro`.
-This puts a restriction that 2 pads (power/ground) should be paired to build the I/O ring.
-
-ESD design details
-~~~~~~~~~~~~~~~~~~
-
-The architecture for the RC ESD clamps trigger circuit is the simple one-time constant RC trigger circuit.
-For the over-voltage tolerant :cell:`sky130_fd_io__sio`, use ESD rail clamp :cell:`sky130_fd_io__top_hvclamp_wopad_sio`.
-
-The HV and LV RC ESD clamps are robust up to 3.3KV HBM.
-
-ESD HV RC ESD Clamp design
-
--  Single trigger - 2us time constant
-
--  Driver width of 2880 um was used
-
--  Cell height the same as the :cell:`sky130_fd_io__gpio`
-
-Usage of Outer Guard ring Connection (OGC) in ESD HV and LV clamps for :lib:`sky130_fd_io`
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Power and Ground pads in :lib:`sky130_fd_io` library come along with ESD HV and LV clamps embedded within them.
-All the ESD clamps are independent of the power or ground pads providing maximum flexibility, thereby making the end user make proper connections to
-the ESD clamps.
-The end user chip lead is the best-informed person about making these connections and must approve all the ESD connections.
-
-One of the clamp connections is the outer guard ring connection ``(ogc_hvc/ogc_lvc).``
-The basic purpose of this is to connect the outer guard ring (deep nwell) to provide noise isolation.
-The recommended usage of this is to connect it to a HV supply that is available all/most of the time.
-
-Bottlenecks during implementation: The power and ground pads that contain the ESD clamps have a number of pins coming to the boundary interface.
-In order to minimize the resistance inside the cell to these ESD clamps, some of the ``ogc_\*`` connections are floated and connected internally to
-VDDIO.
-
-The following :numref:`ogc connection` lists the different cells in :lib:`sky130_fd_io` library that have this ``ogc_\*`` connection and the recommended way to connect them.
-
-.. table:: OGC connection and Usage
-   :name: ogc connection
-
-   +------+---------------------------------------------+-------------+---------------------------------------------+
-   | S.No | Public Cell                                 | Internally  | Recommended connection to end user          |
-   |      |                                             | connected?  |                                             |
-   +======+=============================================+=============+=============================================+
-   | 1    | :cell:`sky130_fd_io__top_power_hvc_wpad`    | YES (VDDIO) | No need to connect                          |
-   +------+---------------------------------------------+-------------+---------------------------------------------+
-   | 2    | :cell:`sky130_fd_io__top_ground_hvc_wpad`   | YES (VDDIO) | No need to connect                          |
-   +------+---------------------------------------------+-------------+---------------------------------------------+
-   | 3    | :cell:`sky130_fd_io__top_power_lvc_wpad`    | YES (VDDIO) | No need to connect                          |
-   +------+---------------------------------------------+-------------+---------------------------------------------+
-   | 4    | :cell:`sky130_fd_io__top_ground_lvc_wpad`   | YES (VDDIO) | No need to connect                          |
-   +------+---------------------------------------------+-------------+---------------------------------------------+
-   | 5    | :cell:`sky130_fd_io__top_hvclamp_wopad`     | NO          | Connect to HV Supplythat is always present  |
-   +------+---------------------------------------------+-------------+---------------------------------------------+
-   | 6    | :cell:`sky130_fd_io__top_lvclamp_b2b_wopad` | NO          | Connect to HV Supply that is always present |
-   |      |                                             |             | (Outer guard ring is HV rules compliant)    |
-   +------+---------------------------------------------+-------------+---------------------------------------------+
-   | 7    | :cell:`sky130_fd_io__top_lvclamp`           | NO          | Connect to HV Supply that is always present |
-   |      |                                             |             | (Outer guard ring is HV rules compliant)    |
-   +------+---------------------------------------------+-------------+---------------------------------------------+
-
-XRES
-~~~~
-
-The XRES cell is a macro that is used to influence the internal system wide reset.
-The purpose of this cell is to provide a noise free signal from the input buffer to the core.
-Any glitch of 50ns or less on the XRES pad is rejected by the XRES macro.
-
-The XRES cell (:cell:`sky130_fd_io__top_xres`, :cell:`sky130_fd_io__top_xres_2`) is a cell that integrates the input buffer from the :cell:`sky130_fd_io__gpio` and an HV RC
-filter.
-It also has a 5k weak pull up on the XRES pad.
-
-The XRES cell has two outputs, out (LV) and ``out_h`` (HV).
-The HV output will be functional even when the LV supply to the input buffer is gone (STOP mode).
-
-There are 5 variants of XRES cells in :lib:`sky130_fd_io` IP:
-
-1. :cell:`sky130_fd_io__top_xres` and :cell:`sky130_fd_io__top_xres_2`
-
-The two versions are the same except for layout differences.
-
-2. :cell:`sky130_fd_io__top_xres2v2`
-
-This cell is essentially a copy of the current :cell:`sky130_fd_io__top_xres_2` cell.
-One minor layout modification is made to this cell which is to make the height of the new cell=200u (:cell:`sky130_fd_io__top_xres_2` has 198u height).
-No change in functionality compared to current :cell:`sky130_fd_io__top_xres_2`.
-
-.. figure:: figures/sky130_fd_io__xres2v2.png
-   :name: sky130_fd_io__top_xres2v2 block diagram
-   :width: 3.21875in
-   :height: 1.47917in
-
-   :cell:`sky130_fd_io__top_xres2v2`
-
-3. :cell:`sky130_fd_io__top_xres3v2`
-
-This cell is also a copy of the :cell:`sky130_fd_io__top_xres_2` cell but with the pull-up disabled.
-(I.e.
-pull-up metal connection will be cut).
-
-There is a metal option provided to connect the pullup back on if required.
-This requires 2 extra pins in this cell.
-
-.. figure:: figures/sky130_fd_io__xres3v2.png
-   :name: sky130_fd_io__top_xres3v2 block diagram
-   :width: 3.44792in
-   :height: 1.56250in
-
-   :cell:`sky130_fd_io__top_xres3v2`
-
-4. :cell:`sky130_fd_io__top_axresv2`
-
-Glitch filter to filter out pulses less than 50ns pulse width.
-This glitch filter currently resides inside of the xres cells.
-In order to provide more flexibility, the glitch filter portion of the existing xres cell will be copied into this new public cell.
-
-Pull-up cell to connect the pad to the power supply (vddio) through a 5k ohm resistor.
-A control bit ``(disable_pullup_h)`` is used to enable/disable the pull-up.
-
-.. figure:: figures/sky130_fd_io__top_axresv2.png
-   :name: sky130_fd_io__top_axresv2 block diagram
-   :width: 3.04996in
-   :height: 1.07135in
-
-   :cell:`sky130_fd_io__top_axresv2`
-
-Use case for the XRES cells
-^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-.. figure:: figures/use_case_for_the_xres_cells.png
-   :name: xres use case
-   :width: 6.50000in
-   :height: 4.06181in
-
-   Use case for the XRES cells
-
-Usage guidelines on when to use the different cells:
-
-:cell:`sky130_fd_io__top_xres`:
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The first XRES cell :cell:`sky130_fd_io__top_xres` can ONLY be abutted to the :cell:`sky130_fd_io__sio_macro` on its right and to TP2 on its left.
-This will not have any physical verification errors with the above mentioned placement of :cell:`sky130_fd_io__top_xres` cell.
-This cell CANNOT be abutted with any other cells in the :lib:`sky130_fd_io` library to form the I/O ring.
-
-:cell:`sky130_fd_io__top_xres_2`:
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-This is a generic cell that can be abutted to most of the existing cells inside the :lib:`sky130_fd_io` library.
-
-:cell:`sky130_fd_io__top_xres2v2`, :cell:`sky130_fd_io__top_xres3v2`, :cell:`sky130_fd_io__top_axresv2`:
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-All the :cell:`sky130_fd_io__top_xres` cells have the I/O bussing running through them in M5/M4, thereby forming an I/O ring when abutted to each other.
-This is a generic cell that can be abutted to most of the existing cells inside the :lib:`sky130_fd_io` library.
-
-
-Test Pads (TP1, TP2, TP3)
-~~~~~~~~~~~~~~~~~~~~~~~~~
-
-TP1 and TP2 are used to monitor the flash voltages.
-TP3 is an analog pad.
-The TP1 and TP2 pads do not have any state elements and have no initialization requirements.
-It is expected that ``en_tp1`` and ``en_tp2`` input will be driven low during startup and during normal operation - only toggling high during test modes
-(class test or characterization, in particular).
-
-The TP1 and TP2 pad are specifically for test mode.
-
-There are two modes: ``en_tp1`` and ``en_tp2`` = 0 and ``en_tp1`` and ``en_tp2`` = 1.
-
-The ``en_tp1`` and ``en_tp2`` inputs must be asserted high to enable scaled/divided version of outputs for full-chip hook-up.
-In this mode the ``tp1_out`` voltages and ``tp2_out_voltages`` are directly observed on the TP1 and TP2 pads.
-
-The TP1, TP2, TP3 pads have snap back ESD protection inside them.
-
-Below are the truth tables for the TP1, TP2, TP3 pads:
-
-.. table:: Truth Table for :cell:`sky130_fd_io__top_tp1`
-   :name: sky130_fd_io__top_tp1 truth table
-
-   +------------+-------------+---------------+
-   | ``en_tp1`` | tp1         | ``tp1_div``   |
-   +============+=============+===============+
-   | 0          | ``tp1_out`` | Hi-Z          |
-   +------------+-------------+---------------+
-   | 1          | ``tp1_out`` | ``tp1_out/7`` |
-   +------------+-------------+---------------+
-
-.. table:: Truth Table for :cell:`sky130_fd_io__top_tp2`
-   :name: sky130_fd_io__top_tp2 truth table
-
-   +------------+-------------+-----------------------------+
-   | ``en_tp2`` | tp2         | ``tp2_div``                 |
-   +============+=============+=============================+
-   | 0          | ``tp2_out`` | Hi-Z                        |
-   +------------+-------------+-----------------------------+
-   | 1          | ``tp2_out`` | ``tp1_out/9`` + (8/9)\*vccd |
-   +------------+-------------+-----------------------------+
-
-.. table:: Truth Table for :cell:`sky130_fd_io__top_tp3`
-   :name: sky130_fd_io__top_tp3 truth table
-
-   +------+-------------+
-   | tp3  | ``tp3_out`` |
-   +======+=============+
-   | 0    | 0           |
-   +------+-------------+
-   | 1    | 1           |
-   +------+-------------+
-   | Hi-Z | Hi-Z        |
-   +------+-------------+
-
-Overlay Cells
-~~~~~~~~~~~~~
-
-There are two kinds of overlays that exist in the :lib:`sky130_fd_io` I/O library:
-
--  Power Ground (PG) overlays - These overlay cells (12) are coupled with the existing generic power and ground public cells and made into a specific power and ground pad. The overlays connect the pad to the one of the horizontally running I/O ring busses.
-
--  :cell:`sky130_fd_io__gpio`
-
-1. Power Ground Overlays
-
-   :lib:`sky130_fd_io` I/O library has twelve overlays that go with the two existing power and ground pads.
-   The purpose of the overlays is to convert a generic power/ground pad to a specific power/ground pad.
-   For example: :cell:`sky130_fd_io__top_power_hvc_wpad` is just a power pad with no hook-up to the horizontally running I/O busses in the I/O ring.
-   By placing an overlay called :cell:`sky130_fd_io__overlay_vddio_hvc` on top of :cell:`sky130_fd_io__top_power_hvc_wpad`, this would become a VDDIO power pad (in that the
-   PAD is physically connected to the VDDIO bus in the I/O ring).
-
-   Below are the important busses running in the I/O ring for which these overlays are built:
-
-   1. VDDIO
-
-   2. VSSIO
-
-   3. VDDA
-
-   4. VSSA
-
-   5. VCCD
-
-   6. VSSD
-
-   Since any power or ground pad can be connected to an ESD HV or an ESD LV clamp, there are twelve overlays for the above mentioned buses.
-   :numref:`overlay cells` shows the usage.
-
-.. table:: Overlay Cell along with usage
-   :name: overlay cells
-
-   +------+-----------------------------------------+-------------------------------------------+-----------------+------------------+
-   | S.No | Overlay                                 | Used in conjunciton with                  | Converts above  | Using underneath |
-   |      |                                         |                                           | power PAD to    | clamp of         |
-   +======+=========================================+===========================================+=================+==================+
-   | 1    | :cell:`sky130_fd_io__overlay_vddio_hvc` | :cell:`sky130_fd_io__top_power_hvc_wpad`  | VDDIO power pad | HV ESD clamp     |
-   +------+-----------------------------------------+-------------------------------------------+-----------------+------------------+
-   | 2    | :cell:`sky130_fd_io__overlay_vddio_lvc` | :cell:`sky130_fd_io__top_power_lvc_wpad`  | VDDIO power pad | LV ESD clamp     |
-   +------+-----------------------------------------+-------------------------------------------+-----------------+------------------+
-   | 3    | :cell:`sky130_fd_io__overlay_vdda_hvc`  | :cell:`sky130_fd_io__top_power_hvc_wpad`  | VDDA  power pad | HV ESD clamp     |
-   +------+-----------------------------------------+-------------------------------------------+-----------------+------------------+
-   | 4    | :cell:`sky130_fd_io__overlay_vdda_lvc`  | :cell:`sky130_fd_io__top_power_lvc_wpad`  | VDDA  power pad | LV ESD clamp     |
-   +------+-----------------------------------------+-------------------------------------------+-----------------+------------------+
-   | 5    | :cell:`sky130_fd_io__overlay_vccd_hvc`  | :cell:`sky130_fd_io__top_power_hvc_wpad`  | VCCD  power pad | HV ESD clamp     |
-   +------+-----------------------------------------+-------------------------------------------+-----------------+------------------+
-   | 6    | :cell:`sky130_fd_io__overlay_vccd_lvc`  | :cell:`sky130_fd_io__top_power_lvc_wpad`  | VCCD  power pad | LV ESD clamp     |
-   +------+-----------------------------------------+-------------------------------------------+-----------------+------------------+
-   | 7    | :cell:`sky130_fd_io__overlay_vssio_hvc` | :cell:`sky130_fd_io__top_ground_hvc_wpad` | VSSIO power pad | HV ESD clamp     |
-   +------+-----------------------------------------+-------------------------------------------+-----------------+------------------+
-   | 8    | :cell:`sky130_fd_io__overlay_vssio_lvc` | :cell:`sky130_fd_io__top_ground_lvc_wpad` | VSSIO power pad | LV ESD clamp     |
-   +------+-----------------------------------------+-------------------------------------------+-----------------+------------------+
-   | 9    | :cell:`sky130_fd_io__overlay_vssa_hvc`  | :cell:`sky130_fd_io__top_ground_hvc_wpad` | VSSA  power pad | HV ESD clamp     |
-   +------+-----------------------------------------+-------------------------------------------+-----------------+------------------+
-   | 10   | :cell:`sky130_fd_io__overlay_vssa_lvc`  | :cell:`sky130_fd_io__top_ground_lvc_wpad` | VSSA  power pad | LV ESD clamp     |
-   +------+-----------------------------------------+-------------------------------------------+-----------------+------------------+
-   | 11   | :cell:`sky130_fd_io__overlay_vssd_hvc`  | :cell:`sky130_fd_io__top_ground_hvc_wpad` | VSSD  power pad | HV ESD clamp     |
-   +------+-----------------------------------------+-------------------------------------------+-----------------+------------------+
-
-Power detector
-~~~~~~~~~~~~~~
-
-This cell is developed to detect vddd and vddio power supplies and to level shift the hv control signals across vddio<->vddd voltage domains.
-This cell is made of the following sub-blocks.
-
-1. vddd detector : It detects the presence of vddd supply in vddio domain
-
-2. vddio detector : It detects the presence of vddio supply in vddd domain
-
-3. There are 6 level shifters inside the top cell. The first 3 level shifters are enabled by the vddd detector and the later three are enabled by the vddio detector. The detectors make sure that the level shifters are powered down to a safe state when the input power supply to the level shifters is not present.
-
-Use case for the detector
-^^^^^^^^^^^^^^^^^^^^^^^^^
-
-.. figure:: figures/use_case_for_power_detector_sky130_fd_io__pwrdet.png
-   :name: power detector use case
-   :width: 6.10417in
-   :height: 5.89583in
-
-   Use case for the Power detector
-
-
-Block diagram
-^^^^^^^^^^^^^
-
-The following diagram shows the complete sub-blocks of the power detector in detail.
-
-.. figure:: figures/sky130_fd_io__top_pwrdet.png
-   :name: sky130_fd_io__top_pwrdet block diagram
-   :width: 6.50000in
-   :height: 6.71875in
-
-   :cell:`sky130_fd_io__top_pwrdet`
-
-Truth Table
-^^^^^^^^^^^
-
-The table below captures all steady state combinations of ``vddio_q,`` vccd and vddd1 for the vddio detector and explains the behavior of the vddio
-detector for each of the cases.
-
-.. table:: Truth Table for Power detector
-   :name: power detector truth table
-
-   +-------+-------+-------------+---------------------------------------------------------+--------------------------------------------------------------------+
-   | vccd  | vddd1 | ``vddio_q`` | vddio detector behavior                                 | Comment                                                            |
-   +=======+=======+=============+=========================================================+====================================================================+
-   | 0     | 0     | 0           | Output is floating.                                     | Chip shutdown                                                      |
-   +-------+-------+-------------+---------------------------------------------------------+--------------------------------------------------------------------+
-   | 0     | 0     | 1           | Output is floating.                                     | vddd is absent                                                     |
-   +-------+-------+-------------+---------------------------------------------------------+--------------------------------------------------------------------+
-   | 0     | 1     | 0           | The detector is unreliable in this condition            | Sec.2.4.9 of SAS calls out this condition.                         |
-   |       |       |             |                                                         | It states the circuit above is unreliable when vddio is 0          |
-   |       |       |             |                                                         | and ``vpwr_lv`` is 0, which is the case during POR and when XRES=0 |
-   +-------+-------+-------------+---------------------------------------------------------+--------------------------------------------------------------------+
-   | 0     | 1     | 1           | * Detector output will be high.                         | xres mode                                                          |
-   |       |       |             | * vccd=0 does not affect circuit behavior when vddio=1  |                                                                    |
-   +-------+-------+-------------+---------------------------------------------------------+--------------------------------------------------------------------+
-   | 1     | 0     | 0           | Output is floating.                                     | Invalid combination. Vccd cannot be ``1`` when vddd is 0           |
-   +-------+-------+-------------+---------------------------------------------------------+--------------------------------------------------------------------+
-   | 1     | 0     | 1           | Output is floating.                                     | Invalid combination. Vccd cannot be ``1`` when vddd is 0           |
-   +-------+-------+-------------+---------------------------------------------------------+--------------------------------------------------------------------+
-   | 1     | 1     | 0           | Output will be low. since ``vddio_q=0``                 | When vddio de-asserts in a working system -                        |
-   |       |       |             |                                                         | it what leads the system to reset as a result of it                |
-   +-------+-------+-------------+---------------------------------------------------------+--------------------------------------------------------------------+
-   | 1     | 1     | 1           | Output of detector is high.                             | Active mode.                                                       |
-   +-------+-------+-------------+---------------------------------------------------------+--------------------------------------------------------------------+
-
-The table below captures all steady state combinations of ``vddio_q,`` and vddd2 for the vddd detector and explains the behavior of the vddd detector for each of the cases.
-
-.. table:: Steady state combinations of ``vddio_q,`` and vddd2
-   :name: steady state vddio_q and vddd2
-
-   +-------------+-----------+----------------------+---------------------------+
-   | ``vddio_q`` | ``vddd2`` | vddd detector behavio| Comment                   |
-   +=============+===========+======================+===========================+
-   | 0           | 0         | Output is floating.  | Chip shutdown             |
-   +-------------+-----------+----------------------+---------------------------+
-   | 0           | 1         | Output is floating   | ``vddio_q`` (power supply |
-   |             |           |                      | of detector) is absent.   |
-   +-------------+-----------+----------------------+---------------------------+
-   | 1           | 0         | Output will be low,  | ``vddio_q`` is present    |
-   |             |           | since vddd2 =0       | and vddd2 is absent.      |
-   +-------------+-----------+----------------------+---------------------------+
-   | 1           | 1         | Output will be high, | Active mode.              |
-   |             |           | since vddd2=1        |                           |
-   +-------------+-----------+----------------------+---------------------------+
-
-
-The output of the level shifter will be zero when the power supply that is being detected is not present (=0).
-
-Block Integration Guidelines
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The cell uses metal routing untill Met3.
-Met4 and Met5 can be routed above this block.
-
-The ``rst_por_hv_n`` pin should be hooked up to the ``rst_por_hv_n`` coming from the SRSS IP for proper functionality.
-
-The cell does not include any circuitry for test mode control or for self-test.
-
-IP block test coverage goals should be met by asserting the inputs of the level shifter and observing the respective outputs.
-The block is mainly used to carry global enable signals and hence this functionality is tested implicitly.
-
-The detector outputs are buffered using buffer sizes similar to buf4 cell.
-The user must insert an additional buffer if one intends to cater to a higher load than that is supported by this buffer.
-
-The level shifter outputs are buffered to drive a 3pf load at about 10ns rise/fall times.
-Any additional load requirement must be taken care by inserting additional buffers.
-
-The reset signal connected to vddio detector should be high in steady state condition for proper functionality.
-
-If the VDDD detector is not to be used then the vddd2 has to be tied to ``vddio_q.``
-The inputs of the corresponding level shifters ``(in1_vddd_hv,`` ``in2_vddd_hv`` and ``in3_vddd_hv`` must be tied to ground.
-The outputs of the level shifters and detector must not be used anywhere.
-
-If the VDDIO detector is not planned to be used then the vddd1, ``rst_por_hv_n`` and vccd has to be tied to ``vddio_q.``
-The inputs of the corresponding level shifters ``(in1_vddio_hv,`` ``in2_vddio_hv`` and ``in3_vddio_hv`` must be tied to ground.
-The outputs of the level shifters and detector must not be used anywhere.
-
-This cell can be placed in critical corner.
-
-The cell has power connections in Met3.
-The power connections must be properly connected in Met4 and Met5 at the chip level.
-The MET4 and MET5 power hookups should be at least 6um.
-Minimum 10 VIA3 and VIA4 must be used in the power hookups.
-
-If the block is placed in the I/O ring in the ESD routing path the power bussing should follow that of the I/O ring.
-
-The vddio and vddd detectors were tested with 500mV, 10ns pulse width noise at 1 MHz and 25 MHz frequencies at the input power supply domain assuming
-no noise at the output power supply domain.
-
-The vddio and vddd detectors were tested with 500mV, 10ns pulse width noise at 1 MHz and 25 MHz frequencies at the output power supply domain assuming
-no noise at the input power supply domain.
-
-The vddio and vddd detectors were tested with 100mV, 10ns pulse width noise at 1 MHz and 25 MHz frequencies at the vssa domain.
-
-The vddio and vddd detectors were tested with 100mV, 10ns pulse width noise at 1 MHz and 25 MHz frequencies at the vssd and ``vssio_q`` domain.
-
-The outputs of the level shifters should be routed in Met2 of 0.5um width or Met3
-
-The default state of the level shifters outputs is zero.
-Hence the level shifters must be used to shift active high control signals to avoid glitches on this control signals during various power supply
-ramps.
-
-The power detector carries the ``enable_io`` signals to the :cell:`sky130_fd_io__sio` and :cell:`sky130_fd_io__gpio_ovtv2`.
-Hence any glitches on the VDDD level shifter output when VDDIO ramping will cause a possible glitch in I2C communication.
-The following table shows the outputs with various power supply ramp scenarios for the detector and level shifters outputs with the input to the level
-shifter driven by zero.
-
-.. table:: Power detector outputs with various power supply ramp scenarios
-   :name: power detector outputs
-
-   +--------+---------+---------+----------------+----------------+---------------+----------------+
-   | Case # | vddd    | vddio   | vddio detector | vddio Level    | vddd detector | vddd Level     |
-   |        |         |         | output         | shifter output | output        | shifter output |
-   +========+=========+=========+================+================+===============+================+
-   | 1      | Stable  | Ramping | no glitch      | no glitch      | glitches      | no glitch      |
-   +--------+---------+---------+----------------+----------------+---------------+----------------+
-   | 2      | Ramping | Stable  | glitches       | no glitch      | no glitch     | no glitch      |
-   +--------+---------+---------+----------------+----------------+---------------+----------------+
-   | 3      | Stable  | Stable  | no glitch      | no glitch      | no glitch     | no glitch      |
-   +--------+---------+---------+----------------+----------------+---------------+----------------+
-   | 4      | Ramping | Ramping | glitches       | glitches       | glitches      | glitches       |
-   +--------+---------+---------+----------------+----------------+---------------+----------------+
-
-**Case 1:** vddio ramp - vddd detector
-
-VDDIO detector is keeping system in reset, so ``enable_`` signals are 0.
-Hence LS input is being driven by 0, so a glitch on VDDD detector output is of no concern.
-
-**Case 2**: vddd ramp - vddio detector
-
-The system is not listening to output of VDDIO detector/level shifter when vddd ramps.
-Hence this is not a concern.
-
-**Case 3:** No concerns
-
-**Case 4:** Glitches on detector/level shifter outputs not a problem during concurrent ramps.
-
-The user must connect the power and ground to the less noisy sources.
-
-
-:lib:`sky130_fd_io` Pin Information
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-#. DFT, BIST Pins
-
-   As a summary, there is no additional DFT circuitry needed to test the :cell:`sky130_fd_io__gpio`.
-   However, DFT circuitry has been added to the :cell:`sky130_fd_io__sio` macro to test the references from the :cell:`sky130_fd_io__refgen` to the :cell:`sky130_fd_io__sio` macro.
-
-#. Bulk Pins
-
-   There are no bulk pins to the LV devices in this library.
-
-   Some high voltage pfet bodies are connected to their sources.
-   These pfet bodies are connected to the I/O supply ``vddio``.
-   There are some high voltage pfet bodies that are associated with the pad during an overvoltage or hot swap event.
-   When a hot swap or overvoltage event occurs, these bodies are connected to the pad otherwise they are connected to the I/O supply ``vddio``.
-
-   There are nfet bodies that do not connect to common ground.
-   These bodies are in an isolated psub and are connected to ``vssd``.
-   This is required in order to ensure that the threshold voltage does not change if substrate bias is applied.
-   Normally, this scheme is used in the input buffer to ensure that the input trip does not shift due to substrate biasing.
-
-#. Power Supply Pins
-
--  The :cell:`sky130_fd_io__gpio` cells use the main Vddio/Vssio connections for their ESD current steering diodes.
-
--  The main Vddio/Vssio power rails are used for the digital output driver only. A separately routed ``Vddio_quiet/Vssio_quiet`` bus is used for all lower current circuits.
-
--  Most LV logic is in the Vccd domain. A few signals are in the Vcchib domain to enable DeepSleep functionality.
-
--  The AMUXBUS section contains switches that are supplied from the Vdda domain. The gates are driven using the Vswitch supply, which is either equal to Vdda or pumped up from it. If the product has no Programmable Analog, these supplies can be connected to Vddio (e.g. TSGx).
-
--  The AMUXBUS section contains shunting switches to Vssio/Vddio for the sensing/shielding currents during CSD operation. These use the ``Vssio_quiet/Vddio_quiet`` rails with private routes to the corresponding Vssio/Vddio pads to minimize the noise experienced due to IR- Drop caused by switching current of regular digital drivers.
-
--  There are no control signals in the Vdda domain. Only the AMUXBUS buses themselves are in the Vdda domain.
-
-
-Timing Requirements and Diagrams
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The following diagrams apply to the input buffer AC parameters.
-
-.. figure:: figures/timing_diagram_gpio_tpd_trfout.png
-   :name: sky130_fd_io__gpio tpd trfout
-   :width: 5.17000in
-   :height: 3.50000in
-
-   :cell:`sky130_fd_io__gpio`, tPD, tRFout
-
-.. figure:: figures/timing_diagram_sio_tpd_trfout.png
-   :name: sky130_fd_io__sio tpd trfout
-   :width: 5.40000in
-   :height: 3.50000in
-
-   :cell:`sky130_fd_io__sio` tPD, tRFout
-
-.. figure:: figures/timing_diagram_gpio_sio_tdis_ten.png
-   :name: gpio sio tdis ten
-   :width: 5.40000in
-   :height: 2.48000in
-
-   :cell:`sky130_fd_io__gpio` & :cell:`sky130_fd_io__sio` tDIS, tEN
-
-The following timing diagrams apply to the output buffer AC parameters.
-
-.. figure:: figures/timing_diagram_gpio_tpd_trfout_tslew.png
-   :name: sky130_fd_io__gpio tpd trfout
-   :width: 5.40000in
-   :height: 3.45000in
-
-   :cell:`sky130_fd_io__gpio` tPD, tRFout (tSLEW)
-
-.. figure:: figures/timing_diagram_gpio_and_sio_non-regulated_outbuf_tolz_internal_measurement_method_for_tohz.png
-   :name: non-regulated outbuf tolz
-   :width: 5.40000in
-   :height: 3.44000in
-
-   :cell:`sky130_fd_io__gpio` and :cell:`sky130_fd_io__sio` non-regulated outbuf tOLZ & internal measurement method for tOHZ
-
-.. figure:: figures/timing_diagram_gpio_and_sio_non-regulated_outbuf_tohz_external_measurement_method.png
-   :name: non-regulated outbuf tohz
-   :width: 5.40000in
-   :height: 2.91000in
-
-   :cell:`sky130_fd_io__gpio` and :cell:`sky130_fd_io__sio` non-regulated outbuf tOHZ external measurement method
-
-.. figure:: figures/timing_diagram_sio_regulated_outbuf_ttrfout_tslew.png
-   :name: sky130_fd_io__sio regulated outbuf ttrfout
-   :width: 5.40000in
-   :height: 3.38000in
-
-   :cell:`sky130_fd_io__sio` regulated outbuf ttRFout(tSLEW)
-
-.. figure:: figures/timing_diagram_sio_regulated_outbuf_tolz_external_measurement_method_for_tohz.png
-   :name: sky130_fd_io__sio regulated outbuf tolz
-   :width: 5.40000in
-   :height: 3.62000in
-
-   :cell:`sky130_fd_io__sio` regulated outbuf tOLZ & external measurement method for tOHZ
-
-.. figure:: figures/timing_diagram_sio_regulated_outbuf_tohz_external_measurement_method.png
-   :name: sky130_fd_io__sio regulated outbuf tohz
-   :width: 5.40000in
-   :height: 3.16000in
-
-   :cell:`sky130_fd_io__sio` regulated outbuf tOHZ external measurement method
-
-.. figure:: figures/timing_diagram_gpio_and_sio_hold_state_mode_timing_diagram.png
-   :name: hold state mode timing diagram
-   :width: 5.40000in
-   :height: 3.25000in
-
-   :cell:`sky130_fd_io__gpio` and :cell:`sky130_fd_io__sio` Hold State Mode Timing Diagram
-
-Block Level Interfaces
-~~~~~~~~~~~~~~~~~~~~~~
-
-The :cell:`sky130_fd_io__gpio` and :cell:`sky130_fd_io__sio` cells interface with the core and the external world.
-These cells accept inputs from the core at ``vcchib``, ``vccd``, ``vdda`` and ``vddio`` voltage levels.
-The cell interfaces with the external world at ``vddio`` and ``vdda`` levels.
-This cell also produces output signals to the core at ``vcchib`` and ``vddio`` levels.
-``vcchib`` tracks vccd in normal operation and does not track ``vccd`` in sleep mode in which ``vddio`` and ``vcchib`` are up and ``vccd`` is down.
-
-The :cell:`sky130_fd_io__sio_macro` cell is like the :cell:`sky130_fd_io__gpio` cell and it also accepts analog voltage levels as inputs and produces analog voltages at the pad.
-
-The internal blocks on the ``vcchib`` power domain are input buffers and control logic for ``oe_hs`` (hot swap output enable).
-
-The Reference voltage generator block receives the vohref analog global signal and has low voltage input configuration signals
-(``vreg_en``, ``vref_sel`` , ``ibuf_sel`` , ``vtrip_sel`` ).
-This block provides ``voutref`` reference voltage and ``refleak_bias`` bias voltage for the :cell:`sky130_fd_io__sio` Regulated Output Buffer and the ``vinref`` reference
-voltage for the :cell:`sky130_fd_io__sio` differential input buffer.
-The internal blocks on the ``vcchib`` power domain is the internal current bias generator and a level shifter block, that controls that sub-block.
-
-The Reference voltage generator ``vcc_a`` pin must be connected to the analog supply of the chip, to reduce its noise sensitivity at its Vinref and
-Voutref outputs.
-This issue affects the supply noise sensitivity in the :cell:`sky130_fd_io__sio` input buffer and the :cell:`sky130_fd_io__sio` Regulated Output Buffer, respectively.
-
-Reset and Initialization
-~~~~~~~~~~~~~~~~~~~~~~~~
-
-There are two resets to the I/O blocks -
-
--  ``Enable_h`` - This is a reset issued by the SRSS in VDDD (VDDIO) domain that resets everything when it is at logic 0 in the I/O block and ensures that the I/O blocks are tri-stated
-
--  ``Enable_vdda_h`` - This is reset issued by the SRSS in VDDA domain to ensure that any analog blocks in VDDA domain are reset when ``enable_vdda_h`` is at logic 0. This will ensure that any portions of the I/O (Analog Mux) that are tied to PAD are reset and the I/O block is in reset state.
-
-Power Modes
-~~~~~~~~~~~
-
-The :cell:`sky130_fd_io__gpio` and :cell:`sky130_fd_io__sio` buffers support multiple standby modes.
-The following tables list the input and output standby modes and their dependency on the related control inputs.
-
-.. table:: :cell:`sky130_fd_io__gpio` & :cell:`sky130_fd_io__sio` Input Buffer Standby Modes
-   :name: input buffer standby modes
-
-   +--------------+-------------+---------+-------------------------------+
-   | ``enable_h`` | ``inp_dis`` | dm<2:0> | Standby Mode Description      |
-   +==============+=============+=========+===============================+
-   | 1            | X           | 000     | Input Buffer disabled         |
-   |              |             |         | by drive mode state           |
-   +--------------+-------------+---------+-------------------------------+
-   | 1            | 1           | XXX     | Input Buffer disabled         |
-   |              |             |         | by input buffer disable input |
-   +--------------+-------------+---------+-------------------------------+
-   | 0            | X           | XXX     | Input Buffer disabled         |
-   +--------------+-------------+---------+-------------------------------+
-
-.. table:: :cell:`sky130_fd_io__gpio` & :cell:`sky130_fd_io__sio` Output Buffer Standby Modes
-   :name: output buffer standby modes
-
-   +--------------+-------------+----------+---------+-----------------------------+
-   | ``enable_h`` | ``hld_h_n`` | ``oe_n`` | dm<2:0> | Standby Mode Description    |
-   +==============+=============+==========+=========+=============================+
-   | 1            | 1           | X        | 00X     | Output Buffer disabled      |
-   |              |             |          |         | by drive mode state         |
-   +--------------+-------------+----------+---------+-----------------------------+
-   | 1            | 1           | 1        | * 1XX   | Output Buffer disabled by   |
-   |              |             |          | * X1X   | output buffer enable signal |
-   +--------------+-------------+----------+---------+-----------------------------+
-   | 1            | 0           | X        | XXX     | Output Buffer maintains     |
-   |              |             |          |         | previous state              |
-   +--------------+-------------+----------+---------+-----------------------------+
-   | 0            | X           | X        | XXX     | Output Buffer tri-stated    |
-   +--------------+-------------+----------+---------+-----------------------------+
-
-The standby power consumption depends on the state of the control bits.
-For example, the lowest standby current mode is achieved when oe_n=1, inp_dis=1, dm<2:0>=000.
-During this mode the input and output buffer are permanently disabled allowing the circuits to be configured for minimal leakage current.
-
-For all control bit states not covered in :numref:`power detector outputs` and :numref:`input buffer standby modes` either the input buffer, output buffer, or both buffers will be enabled.
-During these modes the I/O buffer is considered active.
-The power consumption for these modes depends on the drive mode setting and the switching frequency.
-
-Register Definitions
-~~~~~~~~~~~~~~~~~~~~
-
-This IP contains latches to hold the previous state of the output when the hold state mode is selected.
-When the hold state mode is selected the internal power supply connected to the output path may float.
-The hold state latches are required to hold the previous output state regardless of the current state of the control signals.
-
-Power Architecture and Modes
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The IP cells include multiple power domains.
-In general there is a high voltage domain and a low voltage domain.
-The high voltage domain is supplied by the I/O power supply ``vddio``.
-There are no switched domains located inside the cell for the ``vddio`` power supply domain.
-
-The low voltage domain consists of two internally generated supplies, vccd and vcchib.
-The vccd supply is the regulated internal supply that can be forced low during low standby current modes.
-The vcchib supply is the low voltage regulated keep alive supply.
-This supply is kept active during low standby current modes and the level can drop to 1.2V.
-The chip team is responsible to correctly controlling the levels on these supplies during the appropriate modes of operation.
-
-Grounded Power Supplies
-~~~~~~~~~~~~~~~~~~~~~~~
-
-As there are multiple power supplies to the I/O's, no single power supply will be grounded while another supply is active.
-This will help alleviate the grounded NWELL issues that induce latch-up.
-It is OK to float a supply while another is active though.
-
-Block behavioral model requirements
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The :cell:`sky130_fd_io__gpio` and :cell:`sky130_fd_io__sio` input buffers are operating from the vcchib supply.
-This means that the input buffer can operate even when vccd is taken down to 0 or floats.
-But, note that before taking vccd=0 (or floating vccd), the hold mode must be asserted i.e.
-hld_h_n=0 must go to 0 before vccd is taken to 0.
-During the hold mode of operation and with vccd=0 (or floating), the input buffer can actively drive out depending on pad input if there is a valid
-I/O (vddio, vddioq and vcchib) power supply.
-This functionality is implemented in the behavioral model.
-If vccd=0 (or floats) and when the I/O is not in the hold mode of operation, the behavioral model would force an ``X`` on the outputs of the input
-buffer (``out`` and ``out_h``) and the input buffer cannot be actively driven from pad.
-
-Block Integration Requirements and Constraints
-----------------------------------------------
-
-General Integration Requirements
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The following is a list of items users must be aware of before using this IP.
-
-1. The IP cells described within this document are I/O cells and Power and Ground pads. Each cell (GPIO and :cell:`sky130_fd_io__sio`) contains an input and output buffer, with a bond pad.
-
-2. The circuit blocks do not include any circuitry for test mode control or for self-test. All input pin states will be exercisable in all product applications so that the IP block test coverage goals will be met.
-
-3. The control signal ``enable_h`` will override all other input and control pins to force the input and output to a predetermined state. When ``enable_h`` transitions from logic 0 to logic 1, the block expects all of the inputs to be valid state. If ``hld_h_n=0`` when the ``enable_h`` pin transitions 0->1 (inactive->active) the state set by ``enable_h`` is latched in the output driver.
-
-4. There is a separate ``enable_vdda_h`` control signal to the :cell:`sky130_fd_io__gpio`. This control signal is logic 0 when VDDA supply is ramping up. This control signal ensures that the AMUX is completely turned OFF when ``enable_vdda_h`` is at logic 0.
-
-5. It is permissible to externally connect the I/O pin to a voltage above vddio or below ``vssd_io``, provided that the current flowing into/out of the pin is externally limited to 100uA.
-
-6. The :cell:`sky130_fd_io__gpio` and :cell:`sky130_fd_io__sio` input buffers are operating from the vcchib supply. This means that the input buffer can operate even when vccd is taken down to 0V or floats. But note that before taking vccd=0 (or floating vccd), the hold mode must be asserted i.e. ``hld_h_n=0`` must go to 0 before vccd is taken to 0. During the hold mode of operation and with vccd=0 (or floating), the input buffer can actively drive out depending on pad input if there is a valid I/O (vddio, vddioq and vcchib) power supply. This functionality is implemented in the behavioral model. If vccd=0 (or floats) and when the I/O is not in the hold mode of operation, the behavioral model would force an ``X`` on the outputs of the input buffer (``out`` and ``out_h``) and the input buffer cannot be actively driven from pad.
-
-7. In hibernate mode, the I/P buffer just needs to toggle. It need not meet the VIH/VIL specs.
-
-8. The charge pump is powered down during startup and thus VSWITCH=VDDA during startup.
-
-9. ``tie_weak_hi_h`` signal for the :cell:`sky130_fd_io__top_xres3v2` is really a pull up and not intended to interact with any other intermediate strength drivers (weak, pull).
-
-10. For the cell :cell:`sky130_fd_io__top_axresv2`, glitch filter input (``filter_in_h``) is intended to be connected to only the :cell:`sky130_fd_io__gpio` output and no other uses are permitted.
-
-11. The glitch filter in :cell:`sky130_fd_io__top_xres2v2`, :cell:`sky130_fd_io__top_xres3v2` and :cell:`sky130_fd_io__top_axresv2` cells have metal1 option to increase/decrease the glitch rejection pulse width.
-
-12. When using the pad connections of the :cell:`sky130_fd_io__sio_macro`, care should be taken about power-domain interaction at PAD (when used as I2C pads). The :cell:`sky130_fd_io__sio_macro` has a tracking NWELL on its PAD which is driven to VDDIO when PAD<VDDIO. If a pad is being connected to a signal from any other power-domain other than VDDIO, power- supply sequencing issues must be analyzed at chip- level.
-
-
-1. Chip Floor planning guidelines when using :lib:`sky130_fd_io` to build I/O ring
-
-   The following information is a MUST know when using the :lib:`sky130_fd_io` library components to build an I/O ring.
-   Due to the complex nature of these I/O's and other PG pads, it is critical that the following matrix be understood when placing the cells that form
-   the I/O ring.
-
-   -  ALL cells CANNOT be abutted with each other. There are limitations because of the ESD LU rules and due to the different Deep NWELLS being used in different cells.
-
-   -  It is strongly recommended to run a DRC at the chip level as soon as the I/O cell placements are complete. Also, scheduling a preliminary ESD review is recommended before routing is started.
-
-2. Layout Integration guidelines specific to :cell:`sky130_fd_io__gpio`
-
-   1. The GPIO cell (:cell:`sky130_fd_io__top_gpio`) forms part of the I/O ring. If multiple instances of this cell are used, they must be mirrored and placed by abutment.
-
-   2. The boundary of the :cell:`sky130_fd_io__gpio` cell (PAD side) can be abutted with the seal ring. It takes care of the pad to seal ring rules internally.
-
-   3. The :cell:`sky130_fd_io__gpio` cell can be abutted to the rest of the cells in this IP by proper placement as documented below for the rest of the public cells.
-
-3. ``enable_h`` integration guidelines for :cell:`sky130_fd_io__gpio_ovtv2` and :cell:`sky130_fd_io__sio_macro`
-
-   Any product that has I2C ports and is claiming over-voltage tolerance needs to ensure that the glitch on ``enable_h`` coming into the :cell:`sky130_fd_io__top_gpio_ovtv2` or :cell:`sky130_fd_io__sio_macro` is less than 300mV.
-
-Scan Attributes to be used for :lib:`sky130_fd_io` cells
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-:cell:`sky130_fd_io__gpio`'s can be used as SCAN IN and SCAN Out pads based on the configuration.
-
-However, if a :cell:`sky130_fd_io__gpio` is configured as a SCAN IN pad, all the output buffer control signals can be toggled.
-Likewise, if the :cell:`sky130_fd_io__gpio` is used as a SCAN OUT pad, all the input buffer control signals can be toggled.
-
-.. table:: Control signals that can be toggled for public cells
-   :name: public cells control signals
-
-   +------+---------------------------------------+--------------------------+-----------------------------+----------------------+
-   | S.No | Public Cell                           | * Used as SCAN IN        | * Used as SCAN OUT          | * Others             |
-   |      |                                       | * dm[3]=001              | * dm=110                    | * ``analog_en=0``    |
-   |      |                                       | * ``analog_en=0``        | * ``inp_dis=1``             | * ``hld_vdda_h_n=0`` |
-   |      |                                       |                          | * ``analog_en=0``           |                      |
-   +======+=======================================+==========================+=============================+======================+
-   | 1    | :cell:`sky130_fd_io__top_gpiov2`      | * out                    | * ``vtrip_sel ib_mode_sel`` |                      |
-   |      |                                       | * ``oe_n``               | * ``analog_sel analog_pol`` |                      |
-   |      |                                       | * slow                   |                             |                      |
-   |      |                                       | * ``analog_sel``         |                             |                      |
-   |      |                                       | * ``analog_pol``         |                             |                      |
-   +------+---------------------------------------+--------------------------+-----------------------------+----------------------+
-   | 2    | :cell:`sky130_fd_io__top_gpio_ovtv2`  | * out                    | * ``vtrip_sel``             |                      |
-   |      |                                       | * ``oe_n``               | * ``ib_mode_sel<1:0>``      |                      |
-   |      |                                       | * slow                   | * ``analog_sel``            |                      |
-   |      |                                       | * ``analog_sel``         | * ``analog_pol``            |                      |
-   |      |                                       | * ``analog_pol``         | * ``hys_trim``              |                      |
-   |      |                                       | * ``hys_trim``           | * ``slew_ctl<1:0>``         |                      |
-   |      |                                       | * ``slew_ctl<1:0>``      |                             |                      |
-   +------+---------------------------------------+--------------------------+-----------------------------+----------------------+
-   | 3    | :cell:`sky130_fd_io__sio_macro`       | * ``inp_dis=0``          | * ``vreg_en=0``             |                      |
-   |      |                                       | * ``vtrip_sel=0``        | * ``vreg_en_refgen=0``      |                      |
-   |      | (assuming both the pad in macro       | * ``hld_h_n=1``          | * ``vtrip_sel<1:0>``        |                      |
-   |      | are used the same way)                |                          |                             |                      |
-   |      |                                       | * ``ibuf_sel=0``         | * ``ibuf_sel<1:0>``         |                      |
-   |      |                                       | * ``vreg_en_refgen=0``   | * ``voh_sel<2:0>``          |                      |
-   |      |                                       | * out<1:0>               | * ``vref_sel<1:0>``         |                      |
-   |      |                                       | * ``oe_n<1:0>``          | * ``vtrip_sel_refgen``      |                      |
-   |      |                                       | * slow<1:0>              | * ``ibuf_sel_refgen``       |                      |
-   |      |                                       | * ``voh_sel<1:0>``       | * ``dft_refgen=0``          |                      |
-   |      |                                       | * ``vref_sel<1:0>``      |                             |                      |
-   |      |                                       | * ``vtrip_sel_refgen=0`` |                             |                      |
-   |      |                                       | * ``ibuf_sel_refgen=0``  |                             |                      |
-   |      |                                       | * ``dft_refgen=0``       |                             |                      |
-   +------+---------------------------------------+--------------------------+-----------------------------+----------------------+
-   | 4    | :cell:`sky130_fd_io__top_amuxsplitv2` |                          |                             | * ``switch_aa_sl``   |
-   |      |                                       |                          |                             | * ``switch_aa_sr``   |
-   |      |                                       |                          |                             | * ``switch_aa_s0``   |
-   |      |                                       |                          |                             | * ``switch_bb_sl``   |
-   |      |                                       |                          |                             | * ``switch_bb_sr``   |
-   |      |                                       |                          |                             | * ``switch_bb_s0``   |
-   +------+---------------------------------------+--------------------------+-----------------------------+----------------------+
diff --git a/libraries/sky130_fd_io/v0.0.1 b/libraries/sky130_fd_io/v0.0.1
new file mode 160000
index 0000000..e89f551
--- /dev/null
+++ b/libraries/sky130_fd_io/v0.0.1
@@ -0,0 +1 @@
+Subproject commit e89f551c5b934870b1eeef1898d410554713fb74
diff --git a/libraries/sky130_fd_io/v0.0.2 b/libraries/sky130_fd_io/v0.0.2
new file mode 160000
index 0000000..4048fc6
--- /dev/null
+++ b/libraries/sky130_fd_io/v0.0.2
@@ -0,0 +1 @@
+Subproject commit 4048fc6e03b5a246a1287777ac4f0e4a99ef484f
diff --git a/libraries/sky130_fd_io/v0.1.0 b/libraries/sky130_fd_io/v0.1.0
new file mode 160000
index 0000000..40adf19
--- /dev/null
+++ b/libraries/sky130_fd_io/v0.1.0
@@ -0,0 +1 @@
+Subproject commit 40adf19b0baa59da5fb0b8b8b63d0e52dc8697c6
diff --git a/libraries/sky130_fd_io/v0.2.0 b/libraries/sky130_fd_io/v0.2.0
new file mode 160000
index 0000000..80ef9b2
--- /dev/null
+++ b/libraries/sky130_fd_io/v0.2.0
@@ -0,0 +1 @@
+Subproject commit 80ef9b27e7e677f4c0e9f9ee39ea94b9cd261f39
diff --git a/libraries/sky130_fd_io/v0.2.1 b/libraries/sky130_fd_io/v0.2.1
new file mode 160000
index 0000000..01b1869
--- /dev/null
+++ b/libraries/sky130_fd_io/v0.2.1
@@ -0,0 +1 @@
+Subproject commit 01b18699b4102d8e54ad1406b3991ecb652e5aee
diff --git a/libraries/sky130_fd_pr/latest b/libraries/sky130_fd_pr/latest
index 6b9ba08..f62031a 160000
--- a/libraries/sky130_fd_pr/latest
+++ b/libraries/sky130_fd_pr/latest
@@ -1 +1 @@
-Subproject commit 6b9ba083ee94f92e2702f9993f3e5b9fe71beef7
+Subproject commit f62031a1be9aefe902d6d54cddd6f59b57627436
diff --git a/libraries/sky130_fd_pr/v0.10.0 b/libraries/sky130_fd_pr/v0.10.0
index 54c1ee1..6a45d86 160000
--- a/libraries/sky130_fd_pr/v0.10.0
+++ b/libraries/sky130_fd_pr/v0.10.0
@@ -1 +1 @@
-Subproject commit 54c1ee17b8482cb0a0ab981a68f1fefb39c5e790
+Subproject commit 6a45d866c3d92404c024419c16ca3ea2fbbde18b
diff --git a/libraries/sky130_fd_pr/v0.10.1 b/libraries/sky130_fd_pr/v0.10.1
index 46a6658..5f8c221 160000
--- a/libraries/sky130_fd_pr/v0.10.1
+++ b/libraries/sky130_fd_pr/v0.10.1
@@ -1 +1 @@
-Subproject commit 46a665858883cf44b09fad0777aa32b9527d8f30
+Subproject commit 5f8c22105c91565be4eb1ff020180cc1aba5ef8c
diff --git a/libraries/sky130_fd_pr/v0.11.0 b/libraries/sky130_fd_pr/v0.11.0
index 4596aee..c424389 160000
--- a/libraries/sky130_fd_pr/v0.11.0
+++ b/libraries/sky130_fd_pr/v0.11.0
@@ -1 +1 @@
-Subproject commit 4596aee61b03570235f987cc33df9733983214f0
+Subproject commit c424389932c4d81256fb892d11f6a2c814af6b1e
diff --git a/libraries/sky130_fd_pr/v0.12.0 b/libraries/sky130_fd_pr/v0.12.0
index 30e5e33..0cd300e 160000
--- a/libraries/sky130_fd_pr/v0.12.0
+++ b/libraries/sky130_fd_pr/v0.12.0
@@ -1 +1 @@
-Subproject commit 30e5e33ed4259974cd851867c6df30a4b74914ce
+Subproject commit 0cd300eedf6c91b53bf6a3574718e9d2405e6c13
diff --git a/libraries/sky130_fd_pr/v0.12.1 b/libraries/sky130_fd_pr/v0.12.1
index 3f9ec20..be3566d 160000
--- a/libraries/sky130_fd_pr/v0.12.1
+++ b/libraries/sky130_fd_pr/v0.12.1
@@ -1 +1 @@
-Subproject commit 3f9ec205ee5fd6a815d56b7677de13d4c174a958
+Subproject commit be3566d27f9fb3f96d788caa23887931c376189e
diff --git a/libraries/sky130_fd_pr/v0.13.0 b/libraries/sky130_fd_pr/v0.13.0
index 29fa6f3..32aede2 160000
--- a/libraries/sky130_fd_pr/v0.13.0
+++ b/libraries/sky130_fd_pr/v0.13.0
@@ -1 +1 @@
-Subproject commit 29fa6f30f471694c6d7f6376233634600f82660f
+Subproject commit 32aede2994dd27cd791155e0aa1a73a5785af617
diff --git a/libraries/sky130_fd_pr/v0.20.0 b/libraries/sky130_fd_pr/v0.20.0
index 66a8c2d..9e08415 160000
--- a/libraries/sky130_fd_pr/v0.20.0
+++ b/libraries/sky130_fd_pr/v0.20.0
@@ -1 +1 @@
-Subproject commit 66a8c2dbd82743ac39bb9cb33bf6fd3a6762ed82
+Subproject commit 9e08415b20a813ba7038177da5f18aaaaea0b56b
diff --git a/libraries/sky130_fd_pr/v0.20.1 b/libraries/sky130_fd_pr/v0.20.1
index 6b9ba08..f62031a 160000
--- a/libraries/sky130_fd_pr/v0.20.1
+++ b/libraries/sky130_fd_pr/v0.20.1
@@ -1 +1 @@
-Subproject commit 6b9ba083ee94f92e2702f9993f3e5b9fe71beef7
+Subproject commit f62031a1be9aefe902d6d54cddd6f59b57627436
diff --git a/libraries/sky130_fd_sc_hd/latest b/libraries/sky130_fd_sc_hd/latest
index 28019fc..ac7fb61 160000
--- a/libraries/sky130_fd_sc_hd/latest
+++ b/libraries/sky130_fd_sc_hd/latest
@@ -1 +1 @@
-Subproject commit 28019fca60c8a65d4a37a3ec0db0b90a1fe26630
+Subproject commit ac7fb61f06e6470b94e8afdf7c25268f62fbd7b1
diff --git a/libraries/sky130_fd_sc_hd/v0.0.1 b/libraries/sky130_fd_sc_hd/v0.0.1
index 3b14174..28c101f 160000
--- a/libraries/sky130_fd_sc_hd/v0.0.1
+++ b/libraries/sky130_fd_sc_hd/v0.0.1
@@ -1 +1 @@
-Subproject commit 3b141743ef43d12f6dc7906ea41d8a48aa927705
+Subproject commit 28c101fc5db17bb6cadefa4c2a146693c685f1dc
diff --git a/libraries/sky130_fd_sc_hd/v0.0.2 b/libraries/sky130_fd_sc_hd/v0.0.2
index 28019fc..ac7fb61 160000
--- a/libraries/sky130_fd_sc_hd/v0.0.2
+++ b/libraries/sky130_fd_sc_hd/v0.0.2
@@ -1 +1 @@
-Subproject commit 28019fca60c8a65d4a37a3ec0db0b90a1fe26630
+Subproject commit ac7fb61f06e6470b94e8afdf7c25268f62fbd7b1
diff --git a/libraries/sky130_fd_sc_hs/latest b/libraries/sky130_fd_sc_hs/latest
index 98372f0..1d051f4 160000
--- a/libraries/sky130_fd_sc_hs/latest
+++ b/libraries/sky130_fd_sc_hs/latest
@@ -1 +1 @@
-Subproject commit 98372f07325278030d44abc451f2cd919ba2429e
+Subproject commit 1d051f49bfe4e2fe9108d702a8bc2e9c081005a4
diff --git a/libraries/sky130_fd_sc_hs/v0.0.1 b/libraries/sky130_fd_sc_hs/v0.0.1
index 7ad9f32..81f5034 160000
--- a/libraries/sky130_fd_sc_hs/v0.0.1
+++ b/libraries/sky130_fd_sc_hs/v0.0.1
@@ -1 +1 @@
-Subproject commit 7ad9f328a4af07c8fd5f7d848d74709450168fb3
+Subproject commit 81f50340c068801dd2fd07d4343be6b28e241a9d
diff --git a/libraries/sky130_fd_sc_hs/v0.0.2 b/libraries/sky130_fd_sc_hs/v0.0.2
index 98372f0..1d051f4 160000
--- a/libraries/sky130_fd_sc_hs/v0.0.2
+++ b/libraries/sky130_fd_sc_hs/v0.0.2
@@ -1 +1 @@
-Subproject commit 98372f07325278030d44abc451f2cd919ba2429e
+Subproject commit 1d051f49bfe4e2fe9108d702a8bc2e9c081005a4
diff --git a/libraries/sky130_fd_sc_hvl/latest b/libraries/sky130_fd_sc_hvl/latest
new file mode 160000
index 0000000..4fd4f85
--- /dev/null
+++ b/libraries/sky130_fd_sc_hvl/latest
@@ -0,0 +1 @@
+Subproject commit 4fd4f858d16c558a6a488b200649e909bb4dd800
diff --git a/libraries/sky130_fd_sc_hvl/v0.0.1 b/libraries/sky130_fd_sc_hvl/v0.0.1
new file mode 160000
index 0000000..c86542d
--- /dev/null
+++ b/libraries/sky130_fd_sc_hvl/v0.0.1
@@ -0,0 +1 @@
+Subproject commit c86542d2d658a2fa689b2266d4e4e227a660fcc9
diff --git a/libraries/sky130_fd_sc_hvl/v0.0.2 b/libraries/sky130_fd_sc_hvl/v0.0.2
new file mode 160000
index 0000000..fc47788
--- /dev/null
+++ b/libraries/sky130_fd_sc_hvl/v0.0.2
@@ -0,0 +1 @@
+Subproject commit fc477882eaf986336a069c62b70a67d45487a4d7
diff --git a/libraries/sky130_fd_sc_hvl/v0.0.3 b/libraries/sky130_fd_sc_hvl/v0.0.3
new file mode 160000
index 0000000..4fd4f85
--- /dev/null
+++ b/libraries/sky130_fd_sc_hvl/v0.0.3
@@ -0,0 +1 @@
+Subproject commit 4fd4f858d16c558a6a488b200649e909bb4dd800
diff --git a/libraries/sky130_fd_sc_lp/latest b/libraries/sky130_fd_sc_lp/latest
new file mode 160000
index 0000000..e2c1e06
--- /dev/null
+++ b/libraries/sky130_fd_sc_lp/latest
@@ -0,0 +1 @@
+Subproject commit e2c1e0646999163d35ea7b2521c3ec5c28633e63
diff --git a/libraries/sky130_fd_sc_lp/v0.0.1 b/libraries/sky130_fd_sc_lp/v0.0.1
new file mode 160000
index 0000000..9ade3f1
--- /dev/null
+++ b/libraries/sky130_fd_sc_lp/v0.0.1
@@ -0,0 +1 @@
+Subproject commit 9ade3f192eba16db62624174859690211a660806
diff --git a/libraries/sky130_fd_sc_lp/v0.0.2 b/libraries/sky130_fd_sc_lp/v0.0.2
new file mode 160000
index 0000000..e2c1e06
--- /dev/null
+++ b/libraries/sky130_fd_sc_lp/v0.0.2
@@ -0,0 +1 @@
+Subproject commit e2c1e0646999163d35ea7b2521c3ec5c28633e63
diff --git a/libraries/sky130_fd_sc_ms/latest b/libraries/sky130_fd_sc_ms/latest
index 390bbc9..ae1b7f6 160000
--- a/libraries/sky130_fd_sc_ms/latest
+++ b/libraries/sky130_fd_sc_ms/latest
@@ -1 +1 @@
-Subproject commit 390bbc90badd0f63195b968a7a77bb45f9797fe7
+Subproject commit ae1b7f68821505cf2d93d9d44cce5ece22710fad
diff --git a/libraries/sky130_fd_sc_ms/v0.0.1 b/libraries/sky130_fd_sc_ms/v0.0.1
index e1bcbf8..14d70b1 160000
--- a/libraries/sky130_fd_sc_ms/v0.0.1
+++ b/libraries/sky130_fd_sc_ms/v0.0.1
@@ -1 +1 @@
-Subproject commit e1bcbf8eed456f6fa061581fec050f10da19ba3a
+Subproject commit 14d70b1f15931f2eeb093a2ea10e350c19dd88f9
diff --git a/libraries/sky130_fd_sc_ms/v0.0.2 b/libraries/sky130_fd_sc_ms/v0.0.2
index 390bbc9..ae1b7f6 160000
--- a/libraries/sky130_fd_sc_ms/v0.0.2
+++ b/libraries/sky130_fd_sc_ms/v0.0.2
@@ -1 +1 @@
-Subproject commit 390bbc90badd0f63195b968a7a77bb45f9797fe7
+Subproject commit ae1b7f68821505cf2d93d9d44cce5ece22710fad