diff --git a/docs/Makefile b/docs/Makefile
index 8e28876..db06a05 100644
--- a/docs/Makefile
+++ b/docs/Makefile
@@ -42,6 +42,13 @@
 
 .PHONY: help livehtml Makefile
 
+# Generate the rules/periphery-rules.rst from CSV files in rules/periphery/
+$(wildcard rules/periphery/*): | $(CONDA_ENV_PYTHON)
+	true
+
+rules/periphery-rules.rst: $(wildcard rules/periphery/*) | $(CONDA_ENV_PYTHON)
+	$(IN_CONDA_ENV) cd rules/periphery; ./periphery-split-csv.py > /dev/null
+
 # Various automated fixups that can be run
 fixup:
 	# Make sure it is SkyWater
diff --git a/docs/_static/extra.css b/docs/_static/extra.css
index c9b2423..93d4aa8 100644
--- a/docs/_static/extra.css
+++ b/docs/_static/extra.css
@@ -41,3 +41,11 @@
 	white-space: pre;
 	display: inline-block;
 }
+
+.page-content table thead th {
+	position: sticky !important;
+	top: 0;
+	z-index: 2;
+	background-color: #fff;
+	box-shadow: 0 1px 1px -1px rgba(0, 0, 0, 0.4);
+}
diff --git a/docs/_static/metal_stack.svg b/docs/_static/metal_stack.svg
index 0002aa8..d6f5d33 100644
--- a/docs/_static/metal_stack.svg
+++ b/docs/_static/metal_stack.svg
@@ -27,8 +27,8 @@
 <path d="M643,923 L643,779 1619,779 1619,923 z" fill="#cbf3f3" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#cbf3f3" />
 <path d="M643,715 L643,571 1619,571 1619,715 z" fill="#cbf3f3" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#cbf3f3" />
 <path d="M659,491 L659,283 1571,283 1571,491 z" fill="#cbf3f3" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#cbf3f3" />
-<g transform="matrix(   1    0   -0    1 579  27)" fill="#000000" >
-<text stroke="none" font-family="Times" font-size="40" ><tspan x="0" y="0">SkyWater Sky130A metal stack (not to scale!):</tspan>
+<g transform="matrix(   1    0   -0    1 950  27)" fill="#000000" >
+<text stroke="none" font-family="Times" font-size="40" ><tspan x="0" y="0">(Diagram not to scale!)</tspan>
 </text></g>
 <path d="M443,1483 L1619,1483 " fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
 <path d="M931,1483 L931,1499 " fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
diff --git a/docs/conf.py b/docs/conf.py
index 88e0f0f..31fb98f 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -120,7 +120,9 @@
     'env',
     'Thumbs.db',
     '.DS_Store',
+    # Files included in other rst files.
     'code-of-conduct.rst',
+    'rules/periphery-rules.rst',
 ]
 
 # The name of the Pygments (syntax highlighting) style to use.
@@ -306,6 +308,7 @@
 # A list of files that should not be packed into the epub file.
 epub_exclude_files = ['search.html']
 
+
 # -- Extension configuration -------------------------------------------------
 
 # -- Options for todo extension ----------------------------------------------
@@ -362,6 +365,7 @@
 
 def setup(app):
     app.add_css_file('extra.css')
+    add_role(app, 'cell_name')
     add_role(app, 'lib_process')
     add_role(app, 'lib_src')
     add_role(app, 'lib_type')
diff --git a/docs/contents.rst b/docs/contents.rst
new file mode 100644
index 0000000..afed585
--- /dev/null
+++ b/docs/contents.rst
@@ -0,0 +1,9 @@
+PDK Contents
+============
+
+.. toctree::
+    :name: pdk-contents
+    :maxdepth: 4
+
+    Libraries <contents/libraries>
+    File Types <contents/file_types>
diff --git a/docs/contents/file_types.rst b/docs/contents/file_types.rst
new file mode 100644
index 0000000..840d1a2
--- /dev/null
+++ b/docs/contents/file_types.rst
@@ -0,0 +1,45 @@
+File Types
+==========
+
+
++------------------------------+-------------------------------------------+---------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+
+| File Type                    | What does it do?                          |                            Open Tooling Options                     |                                    Closed Tooling Options                                              |
+|                              |                                           +-----------------+--------+------------------------+-----------------+-------------------+--------------+-------------------------+-------------------------------------------+
+|                              |                                           | Tool            | Status | File format            | Source          | Tool              | Status       | File format             | Source                                    |
++==============================+===========================================+=================+========+========================+=================+===================+==============+=========================+===========================================+
+| Parameterized Cell           | Primitive devices that have layouts       | Magic           | Ready  | TCL script             | Hand Written    | Cadence Virtuoso  | In Progress  | Cadence PCells          | Hand Written                              |
+| Generators                   | determined by parameterization.           |                 |        |                        |                 |                   |              |                         |                                           |
+|                              |                                           |                 |        |                        |                 |                   |              |                         |                                           |
++------------------------------+-------------------------------------------+-----------------+--------+------------------------+-----------------+-------------------+--------------+-------------------------+-------------------------------------------+
+| DRC Deck                     | Verifies a design meets the design rules  | Magic           | Ready  | Magic techfile         | Hand Written    | Mentor Calibre    | In progress  | SVRF Rule Decks         | Generated from documentation data         |
++------------------------------+-------------------------------------------+-----------------+--------+------------------------+-----------------+-------------------+--------------+-------------------------+-------------------------------------------+
+| LVS Deck                     | Verifies layout and schematic are         | Magic           | Ready  | Magic techfile         | Hand Written    | Mentor Calibre    | In progress  | SVRF Rule Decks         | Generated from documentation data         |
+|                              | equivalent.                               +-----------------+--------+------------------------+-----------------+                   |              |                         |                                           |
+|                              |                                           | Netgen          | Ready  | Netgen setup file      | Hand Written    |                   |              |                         |                                           |
++------------------------------+-------------------------------------------+-----------------+--------+------------------------+-----------------+-------------------+--------------+-------------------------+-------------------------------------------+
+| GDS Generator                | Creates mask layout data.                 | Magic           | Ready  | Magic techfile         | Hand designed   |                                                                                                        |
++------------------------------+-------------------------------------------+-----------------+--------+------------------------+-----------------+--------------------------------------------------------------------------------------------------------+
+| Library Exchange Format      | Abstract cell view.                       | Magic           | Ready  | LEF                    | Generated from  | ?                                                                                                      |
+| Macros                       |                                           |                 |        |                        | GDS data        |                                                                                                        |
++------------------------------+-------------------------------------------+-----------------+--------+------------------------+-----------------+--------------------------------------------------------------------------------------------------------+
+| Timing Files                 | Describes pin-to-pin timing               | ?               | Ready  | Liberty                | Generated from  | ?                                                                                                      |
+|                              |                                           |                 |        |                        | JSON data       |                                                                                                        |
++------------------------------+-------------------------------------------+-----------------+--------+------------------------+-----------------+-------------------+--------------+-------------------------+-------------------------------------------+
+| Netlists                     | Transistor level circuit description      | Ngspice         | Ready  | Ngspice or CDL         | ?               | ?                 | ?            | OpenAccess?             | Generated from spice files                |
++------------------------------+-------------------------------------------+-----------------+--------+------------------------+-----------------+-------------------+--------------+-------------------------+-------------------------------------------+
+| Device Models                | Models for use with SPICE                 | Ngspice         | Ready  | SPICE simulation file  | ?               | Cadence Spectre   | In Progress  | Spectre?                | Generated from spice files                |
++------------------------------+-------------------------------------------+-----------------+--------+------------------------+-----------------+-------------------+--------------+-------------------------+-------------------------------------------+
+| Schematic                    | Transistor level circuit description      | Xcircuit?       | None   | EDIF                   | ?               | Cadence Virtuoso  | In Progress  | OpenAccess?             | ?                                         |
++------------------------------+-------------------------------------------+-----------------+--------+------------------------+-----------------+-------------------+--------------+-------------------------+-------------------------------------------+
+| Schematic Symbol             | Symbol for use in schematics              | Xcircuit?       | None   | EDIF                   | ?               | Cadence Virtuoso  | In Progress  | OpenAccess?             | ?                                         |
++------------------------------+-------------------------------------------+-----------------+--------+------------------------+-----------------+-------------------+--------------+-------------------------+-------------------------------------------+
+| Verilog testbench            | Digital simulation                        | Icarus Verilog  | Ready  | Verilog                | ngsim           | Cadence ?         | ?            | OpenAccess?             | Generated from Verilog files              |
++------------------------------+-------------------------------------------+-----------------+--------+------------------------+-----------------+-------------------+--------------+-------------------------+-------------------------------------------+
+| XSPICE                       | Mixed-signal simulation                   | Ngspice         | Ready  | SPICE                  | ?               | ?                 | ?            | ?                       | ?                                         |
++------------------------------+-------------------------------------------+-----------------+--------+------------------------+-----------------+-------------------+--------------+-------------------------+-------------------------------------------+
+|                              | Rules for scribe lines and saw lines      | ?               | None   | Unknown                | ?               | Cadence ?         | In Progress  | Cadence SKILL script    | Hand written                              |
++------------------------------+-------------------------------------------+-----------------+--------+------------------------+-----------------+-------------------+--------------+-------------------------+-------------------------------------------+
+| Parameterized Cell           | Rules for seal ring                       | Magic           | Ready  | TCL script             | ?               | Cadence ?         | In Progress  | Cadence SKILL script    | Hand written                              |
++------------------------------+-------------------------------------------+-----------------+--------+------------------------+-----------------+-------------------+--------------+-------------------------+-------------------------------------------+
+|                              | Fill structure rules                      | Magic           | None   | Magic techfile         | ?               | Cadence ?         | In Progress  | Cadence SKILL script    | Hand written                              |
++------------------------------+-------------------------------------------+-----------------+--------+------------------------+-----------------+-------------------+--------------+-------------------------+-------------------------------------------+
diff --git a/docs/contents/libraries.rst b/docs/contents/libraries.rst
new file mode 100644
index 0000000..595a606
--- /dev/null
+++ b/docs/contents/libraries.rst
@@ -0,0 +1,148 @@
+Libraries
+=========
+
+Library Naming
+--------------
+
+Libraries in the SKY130 PDK are named using the following scheme;
+
+  :lib_process:`<Process name>` _ :lib_src:`<Library Source Abbreviation>` _ :lib_type:`<Library Type Abbreviation>` [_ :lib_name:`<Library Name>`]
+
+All sections are **lower case** and separated by an **underscore**. The sections are;
+
+
+- The :lib_process:`Process name` in is the name of the process technology, for this PDK it is always :lib_process:`sky130`.
+
+- The :lib_src:`Library Source Abbreviations` is a short abbreviation for who created and is responsible for the library. The table below shows the current list of :lib_src:`Library Source Abbreviations`;
+
+  +----------------------------+----------------------------------------+
+  | Library Source             | :lib_src:`Library Source Abbreviation` |
+  +============================+========================================+
+  | The SkyWater Foundry       | :lib_src:`fd`                          |
+  +----------------------------+----------------------------------------+
+  | Efabless                   | :lib_src:`ef`                          |
+  +----------------------------+----------------------------------------+
+  | Oklahoma State University  | :lib_src:`osu`                         |
+  +----------------------------+----------------------------------------+
+
+- The :lib_type:`Library Type Abbreviation` is a short two letter abbreviation for the type of content found in the library. The table below shows the current list of :lib_type:`Library Type Abbreviations`;
+
+  +--------------------------------+---------------------------------------+
+  | Library Type                   | :lib_type:`Library Type Abbreviation` |
+  +================================+=======================================+
+  | Primitive Cells                | :lib_type:`pr`                        |
+  +--------------------------------+---------------------------------------+
+  | Digital Standard Cells         | :lib_type:`sc`                        |
+  +--------------------------------+---------------------------------------+
+  | Build Space (Flash, SRAM, etc) | :lib_type:`sp`                        |
+  +--------------------------------+---------------------------------------+
+  | IO and Periphery               | :lib_type:`io`                        |
+  +--------------------------------+---------------------------------------+
+  | Miscellaneous                  | :lib_type:`xx`                        |
+  +--------------------------------+---------------------------------------+
+
+- The :lib_name:`Library Name` is an optional short abbreviated name used when there are multiple libraries of a given type released from a single :lib_src:`library source`. If only one library of a given type is going to ever be released, this can be left out.
+
+Creating New Libraries
+----------------------
+
+Third party developers are encourage to create new and interesting libraries for usage with the SKY130 process technology. These libraries can even be included in the SKY130 PDK if it meets the following criteria;
+
+ - It is released under an OSI approved license.
+ - TODO: Finish the criteria.
+
+
+.. _sky130-lib-primitives:
+
+:lib_type:`Primitive` Libraries
+-------------------------------
+
+.. _sky130-lib-primitives-foundry:
+
+:lib_src:`Foundry` provided
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. toctree::
+    :glob:
+    :maxdepth: 1
+    :caption: Foundry provided Primitives
+    :name: sky130-lib-foundry-primitives
+
+    libraries/sky130_fd_pr_*/README
+
+
+.. _sky130-lib-standardcells:
+
+:lib_type:`Digital Standard Cell` Libraries
+-------------------------------------------
+
+.. _sky130-lib-standardcells-foundry:
+
+:lib_src:`Foundry` provided :lib_type:`Digital Standard Cell` Libraries
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. toctree::
+    :glob:
+    :maxdepth: 1
+    :name: sky130-lib-foundry-sc
+
+    libraries/sky130_fd_sc_*/README
+
+.. _sky130-lib-standardcells-thirdparty:
+
+:lib_src:`Third party` provided :lib_type:`Digital Standard Cell` Libraries
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. toctree::
+    :maxdepth: 1
+    :name: sky130-lib-thirdparty-sc
+
+    libraries/sky130_osu_sc/README
+
+.. _sky130-lib-buildspace:
+
+:lib_type:`Build Space` Libraries
+---------------------------------
+
+The SKY130 currently offers two :lib_type:`build space` libraries. Build space libraries are designed to be used with technologies like memory compilers and built into larger macros. The provided libraries have specially crafted design rules to enable higher density compared to other libraries.
+
+.. _sky130-lib-buildspace-foundry:
+
+:lib_src:`Foundry` provided :lib_type:`Build Space` Libraries
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. toctree::
+    :glob:
+    :maxdepth: 1
+    :caption: Foundry provided Build Spaces
+    :name: sky130-lib-foundry-sp
+
+    libraries/sky130_fd_sp_*/README
+
+.. _sky130-lib-io:
+
+:lib_type:`IO and Periphery` Libraries
+--------------------------------------
+
+.. _sky130-lib-io-foundry:
+
+:lib_src:`Foundry` provided :lib_type:`IO and Periphery` Libraries
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. toctree::
+    :maxdepth: 1
+    :name: sky130-lib-foundry-io
+
+    libraries/sky130_fd_io/README
+
+.. _sky130-lib-io-thirdparty:
+
+:lib_src:`Third party` provided :lib_type:`IO and Periphery` Libraries
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. toctree::
+    :maxdepth: 1
+    :name: sky130-lib-thirdparty-io
+
+    libraries/sky130_ef_io/README
+
diff --git a/docs/contents/libraries/Makefile b/docs/contents/libraries/Makefile
new file mode 100644
index 0000000..42c8388
--- /dev/null
+++ b/docs/contents/libraries/Makefile
@@ -0,0 +1,6 @@
+update:
+	for i in ../../../libraries/*; do \
+		if [ ! -d $$i ]; then continue; fi; \
+		ln -sf -T $$i/latest $$(basename $$i); \
+	done
+	git add *
diff --git a/docs/contents/libraries/sky130_fd_sc_ms b/docs/contents/libraries/sky130_fd_sc_ms
new file mode 120000
index 0000000..d754348
--- /dev/null
+++ b/docs/contents/libraries/sky130_fd_sc_ms
@@ -0,0 +1 @@
+../../../libraries/sky130_fd_sc_ms/latest
\ No newline at end of file
diff --git a/docs/index.rst b/docs/index.rst
index 0013a95..7e4cc70 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -3,6 +3,10 @@
 .. toctree::
     :hidden:
 
+    Design Rules <rules>
+
+    contents
+
     versioning
     Current Status <status>
     known_issues
diff --git a/docs/known_issues.rst b/docs/known_issues.rst
index 4c8292a..d6af494 100644
--- a/docs/known_issues.rst
+++ b/docs/known_issues.rst
@@ -19,8 +19,8 @@
 
 The current cell datasheets only include basic information about the cell. These datasheets will be continuously updated with new information as the generator is improved.
 
-PDK Contents
-------------
+PDK Contents Issues
+-------------------
 
 Tooling Compatibility
 ~~~~~~~~~~~~~~~~~~~~~
@@ -85,7 +85,7 @@
 The SKY130 Oklahoma State University provided standard cells library will be integrated at a future date (see `Issue #10 <https://github.com/google/skywater-pdk/issues/10>`_).
 
 :lib:`sky130_fd_sp_flash` - SKY130 Flash Build Space
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 The flash build space is currently empty, only a placeholder is currently provided.
 
diff --git a/docs/rules.rst b/docs/rules.rst
new file mode 100644
index 0000000..bd1d5bd
--- /dev/null
+++ b/docs/rules.rst
@@ -0,0 +1,12 @@
+SkyWater SKY130 Process Design Rules
+====================================
+
+.. toctree::
+    :caption: Process Design Rules
+    :name: rules
+    :maxdepth: 2
+
+    rules/background
+    rules/assumptions
+    rules/periphery
+    rules/errors
diff --git a/docs/rules/assumptions.rst b/docs/rules/assumptions.rst
new file mode 100644
index 0000000..93ac6be
--- /dev/null
+++ b/docs/rules/assumptions.rst
@@ -0,0 +1,167 @@
+Criteria & Assumptions
+======================
+
+Process Stack Diagram
+---------------------
+
+.. image:: ../_static/metal_stack.svg
+   :width: 100%
+   :alt: SkyWater SKY130 Process Stack
+
+General
+-------
+
+.. csv-table:: Table 1 - General
+   :file: assumptions/01-general.csv
+   :header-rows: 1
+   :stub-columns: 1
+
+Minimum Critical Dimensions
+---------------------------
+
+.. csv-table:: Table 2 - Minimum CDs in Design or on Wafer, required by Technology (Core or Periphery)
+   :file: assumptions/02-mins.csv
+   :header-rows: 1
+   :widths: 20, 20, 10, 10, 10, 10
+
+Semiconductor Criteria
+----------------------
+
+Basic Parameters
+~~~~~~~~~~~~~~~~
+
+.. csv-table:: Table 3a - Semiconductor Criteria - Basic Parameters
+   :header-rows: 1
+   :width: 100%
+   :widths: 30, 10, 20, 10
+
+    ,Units,Value,Variable name
+    n-well peak concentration,cm-3,6.00E+017,NWPCONC
+    background concentration,cm-3,8.00E+14,NWBCONC
+    y.char,um,0.43,NWYCHAR
+    desired Nmin/Ns ratio,,0.9,NMINNSRATIO
+    min n-well width to guarantee 90 % peak concentr.,um,0.55,MINNWWID
+    p-well peak concentration,cm-3,4E+017,PWPCONC
+    p-well peak coordinate,um,0.42,PWPCOORD
+    y.char,um,0.13,PWYCHAR
+    min. p-well width to guarantee 90 % peak concentr.,um,0.33,MINPWWID
+
+Junction Depths
+~~~~~~~~~~~~~~~
+
+.. csv-table:: Table 3b - Semiconductor Criteria - Junction Depths
+   :header-rows: 1
+   :width: 100%
+   :widths: 30, 10, 10, 10, 10
+
+    ,Units,Vertical Feature,Vertical Space,Variable name
+    Baseline: N-Well,um,1.1, ,NWVDIM
+    P-Well,um,0.75,,PWVDIM
+    N-w/P-w junction (from drawn edge),um,*,0.034,WELLJCT
+    N+ or P+ S/D (XJ),um,0.1,0.06,JCTD / LD
+    Max (N+ or P+ S/D outdiff.) next to isol. edge,um,,0.007,LDST
+    Max (N+ or P+ S/D outdiff.) next to isol. edge for 6 V reg. devices,,,0.05,LDST5
+    N Tip (As),um, ,0.01,LDNTIP
+
+Other Width Criteria
+~~~~~~~~~~~~~~~~~~~~
+
+.. csv-table:: Table 3c - Semiconductor Criteria - Other Width Criteria
+   :header-rows: 1
+   :width: 100%
+   :widths: 30, 10, 20, 10
+
+    ,Units,Value,Variable name
+    Min. diff/tap width for reproducible resistivity,um,0.12,MINFWR
+    Min. width to open a strip of tap between two diffs,um,0.34,SDM3
+    "Max s/d diff width without contact, consistent w/Ram4,5,6",um,5.7,XMAXCON
+
+Punchthrough Criteria
+~~~~~~~~~~~~~~~~~~~~~
+
+.. csv-table:: Table 3d - Semiconductor Criteria - Minimum Spacing for 3.3V Punchthrough (1.8V devices)
+   :header-rows: 1
+   :width: 100%
+   :widths: 30, 10, 20, 10
+
+    ,Units,Value,Variable name
+    n-well - n-well ,um,0.835,NWPTS
+    n+ - n+ or p+-p+,um,0.23,DPTS
+    p+ in nwell to pwell,um,0.05,PPTS
+    n+ in pwell to nwell,um,0.15,PNPTS
+
+Latch-up/ESD Criteria
+~~~~~~~~~~~~~~~~~~~~~
+
+.. csv-table:: Table 3e - Semiconductor Criteria - Latch-up/ESD Criteria
+   :header-rows: 1
+   :width: 100%
+   :widths: 30, 10, 20, 10
+
+    Minimum n+ or p+ - nwell spacing to prevent latch-up,um,0.23,NPNWLU
+    Min n-well enclos. of tap to ensure bkdwn N-w/P-w before N+/P-w (ESD),um,0.04,XNWESD
+    Max. overlap of n-well by p+ tap,um,0.06,XNWPTS
+
+Implant angles
+~~~~~~~~~~~~~~
+
+.. csv-table:: Table 3f - Semiconductor Criteria - Implant angles
+   :header-rows: 1
+   :width: 100%
+   :widths: 30, 10, 10, 10, 10
+
+    ,Units,Angle,,Variable name
+    High current,deg,0,0,HCIMPA
+    Angle for tip implant ,deg,7,,TipAng
+    Angle for HV tip implant ,deg,40,,HvTipAngle
+    Twist angle for HV Tip ,deg,23,,HvTipTwist
+
+Physical Criteria
+-----------------
+
+.. csv-table:: Table 4 - Physical Criteria
+   :file: assumptions/04-physical.csv
+   :header-rows: 1
+   :widths: 60, 10, 1, 10, 10, 10
+
+Laser Fuse Criteria
+-------------------
+
+.. csv-table:: Table 5 - Laser Fuse Criteria
+   :file: assumptions/05-laser-fuse.csv
+   :header-rows: 1
+   :widths: 60, 10, 1, 10, 10, 10
+
+.. What happened to 6!?
+
+Other criteria and parameters
+-----------------------------
+
+.. csv-table:: Table 7 - Other criteria and parameters
+   :file: assumptions/07-other.csv
+   :header-rows: 1
+   :widths: 60, 10, 1, 10, 10, 10
+
+Criteria for High Voltage FET
+-----------------------------
+
+.. csv-table:: Table 8 - Criteria for High Voltage FET
+   :file: assumptions/08-hv.csv
+   :header-rows: 1
+   :widths: 60, 10, 1, 10, 10, 10
+
+Criteria for polyimide manufacturability
+----------------------------------------
+
+.. csv-table:: Table 9 - Criteria for polyimide manufacturability
+   :file: assumptions/09-polyimide.csv
+   :header-rows: 1
+   :widths: 60, 10, 1, 10, 10, 10
+
+Criteria for VPP capacitor
+--------------------------
+
+.. csv-table:: Table 10 - Criteria for VPP capacitor
+   :file: assumptions/10-vpp-capacitor.csv
+   :header-rows: 1
+   :widths: 60, 10, 1, 10, 10, 10
diff --git a/docs/rules/assumptions/01-general.csv b/docs/rules/assumptions/01-general.csv
new file mode 100644
index 0000000..b217fdd
--- /dev/null
+++ b/docs/rules/assumptions/01-general.csv
@@ -0,0 +1,4 @@
+Parameter,,Units,Value,,Variable name
+Space to Draw,, ,S8,, 
+Grid Size - Drawn,,um,0.005,,GSF
+Approximate Scale Factor for R32 data,,,0.3,,sfr32
diff --git a/docs/rules/assumptions/02-mins.csv b/docs/rules/assumptions/02-mins.csv
new file mode 100644
index 0000000..c2fd3ac
--- /dev/null
+++ b/docs/rules/assumptions/02-mins.csv
@@ -0,0 +1,59 @@
+Layer Name,,Feature Size,Space Size,Feature Name,Space Name
+Field Oxide,,0.14,0.27,FOMCD,FOMCDSP
+Deep N-Well,,3,6.3,DNMCD,DNMCDSP
+P-Well Block Mask,,0.84,1.27,PWBMCD,PWBMCDSP
+P-Well Drain Extended ,,0.84,1.27,PWDEMCD,PWDEMCDSP
+N-Well,,0.84,1.27,NWMCD,NWMCDSP
+High Vt PCh,,0.38,0.38,HVTPMCD,HVTPMCDSP
+Low Vt Nch,,0.38,0.38,LVTNMCD,LVTNMCDSP
+HLow VT PCh Radio,,0.38,0.38,HVTRMCD,HVTRMCDSP
+N-Core Implant,,0.38,0.38,NCMCD,NCMCDSP
+Tunnel Mask,,0.41,0.5,TUNMCD,TUNMCDSP
+ONO Mask,,0.41,0.5,ONOMCD,ONOMCDSP
+Low Voltage Oxide,,0.6,0.7,LVOMCD,LVOMCDSPCSMC
+Resistor Protect,,1.27,0.84,RPMCD,RPMCDSP
+Poly 1,Endcap/Gap,0.15,0.21,P1G,
+Poly 1,,N/A,0.14,P1MCD,P1MCDSP
+N-tip Implant,,0.84,0.7,NTMCD,NTMCDSP
+High Volt. N-tip,,0.7,0.7,HVNTMCD,HVNTMCDSP
+Lightly Doped N-tip,,0.7,0.7,LDNTMCD,LDNTMCDSP
+Nitride Poly Cut,,0.27,0.27,NPCMCD,NPCMCDSP
+P+ Implant,,0.38,0.38,PSDMCD,PSDMCDSP
+N+ Implant,,0.38,0.38,NSDMCD,NSDMCDSP
+Local Intr Cont.1,Slotted,0.17,0.17,LICM1SLCD,LICM1SLCDSP
+Local Intr Cont.1,Core,0.19,0.35,LICM1CD,LICM1CDSP
+Local Intrcnct 1,Core,0.14,0.14,LI1MCD,LI1MCDSP
+Local Intrcnct 1,,0.17,0.17,LI1MCD,LI1MCDSP
+Contact,,0.17,0.19,CTM1CD,CTM1CDSP
+Open Frame Mask,,N/A,N/A,OFMCD,OFMCDSP
+Metal 1,,0.14,0.14,MM1CD,MM1CDSP
+Metal 1 - Cu,,0.14,0.14,MM1_CuCD,MM1_CuCDSP
+Via,,0.15,0.17,VIMCD,VIMCDSP
+Via - Cu,,0.18,0.13,VIM_CuCD,VIM_CuCDSP
+Capacitor MiM,,2,0.84,CAPMCD,CAPMCDSP
+Metal 2,,0.14,0.14,MM2CD,MM2CDSP
+Metal 2 - Cu,,0.14,0.14,MM2_CuCD,MM2_CuCDSP
+Via 2-TNV,,0.28,0.28,VIM2CD,VIM2CDSP
+Via 2-S8TM,,0.8,0.8,VIM2CD,VIM2CDSP
+Via 2-PLM, ,0.2,0.2,VIM2CD,VIM2CDSP
+Via 2-Cu, ,0.21,0.18,VIM2_CuCD,VIM2_CuCDSP
+Metal 3-TLM,,0.36,0.36,MM3CD,MM3CDSP
+Metal 3-S8TM,,0.8,0.8,MM3CD,MM3CDSP
+Metal 3-PLM,,0.3,0.3,MM3CD,MM3CDSP
+Metal 3-Cu, ,0.3,0.3,MM3_CuCD,MM3_CuCDSP
+Pad Via,,1.2,1.27,VIPDMCD,VIPDMCDSP
+Via3-PLM,,0.2,0.2,VIM3CD,VIM3CDSP
+Via3-Cu, ,0.21,0.18,VIM3_CuCD,VIM3_CuCDSP
+Inductor-TLM,,2.5,2.5,INDMCD,INDMCDSP
+Metal 4,,0.3,0.3,MM4CD,MM4CDSP
+Metal 4-Cu, ,0.3,0.3,MM4_CuCD,MM4_CuCDSP
+Via4,,0.8,0.8,VIM4CD,VIM4CDSP
+Metal 5,All flows except S8PF*/S8PIR*,0.8,0.8,MM5CD,MM5CDSP
+Metal 5,S8PF*/S8PIR*,1.6,1.6,MM5CD,MM5CDSP
+Nitride Seal Mask,,3,4,NSMCD,NSMCDSP
+Pad (scribe protect),,2,1.27,PDMCD,PDMCDSP
+Polyimide,,5,15,PMMCD,PMMCDSP
+Polyimide_ExtFab,,5,15,PMM[E]CD,PMM[E]CDSP
+DECA PBO, ,10,10,PBOCD,PBOCDSP
+Cu Inductor/Redist.,,20,20,CU1MCD,CU1MCDSP
+Serifs,,0.1,0.1,SERCD,SERCDSP
diff --git a/docs/rules/assumptions/04-physical.csv b/docs/rules/assumptions/04-physical.csv
new file mode 100644
index 0000000..009fdb1
--- /dev/null
+++ b/docs/rules/assumptions/04-physical.csv
@@ -0,0 +1,73 @@
+Material Thicknesses,,,Value (um),,Variable name
+field oxide (above silicon surface) ... underneath poly,,,0.07,,FOXSTEP
+"min. etch and fill capability for isolation, licon, and met1",,,0.15,,DEFC
+min. etch and fill capability for mcon,,,0.14,,CEFC
+min. etch and fill capability for via,,,0.18,,VEFC
+poly cap after SPE,,,0.2,,OVGTTH
+poly thickness,,,0.18,,POLYTH
+oxide spacer ,,,0.05,,SpThickn
+Pre-LI ILD thickness,,,0.5,,ILDTHICKN
+Licon1 etch angle (deg),,,10,,LICETANG
+Standard Licon bottom CD,,,0.08,,LBCD
+Mcon enclosure by Li,,,0,,mconLiEnclosure
+Via1 slope,,,0.02,,Via1Slope
+Oxide Bias for MM1,,,0.6,,BiasMM1
+Oxide Bias for MM2,,,0.6,,BiasMM2
+Oxide Bias for MM3,,,1.15,,BiasMM3
+Oxide Bias for MM4,,,1.15,,BiasMM4
+LI1 thickness for antenna ratio calculations,,,0.1,,LiThick
+Metal 1 thickness for antenna ratio calculations (S8D*),,,0.35,,Met1Thick
+Metal 2 thickness for antenna ratio calculations (S8D*),,,0.35,,Met2Thick
+Inductor thickness for antenna ratio calculation (S8D*),,,4,,IndmThick
+Metal 3 thickness for antenna ratio calculation  (S8Q/SP8Q),,,0.8,,Met3thick_q
+Metal4 thickness for antenna ratio calculation (S8Q*/SP8Q),,,2,,Met4Thick_q
+Metal 3 thickness for antenna ratio calculation  (S8P*/SP8P*),,,0.8,,Met3thick_p
+Metal4 thickness for antenna ratio calculation (S8P*/SP8P*),,,0.8,,Met4Thick_p
+Metal5 thickness for antenna ratio calculation (S8P*/SP8P* with 2um thick metal),,,2,,Met5Thick_p
+Metal5 thickness for antenna ratio calculation (S8P*/SP8P* with 1.2um thick metal),,,1.2,,Met5Thickp_12
+Metal 2 thickness for antenna ratio calculations (SP8T/S8T*),,,0.35,,Met2_Qthick
+Metal 3 thickness for antenna ratio calculations (S8T* other than S8TM*),,,0.85,,Met3_Qthick
+Metal 3 thickness for antenna ratio calculations (S8TM* flow),,,2,,Met3_TMthick
+Metal 3 thickness for antenna ratio calculations (SP8T flow),,,0.8,,Met3_SP8Tthick
+Photoresist thickness,,,1.14,,PRTHICKN
+Photoresist thickness for HV Tip Implants,,,0.3,,PrThickImplant
+Min width of tip implant opening,,,0.1,,minTip_impW
+NTM shadowing,,,0.16,,ntmShadowing
+HVNTM shadowing,,,0.232,,hvntmShadowing
+HVPTM shadowing,,,0.089,,hvptmShadowing
+pseudo-shadowing,,,0.045,,pseudoShadowing
+Channel length for low Vt PMOS,,,0.35,,lvtpmos_poly
+Width of the Low Leakage gate on each side of LowVt Pmos connected to power rails (requirement based on exp data),,,0.28,,LvtEnc_forPowerRail
+CD tolerance for PDM (3s),,,1,,PdmCD_tol
+Min process bias 3s tolerance,,,0.032,,PHTOL
+Min process bias 3s tolerance for poly,,,0.02,,PHP1TOL
+Minimum Space and Overlap,,,Value (um),,Variable name
+Minimum mcon overlap onto LI for reproducible contact resistance,,,0.12,,TCONOVLP 
+Dogbone PR decay length (SRS 8/4/99),,,0.2,,DBPRDEC
+Bowing of rectangular contact (per edge) -- seal ring sizing,,,0.015,,TBOWINGSEAL
+Waffling / Pattern Density,,,Value,,Variable name
+S8 average FOM PD (extractions from logic device),,,0.45,,FOMPDAVG
+Size of small PD extraction box for rough tolerance (um),,,700,,SMALLPDBOX
+Size of large PD extraction box for rough tolerance (um),,,2000,,LARGEPDBOX
+Min pattern density for oxide,,,0.75,,OxideMinPD
+Min MM* PD range,,,0.3,,MMPDrange
+FOM 700um box PD tolerance for CMP (SOI8 PCR2) for all technologies,,,0.15,,FOM700TOL
+Stepping box shift as a percent of box size,,,0.5,,BOXSHIFT
+Maximum metal waffle drop pattern density in the frame,,,0.55,,PD_FrameWP
+Window size for frame waffle drop PD check,,,100,,WP_PDWINDOW
+Step size for frame waffle drop PD check,,,10,,WP_PDSTEP
+Other,,,Value,,Variable name
+Poly resistor width and spacing to reduce CD variation (um),,,0.33,,POLYRCD
+Poly resistor width and spacing to reduce CD variation (um),,,0.48,,POLYRSPC
+Spacing between slotted_licons (Not applicable when the two edges L= 0.19um),,,0.51,,LICM1SLSP1
+Precision resistor width to accommodate 6 contacts across,,,2.03,,PRECRESW
+Li resistor width (to drop one Licon w/o dogbones),,,0.29,,LIRESCD
+Correction factor for spacing to a wide metal line,,,2,,BIGMF
+Min spacing for created dnwell to pnp.dg (more restrictive than dnwell.4 rule),,,5,,cdnwPnpSpc
+"Min spacing between nwell and deep nwell on separate nets (Taken from dnwell.3 from S4* TDR *N plus rounded up, IGK request.)",,,6,,nwellDnwellSpc
+Min space between deep nwells used as photo diode (um),,,5,,PDDnwSpc
+Min space between dnwell (used for photo diode and other deep nwell (um),,,5.3,,PDDnwSpc1
+Min/Max width of nwell inside deep nwell (for photo diodes),,,0.84,,PDNwmCD
+Min/Max enclosure of nwell by deep nwell (for photo diode),,,1.08,,PDNwmDnwEnc
+Min/Max width of tap inside deep nwell (for photo diode),,,0.41,,PDTapCD
+Min/Max enclosure of tap by nwell inside deep nwell (for photo diode),,,0.215,,PDTapNwmEnc
diff --git a/docs/rules/assumptions/05-laser-fuse.csv b/docs/rules/assumptions/05-laser-fuse.csv
new file mode 100644
index 0000000..09dbd1a
--- /dev/null
+++ b/docs/rules/assumptions/05-laser-fuse.csv
@@ -0,0 +1,15 @@
+,,,Value (um),,Variable name
+Min. spac. of laser spot to diffused junction to ensure jct integrity,,,0.6,,XLASJUN
+Max. width of a metal fuse line that can be removed reliably,,,0.8,,FSW
+Min. L of met. fuse at which damage doesn't extend beyond ends,,,6.605,,FSLE
+Max. extension of met2 beyond fuse boundary,,,0.005,,FEXT
+Min. distance between laser spot and active junction,,,0.545,,LASJCT
+Standard contact bottom CD,,,0.09,,
+Positioning tolerance of laser spot (3 s),,,0.3,,LASMA
+Nominal effective laser spot diameter,,,3.5,,LASSPT
+Max. increase in spot diameter at max. distance from focus (3 s),,,0.9,,LASCDTOL
+Fuse melting radius,,,3.6,,MELTRAD
+Melting related crack size in ILD,,,0.36,,FUSECRACK
+Min space between fuse and any feature not connected to it,,,0.2,,MinFuseSpace
+Space between fuse and any unrelated layer,,,0.5,,SP_fuse_to_unrelated
+DC offset in some fuse rules,,,0.87,,LASDC1
diff --git a/docs/rules/assumptions/07-other.csv b/docs/rules/assumptions/07-other.csv
new file mode 100644
index 0000000..2a4cfc6
--- /dev/null
+++ b/docs/rules/assumptions/07-other.csv
@@ -0,0 +1,42 @@
+Layer / Design rule,CD,,space,,Comment
+MOSFET width,0.135,,,,FOMSE
+MOSFET width in standard cells,0.075,,,,FOMSESC
+Spacing of poly on field to diff,,,0.065,,PFDSE
+Spacing of poly on field to tap,,,0.005,,PFTSE
+Enclosure of tap by nwell for pwell res,,,0.22,,PTAP_NWL_SP
+Grid conversion rounding factor,,,0.005,,GRCF
+Licon enclosure rounding,,,0.02,,LICENCLR
+LI1CD add/drop,0.01,,0.04,,
+Huge metal X min. W and L,3,,,,HugeM
+Min Nsdm area ,0.265,,,,MinNsdmArea
+Min Psdm area,0.255,,,,MinPsdmArea
+Min N/Psdm hole area ,0.265,,,,MinNPsdmHole
+Large waffle size must be divisible by 4,7.2,,,,waffle_large
+P1M additional CD control,0.011,,,,P1MCDcontrol
+Li1 proximity correction,,,0.25,,LI1PROXSpace
+"Serif added to nwell convex corner (SXX-572, 573)",0.22,,,,NwellCvxSerif
+"Serif added to nwell concave corner (SXX-572, 573)",0.12,,,,NwellCveSerif
+NWM extension beyond nwell edge straddling de_nFet_source (for GSMC; QZM-133),0.075,,,,NvhvNwellExt
+Min enclosure of pad by pmm for Cu inductor (JNET-80) ,0,,,,padPMMEncInd
+Min enclosure of pmm by cu1m for Cu inductor (JNET-80) ,10.75,,,,pmmCu1mEncInd
+Min enclosure of pbo by cu1m per DECA 000348 Rev S,10,,,,pboCu1mEnc
+Min enclosure of pmm by pmm2 for radio flow in the die (JNET-80) ,13,,,,pmmPmm2EncInd
+Min enclosure of pmm by pmm2 inside frame,7.5,,,,pmmPmm2EncIndFrame
+Min space between pmm2 and Inductor.dg ,,,7.5,,pmm2IndSpc
+Min cu1m PD across full chip,0.35,,,,MinCU1Mpd
+Max cu1m PD across full chip,0.45,,,,MaxCU1Mpd
+Spacing between RDL and outer edge of seal ring,15,,,,RdlSealSpc
+Spacing between RDL and pmm2,6.16,,,,RdlPmm2Spc
+Enclosure of etest module in die by cpmm2,0,,,,EtestCpmm2Enc
+"Keepout of active, poly, li and metal to NSM (TCS-2253)",,,1,,NSMKeepout
+"3 um keepout of active, poly, li and metal to areaid.dt/areaid.ft (TCS-2253)",,,3,,NSMKeepout_3um
+pnp_emitter sizing (S8P GSMC flow),,,0.05,,PnpEmitterSzGSMC
+pnp_emitter sizing (other flows),,,0.03,,PnpEmitterSz
+MiM Capacitor aspect ration,20,,,,MiM_AR
+Min NCM space to be used to preserve NCM CL algorithm (avoid LVL error),,,1.27,,NCM_0LVL
+Min space of NCM between core and periphery due to existing layout restriction,,,0.96,,NcmCorePeriSP
+Multiplication factor,,,0.01,,S8LVconv
+Minimum scribe width,50,,,,scribew
+spacing of p-well  outside deep n-well to deep n-well mask edge,,,0.12,,NWDNWENCL
+p-well in deep n-well to p-sub,,,1.2,,NWDNWOL
+Field oxide etchback after P1ME before implants,,,0.04,,WFDEL
diff --git a/docs/rules/assumptions/08-hv.csv b/docs/rules/assumptions/08-hv.csv
new file mode 100644
index 0000000..9e1d3b5
--- /dev/null
+++ b/docs/rules/assumptions/08-hv.csv
@@ -0,0 +1,18 @@
+Layer / Design rule,CD,,space,,Comment
+Min HVNwell to any nwell space,,,2,,HVNwell_Nwell_SP
+Min HVDiff width,0.29,,,,HVDiff_CD
+Min HVDiff space,,,0.3,,HVDiff_SP
+Min HV Pmos gate width,0.5,,,,HVP_gate_CD
+Min space between HV poly,,,0.28,,HVPoly_SP
+Min HV Nmos gate width,0.37,,,,HVPoly_CD
+HV P+ Diff enclosure by Nwell,0.33,,,,HVPdiff_nwell_enc
+HV N+ diff space to Nwell,,,0.43,,HVNdiff_nwell_SP
+HV N+ tap enclosure by Nwell,0.33,,,,HVNtap_nwell_enc
+HV P+tap space to Nwell,,,0.43,,HVPtap_nwell_SP
+Photoresist tilted implant penetration,0.02,,,,HVPrPenetration
+Photoresist tilted implant blocking distance,0.013,,,,HVPrBlocking
+Min size of HVTip,0.1,,,,HVTipMinSize
+Extra CD tol for HVNTM to match Ram7 process,0.015,,,,HVNTMExtraCdTol
+Min HVDiff resistor width,0.29,,,,HVDiff_Res_CD
+High voltage n+-n+ or p+-p+,,,0.3,,HVDPTS15
+HV MOSFET channel length,0.5,,,,HVPCD
diff --git a/docs/rules/assumptions/09-polyimide.csv b/docs/rules/assumptions/09-polyimide.csv
new file mode 100644
index 0000000..4f03a9a
--- /dev/null
+++ b/docs/rules/assumptions/09-polyimide.csv
@@ -0,0 +1,13 @@
+Layer / Design rule,CD,,space,,Comment
+Enclosure of fuses by polyimide,12,,,,PimFuseEnc
+Enclosure of bondpad by polyimide (YUY-165),0.5,,,,PimPadEnc
+"Enclosure of pad:dg by PBO inside inductor capture pad, with DECA online monitoring",4.5,,,,PBOPadEnc
+Enclosure of pad:dg by PBO per standard DECA rules,7.5,,,,PBOPadEncDECA
+DECA PBO drawn-to-final process bias per side,0.5,,,,PBOProcBiasPerSide
+Polyimide CD tolerance,1,,,,PimCD_tol
+Min Pim width over pad openings,87,,,,PimOverPad_CD
+Polyimide slope (001-87400),,5.3,,,I_polyimide_slope
+Enclosure of polyimide by polymer tolerance,,7.7,,,Po_po_tol
+Min/Max enclosure of pad.dg inside M5RDL by pmm,0,,,,pmmM5RDLpadEnc
+Min spacing of pmm to (rdl NOT (pad.dg sized by 0.5)),,,19.16,,pmmRDLspc
+Enclosure of laser targets in the die by polyimide,30,,,,PimLaserEnc
diff --git a/docs/rules/assumptions/10-vpp-capacitor.csv b/docs/rules/assumptions/10-vpp-capacitor.csv
new file mode 100644
index 0000000..f29fddc
--- /dev/null
+++ b/docs/rules/assumptions/10-vpp-capacitor.csv
@@ -0,0 +1,7 @@
+Layer / Design rule,CD,,space,,Comment
+Min width of capacitor:dg,4.38,,,,VppWidth
+Max width of unit capacitor:dg,8.58,,,,VppMaxWidth
+Min spacing between two capacitor:dg ,1.5,,,,VppSpc
+Min spacing of capacitor:dg to li1 or met1 or met2 or nwell,1.5,,,,VppOtherSPc
+Min enclosure of capacitor by nwell,1.5,,,,VppNwmEnc
+Min spacing of pmm to (rdl NOT (pad.dg sized by 0.5)),,,19.16,,pmmRDLspc
diff --git a/docs/rules/background.rst b/docs/rules/background.rst
new file mode 100644
index 0000000..8485cc2
--- /dev/null
+++ b/docs/rules/background.rst
@@ -0,0 +1,15 @@
+Background
+==========
+
+SKY130 is a mature 180nm-130nm hybrid technology developed by Cypress Semiconductor that has been used for many production parts. SKY130 is now available as a foundry technology through SkyWater Technology Foundry.
+
+The technology is the 8th generation SONOS technology node (130nm).
+
+The technology stack consists of;
+
+- 5 levels of metal (`p` - penta)
+- Inductor or Inductor-Capable (`i`)
+- Poly resistor (`r`)
+- SONOS shrunken cell (`s`)
+- Supports 10V regulated supply (`10R`)
+
diff --git a/docs/rules/errors.csv b/docs/rules/errors.csv
new file mode 100644
index 0000000..18e2ae1
--- /dev/null
+++ b/docs/rules/errors.csv
@@ -0,0 +1,1557 @@
+ID,Name,Description
+r0,x.1b,off 0.005 grid nwell vertex
+r1,x.1b,off 0.005 grid diff vertex
+r2,x.1b,off 0.005 grid dnwell vertex
+r3,x.1b,off 0.005 grid tap vertex
+r4,x.1b,off 0.005 grid lvtn vertex
+r5,x.1b,off 0.005 grid hvtp vertex
+r6,x.1b,off 0.005 grid hvi vertex
+r7,x.1b,off 0.005 grid tunm vertex
+r8,x.1b,off 0.005 grid poly vertex
+r9,x.1b,off 0.005 grid npc vertex
+r10,x.1b,off 0.005 grid nsdm vertex
+r11,x.1b,off 0.005 grid psdm vertex
+r12,x.1b,off 0.005 grid licon1 vertex
+r13,x.1b,off 0.005 grid li1 vertex
+r14,x.1b,off 0.005 grid mcon vertex
+r15,x.1b,off 0.005 grid met1 vertex
+r16,x.1b,off 0.005 grid via vertex
+r17,x.1b,off 0.005 grid met2 vertex
+r18,x.1b,off 0.005 grid vhvi vertex
+r19,x.1b,off 0.005 grid via2 vertex
+r20,x.1b,off 0.005 grid met3 vertex
+r21,x.1b,off 0.005 grid via3 vertex
+r22,x.1b,off 0.005 grid met4 vertex
+r23,x.1b,off 0.005 grid via4 vertex
+r24,x.1b,off 0.005 grid met5 vertex
+r25,x.1b,off 0.005 grid nsm vertex
+r26,x.1b,off 0.005 grid pad vertex
+r27,x.1b,off 0.005 grid ldntm vertex
+r28,x.1b,off 0.005 grid hvntm vertex
+r29,x.1b,off 0.005 grid pnp vertex
+r30,x.1b,off 0.005 grid capacitor vertex
+r31,x.1b,off 0.005 grid ncm vertex
+r32,x.1b,off 0.005 grid inductor vertex
+r33,x.1b,off 0.005 grid rpm vertex
+r34,x.1b,off 0.005 grid hvtr vertex
+r35,x.1b,off 0.005 grid metop1 vertex
+r36,x.1b,off 0.005 grid metop2 vertex
+r37,x.1b,off 0.005 grid metop3 vertex
+r38,x.1b,off 0.005 grid metop4 vertex
+r39,x.1b,off 0.005 grid metop5 vertex
+r40,x.1b,off 0.005 grid metop6 vertex
+r41,x.1b,off 0.005 grid metop7 vertex
+r42,x.1b,off 0.005 grid metop8 vertex
+r43,x.1b,off 0.005 grid NTMdrop vertex
+r44,x.1b,off 0.005 grid LVTNMdrop vertex
+r45,x.1b,off 0.005 grid HVTPMdrop vertex
+r46,x.1b,off 0.005 grid LI1Mdrop vertex
+r47,x.1b,off 0.005 grid LICM1drop vertex
+r48,x.1b,off 0.005 grid PSDMdrop vertex
+r49,x.1b,off 0.005 grid NSDMdrop vertex
+r50,x.1b,off 0.005 grid FOMdrop vertex
+r51,x.1b,off 0.005 grid NTMadd vertex
+r52,x.1b,off 0.005 grid LVTNMadd vertex
+r53,x.1b,off 0.005 grid HVTPMadd vertex
+r54,x.1b,off 0.005 grid LI1Madd vertex
+r55,x.1b,off 0.005 grid LICM1add vertex
+r56,x.1b,off 0.005 grid PSDMadd vertex
+r57,x.1b,off 0.005 grid NSDMadd vertex
+r58,x.1b,off 0.005 grid FOMadd vertex
+r59,x.1b,off 0.005 grid PMM2mk vertex
+r60,x.1b,off 0.005 grid CU1Mmk vertex
+r61,x.1b,off 0.005 grid RPMmk vertex
+r62,x.1b,off 0.005 grid PBOmk vertex
+r63,x.1b,off 0.005 grid PDMmk vertex
+r64,x.1b,off 0.005 grid NSMmk vertex
+r65,x.1b,off 0.005 grid MM5mk vertex
+r66,x.1b,off 0.005 grid VIM4mk vertex
+r67,x.1b,off 0.005 grid MM4mk vertex
+r68,x.1b,off 0.005 grid VIM3mk vertex
+r69,x.1b,off 0.005 grid MM3mk vertex
+r70,x.1b,off 0.005 grid VIM2mk vertex
+r71,x.1b,off 0.005 grid CTM1mk vertex
+r72,x.1b,off 0.005 grid LI1Mmk vertex
+r73,x.1b,off 0.005 grid LICM1mk vertex
+r74,x.1b,off 0.005 grid PSDMmk vertex
+r75,x.1b,off 0.005 grid NSDMmk vertex
+r76,x.1b,off 0.005 grid LDNTMmk vertex
+r77,x.1b,off 0.005 grid NPCMmk vertex
+r78,x.1b,off 0.005 grid HVNTMmk vertex
+r79,x.1b,off 0.005 grid NTMmk vertex
+r80,x.1b,off 0.005 grid LVOMmk vertex
+r81,x.1b,off 0.005 grid ONOMmk vertex
+r82,x.1b,off 0.005 grid TUNMmk vertex
+r83,x.1b,off 0.005 grid HVTRMmk vertex
+r84,x.1b,off 0.005 grid HVTPMmk vertex
+r85,x.1b,off 0.005 grid LVTNMmk vertex
+r86,x.1b,off 0.005 grid NWMmk vertex
+r87,x.1b,off 0.005 grid DNMmk vertex
+r88,x.1b,off 0.005 grid FOMmk vertex
+r89,x.1b,off 0.005 grid cfom vertex
+r90,x.1b,off 0.005 grid clvtnm vertex
+r91,x.1b,off 0.005 grid chvtpm vertex
+r92,x.1b,off 0.005 grid conom vertex
+r93,x.1b,off 0.005 grid clvom vertex
+r94,x.1b,off 0.005 grid cntm vertex
+r95,x.1b,off 0.005 grid chvntm vertex
+r96,x.1b,off 0.005 grid cnpc vertex
+r97,x.1b,off 0.005 grid cnsdm vertex
+r98,x.1b,off 0.005 grid cpsdm vertex
+r99,x.1b,off 0.005 grid cli1m vertex
+r100,x.1b,off 0.005 grid cviam3 vertex
+r101,x.1b,off 0.005 grid cviam4 vertex
+r102,x.1a,off 0.001 grid P1Mmk vertex
+r103,x.1a,off 0.001 grid P1Madd vertex
+r104,x.1a,off 0.001 grid P1Mdrop vertex
+r105,x.1a,off 0.001 grid VIMmk vertex
+r106,x.1a,off 0.001 grid MM1mk vertex
+r107,x.1a,off 0.001 grid MM2mk vertex
+r108,x.1a,off 0.001 grid pmm vertex
+r109,x.1a,off 0.001 grid rdl vertex
+r110,x.1a,off 0.001 grid pmm2 vertex
+r111,x.1a,off 0.001 grid ubm vertex
+r112,x.1a,off 0.001 grid bump vertex
+r113,x.2,non-manhattan diffNOtSealUHVI edge
+r114,x.2,non-manhattan tapNotSealUHVI edge
+r115,x.2,non-manhattan poly_noESD_noAnch edge
+r116,x.2,non-manhattan li1Peri_noSEAL_noAnch edge
+r117,x.2,non-manhattan licon_nonSEAL edge
+r118,x.2,non-manhattan mcon_nonSEAL edge
+r119,x.2,non-manhattan via_nonSEAL edge
+r120,x.2,non-manhattan via2_nonSEAL edge
+r121,x.2,non-manhattan via3_nonSEAL edge
+r122,x.2,non-manhattan via4_nonSEAL edge
+r123,x.2a,difftap enclosed in areaid.analog must be rectangular
+r124,x.3a,non-octagonal nwell edge
+r125,x.3a,non-octagonal diff edge
+r126,x.3a,non-octagonal dnwell edge
+r127,x.3a,non-octagonal lvtn edge
+r128,x.3a,non-octagonal hvtp edge
+r129,x.3a,non-octagonal hvi edge
+r130,x.3a,non-octagonal tunm edge
+r131,x.3a,non-octagonal npc edge
+r132,x.3a,non-octagonal nsdm edge
+r133,x.3a,non-octagonal psdm edge
+r134,x.3a,non-octagonal met1 edge
+r135,x.3a,non-octagonal met2 edge
+r136,x.3a,non-octagonal vhvi edge
+r137,x.3a,non-octagonal met3 edge
+r138,x.3a,non-octagonal met4 edge
+r139,x.3a,non-octagonal met5 edge
+r140,x.3a,non-octagonal nsm edge
+r141,x.3a,non-octagonal pad edge
+r142,x.3a,non-octagonal ldntm edge
+r143,x.3a,non-octagonal hvntm edge
+r144,x.3a,non-octagonal pnp edge
+r145,x.3a,non-octagonal capacitor edge
+r146,x.3a,non-octagonal ncm edge
+r147,x.3a,non-octagonal inductor edge
+r148,x.3a,non-octagonal rpm edge
+r149,x.3a,non-octagonal hvtr edge
+r150,x.3a,non-octagonal metop1 edge
+r151,x.3a,non-octagonal metop2 edge
+r152,x.3a,non-octagonal metop3 edge
+r153,x.3a,non-octagonal metop4 edge
+r154,x.3a,non-octagonal metop5 edge
+r155,x.3a,non-octagonal metop6 edge
+r156,x.3a,non-octagonal metop7 edge
+r157,x.3a,non-octagonal metop8 edge
+r158,x.3a,non-octagonal NTMdrop edge
+r159,x.3a,non-octagonal LVTNMdrop edge
+r160,x.3a,non-octagonal HVTPMdrop edge
+r161,x.3a,non-octagonal LI1Mdrop edge
+r162,x.3a,non-octagonal LICM1drop edge
+r163,x.3a,non-octagonal PSDMdrop edge
+r164,x.3a,non-octagonal NSDMdrop edge
+r165,x.3a,non-octagonal P1Mdrop edge
+r166,x.3a,non-octagonal FOMdrop edge
+r167,x.3a,non-octagonal NTMadd edge
+r168,x.3a,non-octagonal LVTNMadd edge
+r169,x.3a,non-octagonal HVTPMadd edge
+r170,x.3a,non-octagonal LI1Madd edge
+r171,x.3a,non-octagonal LICM1add edge
+r172,x.3a,non-octagonal PSDMadd edge
+r173,x.3a,non-octagonal NSDMadd edge
+r174,x.3a,non-octagonal P1Madd edge
+r175,x.3a,non-octagonal FOMadd edge
+r176,x.3a,non-octagonal cfom edge
+r177,x.3a,non-octagonal clvtnm edge
+r178,x.3a,non-octagonal chvtpm edge
+r179,x.3a,non-octagonal conom edge
+r180,x.3a,non-octagonal clvom edge
+r181,x.3a,non-octagonal cntm edge
+r182,x.3a,non-octagonal chvntm edge
+r183,x.3a,non-octagonal cnpc edge
+r184,x.3a,non-octagonal cnsdm edge
+r185,x.3a,non-octagonal cpsdm edge
+r186,x.3a,non-octagonal cli1m edge
+r187,x.3a,non-octagonal cviam3 edge
+r188,x.3a,non-octagonal cviam4 edge
+r189,x.3a,non-octagonal PMM2mk edge
+r190,x.3a,non-octagonal CU1Mmk edge
+r191,x.3a,non-octagonal RPMmk edge
+r192,x.3a,non-octagonal PBOmk edge
+r193,x.3a,non-octagonal PDMmk edge
+r194,x.3a,non-octagonal NSMmk edge
+r195,x.3a,non-octagonal MM5mk edge
+r196,x.3a,non-octagonal VIM4mk edge
+r197,x.3a,non-octagonal MM4mk edge
+r198,x.3a,non-octagonal VIM3mk edge
+r199,x.3a,non-octagonal MM3mk edge
+r200,x.3a,non-octagonal VIM2mk edge
+r201,x.3a,non-octagonal MM2mk edge
+r202,x.3a,non-octagonal VIMmk edge
+r203,x.3a,non-octagonal MM1mk edge
+r204,x.3a,non-octagonal CTM1mk edge
+r205,x.3a,non-octagonal LI1Mmk edge
+r206,x.3a,non-octagonal LICM1mk edge
+r207,x.3a,non-octagonal PSDMmk edge
+r208,x.3a,non-octagonal NSDMmk edge
+r209,x.3a,non-octagonal LDNTMmk edge
+r210,x.3a,non-octagonal NPCMmk edge
+r211,x.3a,non-octagonal HVNTMmk edge
+r212,x.3a,non-octagonal NTMmk edge
+r213,x.3a,non-octagonal P1Mmk edge
+r214,x.3a,non-octagonal LVOMmk edge
+r215,x.3a,non-octagonal ONOMmk edge
+r216,x.3a,non-octagonal TUNMmk edge
+r217,x.3a,non-octagonal HVTRMmk edge
+r218,x.3a,non-octagonal HVTPMmk edge
+r219,x.3a,non-octagonal LVTNMmk edge
+r220,x.3a,non-octagonal NWMmk edge
+r221,x.3a,non-octagonal DNMmk edge
+r222,x.3a,non-octagonal FOMmk edge
+r223,x.3a,non-octagonal tap_SEAL edge
+r224,x.3a,non-octagonal tap_ENID edge
+r225,x.3a,non-octagonal poly_ESD edge
+r226,x.3a,"non-octagonal ""li1"" in core edge"
+r227,x.3a,non-octagonal li1_SEAL edge
+r228,x.3a,non-octagonal licon_SEAL edge
+r229,x.3a,non-octagonal mcon_SEAL edge
+r230,x.3a,non-octagonal via_SEAL edge
+r231,x.3a,non-octagonal via2_SEAL edge
+r232,x.3a,non-octagonal via3_SEAL edge
+r233,x.5,met5Pin must be enclosed by met5
+r234,x.5,met4Pin must be enclosed by met4
+r235,x.5,met3Pin must be enclosed by met3
+r236,x.5,met2Pin must be enclosed by met2
+r237,x.5,met1Pin must be enclosed by met1
+r238,x.5,li1Pin must be enclosed by li1
+r239,x.5,polyPin must be enclosed by poly
+r240,x.5,diffPin must be enclosed by diff
+r241,x.9,NTMdrop must be enclosed by COREID
+r242,x.9,LVTNMdrop must be enclosed by COREID
+r243,x.9,HVTPMdrop must be enclosed by COREID
+r244,x.9,LI1Mdrop must be enclosed by COREID
+r245,x.9,LICM1drop must be enclosed by COREID
+r246,x.9,PSDMdrop must be enclosed by COREID
+r247,x.9,NSDMdrop must be enclosed by COREID
+r248,x.9,P1Mdrop must be enclosed by COREID
+r249,x.9,NTMadd must be enclosed by COREID
+r250,x.9,LVTNMadd must be enclosed by COREID
+r251,x.9,HVTPMadd must be enclosed by COREID
+r252,x.9,LI1Madd must be enclosed by COREID
+r253,x.9,LICM1add must be enclosed by COREID
+r254,x.9,PSDMadd must be enclosed by COREID
+r255,x.9,NSDMadd must be enclosed by COREID
+r256,x.9,P1Madd must be enclosed by COREID
+r257,x.9,FOMadd must be enclosed by COREID
+r258,x.9,FOM outside advSeal_6um must be enclosed by COREID
+r259,x.10,diffres must not overlap licon1
+r260,x.10,polyres must not overlap licon1
+r261,x.12a,0.635 min. spacing of moduleCutAREA & q0nwellnotBuildSpace
+r262,x.12b,0.635 min. enclosure of q0nwellnotBuildSpace by moduleCutAREA
+r263,x.12a,0.135 min. spacing of moduleCutAREA & q0diffnotBuildSpace
+r264,x.12b,0.135 min. enclosure of q0diffnotBuildSpace by moduleCutAREA
+r265,x.12a,3.15 min. spacing of moduleCutAREA & q0dnwellnotBuildSpace
+r266,x.12b,3.15 min. enclosure of q0dnwellnotBuildSpace by moduleCutAREA
+r267,x.12a,0.135 min. spacing of moduleCutAREA & q0tapnotBuildSpace
+r268,x.12b,0.135 min. enclosure of q0tapnotBuildSpace by moduleCutAREA
+r269,x.12a,0.19 min. spacing of moduleCutAREA & q0lvtnnotBuildSpace
+r270,x.12b,0.19 min. enclosure of q0lvtnnotBuildSpace by moduleCutAREA
+r271,x.12a,0.19 min. spacing of moduleCutAREA & q0hvtpnotBuildSpace
+r272,x.12b,0.19 min. enclosure of q0hvtpnotBuildSpace by moduleCutAREA
+r273,x.12a,0.35 min. spacing of moduleCutAREA & q0hvinotBuildSpace
+r274,x.12b,0.35 min. enclosure of q0hvinotBuildSpace by moduleCutAREA
+r275,x.12a,0.25 min. spacing of moduleCutAREA & q0tunmnotBuildSpace
+r276,x.12b,0.25 min. enclosure of q0tunmnotBuildSpace by moduleCutAREA
+r277,x.12a,0.105 min. spacing of moduleCutAREA & q0polynotBuildSpace
+r278,x.12b,0.105 min. enclosure of q0polynotBuildSpace by moduleCutAREA
+r279,x.12a,0.135 min. spacing of moduleCutAREA & q0npcnotBuildSpace
+r280,x.12b,0.135 min. enclosure of q0npcnotBuildSpace by moduleCutAREA
+r281,x.12a,0.19 min. spacing of moduleCutAREA & q0nsdmnotBuildSpace
+r282,x.12b,0.19 min. enclosure of q0nsdmnotBuildSpace by moduleCutAREA
+r283,x.12a,0.19 min. spacing of moduleCutAREA & q0psdmnotBuildSpace
+r284,x.12b,0.19 min. enclosure of q0psdmnotBuildSpace by moduleCutAREA
+r285,x.12a,0.085 min. spacing of moduleCutAREA & q0licon1notBuildSpace
+r286,x.12b,0.085 min. enclosure of q0licon1notBuildSpace by moduleCutAREA
+r287,x.12a,0.085 min. spacing of moduleCutAREA & q0li1notBuildSpace
+r288,x.12b,0.085 min. enclosure of q0li1notBuildSpace by moduleCutAREA
+r289,x.12a,0.095 min. spacing of moduleCutAREA & q0mconnotBuildSpace
+r290,x.12b,0.095 min. enclosure of q0mconnotBuildSpace by moduleCutAREA
+r291,x.12a,0.07 min. spacing of moduleCutAREA & q0met1notBuildSpace
+r292,x.12b,0.07 min. enclosure of q0met1notBuildSpace by moduleCutAREA
+r293,x.12a,0.085 min. spacing of moduleCutAREA & q0vianotBuildSpace
+r294,x.12b,0.085 min. enclosure of q0vianotBuildSpace by moduleCutAREA
+r295,x.12a,0.07 min. spacing of moduleCutAREA & q0met2notBuildSpace
+r296,x.12b,0.07 min. enclosure of q0met2notBuildSpace by moduleCutAREA
+r297,x.12a,0.1 min. spacing of moduleCutAREA & q0via2notBuildSpace
+r298,x.12b,0.1 min. enclosure of q0via2notBuildSpace by moduleCutAREA
+r299,x.12a,0.15 min. spacing of moduleCutAREA & q0met3notBuildSpace
+r300,x.12b,0.15 min. enclosure of q0met3notBuildSpace by moduleCutAREA
+r301,x.12a,0.1 min. spacing of moduleCutAREA & q0via3notBuildSpace
+r302,x.12b,0.1 min. enclosure of q0via3notBuildSpace by moduleCutAREA
+r303,x.12a,0.15 min. spacing of moduleCutAREA & q0met4notBuildSpace
+r304,x.12b,0.15 min. enclosure of q0met4notBuildSpace by moduleCutAREA
+r305,x.12a,0.4 min. spacing of moduleCutAREA & q0via4notBuildSpace
+r306,x.12b,0.4 min. enclosure of q0via4notBuildSpace by moduleCutAREA
+r307,x.12a,0.8 min. spacing of moduleCutAREA & q0met5notBuildSpace
+r308,x.12b,0.8 min. enclosure of q0met5notBuildSpace by moduleCutAREA
+r309,x.12a,2 min. spacing of moduleCutAREA & q0nsmnotBuildSpace
+r310,x.12b,2 min. enclosure of q0nsmnotBuildSpace by moduleCutAREA
+r311,x.12a,0.635 min. spacing of moduleCutAREA & q0padnotBuildSpace
+r312,x.12b,0.635 min. enclosure of q0padnotBuildSpace by moduleCutAREA
+r313,x.12a,0.35 min. spacing of moduleCutAREA & q0ldntmnotBuildSpace
+r314,x.12b,0.35 min. enclosure of q0ldntmnotBuildSpace by moduleCutAREA
+r315,x.12a,0.19 min. spacing of moduleCutAREA & q0hvntmnotBuildSpace
+r316,x.12b,0.19 min. enclosure of q0hvntmnotBuildSpace by moduleCutAREA
+r317,x.12a,0.19 min. spacing of moduleCutAREA & q0ncmnotBuildSpace
+r318,x.12b,0.19 min. enclosure of q0ncmnotBuildSpace by moduleCutAREA
+r319,x.12a,5 min. spacing of moduleCutAREA & q0rdlnotBuildSpace
+r320,x.12b,5 min. enclosure of q0rdlnotBuildSpace by moduleCutAREA
+r321,x.12a,0.19 min. spacing of moduleCutAREA & q0hvtrnotBuildSpace
+r322,x.12b,0.19 min. enclosure of q0hvtrnotBuildSpace by moduleCutAREA
+r323,x.12d,0.14 min. spacing of moduleCutAREA & q1met1notBuildSpace
+r324,x.12e,0.14 min. enclosure of q1met1notBuildSpace by moduleCutAREA
+r325,x.12d,0.14 min. spacing of moduleCutAREA & q1met2notBuildSpace
+r326,x.18b,0.42 min. enclosure of capm by moduleCutAREA
+r327,x.18a,0.42 min. spacing of moduleCutAREA & cap2m
+r328,x.18b,0.42 min. enclosure of cap2m by moduleCutAREA
+r329,x.12d,0.2 min. spacing of moduleCutAREA & q1met4notBuildSpace
+r330,x.12e,0.2 min. enclosure of q1met4notBuildSpace by moduleCutAREA
+r331,x.15a,X.15a: layer cfom allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r332,x.15a,X.15a: layer clvtnm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r333,x.15a,X.15a: layer chvtpm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r334,x.15a,X.15a: layer conom allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r335,x.15a,X.15a: layer clvom allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r336,x.15a,X.15a: layer cntm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r337,x.15a,X.15a: layer chvntm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r338,x.15a,X.15a: layer cnpc allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r339,x.15a,X.15a: layer cnsdm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r340,x.15a,X.15a: layer cpsdm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r341,x.15a,X.15a: layer cli1m allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r342,x.15a,X.15a: layer cviam3 allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r343,x.15a,X.15a: layer cviam4 allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r344,x.15a,X.15a: layer PMM2mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r345,x.15a,X.15a: layer CU1Mmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r346,x.15a,X.15a: layer RPMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r347,x.15a,X.15a: layer PBOmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r348,x.15a,X.15a: layer PDMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r349,x.15a,X.15a: layer NSMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r350,x.15a,X.15a: layer MM5mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r351,x.15a,X.15a: layer VIM4mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r352,x.15a,X.15a: layer MM4mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r353,x.15a,X.15a: layer VIM3mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r354,x.15a,X.15a: layer MM3mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r355,x.15a,X.15a: layer VIM2mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r356,x.15a,X.15a: layer MM2mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r357,x.15a,X.15a: layer VIMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r358,x.15a,X.15a: layer MM1mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r359,x.15a,X.15a: layer CTM1mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r360,x.15a,X.15a: layer LI1Mmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r361,x.15a,X.15a: layer LICM1mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r362,x.15a,X.15a: layer PSDMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r363,x.15a,X.15a: layer NSDMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r364,x.15a,X.15a: layer LDNTMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r365,x.15a,X.15a: layer NPCMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r366,x.15a,X.15a: layer HVNTMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r367,x.15a,X.15a: layer NTMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r368,x.15a,X.15a: layer P1Mmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r369,x.15a,X.15a: layer LVOMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r370,x.15a,X.15a: layer ONOMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r371,x.15a,X.15a: layer TUNMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r372,x.15a,X.15a: layer HVTRMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r373,x.15a,X.15a: layer HVTPMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r374,x.15a,X.15a: layer LVTNMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r375,x.15a,X.15a: layer NWMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r376,x.15a,X.15a: layer DNMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r377,x.15a,X.15a: layer FOMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft
+r378,x.16,extentDie must not overlap moduleCutAREA
+r379,x.19,"SEAL ring is not at origin (0,0)"
+r380,x.21,prune must overlap areaidMTorSC
+r381,x.23b,diff must not straddle SEALID
+r382,x.23c,tap must not overlap SEALID
+r383,x.23c,poly must not overlap SEALID
+r384,x.23c,li1 must not overlap SEALID
+r385,x.23c,met1 must not overlap SEALID
+r386,x.23c,met2 must not overlap SEALID
+r387,x.23c,met3 must not overlap SEALID
+r388,x.23c,met4 must not overlap SEALID
+r389,x.23c,met5 must not overlap SEALID
+r390,x.26,SEALID_6um must overlap diff
+r391,x.25,pnp layer must be within specified fixed layout cells sky130rf_pnp/sky130rf_pnp5x
+r392,x.28,6 min. width of SEALID
+r393,dnwell.2,3 min. width of dnwell
+r394,dnwell.3,6.3 min. spacing/notch of dnwellNotPhotoNotUHVI
+r395,dnwell.4,dnwell must not overlap pnp
+r396,ulvt.3,LOWVTID must not straddle uhvi
+r397,dnwell.7,dnwell cannot straddle localSub
+r398,nwell.1,0.84 min. width of nwell
+r399,nwell.2a,1.27 min. spacing/notch of nwell
+r400,nwell.4,nwell_nonUHVI must overlap metal contacted tap to nwell
+r401,nwell.5,0.4 min. enclosure of dnwellNotTechCDLOWVTID by filledNwell
+r402,nwell.5,dnwellNotTechCDLOWVTID must be enclosed by filledNwell
+r403,nwell.6,1.03 min enclosure of nwellHole by dnwell
+r404,nwell.7,4.5 min spacing between nwell and dnwell on separate nets
+r405,hvtp.1,0.38 min. width of hvtp
+r406,hvtp.2,0.38 min. spacing/notch of hvtp
+r407,hvtp.3,0.18 min. enclosure of PFET_PERI by hvtp
+r408,hvtp.4,0.18 min. spacing of PFET_PERI & hvtp
+r409,hvtp.5,0.265 min. area of hvtp
+r410,hvtp.6,0.265 min. area of hvtpHoles
+r411,hvtp.c1,Min/Max enclosure of nwell by hvtp
+r412,lvtn.1a,0.38 min. width of lvtn
+r413,lvtn.2,0.38 min. spacing/notch of lvtn
+r414,lvtn.3a,"0.18 min. spacing of Gate in Periphery outside UHVI layer & ""lvtn"" in periphery"
+r415,lvtn.3b,0.19 min spacing of lvtn(peri) to pfet along S/D direction
+r416,lvtn.4b,"0.18 min. enclosure of Gate in Periphery outside UHVI layer by ""lvtn"" in periphery"
+r417,lvtn.9,0.38 min. spacing of lvtn & hvtp
+r418,lvtn.9,lvtn must not overlap hvtp
+r419,lvtn.10,0.38 min enclosure of lvtn by (nwell not overlapping Varactor Channel)
+r420,lvtn.12,0.38 min. spacing of lvtn & coreNwell
+r421,lvtn.13,0.265 min. area of lvtn
+r422,lvtn.14,0.265 min. area of lvtnHoles
+r423,hvtr.1,0.38 min. width of hvtr
+r424,hvtr.2,0.38 min. spacing of hvtr & hvtp
+r425,hvtr.2,hvtr must not overlap hvtp
+r426,hvtr.3,0.18 min. enclosure of PFET by hvtr
+r427,difftap.1,0.15 min. width of diff across areaid:ce
+r428,difftap.1,0.15 min. width of diff in PERI
+r429,difftap.c1,0.14 min. width of diff in COREID
+r430,difftap.1,0.15 min. width of tap across areaid:ce
+r431,difftap.1,0.15 min. width of tap in PERI
+r432,difftap.c1,0.14 min. width of tap in COREID
+r433,difftap.2,0.42 min. width of GATE_PERI_noSC
+r434,difftap.2b,0.36 min. width of GATE_PERI_SC
+r435,difftap.3,0.27 min. spacing/notch of diff or tap
+r436,difftap.4,0.29 min. width of tap butting diff
+r437,difftap.5,"0.4 min. width of ""tap"" in periphery butting & between diff"
+r438,difftap.6,diff and tap are not allowed to extend beyond their abutting edge
+r439,difftap.7,0.13 spacing of diff/tap butting edge to non-coincident diff/tap edge
+r440,difftap.8,0.18 min. enclosure of PDIFF_PERI_nonESDuhvi by nwell
+r441,difftap.9,0.34 min. spacing of NDIFF_PERI_nonESDuhvi & nwell_noesd
+r442,difftap.10,0.18 min. enclosure of NTAP_nonESD_nonuhvi by nwell
+r443,difftap.11,0.13 min. spacing of PTAP_nonUHVI & nwell
+r444,difftap.c1,"0.14 min. width of ""gate"" in core"
+r445,difftap.c5,"0.38 min. width of ""tap"" in core butting & between diff"
+r446,difftap.c8,"0.15 min. enclosure of ""pdiff"" in core by nwell"
+r447,difftap.c10,"0.15 min. enclosure of ""ntap"" in core by nwell"
+r448,difftap.c12,"0.18 min. enclosure of adj. sides of ""pdiff"" in core by nwell"
+r449,difftap.c13,"0.32 min. spacing of ""ndiff"" in core & nwell"
+r450,difftap.c14,"0.34 min. enclosure of adj. sides of ""ndiff"" in core by chipNotNwell"
+r451,tunm.1,0.41 min. width of tunm
+r452,tunm.2,0.5 min. spacing/notch of tunm
+r453,tunm.3,0.095 min. extension of tunm beyond gate
+r454,tunm.4,0.095 min. spacing of GATE_outsidetunm & tunm
+r455,tunm.5,gate must not straddle tunm
+r456,tunm.6a,tunm outside deep nwell is not allowed
+r457,tunm.7,0.672 min. area of tunm
+r458,tunm.8,tunm must be enclosed by COREID
+r459,nsd.1,0.38 min. width of nsdm across areaid:ce
+r460,nsd.1,0.38 min. width of nsdm in PERI
+r461,nsd.c1b,0.29 min. width of nsdm in COREID
+r462,nsd.2,"0.38 min. spacing/notch of ""nsdm"" in periphery"
+r463,nsd.2,0.38 min. spacing of nsdm across COREID boundary
+r464,nsd.5a,0.125 min. enclosure of n+ diff by nsdm
+r465,nsd.5b,0.125 min. enclosure of n+ tap in peri by nsdm
+r466,nsd.7,0.13 min. spacing of nsdm & opposite implant diffTap
+r467,nsd.8,nsdm must not overlap pdiff/ptap (source of extendedDrain fet exempted)
+r468,nsd.9,ndiff/ntap (source of extendedDrain fet and gated_npn exempted) must be enclosed by nsdmZENERID
+r469,nsd.10a,0.265 min. area of nsdm
+r470,nsd.11,0.265 min. area of nsdmHole
+r471,nsd.c1a,0.38 min. width of nsdm (opposite parallel)
+r472,nsd.c2a,"0.38 min. spacing/notch of ""nsdm"" in core"
+r473,nsd.c2b,"0.29 min. spacing/notch of ""nsdm"" in core"
+r474,nsd.c5a,0.13 min. enclosure of n+ tap in core by nsdm
+r475,psd.1,0.38 min. width of psdm across areaid:ce
+r476,psd.1,0.38 min. width of psdm in PERI
+r477,psd.c1b,0.29 min. width of psdm in COREID
+r478,psd.2,"0.38 min. spacing/notch of ""psdm"" in periphery"
+r479,psd.2,0.38 min. spacing of psdm across COREID boundary
+r480,psd.5a,0.125 min. enclosure of p+ diff by psdm
+r481,psd.5b,0.125 min. enclosure of p+ tap in peri by psdm
+r482,psd.7,0.13 min. spacing of psdm & opposite implant diffTap
+r483,psd.8,psdm must not overlap ndiff/ntap (source of extendedDrain fet exempted)
+r484,psd.9,pdiff/ptap (source of extendedDrain fet exempted) must be enclosed by psdmZENERID
+r485,psd.10b,0.255 min. area of psdm
+r486,psd.11,0.265 min. area of psdmHole
+r487,psd.c1a,0.38 min. width of psdm (opposite parallel)
+r488,psd.c2a,"0.38 min. spacing/notch of ""psdm"" in core"
+r489,psd.c2b,"0.29 min. spacing/notch of ""psdm"" in core"
+r490,psd.c5b,0.12 min. enclosure of p+ tap in core by psdm
+r491,hvi.1,0.6 min. width of hvi_peri
+r492,hvi.2a,0.7 min. spacing/notch of hvi_peri
+r493,hvi.4,hvi must not overlap tunm
+r494,hvi.5,0.7 min. spacing between non-butting hvi and nwell
+r495,nwell.8,2 min. spacing of HV_nwell & nwell
+r496,hv.nwell.1,2.5 min. spacing of nwell with text (shv_nwell) & nwell
+r497,nwell.9,HVnwell must be enclosed by hvi
+r498,nwell.10,LVnwell should not be on the same net as HVnwell
+r499,difftap.14,0.29 min. width of Hdiff in periphery not Hv Pdiff Res
+r500,difftap.14a,0.15 min. width of Hv Pdiff Res in periphery
+r501,difftap.15a,0.3 min. spacing/notch of Hdiff in periphery
+r502,difftap.15b,0.37 min. spacing of n+ diff inside hvi in periphery & ptapHV_PERI_noAbut
+r503,difftap.16,0.7 min. width of tapHV butting diffHV_noUHVI
+r504,difftap.16,0.7 min. width of tapHV_noUHVI butting & between Hdiff
+r505,difftap.17,0.33 min. enclosure of p+ Hdiff (no ESD)(no UHVI) by HV_nwell
+r506,difftap.18,0.43 min. spacing of ndiff_nonESDuhvi & HV_nwell
+r507,difftap.19,0.33 min. enclosure of n+ Htap (no ESD)(no UHVI) by HV_nwell
+r508,difftap.20,0.43 min. spacing of PTAP_noPwellRes_noUHVI & HV_nwell
+r509,difftap.21,"""diffTap"" in periphery must not straddle hvi"
+r510,difftap.22,0.18 min. enclosure of Hdiff/Htap in periphery without UHVI by hvi
+r511,difftap.23,0.18 min. spacing of diffTapNoHv_PERI & hvi
+r512,difftap.24,0.43 min. spacing of ndiffHV_nonESDuhvi & nwell
+r513,difftap.c11,0.15 min. width of Hdiff in COREID
+r514,poly.13,0.5 min. width of poly over diff inside hvi in periphery
+r515,poly.14,gate must not straddle hvi
+r516,poly.1a,0.15 min. width of poly
+r517,poly.1b,poly.1b: 0.350 min. channel length of pfet overlapping lvtn
+r518,poly.2,"0.21 min. spacing/notch of ""poly"" in periphery"
+r519,poly.2,0.21 min. spacing of poly2noXmt across COREID boundary
+r520,poly.c3,poly.c3: 0.175 min. spacing of poly (except for poly.c2)
+r521,poly.c2,poly.c2: 0.160 min. spacing of poly for poly core gap
+r522,poly.3,0.33 min. width of poly resistor
+r523,poly.4,"0.075 min. spacing of ""poly"" in periphery & diff"
+r524,poly.5,"0.055 min. spacing of ""poly"" in periphery & tap"
+r525,poly.6,0.3 min. extension of diff edge butting tap beyond gate edge in periphery
+r526,poly.7,0.25 min. extension of diff beyond gate edge in periphery
+r527,poly.8,0.13 min. extension of poly beyond gate end in periphery
+r528,poly.9,0.48 min. spacing of poly resistor & diffTap
+r529,poly.9,poly resistor must not overlap diffTap
+r530,poly.9,0.48 min. spacing of poly resistor & poly
+r531,poly.10,poly must not overlap any inner corner of diff
+r532,poly.11,No 90 degree bends of poly on diff
+r533,poly.12,"PolyNotLvNwellnoUHVI must not overlap ""tap"" in periphery"
+r534,poly.15,poly must not overlap diffres
+r535,poly.c1,"0.03 min. spacing of ""poly"" in core & diff"
+r536,poly.c1,"0.03 min. spacing of ""poly"" in core & tap"
+r537,dnwell.6,rfNMOS must be enclosed by dnwell
+r538,poly.x.1a,0.5 min. width of dummy_nhv
+r539,poly.x.1a,0.15 min. width of dummy_nlowvt
+r540,poly.x.1a,0.15 min. width of dummy_nshort
+r541,poly.x.1a,0.15 min. width of dummy_pshort
+r542,poly.x.1a,0.35 min. width of dummy_plowvt
+r543,poly.x.1,This is an invalid nfet
+r544,poly.x.1,This is an invalid pfet
+r545,poly.x.1,This nhvnative is only allow in the FGR
+r546,poly.x.1,This sky130rf_pmedlvt_W0p84_L0p15_2F device has an invalid W/L. Please see MRGA
+r547,poly.x.1,This sky130rf_pshort_W3p0_L0p25_M4_b device has an invalid W/L. Please see MRGA
+r548,poly.x.1,This sky130rf_pshort_W5p0_L0p15_2F device has an invalid W/L. Please see MRGA
+r549,poly.x.1,This sky130rf_pshort_W1p65_L0p25_M4_b device has an invalid W/L. Please see MRGA
+r551,poly.x.1,This sky130rf_pshort_W3p0_L0p15_M4_b device has an invalid W/L. Please see MRGA
+r552,poly.x.1,This sky130rf_pshort_W5p0_L0p25_M4_b device has an invalid W/L. Please see MRGA
+r553,poly.x.1,This sky130rf_pshort_W5p0_L0p25_M2_b device has an invalid W/L. Please see MRGA
+r555,poly.x.1,This sky130rf_pshort_W0p84_L0p15_2F device has an invalid W/L. Please see MRGA
+r556,poly.x.1,This sky130rf_pshort_W1p65_L0p25_M2_b device has an invalid W/L. Please see MRGA
+r558,poly.x.1,This sky130rf_pshort_W3p0_L0p15_M2_b device has an invalid W/L. Please see MRGA
+r559,poly.x.1,This sky130rf_pshort_W5p0_L0p15_M4_b device has an invalid W/L. Please see MRGA
+r560,poly.x.1,This sky130rf_pshort_W5p0_L0p15_M2_b device has an invalid W/L. Please see MRGA
+r561,poly.x.1,This sky130rf_pshort_W3p0_L0p15_2F device has an invalid W/L. Please see MRGA
+r562,poly.x.1,This sky130rf_pshort_W5p0_L0p18_M4_b device has an invalid W/L. Please see MRGA
+r563,poly.x.1,This sky130rf_pshort_W1p68_L0p15_4F device has an invalid W/L. Please see MRGA
+r564,poly.x.1,This sky130rf_pshort_W3p0_L0p18_M4_b device has an invalid W/L. Please see MRGA
+r565,poly.x.1,This sky130rf_pshort_W5p0_L0p18_M2_b device has an invalid W/L. Please see MRGA
+r566,poly.x.1,This sky130rf_pshort_W3p0_L0p25_M2_b device has an invalid W/L. Please see MRGA
+r567,poly.x.1,This sky130rf_pshort_W1p65_L0p15_M2_b device has an invalid W/L. Please see MRGA
+r569,poly.x.1,This ppu device has an invalid W/L. Please see MRGA
+r570,poly.x.1,This sky130rf_pshort_W1p68_L0p15_2F device has an invalid W/L. Please see MRGA
+r571,poly.x.1,This sky130rf_pshort_W1p65_L0p18_M4_b device has an invalid W/L. Please see MRGA
+r572,poly.x.1,This sky130rf_pmedlvt_W1p68_L0p15_4F device has an invalid W/L. Please see MRGA
+r573,poly.x.1,This sky130rf_pshort_W1p65_L0p18_M2_b device has an invalid W/L. Please see MRGA
+r574,poly.x.1,This sky130rf_pshort_W1p65_L0p15_M4_b device has an invalid W/L. Please see MRGA
+r576,poly.x.1,This sky130rf_pshort_W3p0_L0p18_M2_b device has an invalid W/L. Please see MRGA
+r577,poly.x.1,This sky130rf_pmedlvt_W1p68_L0p15_2F device has an invalid W/L. Please see MRGA
+r578,poly.x.1,This sky130rf_nlowvt_W0p42_L0p15_2F device has an invalid W/L. Please see MRGA
+r579,poly.x.1,This sky130rf_nlowvt_W0p84_L0p15_2F device has an invalid W/L. Please see MRGA
+r580,poly.x.1,This sky130rf_nhv_W7p0_L0p5_M10_b device has an invalid W/L. Please see MRGA
+r582,poly.x.1,This sky130rf_nshort_W5p0_L0p25_M4_b device has an invalid W/L. Please see MRGA
+r583,poly.x.1,This npass device has an invalid W/L. Please see MRGA
+r584,poly.x.1,This sky130rf_nlowvt_W1p65_L0p15_M2_b device has an invalid W/L. Please see MRGA
+r585,poly.x.1,This sky130rf_nhv_W3p0_L0p5_M10_b device has an invalid W/L. Please see MRGA
+r586,poly.x.1,This sonos_p device has an invalid W/L. Please see MRGA
+r587,poly.x.1,This nhvnativeesd device has an invalid W/L. Please see MRGA
+r588,poly.x.1,This npd device has an invalid W/L. Please see MRGA
+r589,poly.x.1,This ntvnative device has an invalid W/L. Please see MRGA
+r590,poly.x.1,This sky130rf_nhv_W5p0_L0p5_M4_b device has an invalid W/L. Please see MRGA
+r591,poly.x.1,This sky130rf_nshort_W1p65_L0p18_M4_b device has an invalid W/L. Please see MRGA
+r592,poly.x.1,This sky130rf_nlowvt_W3p0_L0p15_4F device has an invalid W/L. Please see MRGA
+r593,poly.x.1,This fnpass device has an invalid W/L. Please see MRGA
+r594,poly.x.1,This sky130rf_nlowvt_W1p65_L0p15_M4_b device has an invalid W/L. Please see MRGA
+r595,poly.x.1,This sky130rf_nlowvt_W3p0_L0p18_M4_b device has an invalid W/L. Please see MRGA
+r596,poly.x.1,This sky130rf_nlowvt_W3p0_L0p15_8F device has an invalid W/L. Please see MRGA
+r597,poly.x.1,This sky130rf_nlowvt_W3p0_L0p15_M4_b device has an invalid W/L. Please see MRGA
+r598,poly.x.1,This sky130rf_nlowvt_W3p0_L0p25_M4_b device has an invalid W/L. Please see MRGA
+r599,poly.x.1,This sky130rf_nlowvt_W3p0_L0p15_M2_b device has an invalid W/L. Please see MRGA
+r600,poly.x.1,This sky130rf_nlowvt_W5p0_L0p15_M2_b device has an invalid W/L. Please see MRGA
+r601,poly.x.1,This sky130rf_nlowvt_W0p84_L0p15_4F device has an invalid W/L. Please see MRGA
+r602,poly.x.1,This sky130rf_nshort_W3p0_L0p18_M4_b device has an invalid W/L. Please see MRGA
+r603,poly.x.1,This sky130rf_nshort_W5p0_L0p18_M2_b device has an invalid W/L. Please see MRGA
+r604,poly.x.1,This sky130rf_nshort_W5p0_L0p25_M2_b device has an invalid W/L. Please see MRGA
+r606,poly.x.1,This sky130rf_nshort_W3p0_L0p25_M2_b device has an invalid W/L. Please see MRGA
+r607,poly.x.1,This sonos_e device has an invalid W/L. Please see MRGA
+r608,poly.x.1,This sky130rf_nshort_W5p0_L0p15_M4_b device has an invalid W/L. Please see MRGA
+r609,poly.x.1,This sky130rf_nhv_W3p0_L0p5_M4_b device has an invalid W/L. Please see MRGA
+r610,poly.x.1,This sky130rf_nlowvt_W3p0_L0p18_M2_b device has an invalid W/L. Please see MRGA
+r611,poly.x.1,This sky130rf_nshort_W1p65_L0p25_M4_b device has an invalid W/L. Please see MRGA
+r612,poly.x.1,This sky130rf_nshort_W3p0_L0p15_M2_b device has an invalid W/L. Please see MRGA
+r614,poly.x.1,This sky130rf_nshort_W5p0_L0p15_M2_b device has an invalid W/L. Please see MRGA
+r615,poly.x.1,This sky130rf_nhv_W5p0_L0p5_M2_b device has an invalid W/L. Please see MRGA
+r616,poly.x.1,This sky130rf_nlowvt_W0p84_L0p15_8F device has an invalid W/L. Please see MRGA
+r617,poly.x.1,This sky130rf_nshort_W1p65_L0p15_M4_b device has an invalid W/L. Please see MRGA
+r618,poly.x.1,This sky130rf_nlowvt_W3p0_L0p25_M2_b device has an invalid W/L. Please see MRGA
+r619,poly.x.1,This sky130rf_nlowvt_W5p0_L0p25_M4_b device has an invalid W/L. Please see MRGA
+r620,poly.x.1,This nshortesd device has an invalid W/L. Please see MRGA
+r621,poly.x.1,This sky130rf_nlowvt_W5p0_L0p25_M2_b device has an invalid W/L. Please see MRGA
+r622,poly.x.1,This sky130rf_nshort_W3p0_L0p15_M4_b device has an invalid W/L. Please see MRGA
+r624,poly.x.1,This sky130rf_nshort_W5p0_L0p18_M4_b device has an invalid W/L. Please see MRGA
+r625,poly.x.1,This sky130rf_nlowvt_W1p65_L0p25_M2_b device has an invalid W/L. Please see MRGA
+r626,poly.x.1,This sky130rf_nhv_W5p0_L0p5_M10_b device has an invalid W/L. Please see MRGA
+r627,poly.x.1,This sky130rf_nshort_W3p0_L0p25_M4_b device has an invalid W/L. Please see MRGA
+r628,poly.x.1,This sky130rf_nhv_W3p0_L0p5_M2_b device has an invalid W/L. Please see MRGA
+r629,poly.x.1,This sky130rf_nlowvt_W1p65_L0p18_M2_b device has an invalid W/L. Please see MRGA
+r630,poly.x.1,This nlvtpass device has an invalid W/L. Please see MRGA
+r631,poly.x.1,This sky130rf_nshort_W1p65_L0p18_M2_b device has an invalid W/L. Please see MRGA
+r632,poly.x.1,This sky130rf_nlowvt_W5p0_L0p15_M4_b device has an invalid W/L. Please see MRGA
+r633,poly.x.1,This sky130rf_nlowvt_W1p65_L0p18_M4_b device has an invalid W/L. Please see MRGA
+r634,poly.x.1,This sky130rf_nlowvt_W5p0_L0p18_M4_b device has an invalid W/L. Please see MRGA
+r635,poly.x.1,This sky130rf_nlowvt_W3p0_L0p15_2F device has an invalid W/L. Please see MRGA
+r636,poly.x.1,This sky130rf_nshort_W3p0_L0p18_M2_b device has an invalid W/L. Please see MRGA
+r637,poly.x.1,This sky130rf_nlowvt_W5p0_L0p18_M2_b device has an invalid W/L. Please see MRGA
+r638,poly.x.1,This sky130rf_nhv_W7p0_L0p5_M4_b device has an invalid W/L. Please see MRGA
+r639,poly.x.1,This nhvesd device has an invalid W/L. Please see MRGA
+r640,poly.x.1,This sky130rf_nshort_W1p65_L0p25_M2_b device has an invalid W/L. Please see MRGA
+r641,poly.x.1,This sky130rf_nlowvt_W1p65_L0p25_M4_b device has an invalid W/L. Please see MRGA
+r642,poly.x.1,This sky130rf_nshort_W1p65_L0p15_M2_b device has an invalid W/L. Please see MRGA
+r643,poly.x.1,This pvhv device has an invalid W/L. Please see MRGA
+r644,poly.x.1,This nvhv device has an invalid W/L. Please see MRGA
+r645,diff.13,sky130rf_nlowvt_W0p42_L0p15_2F_cell should be rectangular
+r646,diff.13,0.42 min. width of sky130rf_nlowvt_W0p42_L0p15_2F_cell
+r647,diff.13,0.42 max. width of sky130rf_nlowvt_W0p42_L0p15_2F_cell
+r648,diff.13,1.14 min. length of sky130rf_nlowvt_W0p42_L0p15_2F_cell
+r649,diff.13,1.14 max. length of sky130rf_nlowvt_W0p42_L0p15_2F_cell
+r650,diff.13,sky130rf_nlowvt_W0p84_L0p15_2F_cell should be rectangular
+r651,diff.13,0.84 min. width of sky130rf_nlowvt_W0p84_L0p15_2F_cell
+r652,diff.13,0.84 max. width of sky130rf_nlowvt_W0p84_L0p15_2F_cell
+r653,diff.13,1.14 min. length of sky130rf_nlowvt_W0p84_L0p15_2F_cell
+r654,diff.13,1.14 max. length of sky130rf_nlowvt_W0p84_L0p15_2F_cell
+r655,diff.13,sky130rf_nlowvt_W0p84_L0p15_4F_cell should be rectangular
+r656,diff.13,0.84 min. width of sky130rf_nlowvt_W0p84_L0p15_4F_cell
+r657,diff.13,0.84 max. width of sky130rf_nlowvt_W0p84_L0p15_4F_cell
+r658,diff.13,2 min. length of sky130rf_nlowvt_W0p84_L0p15_4F_cell
+r659,diff.13,2 max. length of sky130rf_nlowvt_W0p84_L0p15_4F_cell
+r660,diff.13,sky130rf_nlowvt_W0p84_L0p15_8F_cell should be rectangular
+r661,diff.13,0.84 min. width of sky130rf_nlowvt_W0p84_L0p15_8F_cell
+r662,diff.13,0.84 max. width of sky130rf_nlowvt_W0p84_L0p15_8F_cell
+r663,diff.13,3.72 min. length of sky130rf_nlowvt_W0p84_L0p15_8F_cell
+r664,diff.13,3.72 max. length of sky130rf_nlowvt_W0p84_L0p15_8F_cell
+r665,diff.13,sky130rf_nlowvt_W3p0_L0p15_2F_cell should be rectangular
+r666,diff.13,1.14 min. width of sky130rf_nlowvt_W3p0_L0p15_2F_cell
+r667,diff.13,1.14 max. width of sky130rf_nlowvt_W3p0_L0p15_2F_cell
+r668,diff.13,3 min. length of sky130rf_nlowvt_W3p0_L0p15_2F_cell
+r669,diff.13,3 max. length of sky130rf_nlowvt_W3p0_L0p15_2F_cell
+r670,diff.13,sky130rf_nlowvt_W3p0_L0p15_4F_cell should be rectangular
+r671,diff.13,2 min. width of sky130rf_nlowvt_W3p0_L0p15_4F_cell
+r672,diff.13,2 max. width of sky130rf_nlowvt_W3p0_L0p15_4F_cell
+r673,diff.13,3 min. length of sky130rf_nlowvt_W3p0_L0p15_4F_cell
+r674,diff.13,3 max. length of sky130rf_nlowvt_W3p0_L0p15_4F_cell
+r675,diff.13,sky130rf_nlowvt_W3p0_L0p15_8F_cell should be rectangular
+r676,diff.13,3 min. width of sky130rf_nlowvt_W3p0_L0p15_8F_cell
+r677,diff.13,3 max. width of sky130rf_nlowvt_W3p0_L0p15_8F_cell
+r678,diff.13,3.72 min. length of sky130rf_nlowvt_W3p0_L0p15_8F_cell
+r679,diff.13,3.72 max. length of sky130rf_nlowvt_W3p0_L0p15_8F_cell
+r680,diff.13,sky130rf_pshort_W0p84_L0p15_2F_cell should be rectangular
+r681,diff.13,0.84 min. width of sky130rf_pshort_W0p84_L0p15_2F_cell
+r682,diff.13,0.84 max. width of sky130rf_pshort_W0p84_L0p15_2F_cell
+r683,diff.13,1.11 min. length of sky130rf_pshort_W0p84_L0p15_2F_cell
+r684,diff.13,1.11 max. length of sky130rf_pshort_W0p84_L0p15_2F_cell
+r685,diff.13,sky130rf_pshort_W1p68_L0p15_2F_cell should be rectangular
+r686,diff.13,1.11 min. width of sky130rf_pshort_W1p68_L0p15_2F_cell
+r687,diff.13,1.11 max. width of sky130rf_pshort_W1p68_L0p15_2F_cell
+r688,diff.13,1.68 min. length of sky130rf_pshort_W1p68_L0p15_2F_cell
+r689,diff.13,1.68 max. length of sky130rf_pshort_W1p68_L0p15_2F_cell
+r690,diff.13,sky130rf_pshort_W1p68_L0p15_4F_cell should be rectangular
+r691,diff.13,1.68 min. width of sky130rf_pshort_W1p68_L0p15_4F_cell
+r692,diff.13,1.68 max. width of sky130rf_pshort_W1p68_L0p15_4F_cell
+r693,diff.13,1.97 min. length of sky130rf_pshort_W1p68_L0p15_4F_cell
+r694,diff.13,1.97 max. length of sky130rf_pshort_W1p68_L0p15_4F_cell
+r695,diff.13,sky130rf_pshort_W3p0_L0p15_2F_cell should be rectangular
+r696,diff.13,1.11 min. width of sky130rf_pshort_W3p0_L0p15_2F_cell
+r697,diff.13,1.11 max. width of sky130rf_pshort_W3p0_L0p15_2F_cell
+r698,diff.13,3 min. length of sky130rf_pshort_W3p0_L0p15_2F_cell
+r699,diff.13,3 max. length of sky130rf_pshort_W3p0_L0p15_2F_cell
+r700,diff.13,sky130rf_pshort_W5p0_L0p15_2F_cell should be rectangular
+r701,diff.13,1.11 min. width of sky130rf_pshort_W5p0_L0p15_2F_cell
+r702,diff.13,1.11 max. width of sky130rf_pshort_W5p0_L0p15_2F_cell
+r703,diff.13,5 min. length of sky130rf_pshort_W5p0_L0p15_2F_cell
+r704,diff.13,5 max. length of sky130rf_pshort_W5p0_L0p15_2F_cell
+r705,poly.16,Poly of the RF FETs defined in Table H5 cannot overlap
+r706,npc.1,0.27 min. width of npc
+r707,npc.2,0.27 min. spacing/notch of npc
+r708,npc.4,0.09 min. spacing of npc & gate
+r709,npc.4,npc must not overlap gate
+r710,npc.5,0.095 max enclosure of poly overlapping slotted_licon by npcm
+r711,licon.2,"0.17 min. spacing/notch of ""licon1"" in periphery"
+r712,licon.2,0.17 min. spacing of licon1 across COREID boundary
+r713,licon.3,0.17 min. width of ring licon1
+r714,licon.3,0.175 max. width of ring licon1
+r715,licon.3,ring licon1 must be enclosed by SEALID
+r716,licon.4,licon1 must overlap li1 and (poly or diff or tap)
+r717,licon.5a,"0.04 min. enclosure of ""licon1"" in periphery by diff"
+r718,licon.5b,0.06 min. spacing of tapLicon_PERI & diffTap butting edge
+r719,licon.5c,"0.06 min. enclosure of adj. sides of ""licon1"" in periphery by diff"
+r720,licon.6,"""licon1"" in periphery must not straddle tap"
+r721,licon.7,"0.12 min. enclosure of adj. sides of ""licon1"" in periphery by noButtTap"
+r722,licon.8,"0.05 min. enclosure of ""poly_licon1"" in periphery by poly"
+r723,licon.8a,"0.08 min. enclosure of adj. sides of ""poly_licon1"" in periphery by poly"
+r724,licon.10,0.25 min. spacing of varLiconPer & varChannel
+r725,licon.11,"0.055 min. spacing of ""licon1 on diffTap"" in periphery & gateNoSC"
+r726,licon.11,"""licon1 on diffTap"" in periphery must not overlap gateNoSC"
+r727,licon.11a,"0.05 min. spacing of ""licon1 on diffTap"" in periphery & (gate and areaid.sc) except 0.15 phighvt"
+r728,licon.11a,"""licon1 on diffTap"" in periphery must not overlap (gate and areaid.sc) except 0.15 phighvt"
+r729,licon.11b,"0.05 min. spacing of ""licon1 on diffTap"" in periphery & gateSCPhighvt"
+r730,licon.11b,"""licon1 on diffTap"" in periphery must not overlap gateSCPhighvt"
+r731,licon.11c,"0.04 min. spacing of ""licon1 on diffTap"" in periphery & licon11cGate"
+r732,licon.11c,"""licon1 on diffTap"" in periphery must not overlap licon11cGate"
+r733,licon.11d,"0.045 min. spacing of ""licon1 on diffTap"" in periphery & licon11dGate"
+r734,licon.11d,"""licon1 on diffTap"" in periphery must not overlap licon11dGate"
+r735,licon.1,rectLCON1OutRpm should be rectangular
+r736,licon.1,0.17 min. width of rectLCON1OutRpm
+r737,licon.1,0.17 max. length of rectLCON1OutRpm
+r738,licon.1b/c,rectLCON1AndRpm should be rectangular
+r739,licon.1b/c,0.19 min. width of rectLCON1AndRpm
+r740,licon.1b/c,0.19 max. width of rectLCON1AndRpm
+r741,licon.1b/c,2 min. length of rectLCON1AndRpm
+r742,licon.1b/c,2 max. length of rectLCON1AndRpm
+r743,licon.2b,0.35 min. spacing/notch of rectLCON1AndRpm
+r744,licon.2c,min spacing between slotted licon in lateral dir is 0.510
+r745,licon.2d,0.51 min. spacing of rectLCON1AndRpm & rectLCON1OutRpm
+r746,licon.9,0.11 min. spacing of polyLicon1OutRpm & psdm
+r747,licon.9,polyLicon1OutRpm must not overlap psdm
+r748,licon.13,"0.09 min. spacing of ""licon1 on diffTap"" in periphery & npc"
+r749,licon.13,"""licon1 on diffTap"" in periphery must not overlap npc"
+r750,licon.14,"0.19 min. spacing of poly_licon1 & ""diffTap"" in periphery"
+r751,licon.15,"0.1 min. enclosure of ""poly_licon1"" in periphery by npc"
+r752,licon.15,"""poly_licon1"" in periphery must be enclosed by npc"
+r753,npcon.c6,"0.045 min. enclosure of ""poly_licon1"" in core by npc"
+r754,npcon.c6,"""poly_licon1"" in core must be enclosed by npc"
+r755,licon.16,source must enclose at least one licon in peri
+r756,licon.16,tap must enclose at least one licon in peri
+r757,licon.17,licon1 overlapping poly must not overlap diffTap
+r758,licon.18,npc must enclose poly_licon
+r759,licon.19,poly on HV varactor must not interact with licon
+r760,licon.c1,"0.13 min. spacing of poly_licon1 & ""diffTap"" in core"
+r761,licon.c3,"0.165 min. spacing/notch of ""licon1"" in core"
+r762,licon.c4,"""poly_licon1"" in core must not overlap psdm"
+r763,li.1,0.17 min. width of liNoVppCaps across areaid:ce
+r764,li.1,0.17 min. width of liNoVppCaps in PERI
+r765,li.c1,0.14 min. width of liNoVppCaps in COREID
+r766,li.1a,0.14 min. width of liVppCaps
+r767,li.3,0.17 min. spacing/notch of li1_3_PERI
+r768,li.3,0.17 min. spacing of li1 across COREID boundary
+r769,li.3a,0.14 min. spacing/notch of li1_3a_PERI
+r770,li.4,"""licon1"" in periphery must be enclosed by li1"
+r771,li.5,"0.08 min. enclosure of adj. sides of ""licon1"" in periphery by li1"
+r772,li.6,0.0561 min. area of li1 across areaid:ce
+r773,li.6,0.0561 min. area of li1
+r774,li.7,0.29 min. width of li1AndResNoESD
+r775,li.c1,"0.14 min. width of ""li1"" in core"
+r776,li.c2,"0.14 min. spacing/notch of ""li1"" in core"
+r777,ct.1,non-ring mcon should be rectangular
+r778,ct.1,0.17 min. width of non-ring mcon
+r779,ct.1,0.17 max. length of non-ring mcon
+r780,ct.2,0.19 min. spacing/notch of mcon
+r781,ct.3,0.17 min. width of ring-shaped mcon
+r782,ct.3,0.175 max. width of ring-shaped mcon
+r783,ct.3,ring-shaped mcon must be enclosed by SEALID
+r784,ct.4,"""mcon"" in periphery must be enclosed by li1"
+r785,ct.c1,"""mcon"" in core must overlap li1"
+r786,ct.c2,"0.19 min. spacing/notch of ""mcon"" in core"
+r787,m1.1,0.14 min. width of met1
+r788,m1.2,0.14 min. spacing/notch of met1
+r789,m1.3b,0.28 min. spacing between huge met1 and normal met1
+r790,m1.3a,0.28 min. spacing/notch of huge met1+nearby met1
+r791,m1.4,0.03 min. enclosure of mcon_PERI_4 by met1
+r792,m1.4,mcon_PERI_4 must be enclosed by met1
+r793,m1.4a,0.005 min. enclosure of mcon_PERI_4a by met1
+r794,m1.4a,mcon_PERI_4a must be enclosed by met1
+r795,m1.5,"0.06 min. enclosure of adj. sides of ""mcon"" in periphery by met1"
+r796,m1.6,0.083 min. area of met1
+r797,m1.7,0.14 min. area of met1Hole
+r798,m1.7,0.14 min. area of met1HoleEmpty
+r799,m1.c1,"""mcon"" in core must be enclosed by met1"
+r800,via.1a,via outside of moduleCut should be rectangular
+r801,via.1a,0.15 min. width of via outside of moduleCut
+r802,via.1a,0.15 max. length of via outside of moduleCut
+r803,via.1b,via size inside module cut must be 0.150 or 0.230 or 0.280
+r804,via.2,0.17 min. spacing/notch of via
+r805,via.3,0.2 min. width of ring-shaped via
+r806,via.3,0.205 max. width of ring-shaped via
+r807,via.3,ring-shaped via must be enclosed by SEALID
+r808,via.4a,0.055 min. enclosure of 0.15um via by met1
+r809,via.4a,0.15um via must be enclosed by met1
+r810,via.4b,0.03 min. enclosure of 0.23 via within modulecut by met1
+r811,via.4b,0.23 via within modulecut must be enclosed by met1
+r812,via.4c,0 min. enclosure of 0.28 via within modulecut by met1
+r813,via.4c,0.28 via within modulecut must be enclosed by met1
+r814,via.5a,0.085 min. enclosure of adj. sides of 0.15um via by met1
+r815,via.5b,0.06 min. enclosure of adj. sides of 0.23 via within modulecut by met1
+r816,via.5c,0 min. enclosure of adj. sides of 0.28 via within modulecut by met1
+r817,m2.1,0.14 min. width of met2
+r818,m2.2,0.14 min. spacing/notch of met2
+r819,m2.3b,0.28 min. spacing between huge met2 and normal met2
+r820,m2.3a,0.28 min. spacing/notch of huge met2+nearby met2
+r821,m2.4,"0.055 min. enclosure of ""via"" in periphery by met2"
+r822,m2.4,"""via"" in periphery must be enclosed by met2"
+r823,m2.5,0.085 min. enclosure of adj. sides of via by met2
+r824,m2.6,0.0676 min. area of met2
+r825,m2.7,0.14 min. area of met2Hole
+r826,m2.7,0.14 min. area of met2HoleEmpty
+r827,m2.c4,"0.04 min. enclosure of ""via"" in core by met2"
+r828,m2.c4,"""via"" in core must be enclosed by met2"
+r829,varac.1,Min channel length of varactor channel is 0.180
+r830,varac.2,Min channel width of varactor channel is 1.000
+r831,varac.3,0.18 min. spacing of varChannel & hvtp
+r832,varac.4,0.25 min. spacing of varChannel & liconOnTap
+r833,varac.5,0.15 min. enclosure of polyonVarChannel by nwell
+r834,varac.6,0.27 min. spacing of taponVarChannel & difftapNotVarChannel
+r835,varac.7,nwell overlapping varacChannel must not overlap p+ diff
+r836,viatop.1,viatop should be rectangular
+r837,viatop.1,0.42 min. width of viatop
+r838,viatop.1,0.42 max. length of viatop
+r839,viatop.2,0.42 min. spacing/notch of viatop
+r840,viatop.3,Only min square ViaTop's are allowed
+r841,viatop.4,0.29 min. enclosure of viatop by met5
+r842,viatop.4,viatop must be enclosed by met5
+r843,viatop.5,ViaTop must not be placed over Pad
+r844,viatop.6,10.00 min. spacing of viatop to pad
+r845,viatop.7,viatop connected to gate must be connected to antenna diode
+r846,photo.11,0.215 min/max enclosure of tap by nwell inside photoDiode
+r847,via2.1d,"via size inside module cut must be 0.200, 0.280, 1.200, OR 1.500"
+r848,via2.1a,rectVIA2noMT should be rectangular
+r849,via2.1a,0.2 min. width of rectVIA2noMT
+r850,via2.1a,0.2 max. length of rectVIA2noMT
+r851,via2.2,0.2 min. spacing/notch of via2
+r852,via2.3,0.2 min. width of ring-shaped via2
+r853,via2.3,0.205 max. width of ring-shaped via2
+r854,via2.3,ring-shaped via2 must be enclosed by SEALID
+r855,via2.4,0.04 min. enclosure of via2 by met2
+r856,via2.4,via2 must be enclosed by met2
+r857,via2.4a,0.14 min. enclosure of rectVIA2Big by met2
+r858,via2.4a,rectVIA2Big must be enclosed by met2
+r859,via2.5,0.085 min. enclosure of adj. sides of via2 by met2
+r860,m3.1,0.3 min. width of met3
+r861,m3.2,0.3 min. spacing/notch of met3
+r862,m3.4,0.065 min. enclosure of via2 by met3
+r863,m3.4,via2 must be enclosed by met3
+r864,m3.6,0.24 min. area of met3
+r865,m3.3d,0.4 min. spacing between huge met3 and normal met3
+r866,m3.3c,0.4 min. spacing/notch of huge met3+nearby met3
+r867,via3.1,rectVIA3noMT should be rectangular
+r868,via3.1,0.2 min. width of rectVIA3noMT
+r869,via3.1,0.2 max. length of rectVIA3noMT
+r870,via3.1a,via size inside module cut must be 0.200 OR 0.800
+r871,via3.2,0.2 min. spacing/notch of via3
+r872,via3.3,0.2 min. width of ring-shaped via3
+r873,via3.3,0.205 max. width of ring-shaped via3
+r874,via3.3,ring-shaped via3 must be enclosed by SEALID
+r875,via3.4,0.06 min. enclosure of non-ring via3 by met3
+r876,via3.4,non-ring via3 must be enclosed by met3
+r877,via3.5,0.09 min. enclosure of adj. sides of via3 by met3
+r878,m4.1,0.3 min. width of met4
+r879,m4.2,0.3 min. spacing/notch of met4
+r880,m4.3,0.065 min. enclosure of via3 by met4
+r881,m4.3,via3 must be enclosed by met4
+r882,m4.4a,0.24 min. area of met4
+r883,m4.5b,0.4 min. spacing between huge met4 and normal met4
+r884,m4.5a,0.4 min. spacing/notch of huge met4+nearby met4
+r885,via4.1,non-ring via4 should be rectangular
+r886,via4.1,0.8 min. width of non-ring via4
+r887,via4.1,0.8 max. length of non-ring via4
+r888,via4.2,0.8 min. spacing/notch of via4
+r889,via4.3,0.8 min. width of ring-shaped via4
+r890,via4.3,0.805 max. width of ring-shaped via4
+r891,via4.3,ring-shaped via4 must be enclosed by SEALID
+r892,via4.4,0.19 min. enclosure of non-ring via4 by met4
+r893,via4.4,non-ring via4 must be enclosed by met4
+r894,m5.1,1.6 min. width of met5
+r895,m5.2,1.6 min. spacing/notch of met5
+r896,m5.3,0.31 min. enclosure of via4 by met5
+r897,m5.3,via4 must be enclosed by met5
+r898,m5.4,4 min. area of met5
+r899,pad.2,1.27 min. spacing/notch of pad
+r900,pad.3,hugepad with area less than 30000.0 not allowed
+r901,denmos.1,1.055 min. width of gate of Drain Extended nFET
+r902,denmos.2,0.28 min. width of deNFetSource not overlapping poly
+r903,denmos.3,0.925 min. width of deNFetSource overlapping poly
+r904,denmos.4,0.17 min. width of drain  of Drain Extended nFET
+r905,denmos.5,min/max extension between de_nFET_source over nwell 0.225
+r906,denmos.6,min/max spacing  between de_nFET_source and de_nFET_drain 1.585
+r907,denmos.7,min channel width 5.000
+r908,denmos.8,90 degree angles are not permitted for nwell over poly
+r909,denmos.10,0.66 min. enclosure of drain  of Drain Extended nFET by nwell
+r910,denmos.11,0.86 min. spacing of ptap & nwellOVRdeNFetDrain
+r911,denmos.12,2.4 min. spacing of nwellOVRdeNFetDrain
+r912,denmos.13,0.13 min. enclosure of source of Drain Extended nFET by nsdm
+r913,denmos.13,source of Drain Extended nFET must be enclosed by nsdm
+r915,depmos.1,1.05 min. width of gate of Drain Extended pFET
+r916,depmos.2,0.28 min. width of dePFetSourceNotpoly
+r917,depmos.3,0.92 min. width of dePFetSource  overlapping poly
+r918,depmos.4,0.17 min. width of drain of Drain Extended pFET
+r919,depmos.5,min/max extension between de_pFET_source beyond nwell 0.260
+r920,depmos.6,min/max spacing  between de_pFET_source and de_pFET_drain 1.190
+r921,depmos.7,min channel width 5.000
+r922,depmos.8,90 degree angles are not permitted for nwellhole over poly
+r923,pwde.6,1.00 min. enclosure of pwde_uhvi by dnwell_uhvi
+r924,pwbm.5,0.84 min. spacing of pwbm_holes
+r925,depmos.12,0.13 min. enclosure of source of Drain Extended pFET by psdm
+r926,depmos.12,source of Drain Extended pFET must be enclosed by psdm
+r927,depmos.13,pvhv_depmos13 must be enclosed by moduleCutAREA
+r928,uhvi.6,UHVI must enclose dnwell
+r929,uhvi.2,poly must not straddle uhvi
+r930,extd.3,deFetPoly must overlap polyGap
+r931,uhvi.3,pwbmNotLOWVTID must be enclosed by uhvi
+r932,pwres.2,PwresDnw should be rectangular
+r933,pwres.2,2.65 min. width of PwresDnw
+r934,pwres.2,2.65 max. width of PwresDnw
+r935,pwres.2,26.5 min. length of PwresDnw
+r936,pwres.2,265 max. length of PwresDnw
+r937,pwres.5,pwres Tap to nwell spacing must be 0.220
+r938,pwres.6,0.53 min. width of PwresTerm
+r939,pwres.6,Exceeds allowed width of pwell res tap
+r940,pwres.7a,Tap in pwell must enclose 12 licon1
+r941,pwres.7b,Tap in pwell must enclose 12 mcon
+r942,pwres.8a,poly must not overlap PwresDnw
+r943,pwres.8b,diff must not overlap PwresDnw
+r944,pwres.9,Nwell around pwell res must have strapped tap with metal
+r945,pwres.11,Pwell res must abut nwell edges on opposite sides
+r946,pwres.10,Pwell res must abut 2 pwres_terminal on opposite sides
+r947,rfdiode.1,non-manhattan RFDIODEID edge
+r948,rfdiode.2,areaid.re must be coincident with nwell for the rf nwell diode
+r949,rfdiode.3,areaid.re must be coincident with inner nwell ring edge for rf pwell-deep nwell diode
+r950,nsm.1,3 min. width of nsm
+r951,nsm.2,4 min. spacing/notch of nsm
+r952,nsm.3,1 min. spacing of diff_not_NSM3_exempt & nsm OR NSMmk
+r953,nsm.3,diff_not_NSM3_exempt must not overlap nsm OR NSMmk
+r954,nsm.3,1 min. spacing of tap_not_NSM3_exempt & nsm OR NSMmk
+r955,nsm.3,tap_not_NSM3_exempt must not overlap nsm OR NSMmk
+r956,nsm.3,1 min. spacing of fomDummyDRC_not_NSM3_exempt & nsm OR NSMmk
+r957,nsm.3,fomDummyDRC_not_NSM3_exempt must not overlap nsm OR NSMmk
+r958,nsm.3,1 min. spacing of FOMmk_not_NSM3_exempt & nsm OR NSMmk
+r959,nsm.3,FOMmk_not_NSM3_exempt must not overlap nsm OR NSMmk
+r960,nsm.3,1 min. spacing of poly_not_NSM3_exempt & nsm OR NSMmk
+r961,nsm.3,poly_not_NSM3_exempt must not overlap nsm OR NSMmk
+r962,nsm.3,1 min. spacing of P1Mmk_not_NSM3_exempt & nsm OR NSMmk
+r963,nsm.3,P1Mmk_not_NSM3_exempt must not overlap nsm OR NSMmk
+r964,nsm.3,1 min. spacing of li1_not_NSM3_exempt & nsm OR NSMmk
+r965,nsm.3,li1_not_NSM3_exempt must not overlap nsm OR NSMmk
+r966,nsm.3,1 min. spacing of LI1Mmk_not_NSM3_exempt & nsm OR NSMmk
+r967,nsm.3,LI1Mmk_not_NSM3_exempt must not overlap nsm OR NSMmk
+r968,nsm.3,1 min. spacing of met1_not_NSM3_exempt & nsm OR NSMmk
+r969,nsm.3,met1_not_NSM3_exempt must not overlap nsm OR NSMmk
+r970,nsm.3,1 min. spacing of MM1mk_not_NSM3_exempt & nsm OR NSMmk
+r971,nsm.3,MM1mk_not_NSM3_exempt must not overlap nsm OR NSMmk
+r972,nsm.3,1 min. spacing of met2_not_NSM3_exempt & nsm OR NSMmk
+r973,nsm.3,met2_not_NSM3_exempt must not overlap nsm OR NSMmk
+r974,nsm.3,1 min. spacing of MM2Mk_not_NSM3_exempt & nsm OR NSMmk
+r975,nsm.3,MM2Mk_not_NSM3_exempt must not overlap nsm OR NSMmk
+r976,nsm.3,1 min. spacing of met3_not_NSM3_exempt & nsm OR NSMmk
+r977,nsm.3,met3_not_NSM3_exempt must not overlap nsm OR NSMmk
+r978,nsm.3,1 min. spacing of MM3mk_not_NSM3_exempt & nsm OR NSMmk
+r979,nsm.3,MM3mk_not_NSM3_exempt must not overlap nsm OR NSMmk
+r980,nsm.3,1 min. spacing of met4_not_NSM3_exempt & nsm OR NSMmk
+r981,nsm.3,met4_not_NSM3_exempt must not overlap nsm OR NSMmk
+r982,nsm.3,1 min. spacing of MM4mk_not_NSM3_exempt & nsm OR NSMmk
+r983,nsm.3,MM4mk_not_NSM3_exempt must not overlap nsm OR NSMmk
+r984,nsm.3,1 min. spacing of met5_not_NSM3_exempt & nsm OR NSMmk
+r985,nsm.3,met5_not_NSM3_exempt must not overlap nsm OR NSMmk
+r986,nsm.3,1 min. spacing of MM5mk_not_NSM3_exempt & nsm OR NSMmk
+r987,nsm.3,MM5mk_not_NSM3_exempt must not overlap nsm OR NSMmk
+r988,nsm.3a,3 min. enclosure of diff_not_NSM3a_exempt by frameBndr
+r989,nsm.3a,3 min. enclosure of tap_not_NSM3a_exempt by frameBndr
+r990,nsm.3a,3 min. enclosure of fomDummyDRC_not_NSM3a_exempt by frameBndr
+r991,nsm.3a,3 min. enclosure of FOMmk_not_NSM3a_exempt by frameBndr
+r992,nsm.3a,3 min. enclosure of poly_not_NSM3a_exempt by frameBndr
+r993,nsm.3a,3 min. enclosure of P1Mmk_not_NSM3a_exempt by frameBndr
+r994,nsm.3a,3 min. enclosure of li1_not_NSM3a_exempt by frameBndr
+r995,nsm.3a,3 min. enclosure of LI1Mmk_not_NSM3a_exempt by frameBndr
+r996,nsm.3a,3 min. enclosure of met1_not_NSM3a_exempt by frameBndr
+r997,nsm.3a,3 min. enclosure of MM1mk_not_NSM3a_exempt by frameBndr
+r998,nsm.3a,3 min. enclosure of met2_not_NSM3a_exempt by frameBndr
+r999,nsm.3a,3 min. enclosure of MM2Mk_not_NSM3a_exempt by frameBndr
+r1000,nsm.3a,3 min. enclosure of met3_not_NSM3a_exempt by frameBndr
+r1001,nsm.3a,3 min. enclosure of MM3mk_not_NSM3a_exempt by frameBndr
+r1002,nsm.3a,3 min. enclosure of met4_not_NSM3a_exempt by frameBndr
+r1003,nsm.3a,3 min. enclosure of MM4mk_not_NSM3a_exempt by frameBndr
+r1004,nsm.3a,3 min. enclosure of met5_not_NSM3a_exempt by frameBndr
+r1005,nsm.3a,3 min. enclosure of MM5mk_not_NSM3a_exempt by frameBndr
+r1006,nsm.3b,3 min. spacing of diff_not_NSM3b_exempt & dieCut
+r1007,nsm.3b,3 min. spacing of tap_not_NSM3b_exempt & dieCut
+r1008,nsm.3b,3 min. spacing of fomDummyDRC_not_NSM3b_exempt & dieCut
+r1009,nsm.3b,3 min. spacing of FOMmk_not_NSM3b_exempt & dieCut
+r1010,nsm.3b,3 min. spacing of poly_not_NSM3b_exempt & dieCut
+r1011,nsm.3b,3 min. spacing of P1Mmk_not_NSM3b_exempt & dieCut
+r1012,nsm.3b,3 min. spacing of li1_not_NSM3b_exempt & dieCut
+r1013,nsm.3b,3 min. spacing of LI1Mmk_not_NSM3b_exempt & dieCut
+r1014,nsm.3b,3 min. spacing of met1_not_NSM3b_exempt & dieCut
+r1015,nsm.3b,3 min. spacing of MM1mk_not_NSM3b_exempt & dieCut
+r1016,nsm.3b,3 min. spacing of met2_not_NSM3b_exempt & dieCut
+r1017,nsm.3b,3 min. spacing of MM2Mk_not_NSM3b_exempt & dieCut
+r1018,nsm.3b,3 min. spacing of met3_not_NSM3b_exempt & dieCut
+r1019,nsm.3b,3 min. spacing of MM3mk_not_NSM3b_exempt & dieCut
+r1020,nsm.3b,3 min. spacing of met4_not_NSM3b_exempt & dieCut
+r1021,nsm.3b,3 min. spacing of MM4mk_not_NSM3b_exempt & dieCut
+r1022,nsm.3b,3 min. spacing of met5_not_NSM3b_exempt & dieCut
+r1023,nsm.3b,3 min. spacing of MM5mk_not_NSM3b_exempt & dieCut
+r1024,ncm.x.3,"ncm_CORE not tech_CD must not overlap ""ndiff"" in periphery"
+r1025,ncm.1,0.38 min. width of ncmPeri
+r1026,ncm.2a,0.38 min. spacing/notch of ncmPeri
+r1027,ncm.7,0.265 min. area of ncm
+r1028,ncm.8,0.265 min. area of ncmHoles
+r1029,ncm.c8,0.235 min. enclosure of PDIFF by ncm_CORE not tech_CD
+r1030,ncm.c9,0.235 min. spacing of ncm_CORE not tech_CD & ndiff
+r1031,ncm.c9,ncm_CORE not tech_CD must not overlap ndiff
+r1032,ncm.c10,0.38 min. spacing of nwellOutCore & ncm_CORE not tech_CD
+r1033,ldntm.c1,0.7 min. width of ldntmCore
+r1034,ldntm.c2,0.7 min. spacing/notch of ldntmCore
+r1035,ldntm.c3,enclosure of ndiff by ldntm must be more than  0.180
+r1036,ldntm.c4,0.125 min. enclosure of nFet by ldntmCore
+r1037,ldntm.c5,ldntm not allowed outside areaid.ce
+r1038,ldntm.c6,0.18 min. spacing of ldntmCoreExempt & pdiff
+r1039,urpm.1a,1.27 min. width of urpm
+r1046,urpm.2,0.84 min. spacing/notch of urpm
+r1047,urpm.3,0.2 min. enclosure of precResistor by rpm
+r1048,rpm.3,precResistor must be enclosed by rpm
+r1049,rpm.4,0.11 min. enclosure of precResistor by psdm
+r1050,rpm.4,precResistor must be enclosed by psdm
+r1051,rpm.5,0.095 min. enclosure of precResistor by npc
+r1052,rpm.5,precResistor must be enclosed by npc
+r1053,rpm.6,0.2 min. spacing of rpm & nsdm
+r1054,rpm.6,rpm must not overlap nsdm
+r1055,rpm.7,0.2 min. spacing of rpm & poly
+r1056,rpm.8,poly must not straddle rpm
+r1057,rpm.9,0.185 min. spacing of precResistor & hvntm
+r1058,rpm.9,precResistor must not overlap hvntm
+r1059,rpm.10,2 min. spacing of rpmNotXmt & pwbm
+r1060,rpm.10,rpmNotXmt must not overlap pwbm
+r1061,hvntm.x.1,hvntm must be drawn inside hvi
+r1062,hvntm.1,0.7 min. width of hvntm_peri
+r1063,hvntm.2,0.7 min. spacing/notch of hvntm_peri
+r1064,hvntm.3,0.185 min. enclosure of ndiffInHviPeri by hvntm_peri
+r1065,hvntm.4,0.185 min. spacing of hvntm_peri & ndiffOutsideHvi
+r1066,hvntm.4,hvntm_peri must not overlap ndiffOutsideHvi
+r1067,hvntm.5,0.185 min. spacing of hvntm_peri & PDIFF_notENID
+r1068,hvntm.5,hvntm_peri must not overlap PDIFF_notENID
+r1069,hvntm.6a,0.185 min. spacing of hvntm_peri & PTAPnoButtDiff
+r1070,hvntm.6a,hvntm_peri must not overlap ptap
+r1071,hvntm.6b,hvntm_peri must not overlap diffpTapButtEdge_sz
+r1072,hvntm.7,0 min. enclosure of ESD_nwell_tap_hvi by hvntm_peri
+r1073,hvntm.7,ESD_nwell_tap_hvi must be enclosed by hvntm_peri
+r1074,hvntm.9,hvntm must not overlap COREID
+r1075,hvntm.10,hvntm must overlap hvi
+r1076,cfom.nikon,FOMmk in the nikon cross has the wrong polarity
+r1077,cfom.nikon,FOMmk is missing from the nikon cross in the layout.
+r1078,cdnm.nikon,DNMmk in the nikon cross has the wrong polarity
+r1079,cdnm.nikon,DNMmk is missing from the nikon cross in the layout.
+r1080,cnwm.nikon,NWMmk in the nikon cross has the wrong polarity
+r1081,cnwm.nikon,NWMmk is missing from the nikon cross in the layout.
+r1082,chvtpm.nikon,HVTPMmk in the nikon cross has the wrong polarity
+r1083,chvtpm.nikon,HVTPMmk is missing from the nikon cross in the layout.
+r1084,clvtnm.nikon,LVTNMmk in the nikon cross has the wrong polarity
+r1085,clvtnm.nikon,LVTNMmk is missing from the nikon cross in the layout.
+r1086,clvom.nikon,LVOMmk in the nikon cross has the wrong polarity
+r1087,clvom.nikon,LVOMmk is missing from the nikon cross in the layout.
+r1088,cp1m.nikon,P1Mmk in the nikon cross has the wrong polarity
+r1089,cp1m.nikon,P1Mmk is missing from the nikon cross in the layout.
+r1090,cntm.nikon,NTMmk in the nikon cross has the wrong polarity
+r1091,cntm.nikon,NTMmk is missing from the nikon cross in the layout.
+r1092,chvntm.nikon,HVNTMmk in the nikon cross has the wrong polarity
+r1093,chvntm.nikon,HVNTMmk is missing from the nikon cross in the layout.
+r1094,cldntm.nikon,LDNTMmk in the nikon cross has the wrong polarity
+r1095,cldntm.nikon,LDNTMmk is missing from the nikon cross in the layout.
+r1096,cnpc.nikon,NPCMmk in the nikon cross has the wrong polarity
+r1097,cnpc.nikon,NPCMmk is missing from the nikon cross in the layout.
+r1098,cnsdm.nikon,NSDMmk in the nikon cross has the wrong polarity
+r1099,cnsdm.nikon,NSDMmk is missing from the nikon cross in the layout.
+r1100,cpsdm.nikon,PSDMmk in the nikon cross has the wrong polarity
+r1101,cpsdm.nikon,PSDMmk is missing from the nikon cross in the layout.
+r1102,clicm1.nikon,LICM1mk in the nikon cross has the wrong polarity
+r1103,clicm1.nikon,LICM1mk is missing from the nikon cross in the layout.
+r1104,cli1m.nikon,LI1Mmk in the nikon cross has the wrong polarity
+r1105,cli1m.nikon,LI1Mmk is missing from the nikon cross in the layout.
+r1106,cctm1.nikon,CTM1mk in the nikon cross has the wrong polarity
+r1107,cctm1.nikon,CTM1mk is missing from the nikon cross in the layout.
+r1108,cmm1.nikon,MM1mk in the nikon cross has the wrong polarity
+r1109,cmm1.nikon,MM1mk is missing from the nikon cross in the layout.
+r1110,cviam.nikon,VIMmk in the nikon cross has the wrong polarity
+r1111,cviam.nikon,VIMmk is missing from the nikon cross in the layout.
+r1112,cmm2.nikon,MM2mk in the nikon cross has the wrong polarity
+r1113,cmm2.nikon,MM2mk is missing from the nikon cross in the layout.
+r1114,cnsm.nikon,NSMmk in the nikon cross has the wrong polarity
+r1115,cnsm.nikon,NSMmk is missing from the nikon cross in the layout.
+r1116,cpdm.nikon,PDMmk in the nikon cross has the wrong polarity
+r1117,cpdm.nikon,PDMmk is missing from the nikon cross in the layout.
+r1118,cviam2.nikon,VIM2mk in the nikon cross has the wrong polarity
+r1119,cviam2.nikon,VIM2mk is missing from the nikon cross in the layout.
+r1120,cmm3.nikon,MM3mk in the nikon cross has the wrong polarity
+r1121,cmm3.nikon,MM3mk is missing from the nikon cross in the layout.
+r1122,cviam3.nikon,VIM3mk in the nikon cross has the wrong polarity
+r1123,cviam3.nikon,VIM3mk is missing from the nikon cross in the layout.
+r1124,cmm4.nikon,MM4mk in the nikon cross has the wrong polarity
+r1125,cmm4.nikon,MM4mk is missing from the nikon cross in the layout.
+r1126,cviam4.nikon,VIM4mk in the nikon cross has the wrong polarity
+r1127,cviam4.nikon,VIM4mk is missing from the nikon cross in the layout.
+r1128,cmm5.nikon,MM5mk in the nikon cross has the wrong polarity
+r1129,cmm5.nikon,MM5mk is missing from the nikon cross in the layout.
+r1130,crpm.nikon,RPMmk in the nikon cross has the wrong polarity
+r1131,crpm.nikon,RPMmk is missing from the nikon cross in the layout.
+r1132,areaid.1,Unapproved cells contain areaid.ce layer
+r1133,vpp.5,"1.5 min spacing of (li1, poly, or met1/2) overlapping cap.dg to other li1"
+r1134,vpp.5,"1.5 min spacing of (li1, poly, or met1/2) overlapping cap.dg to other poly"
+r1135,vpp.5,"1.5 min spacing of (li1, poly, or met1/2) overlapping cap.dg to other met1"
+r1136,vpp.5,"1.5 min spacing of (li1, poly, or met1/2) overlapping cap.dg to other met2"
+r1137,vpp.5a,0.25 max PD ratio of met3.dg to capacitor.dg
+r1138,vpp.5b,0.3 max PD ratio of met4.dg to capacitor.dg
+r1139,vpp.5c,0.4 max PD ratio of met5.dg to capacitor.dg
+r1140,vpp.10,capacitors are not allow to overlap
+r1141,vpp.11,0.87 Minimum vpp_over_MOSCAP density over related gate
+r1142,vpp.12a,capacitor in sky130rf2_xcmvpp8p6x7p9_m3_lim5shield must overlap only 9.0 met4 2.01x2.01 polygons
+r1143,vpp.12b,capacitor in sky130rf2_xcmvpp11p5x11p7_m3_lim5shield must overlap only 16.0 met4 2.01x2.01 polygons
+r1144,vpp.12c,capacitor in sky130rf2_xcmvpp4p4x4p6_m3_lim5shield must overlap only 4.0 met4 1.5x1.5 polygons
+r1145,vpp.1,1.43 min. width of capacitor
+r1146,vpp.1b,11.35 max. width of vpp_1b_err
+r1147,vpp.1c,vppM3shieldA should be rectangular
+r1148,vpp.1c,3.88 min. width of vppM3shieldA
+r1149,vpp.1c,3.88 max. length of vppM3shieldA
+r1150,vpp.3,vpp3NotXmt must not overlap poly
+r1151,vpp.4,capacitor must not straddle nwell
+r1152,vpp.4,capacitor must not straddle dnwell
+r1153,vpp.8,1.5 min. enclosure of capacitor by nwell
+r1154,vpp.9,1.5 min. spacing of capacitor & nwell
+r1155,vhvi.vhv.5,diffusion not in drain-extended devices must not be connected to VHVSrcDrn
+r1156,vhvi.1,0.02 min. width of vhvi
+r1157,vhvi.2,vhvi must not overlap areaid.ce
+r1158,vhvi.3,VHVGate must overlap hvi
+r1159,vhvi.4,poly connected to same net as VHVsourcedrain must be tagged by vhvi
+r1160,vhvi.5,vhvi must not straddle VHVSrcDrn
+r1161,vhvi.6,vhvi overlapping VHVSrcDrn must not overlap poly
+r1162,vhvi.7,vhvi must not straddle VHVPoly
+r1163,vhvi.8,11.24 min. spacing of VHVnwell & VHVnwellNoConn
+r1164,hv.diff.1a,Min space between hv_srcdrn and hv_srcdrn/diff for edges not butting tap is 0.3
+r1165,hv.diff.1b,0.3 min. spacing of diffResButtHV & diff
+r1166,hv.diff.1b,0.3 min. spacing of diffDiodeHV & diff
+r1167,hv.diff.2,0.43 min. spacing of nwellConHVdiff & ndiff (not for source of drain extended device)
+r1168,hv.diff.3a,0.55 min. spacing of HVnSrcDrn & nwell
+r1169,hv.diff.3b,0.55 min. spacing of diffResButtHV & nwell
+r1170,hv.diff.3b,0.55 min. spacing of diffDiodeHV & nwell
+r1171,hv.poly.1,hv poly can be drawn over only one diff
+r1172,hv.poly.1,hvPolyExmpt must not straddle nwell
+r1173,hv.poly.1,hvpoly cannot cross nwell boundary (except nwell hole edge
+r1174,hv.poly.2,0.3 min. spacing of hvPolyExmpt & unrelDiff
+r1175,hv.poly.3,0.55 min. spacing of hvPolyExmpt2 & nwell
+r1176,hv.poly.4,0.3 min. enclosure of hvPolyExmpt2 by nwell
+r1177,hv.poly.6a,0.16 min extension of poly beyond hv gate is
+r1178,hv.poly.6b,0.16 min extension of hvpoly beyond gate
+r1179,x.22,Floating poly_float or poly_tie text not over poly
+r1180,x.22,poly marked with poly_float not floating
+r1181,x.22,Nets on poly is floating
+r1182,x.22,Metal on poly is texted as both tied and floating (IP Level)
+r1183,x.22,Floating li1_float or li1_tie text not over li1
+r1184,x.22,li1 marked with li1_float not floating
+r1185,x.22,Nets on li1 is floating
+r1186,x.22,Metal on li1 is texted as both tied and floating (IP Level)
+r1187,x.22,Floating m1_float or m1_tie text not over met1
+r1188,x.22,met1 marked with m1_float not floating
+r1189,x.22,Nets on met1 is floating
+r1190,x.22,Metal on met1 is texted as both tied and floating (IP Level)
+r1191,x.22,Floating m2_float or m2_tie text not over met2
+r1192,x.22,met2 marked with m2_float not floating
+r1193,x.22,Nets on met2 is floating
+r1194,x.22,Metal on met2 is texted as both tied and floating (IP Level)
+r1195,x.22,Floating m3_float or m3_tie text not over met3
+r1196,x.22,met3 marked with m3_float not floating
+r1197,x.22,Nets on met3 is floating
+r1198,x.22,Metal on met3 is texted as both tied and floating (IP Level)
+r1199,x.22,Floating m4_float or m4_tie text not over met4
+r1200,x.22,met4 marked with m4_float not floating
+r1201,x.22,Nets on met4 is floating
+r1202,x.22,Metal on met4 is texted as both tied and floating (IP Level)
+r1203,x.22,Floating m5_float or m5_tie text not over met5
+r1204,x.22,met5 marked with m5_float not floating
+r1205,x.22,Nets on met5 is floating
+r1206,x.22,Metal on met5 is texted as both tied and floating (IP Level)
+r1207,x.24,condiode label must be in isolated pwell
+r1208,pad.20,"met1 shielding pad, must not float"
+r1209,pad.20,"met1 shielding pad, must not connected to pad"
+r1210,m1.x.1,<70% metal density when 700x700 window 100% covered by mm1.waffledrop
+r1211,m1.x.1,<65% metal density when 700x700 window 80-100% covered by mm1.waffledrop
+r1212,m1.x.1,<60% metal density when 700x700 window 60-80% covered by mm1.waffledrop
+r1213,m1.x.1,<50% metal density when 700x700 window 50-60% covered by mm1.waffledrop
+r1214,m1.x.1,<40% metal density when 700x700 window 40-50% covered by mm1.waffledrop
+r1215,m1.x.1,<30% metal density when 700x700 window 30-40% covered by mm1.waffledrop
+r1216,m2.x.1,<70% metal density when 700x700 window 100% covered by mm2.waffledrop
+r1217,m2.x.1,<65% metal density when 700x700 window 80-100% covered by mm2.waffledrop
+r1218,m2.x.1,<60% metal density when 700x700 window 60-80% covered by mm2.waffledrop
+r1219,m2.x.1,<50% metal density when 700x700 window 50-60% covered by mm2.waffledrop
+r1220,m2.x.1,<40% metal density when 700x700 window 40-50% covered by mm2.waffledrop
+r1221,m2.x.1,<30% metal density when 700x700 window 30-40% covered by mm2.waffledrop
+r1222,m3.x.1,<70% metal density when 700x700 window 100% covered by mm3.waffledrop
+r1223,m3.x.1,<65% metal density when 700x700 window 80-100% covered by mm3.waffledrop
+r1224,m3.x.1,<60% metal density when 700x700 window 60-80% covered by mm3.waffledrop
+r1225,m3.x.1,<50% metal density when 700x700 window 50-60% covered by mm3.waffledrop
+r1226,m3.x.1,<40% metal density when 700x700 window 40-50% covered by mm3.waffledrop
+r1227,m3.x.1,<30% metal density when 700x700 window 30-40% covered by mm3.waffledrop
+r1228,m4.x.1,<70% metal density when 700x700 window 100% covered by mm4.waffledrop
+r1229,m4.x.1,<65% metal density when 700x700 window 80-100% covered by mm4.waffledrop
+r1230,m4.x.1,<60% metal density when 700x700 window 60-80% covered by mm4.waffledrop
+r1231,m4.x.1,<50% metal density when 700x700 window 50-60% covered by mm4.waffledrop
+r1232,m4.x.1,<40% metal density when 700x700 window 40-50% covered by mm4.waffledrop
+r1233,m4.x.1,<30% metal density when 700x700 window 30-40% covered by mm4.waffledrop
+r1234,metblk.1,0.14 min. spacing of met1 & met1Block
+r1235,metblk.1,met1 must not overlap met1Block
+r1236,metblk.3,0.145 min. spacing of met1Block & met1Routing
+r1237,metblk.1,0.14 min. spacing of met2 & met2Block
+r1238,metblk.1,met2 must not overlap met2Block
+r1239,metblk.3,0.145 min. spacing of met2Block & met2Routing
+r1240,metblk.1,0.3 min. spacing of met3 & met3Block
+r1241,metblk.1,met3 must not overlap met3Block
+r1242,metblk.3,0.305 min. spacing of met3Block & met3Routing
+r1243,metblk.1,0.3 min. spacing of met4 & met4Block
+r1244,metblk.1,met4 must not overlap met4Block
+r1245,metblk.3,0.305 min. spacing of met4Block & met4Routing
+r1246,metblk.1,1.6 min. spacing of met5 & met5Block
+r1247,metblk.1,met5 must not overlap met5Block
+r1248,metblk.3,1.605 min. spacing of met5Block & met5Routing
+r1249,metblk.2,0.17 min. spacing of li1 & li1Block
+r1250,metblk.2,li1 must not overlap li1Block
+r1251,metblk.4,0.17 min. spacing of li1Block & li1Routing
+r1252,metblk.6,prBoundary.boundary not allowed in layout
+r1253,metblk.7,poly.boundary not allowed in layout
+r1254,metblk.7,diff.boundary not allowed in layout
+r1255,metblk.7,tap.boundary not allowed in layout
+r1256,fomdmy.1,0.5 min. width of fomDummyDRC
+r1257,fomdmy.1a,max width of fom dummy 25.0
+r1258,fomdmy.2,0.4 min. spacing/notch of fomDummyDRC
+r1259,fomdmy.4,1 min. spacing of fomDummyDRC & SEALID
+r1260,fomdmy.4,fomDummyDRC must not overlap SEALID
+r1261,fomdmy.6,3.25 min. spacing of fomDummyDRC & fuse
+r1262,fomdmy.6,fomDummyDRC must not overlap fuse
+r1263,fomdmy.7,0.13 min. spacing of fomDummyDRC & nsdm
+r1264,fomdmy.7,fomDummyDRC must not overlap nsdm
+r1265,fomdmy.7,0.13 min. spacing of fomDummyDRC & psdm
+r1266,fomdmy.7,fomDummyDRC must not overlap psdm
+r1267,fomdmy.8,0.18 min. enclosure of fomDummyDRC by nwell
+r1268,fomdmy.9,0.34 min. spacing of fomDummyDRC & nwell
+r1269,fomdmy.10,0.43 min. enclosure of fomDummyDRC by HVnwell
+r1270,fomdmy.11,0.33 min. spacing of fomDummyDRC & HVnwell
+r1271,fomdmy.12,0.5 min. enclosure of fomDummyDRC by FRAMEID
+r1272,fomdmy.13,0.5 min. spacing of fomDummyDRC & dieCut
+r1273,rdl.1,10 min. width of rdl
+r1274,rdl.2,10 min. spacing/notch of rdl
+r1275,rdl.2,10 min. spacing/notch of rdl
+r1276,rdl.3,10.75 min. enclosure of pad by nonCSPRDL
+r1277,rdl.4,15 min. enclosure of rdl by SEALnoHoles_ORIGIN
+r1278,rdl.5,(rdl OR ccu1m.mk) in scribe must not overlap areaid.ft.
+r1279,rdl.6,19.66 min. spacing of nonCSPRDL & pad
+r1280,mf.1&2,metal4 fuse should be rectangular
+r1281,mf.1&2,0.8 min. width of metal4 fuse
+r1282,mf.1&2,0.8 max. width of metal4 fuse
+r1283,mf.1&2,7.2 min. length of metal4 fuse
+r1284,mf.1&2,7.2 max. length of metal4 fuse
+r1285,mf.3,2.75 min. spacing of target
+r1286,mf.5,0.83 max extension of met4 beyond fuse boundary
+r1287,mf.22,1.96 min. spacing of METxContact
+r1288,mf.6,3.295 min. spacing of target & met1
+r1289,mf.6,target must not overlap met1
+r1290,mf.7,3.295 min. spacing of target & li1
+r1291,mf.7,target must not overlap li1
+r1292,mf.8,2.655 min. spacing of target & poly
+r1293,mf.8,target must not overlap poly
+r1294,mf.9,2.635 min. spacing of target & tap
+r1295,mf.9,target must not overlap tap
+r1296,mf.10,3.245 min. spacing of target & diff
+r1297,mf.10,target must not overlap diff
+r1298,mf.11,3.315 min. spacing of target & nwell
+r1299,mf.11,target must not overlap nwell
+r1300,mf.19,3.295 min. spacing of target & met2
+r1301,mf.19,target must not overlap met2
+r1302,mf.12,mf.12: 2.40x0.50 size of a fuse_shield
+r1303,mf.4,3.295 min. spacing of target & METnotFUSE
+r1304,mf.13,2.195 min. spacing of target & fuseShield
+r1305,mf.14,max shield to target spacing
+r1306,mf.15a,fuseShield is allowed for non_isolated fuse edges ONLY
+r1307,mf.15b,fuseShield is required between peri metal and non isolated fuse edges
+r1308,mf.18,0.6 min&max space between fuse_shield and met4
+r1309,mf.20,only one fuse allowed per metal line
+r1310,mf.24,3.295 min. spacing of target & met5
+r1311,mf.24,target must not overlap met5
+r1312,pad.1,padPL pcells should be used for bondpad
+r1313,pad.1,padPL pcells should have text plastic to be used for bondpad
+r1314,pad.16,Hermetic package pads are not supported inthis flow
+r1315,pad.4/4a,2.7 min. enclosure of bondpadNormal by met5
+r1316,pad.5,Zero Spacing between lower level met4 ring and Advanced Bondpad
+r1317,pad.6,5 min. spacing of smallGroupingY & met5OutsidePad
+r1318,pad.7,10 min. spacing of largeGroupingY & met5OutsidePad
+r1319,pad.6,5 min. spacing of smallGroupingX & met5OutsidePad
+r1320,pad.7,10 min. spacing of largeGroupingX & met5OutsidePad
+r1321,pad.6,5 min. spacing of smallGroupingY & met4OutsidePad
+r1322,pad.7,10 min. spacing of largeGroupingY & met4OutsidePad
+r1323,pad.6,5 min. spacing of smallGroupingX & met4OutsidePad
+r1324,pad.7,10 min. spacing of largeGroupingX & met4OutsidePad
+r1325,pad.10,bondpadNormalNoprobe must not overlap met4
+r1326,pad.11,Bondpad should not have 90 degree corner
+r1327,pad.11,Bondpad should have 45 degree corner
+r1328,pad.11,Bondpad should have only 4 45 degree corner
+r1329,pad.11,Bondpad should have only 4 orthogonal edges
+r1330,pad.12,7.0 Min length of 45 degree bevel on Bond pad
+r1331,pad.13,8.8 Max length of 45 degree bevel on Bond pad
+r1332,pad.14,16.99 min. enclosure of anyPadPlastic by solid_seal
+r1333,pad.15,500.0 Max spacing between bondpad opening and edge of scribe line(outer end of seal ring)
+r1334,pad.17,1.5 min. spacing/notch of met1UndPadMetOnly
+r1335,pad.18,0.14 min width of met1 under pad metal
+r1336,pad.17,1.5 min. spacing/notch of met2UndPadMetOnly
+r1337,pad.18,0.14 min width of met2 under pad metal
+r1338,pad.17,1.5 min. spacing/notch of met3UndPadMetOnly
+r1339,pad.18,0.3 min width of met3 under pad metal
+r1340,pad.19,25 max width of met1 under pad metal
+r1341,pad.19,25 max width of met2 under pad metal
+r1342,pad.19,6 max width of met3 under pad metal
+r1343,pad.2.1,60 min width  of padPLFP in x direction
+r1344,pad.3.1,60 min length of padPLFP in y direction
+r1345,pad.4.1,60 min width  of padPLSTG in x direction
+r1346,pad.5.1,60 min length of padPLSTG in y direction
+r1347,pad.6.1,60 min width  of padPLHP in x direction
+r1348,pad.6.1,60 min length of padPLHP in y direction
+r1349,pad.6.1a,58 min width  of padPLHPcu in x direction
+r1350,pad.6.1b,60 min length of padPLHPcu in y direction
+r1351,pad.6.1a/b,58x60 min dimensions of padPLHPcu which are not within 50 of other pad
+r1352,pad.7.1,50 min width  of padPLWLBI in x direction
+r1353,pad.8.1,60 min length of padPLWLBI in y direction
+r1354,pad.2/3.1,bondpadCuPillarSz should be rectangular
+r1355,pad.2/3.1,39 min. width of bondpadCuPillarSz
+r1356,pad.2/3.1,39 max. length of bondpadCuPillarSz
+r1357,pad.1.2,8 min space of padPLFP in x direction to padPLFP/HP/STG/WLBI
+r1358,pad.2.2,15 min space of padPLHPorg in x direction to padPLHP/STG/WLBI
+r1359,pad.2.2a,7 min space of padPLHPcu in x direction to padPLHPcu/STG/WLBI
+r1360,pad.3.2,50 min space of padPLWLBI in x direction to padPLSTG/WLBI
+r1361,pad.4.2,30 min space of padPLSTG in x direction to padPLSTG
+r1362,pad.9.1,150.0um Max Width/Length of bond pad
+r1363,pad.6.2,39.8 min. spacing of padCenterSTGinDieXy
+r1364,pad.6.2,39.8 min. spacing of padCenterSTGinDieYy
+r1365,pad.5.2.4,9 min. spacing of padSTGinDieXsp & bondPadSTG
+r1366,pad.7.2.1,284 min space of padPLSTG in x direction to adjacent scribe
+r1367,pad.7.2.2,200 min space of padPLFP  in x direction to adjacent scribe
+r1368,pad.7.2.2,200 min space of padPLWLBI in x direction to adjacent scribe
+r1369,cupad.1,5 min. width of pad opening inside inductor
+r1370,cupad.2,0 min. enclosure of pad opening inside inductor by pmm
+r1371,cupad.2,pad opening inside inductor must be enclosed by pmm
+r1372,cupad.3,2.7 min. enclosure of pad opening inside inductor by met5
+r1373,cupad.3,pad opening inside inductor must be enclosed by met5
+r1374,cupad.4,10.75 min. enclosure of pmm  inside inductor by rdl
+r1375,cupad.4,pmm  inside inductor must be enclosed by rdl
+r1376,scribe.5,Wide diff >= 10.0x10.0um within 150.0 of scribe junction
+r1377,scribe.5,Wide poly >= 10.0x10.0um within 150.0 of scribe junction
+r1378,scribe.5,Wide li1 >= 10.0x10.0um within 150.0 of scribe junction
+r1379,scribe.5,Wide met1 >= 10.0x10.0um within 150.0 of scribe junction
+r1380,scribe.5,Wide met2 >= 10.0x10.0um within 150.0 of scribe junction
+r1381,scribe.5,Wide met3 >= 10.0x10.0um within 150.0 of scribe junction
+r1382,scribe.5,Wide mcon >= 10.0x10.0um within 150.0 of scribe junction
+r1383,scribe.5,Wide licon1 >= 10.0x10.0um within 150.0 of scribe junction
+r1384,scribe.5,Wide via >= 10.0x10.0um within 150.0 of scribe junction
+r1385,scribe.5,Wide via2 >= 10.0x10.0um within 150.0 of scribe junction
+r1386,scribe.5,Wide met4 >= 10.0x10.0um within 150.0 of scribe junction
+r1387,scribe.5,Wide met5 >= 10.0x10.0um within 150.0 of scribe junction
+r1388,scribe.5,Wide via3 >= 10.0x10.0um within 150.0 of scribe junction
+r1389,scribe.5,Wide via4 >= 10.0x10.0um within 150.0 of scribe junction
+r1390,scribe.5,Wide mm1mk >= 10.0x10.0um within 150.0 of scribe junction
+r1391,scribe.5,Wide mm2mk >= 10.0x10.0um within 150.0 of scribe junction
+r1392,scribe.5,Wide mm3mk >= 10.0x10.0um within 150.0 of scribe junction
+r1393,scribe.5,Wide p1mmk >= 10.0x10.0um within 150.0 of scribe junction
+r1394,scribe.5,Wide fommk >= 10.0x10.0um within 150.0 of scribe junction
+r1395,scribe.5,Wide ctm1mk >= 10.0x10.0um within 150.0 of scribe junction
+r1396,scribe.5,Wide licm1mk >= 10.0x10.0um within 150.0 of scribe junction
+r1397,scribe.5,Wide li1mmk >= 10.0x10.0um within 150.0 of scribe junction
+r1398,scribe.5,Wide vimmk >= 10.0x10.0um within 150.0 of scribe junction
+r1399,scribe.5,Wide vim2mk >= 10.0x10.0um within 150.0 of scribe junction
+r1400,scribe.5,Wide mm4mk >= 10.0x10.0um within 150.0 of scribe junction
+r1401,scribe.5,Wide mm5mk >= 10.0x10.0um within 150.0 of scribe junction
+r1402,scribe.5,Wide vim3mk >= 10.0x10.0um within 150.0 of scribe junction
+r1403,scribe.5,Wide vim4mk >= 10.0x10.0um within 150.0 of scribe junction
+r1404,scribe.6a,pad inside frame or moduleCut without text label
+r1405,scribe.6d,mconOrVia must not overlap EUTESTPAD
+r1406,scribe.6e,EUTESTPAD must be enclosed by areaid module cut AND areaid etest
+r1407,scribe.7,nwell drawn layer cannot straddle areaid:ModuleCut
+r1408,scribe.7,diff drawn layer cannot straddle areaid:ModuleCut
+r1409,scribe.7,dnwell drawn layer cannot straddle areaid:ModuleCut
+r1410,scribe.7,tap drawn layer cannot straddle areaid:ModuleCut
+r1411,scribe.7,lvtn drawn layer cannot straddle areaid:ModuleCut
+r1412,scribe.7,hvtp drawn layer cannot straddle areaid:ModuleCut
+r1413,scribe.7,hvi drawn layer cannot straddle areaid:ModuleCut
+r1414,scribe.7,tunm drawn layer cannot straddle areaid:ModuleCut
+r1415,scribe.7,poly drawn layer cannot straddle areaid:ModuleCut
+r1416,scribe.7,npc drawn layer cannot straddle areaid:ModuleCut
+r1417,scribe.7,nsdm drawn layer cannot straddle areaid:ModuleCut
+r1418,scribe.7,psdm drawn layer cannot straddle areaid:ModuleCut
+r1419,scribe.7,licon1 drawn layer cannot straddle areaid:ModuleCut
+r1420,scribe.7,li1 drawn layer cannot straddle areaid:ModuleCut
+r1421,scribe.7,mcon drawn layer cannot straddle areaid:ModuleCut
+r1422,scribe.7,met1 drawn layer cannot straddle areaid:ModuleCut
+r1423,scribe.7,via drawn layer cannot straddle areaid:ModuleCut
+r1424,scribe.7,met2 drawn layer cannot straddle areaid:ModuleCut
+r1425,scribe.7,vhvi drawn layer cannot straddle areaid:ModuleCut
+r1426,scribe.7,via2 drawn layer cannot straddle areaid:ModuleCut
+r1427,scribe.7,met3 drawn layer cannot straddle areaid:ModuleCut
+r1428,scribe.7,via3 drawn layer cannot straddle areaid:ModuleCut
+r1429,scribe.7,met4 drawn layer cannot straddle areaid:ModuleCut
+r1430,scribe.7,via4 drawn layer cannot straddle areaid:ModuleCut
+r1431,scribe.7,met5 drawn layer cannot straddle areaid:ModuleCut
+r1432,scribe.7,nsm drawn layer cannot straddle areaid:ModuleCut
+r1433,scribe.7,pad drawn layer cannot straddle areaid:ModuleCut
+r1434,scribe.7,ldntm drawn layer cannot straddle areaid:ModuleCut
+r1435,scribe.7,hvntm drawn layer cannot straddle areaid:ModuleCut
+r1436,scribe.7,pmm drawn layer cannot straddle areaid:ModuleCut
+r1437,scribe.7,pnp drawn layer cannot straddle areaid:ModuleCut
+r1438,scribe.7,capacitor drawn layer cannot straddle areaid:ModuleCut
+r1439,scribe.7,ncm drawn layer cannot straddle areaid:ModuleCut
+r1440,scribe.7,pmm2 drawn layer cannot straddle areaid:ModuleCut
+r1441,scribe.7,inductor drawn layer cannot straddle areaid:ModuleCut
+r1442,scribe.7,rdl drawn layer cannot straddle areaid:ModuleCut
+r1443,scribe.7,rpm drawn layer cannot straddle areaid:ModuleCut
+r1444,scribe.7,hvtr drawn layer cannot straddle areaid:ModuleCut
+r1445,scribe.7,ubm drawn layer cannot straddle areaid:ModuleCut
+r1446,scribe.7,bump drawn layer cannot straddle areaid:ModuleCut
+r1447,scribe.8,Etest-pad-67 and Etest-pad-35 should not exist in the same module
+r1448,scribe.9,Etest pad Width and Length is either 67.00 um or 35.00um
+r1449,scribe.10,Min/Max Spacing between Etest pad (67um*67um) with in same module should be 90.5um
+r1450,scribe.10,Min/MaxSpacing between Etest pad (67um*67um)with in same module should be 90.5um
+r1451,scribe.11,Min/Max Spacing between Etest pad (35um*35um) with in same module should be 55um
+r1452,scribe.11,Min/MaxSpacing between Etest pad (35um*35um)with in same module should be 55um
+r1453,scribe.12,7.5 min. enclosure of ETESTPAD by areaid module cut
+r1454,scribe.13,2.50um min. enclosure of Etest pad by met1
+r1455,scribe.13,2.5 min. enclosure of ETESTPAD_met1 by met1
+r1456,scribe.13,2.50um min. enclosure of Etest pad by met2
+r1457,scribe.13,2.5 min. enclosure of ETESTPAD_met2 by met2
+r1458,scribe.13,2.50um min. enclosure of Etest pad by met3
+r1459,scribe.13,2.5 min. enclosure of ETESTPAD_met3 by met3
+r1460,scribe.13,2.50um min. enclosure of Etest pad by met4
+r1461,scribe.13,2.5 min. enclosure of ETESTPAD_met4 by met4
+r1462,scribe.13,2.50um min. enclosure of Etest pad by met5
+r1463,scribe.13,2.5 min. enclosure of ETESTPAD_met5 by met5
+r1464,scribe.14,Minimum Utest pad Width and Length is 10um
+r1465,scribe.15,Min Spacing between Utest pad opening should be 15um
+r1466,scribe.16,Min Spacing between Utest pad and Etest pad opening should be 7um
+r1467,scribe.17,2.5 min. enclosure of UTESTPAD by met5
+r1468,scribe.18,Spacing of E-test pad opening to E-test pad opening in the same module must all be equal
+r1469,scribe.18,Spacing of E-test pad opening to E-test pad opening in the same module must all be equal
+r1470,scribe.19,76 min. width of realScribeLine
+r1471,scribe.20,Pad.dg is to be drawn from 3.0um from scribe edge to 13.0um from scribe edge
+r1472,scribe.21,"Scribe must not enclose pdm.dg nor pdm.mk except for etest pads, die pad rings"
+r1473,chvtpm.1,0.38 min. width of CLHVTPM
+r1474,chvtpm.2a,0.38 min. spacing/notch of CLHVTPM
+r1475,chvtpm.3,0 min. enclosure of ((LVnwell not overlapping Var_channel) NOT lvtn) by CLHVTPM
+r1476,chvtpm.4,0 min. enclosure of ((LVnwell overlapping Var_channel) AND hvtp) by CLHVTPM
+r1477,clvtnm.1,0.38 min. width of clvtnm in periphery
+r1478,clvtnm.2,0.38 min. spacing/notch of CLLVTNM
+r1479,cntm.2,0.7 min. spacing/notch of CLNTM
+r1480,cntm.1,0.84 min. width of CLNTM
+r1481,cntm.3,0 min. enclosure of nwell by CLNTM
+r1482,cntm.3,nwell must be enclosed by CLNTM
+r1483,cntm.4a,0 min. enclosure of hvitmp by CLNTM
+r1484,cntm.4a,hvitmp must be enclosed by CLNTM
+r1485,cntm.7,0 min. enclosure of ldntm by CLNTM
+r1486,cntm.7,ldntm must be enclosed by CLNTM
+r1487,chvntm.1,0.7 min. width of CLHVNTM
+r1488,chvntm.2a,0.7 min. spacing/notch of CLHVNTM
+r1489,chvntm.4,0.185 min. spacing of CLHVNTM & NDIFFnoHV
+r1490,chvntm.4,CLHVNTM must not overlap NDIFFnoHV
+r1491,chvntm.5,0.185 min. spacing of CLHVNTM & PDIFF_noENID
+r1492,chvntm.5,CLHVNTM must not overlap PDIFF_noENID
+r1493,chvntm.3,0.185 Min Enclosure of ndiff inside hvi by chvntm
+r1494,chvntm.6a,0.185 min. spacing of CLHVNTM & p+tap (except along the diff butting edge)
+r1495,chvntm.6a,CLHVNTM must not overlap ptap
+r1496,chvntm.6b,CLHVNTM must not overlap p+diff along diff butting edge (ESDnWellTap excluded)
+r1497,chvntm.7,ESDnWellTapHV must be enclosed by CLHVNTM
+s0,x.18,single mcon_NOTAreaidStdCellCore that can be doubled
+s1,x.18,single via_NOTAreaidStdCellCore that can be doubled
+s2,x.18,single via2_NOTAreaidStdCellCore that can be doubled
+s3,x.18,single via3_NOTAreaidStdCellCore that can be doubled
+s4,x.18,single via4_NOTAreaidStdCellCore that can be doubled
+s5,x.23f,ptap must not straddle localSub
+s6,x.27,partnum or partnum exclusion 'partnum_not_necessary' not present on chip
+s7,x.27,partnum*block pcell should be used instead of partnum* pcells
+s8,m2.3c,Crater: spacing matches between met2 areas with via2-to-SurfaceArea ratio >=0.05 and =< 0.032
+s9,x.22,Floating poly_float or poly_tie text not over poly
+s10,x.22,poly marked with poly_float not floating
+s11,x.22,Nets on poly is floating
+s12,x.22,Floating poly marked with poly_tie at chiplevel without connecting
+s13,x.22,Metal on poly is texted as both tied and floating (Chip level)
+s14,x.22,Floating li1_float or li1_tie text not over li1
+s15,x.22,li1 marked with li1_float not floating
+s16,x.22,Nets on li1 is floating
+s17,x.22,Floating li1 marked with li1_tie at chiplevel without connecting
+s18,x.22,Metal on li1 is texted as both tied and floating (Chip level)
+s19,x.22,Floating m1_float or m1_tie text not over met1
+s20,x.22,met1 marked with m1_float not floating
+s21,x.22,Nets on met1 is floating
+s22,x.22,Floating met1 marked with m1_tie at chiplevel without connecting
+s23,x.22,Metal on met1 is texted as both tied and floating (Chip level)
+s24,x.22,Floating m2_float or m2_tie text not over met2
+s25,x.22,met2 marked with m2_float not floating
+s26,x.22,Nets on met2 is floating
+s27,x.22,Floating met2 marked with m2_tie at chiplevel without connecting
+s28,x.22,Metal on met2 is texted as both tied and floating (Chip level)
+s29,x.22,Floating m3_float or m3_tie text not over met3
+s30,x.22,met3 marked with m3_float not floating
+s31,x.22,Nets on met3 is floating
+s32,x.22,Floating met3 marked with m3_tie at chiplevel without connecting
+s33,x.22,Metal on met3 is texted as both tied and floating (Chip level)
+s34,x.22,Floating m4_float or m4_tie text not over met4
+s35,x.22,met4 marked with m4_float not floating
+s36,x.22,Nets on met4 is floating
+s37,x.22,Floating met4 marked with m4_tie at chiplevel without connecting
+s38,x.22,Metal on met4 is texted as both tied and floating (Chip level)
+s39,x.22,Floating m5_float or m5_tie text not over met5
+s40,x.22,met5 marked with m5_float not floating
+s41,x.22,Nets on met5 is floating
+s42,x.22,Floating met5 marked with m5_tie at chiplevel without connecting
+s43,x.22,Metal on met5 is texted as both tied and floating (Chip level)
+s44,m1.x.1,<70% metal density when 700x700 window 100% covered by mm1.waffledrop
+s45,m1.x.1,<65% metal density when 700x700 window 80-100% covered by mm1.waffledrop
+s46,m1.x.1,<60% metal density when 700x700 window 60-80% covered by mm1.waffledrop
+s47,m1.x.1,<50% metal density when 700x700 window 50-60% covered by mm1.waffledrop
+s48,m1.x.1,<40% metal density when 700x700 window 40-50% covered by mm1.waffledrop
+s49,m1.x.1,<30% metal density when 700x700 window 30-40% covered by mm1.waffledrop
+s50,m2.x.1,<70% metal density when 700x700 window 100% covered by mm2.waffledrop
+s51,m2.x.1,<65% metal density when 700x700 window 80-100% covered by mm2.waffledrop
+s52,m2.x.1,<60% metal density when 700x700 window 60-80% covered by mm2.waffledrop
+s53,m2.x.1,<50% metal density when 700x700 window 50-60% covered by mm2.waffledrop
+s54,m2.x.1,<40% metal density when 700x700 window 40-50% covered by mm2.waffledrop
+s55,m2.x.1,<30% metal density when 700x700 window 30-40% covered by mm2.waffledrop
+s56,m3.x.1,<70% metal density when 700x700 window 100% covered by mm3.waffledrop
+s57,m3.x.1,<65% metal density when 700x700 window 80-100% covered by mm3.waffledrop
+s58,m3.x.1,<60% metal density when 700x700 window 60-80% covered by mm3.waffledrop
+s59,m3.x.1,<50% metal density when 700x700 window 50-60% covered by mm3.waffledrop
+s60,m3.x.1,<40% metal density when 700x700 window 40-50% covered by mm3.waffledrop
+s61,m3.x.1,<30% metal density when 700x700 window 30-40% covered by mm3.waffledrop
+s62,m4.x.1,<70% metal density when 700x700 window 100% covered by mm4.waffledrop
+s63,m4.x.1,<65% metal density when 700x700 window 80-100% covered by mm4.waffledrop
+s64,m4.x.1,<60% metal density when 700x700 window 60-80% covered by mm4.waffledrop
+s65,m4.x.1,<50% metal density when 700x700 window 50-60% covered by mm4.waffledrop
+s66,m4.x.1,<40% metal density when 700x700 window 40-50% covered by mm4.waffledrop
+s67,m4.x.1,<30% metal density when 700x700 window 30-40% covered by mm4.waffledrop
+s68,metblk.6,prBoundary.boundary not allowed in layout
+s69,metblk.7,poly.boundary not allowed in layout
+s70,metblk.7,diff.boundary not allowed in layout
+s71,metblk.7,tap.boundary not allowed in layout
+s72,chipint.1,areaid.ld not allowed within 50.0 um of ESDID
+s73,chipint.2,areaid.ij not allowed within 150.0 um of ESDID
diff --git a/docs/rules/errors.rst b/docs/rules/errors.rst
new file mode 100644
index 0000000..2b17609
--- /dev/null
+++ b/docs/rules/errors.rst
@@ -0,0 +1,11 @@
+Error Messages
+==============
+
+The :download:`messages.csv file <./errors.csv>` provides a raw description for many of
+the automated DRC rules that are checked by SkyWater as part of the acceptance
+criteria for GDS data.
+
+.. csv-table:: Table - Error Messages
+   :file: errors.csv
+   :header-rows: 1
+   :widths: 10, 10, 80
diff --git a/docs/rules/periphery-rules.rst b/docs/rules/periphery-rules.rst
new file mode 100644
index 0000000..8fcaeee
--- /dev/null
+++ b/docs/rules/periphery-rules.rst
@@ -0,0 +1,3352 @@
+.. Do **not** modify this file it is generated from the periphery.csv file
+   found in the periphery directory using the
+   ./periphery/periphery-split-csv.py script.
+.. Instead run `make rules/periphery-rules.rst` in the ./docs directory.
+
+.. list-table::
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75
+
+   * - Use
+     - Explanation
+   * -
+       .. _P:
+
+       :drc_flag:`P`
+
+     - Rule applies to periphery only (outside :drc_tag:`areaid.ce`). A corresponding core rule may or may not exist.
+   * -
+       .. _NE:
+
+       :drc_flag:`NE`
+
+     - Rule not checked for esd_nwell_tap. There are no corresponding rule for esd_nwell_tap.
+   * -
+       .. _NC:
+
+       :drc_flag:`NC`
+
+     - Rule not checked by DRC. It should be used as a guideline only.
+   * -
+       .. _TC:
+
+       :drc_flag:`TC`
+
+     - Rule not checked for cell name "*_tech_CD_top*"
+   * -
+       .. _A:
+
+       :drc_flag:`A`
+
+     - Rule documents a functionality implemented in CL algorithms and may not be checked by DRC.
+   * -
+       .. _AD:
+
+       :drc_flag:`AD`
+
+     - Rule documents a functionality implemented in CL algorithms and checked by DRC.
+   * -
+       .. _DE:
+
+       :drc_flag:`DE`
+
+     - Rule not checked for source of Drain Extended device
+   * -
+       .. _LVS:
+
+       :drc_flag:`LVS`
+
+     - Rule handled by LVS
+   * -
+       .. _F:
+
+       :drc_flag:`F`
+
+     - Rule intended for Frame only, not checked inside Die
+   * -
+       .. _DNF:
+
+       :drc_flag:`DNF`
+
+     - Drawn Not equal Final. The drawn rule does not reflect the final dimension on silicon. See table J for details.
+   * -
+       .. _RC:
+
+       :drc_flag:`RC`
+
+     - Recommended rule at the chip level, required rule at the IP level.
+   * -
+       .. _RR:
+
+       :drc_flag:`RR`
+
+     - Recommended rule at any IP level
+   * -
+       .. _AL:
+
+       :drc_flag:`AL`
+
+     - Rules applicable only to Al BE flows
+   * -
+       .. _CU:
+
+       :drc_flag:`CU`
+
+     - Rules applicable only to Cu BE flows
+   * -
+       .. _IR:
+
+       :drc_flag:`IR`
+
+     - IR drop check compering Al database and slotted Cu database for the same product (2 gds files) must be clean
+   * -
+       .. _EXEMPT:
+
+       :drc_flag:`EXEMPT`
+
+     - Rule is an exception?
+
+:drc_rule:`(x.-)`
+-----------------
+
+.. list-table:: Function: Defines General (FIXME)
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(x.1a)`
+     - p1m.md (OPC), DECA and AMKOR layers (pi1.dg, pmm.dg, rdl.dg, pi2.dg, ubm.dg, bump.dg) and mask data for p1m, met1, via, met2 must be on a grid of [mm]
+     - 
+     - 0.001
+   * - :drc_rule:`(x.1b)`
+     - Data for SKY130 layout and mask on all layers except those mentioned in 1a must be on a grid of [mm] (except inside Seal ring)
+     - 
+     - 0.005
+   * - :drc_rule:`(x.2)`
+     - Angles permitted on: diff
+     - 
+     - N/A
+   * - :drc_rule:`(x.2)`
+     - Angles permitted on: diff except for:\n- diff inside "advSeal_6um* OR cuPillarAdvSeal_6um*" pcell, \n- diff rings around the die at min total L>1000 um and W=0.3 um
+     - 
+     - n x 90
+   * - :drc_rule:`(x.2)`
+     - Angles permitted on: tap (except inside :drc_tag:`areaid.en`), poly (except for ESD flare gates or gated_npn), li1(periphery), licon1, capm, mcon, via, via2. Anchors are exempted.
+     - 
+     - n x 90
+   * - :drc_rule:`(x.2)`
+     - Angles permitted on: via3 and via4. Anchors are exempted.
+     - 
+     - n x 90
+   * - :drc_rule:`(x.2a)`
+     - Analog circuits identified by :drc_tag:`areaid.analog` to use rectangular diff and tap geometries only; that are not to be merged into more complex shapes (T's or L's)
+     - 
+     - 
+   * - :drc_rule:`(x.2c)`
+     - 45 degree angles allowed on diff, tap inside UHVI
+     - 
+     - 
+   * - :drc_rule:`(x.3)`
+     - Angles permitted on all other layers and in the seal ring for all the layers
+     - 
+     - 
+   * - :drc_rule:`(x.3a)`
+     - Angles permitted on all other layers except WLCSP layers (pmm, rdl, pmm2, ubm and bump)
+     - 
+     - n x 45
+   * - :drc_rule:`(x.4)`
+     - Electrical DR cover layout guidelines for electromigration
+     - :drc_flag:`NC`
+     - 
+   * - :drc_rule:`(x.5)`
+     - All "pin"polygons must be within the "drawing" polygons of the layer
+     - :drc_flag:`AL`
+     - 
+   * - :drc_rule:`(x.6)`
+     - All intra-layer separation checks will include a notch check
+     - 
+     - 
+   * - :drc_rule:`(x.7)`
+     - Mask layer line and space checks must be done on all layers (checked with s.x rules)
+     - :drc_flag:`NC`
+     - 
+   * - :drc_rule:`(x.8)`
+     - Use of areaid "core" layer ("coreid") must be approved by technology
+     - :drc_flag:`NC`
+     - 
+   * - :drc_rule:`(x.9)`
+     - Shapes on maskAdd or maskDrop layers ("serifs") are allowed in core only. Exempted are: \n- cfom md/mp inside "advSeal_6um* OR cuPillarAdvSeal_6um*" pcell \n- diff rings around the die at min total L>1000 um and W=0.3 um, and PMM/PDMM inside areaid:sl
+     - 
+     - 
+   * - :drc_rule:`(x.9)`
+     - Shapes on maskAdd or maskDrop layers ("serifs") are allowed in core only. PMM/PDMM inside areaid:sl are excluded.
+     - 
+     - N/A
+   * - :drc_rule:`(x.10)`
+     - Res purpose layer for (diff, poly) cannot overlap licon1
+     - 
+     - 
+   * - :drc_rule:`(x.11)`
+     - Metal fuses are drawn in met2
+     - :drc_flag:`LVS`
+     - N/A
+   * - :drc_rule:`(x.11)`
+     - Metal fuses are drawn in met3
+     - :drc_flag:`LVS`
+     - N/A
+   * - :drc_rule:`(x.11)`
+     - Metal fuses are drawn in met4
+     - :drc_flag:`LVS`
+     - 
+   * - :drc_rule:`(x.\n12a\n12b\n12c)`
+     - To comply with the minimum spacing requirement for layer X in the frame:\n- Spacing of :drc_tag:`areaid.mt` to any non-ID layer\n- Enclosure of any non-ID layer by :drc_tag:`areaid.mt`\n- Rules exempted for cells with name "*_buildspace"
+     - :drc_flag:`F`
+     - 
+   * - :drc_rule:`(x.12d)`
+     - - Spacing of :drc_tag:`areaid.mt` to huge_metX (Exempt met3.dg)
+     - :drc_flag:`F`
+     - N/A
+   * - :drc_rule:`(x.12d)`
+     - - Spacing of :drc_tag:`areaid.mt` to huge_metX (Exempt met5.dg)
+     - :drc_flag:`F`
+     - 
+   * - :drc_rule:`(x.12e)`
+     - - Enclosure of huge_metX by :drc_tag:`areaid.mt` (Exempt met3.dg)
+     - :drc_flag:`F`
+     - N/A
+   * - :drc_rule:`(x.12e)`
+     - - Enclosure of huge_metX by :drc_tag:`areaid.mt` (Exempt met5.dg)
+     - :drc_flag:`F`
+     - 
+   * - :drc_rule:`(x.13)`
+     - Spacing between features located across areaid:ce is checked by …
+     - 
+     - 
+   * - :drc_rule:`(x.14)`
+     - Width of features straddling areaid:ce is checked by …
+     - 
+     - 
+   * - :drc_rule:`(x.15a)`
+     - Drawn compatible, mask, and waffle-drop layers are allowed only inside areaid:mt (i.e., etest modules), or inside areaid:sl (i.e., between the outer and inner areaid:sl edges, but not in the die) or inside areaid:ft (i.e., frame, blankings). Exception: FOM/P1M/Metal waffle drop are allowed inside the die
+     - :drc_flag:`P`
+     - 
+   * - :drc_rule:`(x.15b)`
+     - Rule X.15a exempted for cpmm.dg inside cellnames "PadPLfp", "padPLhp", "padPLstg" and "padPLwlbi" (for the SKY130di-5r-gsmc flow)
+     - :drc_flag:`EXEMPT`
+     - 
+   * - :drc_rule:`(x.16)`
+     - Die must not overlap :drc_tag:`areaid.mt` (rule waived for test chips and exempted for cellnames "*tech_CD_*", "*_techCD_*", "lazX_*" or "lazY_*" )
+     - 
+     - 
+   * - :drc_rule:`(x.17)`
+     - All labels must be within the "drawing" polygons of the layer; This check is enabled by using switch "floating_labels"; Identifies floating labels which appear as warnings in LVS. Using this check would enable cleaner LVS run; Not a gate for tapeout
+     - 
+     - 
+   * - :drc_rule:`(x.18)`
+     - Use redundant mcon, via, via2, via3 and via4 (Locations where additional vias/contacts can be added to existing single vias/contacts will be identified by this rule).\nSingle via under :drc_tag:`areaid.core` and :drc_tag:`areaid.standarc` are excluded from the single via check
+     - :drc_flag:`RR`
+     - 
+   * - :drc_rule:`(x.19)`
+     - Lower left corner of the seal ring should be at origin i.e (0,0)
+     - 
+     - 
+   * - :drc_rule:`(x.20)`
+     - Min spacing between pins on the same layer (center to center); Check enabled by switch "IP_block"
+     - 
+     - 
+   * - :drc_rule:`(x.21)`
+     - prunde.dg is allowed only inside :drc_tag:`areaid.mt` or :drc_tag:`areaid.sc`
+     - 
+     - 
+   * - :drc_rule:`(x.22)`
+     - No floating interconnects (poly, li1, met1-met5) or capm allowed; Rule flags interconnects with no path to poly, difftap or metal pins. Exempt floating layers can be excluded using poly_float, li1_float, m1_float, m2_float, m3_float, m4_float and m5_float text labels. Also flags an error if these text labels are placed on connected layers (not floating) and if the labels are not over the appropriate metal layer.  \nIf floating interconnects need to be connected at a higher level (Parent IP or Full chip), such floating interconnects can be exempted using poly_tie, li1_tie, m1_tie, m2_tie, m3_tie, m4_tie and m5_tie text labels.\nIt is the responsibility of the IP owner and chip/product owner to communicate and agree to the node each of these texted lines is connected to, if there is any risk to how a line is tied, and to what node.\nOnly metals outside :drc_tag:`areaid.stdcell` are checked.\n
+        The following are exempt from x.22 violations: _techCD_ , inductor.dg, modulecut, capacitors and s8blerf
+        The 'notPublicCell' switch will deactivate this rule
+     - :drc_flag:`RC`
+     - 
+   * - :drc_rule:`(x.23a)`
+     - :drc_tag:`areaid.sl` must not overlap diff
+     - 
+     - N/A
+   * - :drc_rule:`(x.23b)`
+     - diff cannot straddle :drc_tag:`areaid.sl`
+     - 
+     - 
+   * - :drc_rule:`(x.23c)`
+     - :drc_tag:`areaid.sl` must not overlap tap, poly, li1 and metX
+     - 
+     - 
+   * - :drc_rule:`(x.23d)`
+     - :drc_tag:`areaid.sl` must not overlap tap, poly
+     - 
+     - N/A
+   * - :drc_rule:`(x.23e)`
+     - areaid:sl must not overlap li1 and metX for pcell "advSeal_6um"
+     - 
+     - N/A
+   * - :drc_rule:`(x.23f)`
+     - areaid:SubstrateCut (:drc_tag:`areaid.st`, local_sub) must not straddle p+ tap
+     - :drc_flag:`RR`
+     - 
+   * - :drc_rule:`(x.24)`
+     - condiode label must be in iso_pwell
+     - 
+     - 
+   * - :drc_rule:`(x.25)`
+     - pnp.dg must be only within cell name "s8rf_pnp", "s8rf_pnp5x" or "s8tesd_iref_pnp", "stk14ecx_*"
+     - 
+     - 
+   * - :drc_rule:`(x.26)`
+     - "advSeal_6um" pcell must overlap diff
+     - 
+     - 
+   * - :drc_rule:`(x.27)`
+     - If the sealring is present, then partnum is required.  To exempt the requirement, place text.dg saying "partnum_not_necessary".\n"partnum*block" pcell should be used instead of "partnum*" pcells
+     - :drc_flag:`RR`
+     - N/A
+   * - :drc_rule:`(x.28)`
+     - Min width of :drc_tag:`areaid.sl`
+     - 
+     - N/A
+   * - :drc_rule:`(x.29)`
+     - nfet must be enclosed by dnwell. Rule is checked when switch nfet_in_dnwell is turned on.
+     - 
+     - 
+
+
+.. figure:: periphery/p018-x_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(dnwell.-)`
+----------------------
+
+.. list-table:: Function: Define deep nwell for isolating pwell and noise immunity
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(dnwell.2)`
+     - Min width of deep nwell
+     - 
+     - 3.000
+   * - :drc_rule:`(dnwell.3)`
+     - Min spacing between deep nwells. Rule exempt inside UHVI.
+     - 
+     - 6.300
+   * - :drc_rule:`(dnwell.3a)`
+     - Min spacing between deep nwells on same net inside UHVI.
+     - 
+     - N/A
+   * - :drc_rule:`(dnwell.3b)`
+     - Min spacing between deep-nwells inside UHVI and deep-nwell outside UHVI
+     - 
+     - N/A
+   * - :drc_rule:`(dnwell.3c)`
+     - Min spacing between deep-nwells inside UHVI and nwell outsideUHVI
+     - 
+     - N/A
+   * - :drc_rule:`(dnwell.3d)`
+     - Min spacing between deep-nwells inside UHVI on different nets
+     - 
+     - N/A
+   * - :drc_rule:`(dnwell.4)`
+     - Dnwell can not overlap pnp:dg
+     - 
+     - 
+   * - :drc_rule:`(dnwell.5)`
+     - P+_diff can not straddle Dnwell
+     - 
+     - 
+   * - :drc_rule:`(dnwell.6)`
+     - RF NMOS must be enclosed by deep nwell (RF FETs are listed in $DESIGN/config/tech/model_set/calibre/fixed_layout_model_map of corresponding techs)
+     - 
+     - 
+
+
+.. figure:: periphery/p020-dnwell_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(nwell.-)`
+---------------------
+
+.. list-table:: Function: Define nwell implant regions
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(nwell.1)`
+     - Width of nwell
+     - 
+     - 0.840
+   * - :drc_rule:`(nwell.2a)`
+     - Spacing between two n-wells
+     - 
+     - 1.270
+   * - :drc_rule:`(nwell.2b)`
+     - Manual merge wells if less than minimum
+     - 
+     - 
+   * - :drc_rule:`(nwell.4)`
+     - All n-wells will contain metal-contacted tap  (rule checks only for licon on tap) . Rule exempted from high voltage cells inside UHVI
+     - 
+     - 
+   * - :drc_rule:`(nwell.5)`
+     - Deep nwell must be enclosed by nwell by atleast... Exempted inside UHVI or :drc_tag:`areaid.lw`
+        Nwells can merge over deep nwell if spacing too small (as in rule nwell.2)
+     - :drc_flag:`TC`
+     - 0.400
+   * - :drc_rule:`(nwell.5a)`
+     - min enclosure of nwell by dnwell inside UHVI
+     - 
+     - N/A
+   * - :drc_rule:`(nwell.5b)`
+     - nwell inside UHVI must not be on the same net as nwell outside UHVI
+     - 
+     - N/A
+   * - :drc_rule:`(nwell.6)`
+     - Min enclosure of nwell hole by deep nwell outside UHVI
+     - :drc_flag:`TC`
+     - 1.030
+   * - :drc_rule:`(nwell.7)`
+     - Min spacing between nwell and deep nwell on separate nets
+        Spacing between nwell and deep nwell on the same net is set by the sum of the rules nwell.2 and nwell.5. By default, DRC run on a cell checks for the separate-net spacing, when nwell and deep nwell nets are separate within the cell hierarchy and are joined in the upper hierarchy. To allow net names to be joined and make the same-net rule applicable in this case, the "joinNets" switch should be turned on.
+     - :drc_flag:`TC`
+     - 4.500
+
+
+.. figure:: periphery/p021-nwell_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(pwbm.-)`
+--------------------
+
+.. list-table:: Function: Define p-well block
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(pwbm.1)`
+     - Min width of pwbm.dg
+     - 
+     - N/A
+   * - :drc_rule:`(pwbm.2)`
+     - Min spacing between two pwbm.dg inside UHVI
+     - 
+     - N/A
+   * - :drc_rule:`(pwbm.3)`
+     - Min enclosure of dnwell:dg by pwbm.dg inside UHVI (exempt pwbm hole inside dnwell)
+     - 
+     - N/A
+   * - :drc_rule:`(pwbm.4)`
+     - dnwell inside UHVI must be enclosed by pwbm (exempt pwbm hole inside dnwell)
+     - 
+     - N/A
+
+
+.. figure:: periphery/p022-pwbm_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(pwdem.-)`
+---------------------
+
+.. list-table:: Function: Defines Pwdem (FIXME)
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(pwdem.1)`
+     - Min width of pwdem.dg
+     - 
+     - N/A
+   * - :drc_rule:`(pwdem.2)`
+     - Min spacing between two pwdem.dg inside UHVI on same net
+     - 
+     - N/A
+   * - :drc_rule:`(pwdem.3)`
+     - Min enclosure of pwdem:dg by pwbm.dg inside UHVI
+     - 
+     - N/A
+   * - :drc_rule:`(pwdem.4)`
+     - pwdem.dg must be enclosed by UHVI
+     - 
+     - N/A
+   * - :drc_rule:`(pwdem.5)`
+     - pwdem.dg inside UHVI must be enclosed by deep nwell
+     - 
+     - N/A
+
+
+.. figure:: periphery/p022-pwdem_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(hvtp.-)`
+--------------------
+
+.. list-table:: Function: Define Vt adjust implant region for high Vt LV PMOS; 
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(hvtp.1)`
+     - Min width of hvtp
+     - 
+     - 0.380
+   * - :drc_rule:`(hvtp.2)`
+     - Min spacing between hvtp to hvtp
+     - 
+     - 0.380
+   * - :drc_rule:`(hvtp.3)`
+     - Min enclosure of pfet by hvtp
+     - :drc_flag:`P`
+     - 0.180
+   * - :drc_rule:`(hvtp.4)`
+     - Min spacing between pfet and hvtp
+     - :drc_flag:`P`
+     - 0.180
+   * - :drc_rule:`(hvtp.5)`
+     - Min area of hvtp (um^2)
+     - 
+     - 0.265
+
+
+.. figure:: periphery/p023-hvtp_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(hvtr.-)`
+--------------------
+
+.. list-table:: Function: Define low VT adjust implant region for pmedlvtrf; 
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(hvtr.1)`
+     - Min width of hvtr
+     - 
+     - 0.380
+   * - :drc_rule:`(hvtr.2)`
+     - Min spacing between hvtp to hvtr
+     - 
+     - 0.380
+
+
+
+:drc_rule:`(lvtn.-)`
+--------------------
+
+.. list-table:: Function: Define regions to block Vt adjust implant for low Vt LV PMOS/NMOS, SONOS FETs and Native NMOS
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(lvtn.1a)`
+     - Min width of lvtn
+     - 
+     - 0.380
+   * - :drc_rule:`(lvtn.2)`
+     - Min space lvtn to lvtn
+     - 
+     - 0.380
+   * - :drc_rule:`(lvtn.3a)`
+     - Min spacing of lvtn to gate. Rule exempted inside UHVI.
+     - :drc_flag:`P`
+     - 0.180
+   * - :drc_rule:`(lvtn.3b)`
+     - Min spacing of lvtn to pfet along the S/D direction
+     - :drc_flag:`P`
+     - 0.235
+   * - :drc_rule:`(lvtn.4b)`
+     - Min enclosure of gate by lvtn. Rule exempted inside UHVI.
+     - :drc_flag:`P`
+     - 0.180
+   * - :drc_rule:`(lvtn.9)`
+     - Min spacing, no overlap, between lvtn and hvtp
+     - 
+     - 0.380
+   * - :drc_rule:`(lvtn.10)`
+     - Min enclosure of lvtn by (nwell not overlapping Var_channel) (exclude coincident edges)
+     - 
+     - 0.380
+   * - :drc_rule:`(lvtn.12)`
+     - Min spacing between lvtn and (nwell inside :drc_tag:`areaid.ce`)
+     - 
+     - 0.380
+   * - :drc_rule:`(lvtn.13)`
+     - Min area of lvtn (um^2)
+     - 
+     - 0.265
+
+
+.. figure:: periphery/p024-lvtn_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(ncm.-)`
+-------------------
+
+.. list-table:: Function: Define Vt adjust implant region for LV NMOS in the core of NVSRAM
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(ncm.X.2)`
+     - Ncm overlapping areaid:ce is checked for core rules only
+     - 
+     - 
+   * - :drc_rule:`(ncm.X.3)`
+     - Ncm overlapping core cannot overlap N+diff in periphery
+     - :drc_flag:`TC`
+     - 
+   * - :drc_rule:`(ncm.1)`
+     - Width of ncm
+     - 
+     - 0.380
+   * - :drc_rule:`(ncm.2a)`
+     - Spacing of ncm to ncm
+     - 
+     - 0.380
+   * - :drc_rule:`(ncm.2b)`
+     - Manual merge ncm if space is below minimum
+     - 
+     - 
+   * - :drc_rule:`(ncm.3)`
+     - Min enclosure of P+diff by Ncm
+     - :drc_flag:`P`
+     - 0.180
+   * - :drc_rule:`(ncm.4)`
+     - Min enclosure of P+diff within (areaid:ed AndNot areaid:de) by Ncm
+     - :drc_flag:`P`
+     - 0.180
+   * - :drc_rule:`(ncm.5)`
+     - Min space, no overlap, between ncm and (LVTN_gate) OR (diff containing lvtn)
+     - :drc_flag:`P`
+     - 0.230
+   * - :drc_rule:`(ncm.6)`
+     - Min space, no overlap, between ncm and nfet
+     - :drc_flag:`P`
+     - 0.200
+   * - :drc_rule:`(ncm.7)`
+     - Min area of ncm (um^2)
+     - 
+     - 0.265
+
+
+.. figure:: periphery/p025-ncm_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(difftap.-)`
+-----------------------
+
+.. list-table:: Function: Defines active regions and contacts to substrate
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(difftap.1)`
+     - Width of diff or tap
+     - :drc_flag:`P`
+     - 0.150
+   * - :drc_rule:`(difftap.2)`
+     - Minimum channel width (Diff And Poly) except for FETs inside :drc_tag:`areaid.sc`: Rule exempted in the SP8* flows only, for the cells listed in rule difftap.2a
+     - :drc_flag:`P`
+     - 0.420
+   * - :drc_rule:`(difftap.2a)`
+     - Minimum channel width (Diff And Poly) for cell names "s8cell_ee_plus_sseln_a", "s8cell_ee_plus_sseln_b", "s8cell_ee_plus_sselp_a", "s8cell_ee_plus_sselp_b" , "s8fpls_pl8", "s8fpls_rdrv4" , "s8fpls_rdrv4f" and "s8fpls_rdrv8"
+     - :drc_flag:`P`
+     - NA
+   * - :drc_rule:`(difftap.2b)`
+     - Minimum channel width (Diff And Poly) for FETs inside :drc_tag:`areaid.sc`
+     - :drc_flag:`P`
+     - 0.360
+   * - :drc_rule:`(difftap.3)`
+     - Spacing of diff to diff, tap to tap, or non-abutting diff to tap
+     - 
+     - 0.270
+   * - :drc_rule:`(difftap.4)`
+     - Min tap bound by one diffusion
+     - 
+     - 0.290
+   * - :drc_rule:`(difftap.5)`
+     - Min tap bound by two diffusions
+     - :drc_flag:`P`
+     - 0.400
+   * - :drc_rule:`(difftap.6)`
+     - Diff and tap are not allowed to extend beyond their abutting edge
+     - 
+     - 
+   * - :drc_rule:`(difftap.7)`
+     - Spacing of diff/tap abutting edge to a non-conciding diff or tap edge
+     - :drc_flag:`NE`
+     - 0.130
+   * - :drc_rule:`(difftap.8)`
+     - Enclosure of (p+) diffusion by N-well. Rule exempted inside UHVI.
+     - :drc_flag:`DE` :drc_flag:`NE` :drc_flag:`P`
+     - 0.180
+   * - :drc_rule:`(difftap.9)`
+     - Spacing of (n+) diffusion to N-well outside UHVI
+     - :drc_flag:`DE` :drc_flag:`NE` :drc_flag:`P`
+     - 0.340
+   * - :drc_rule:`(difftap.10)`
+     - Enclosure of (n+)  tap by N-well. Rule exempted inside UHVI.
+     - :drc_flag:`NE` :drc_flag:`P`
+     - 0.180
+   * - :drc_rule:`(difftap.11)`
+     - Spacing of (p+) tap to  N-well. Rule exempted inside UHVI.
+     - 
+     - 0.130
+   * - :drc_rule:`(difftap.12)`
+     - ESD_nwell_tap is considered shorted to the abutting diff
+     - :drc_flag:`NC`
+     - 
+
+
+.. figure:: periphery/p026-difftap_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(tunm.-)`
+--------------------
+
+.. list-table:: Function: Defines SONOS FETs 
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(tunm.1)`
+     - Min width of tunm
+     - 
+     - 0.410
+   * - :drc_rule:`(tunm.2)`
+     - Min spacing of tunm to tunm
+     - 
+     - 0.500
+   * - :drc_rule:`(tunm.3)`
+     - Extension of tunm beyond (poly and diff)
+     - 
+     - 0.095
+   * - :drc_rule:`(tunm.4)`
+     - Min spacing of tunm to (poly and diff) outside tunm
+     - 
+     - 0.095
+   * - :drc_rule:`(tunm.5)`
+     - (poly and diff) may not straddle tunm
+     - 
+     - 
+   * - :drc_rule:`(tunm.6a)`
+     - Tunm outside deep n-well is not allowed
+     - :drc_flag:`TC`
+     - 
+   * - :drc_rule:`(tunm.7)`
+     - Min tunm area
+     - 
+     - 0.672
+
+
+.. figure:: periphery/p027-tunm_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(poly.-)`
+--------------------
+
+.. list-table:: Function: Defines FET gates, interconnects and resistors
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(poly.X.1)`
+     - All FETs would be checked for W/Ls as documented in spec 001-02735  (Exempt FETs that are pruned; exempt for W/L's inside :drc_tag:`areaid.sc` and inside cell name scs8*decap* and listed in the MRGA as a decap only W/L)
+     - 
+     - 
+   * - :drc_rule:`(poly.X.1a)`
+     - Min & max dummy_poly L is equal to min L allowed for corresponding device type (exempt rule for dummy_poly in cells listed on Table H3)
+     - 
+     - 
+   * - :drc_rule:`(poly.1a)`
+     - Width of poly
+     - 
+     - 0.150
+   * - :drc_rule:`(poly.1b)`
+     - Min channel length (poly width) for pfet overlapping lvtn (exempt rule for dummy_poly in cells listed on Table H3)
+     - 
+     - 0.350
+   * - :drc_rule:`(poly.2)`
+     - Spacing of poly to poly except for poly.c2 and poly.c3; Exempt cell: sr_bltd_eq where it is same as poly.c2
+     - 
+     - 0.210
+   * - :drc_rule:`(poly.3)`
+     - Min poly resistor width
+     - 
+     - 0.330
+   * - :drc_rule:`(poly.4)`
+     - Spacing of poly on field to diff (parallel edges only)
+     - :drc_flag:`P`
+     - 0.075
+   * - :drc_rule:`(poly.5)`
+     - Spacing of poly on field to tap
+     - :drc_flag:`P`
+     - 0.055
+   * - :drc_rule:`(poly.6)`
+     - Spacing of poly on diff to abutting tap (min source)
+     - :drc_flag:`P`
+     - 0.300
+   * - :drc_rule:`(poly.7)`
+     - Extension of diff beyond poly (min drain)
+     - :drc_flag:`P`
+     - 0.250
+   * - :drc_rule:`(poly.8)`
+     - Extension of poly beyond diffusion (endcap)
+     - :drc_flag:`P`
+     - 0.130
+   * - :drc_rule:`(poly.9)`
+     - Poly resistor spacing to poly or spacing (no overlap) to diff/tap
+     - 
+     - 0.480
+   * - :drc_rule:`(poly.10)`
+     - Poly can't overlap inner corners of diff
+     - 
+     - 
+   * - :drc_rule:`(poly.11)`
+     - No 90 deg turns of poly on diff
+     - 
+     - 
+   * - :drc_rule:`(poly.12)`
+     - (Poly NOT (nwell NOT hvi)) may not overlap tap; Rule exempted for cell name "s8fgvr_n_fg2" and gated_npn and inside UHVI.
+     - :drc_flag:`P`
+     - 
+   * - :drc_rule:`(poly.15)`
+     - Poly must not overlap diff:rs
+     - 
+     - 
+
+
+.. figure:: periphery/p028-poly_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(rpm.-)`
+-------------------
+
+.. list-table:: Function: Defines p+ poly resistors
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(rpm.1a)`
+     - Min width of rpm
+     - 
+     - 1.270
+   * - :drc_rule:`(rpm.1b)`
+     - Min/Max prec_resistor width xhrpoly_0p35
+     - 
+     - 0.350
+   * - :drc_rule:`(rpm.1c)`
+     - Min/Max prec_resistor width xhrpoly_0p69
+     - 
+     - 0.690
+   * - :drc_rule:`(rpm.1d)`
+     - Min/Max prec_resistor width xhrpoly_1p41
+     - 
+     - 1.410
+   * - :drc_rule:`(rpm.1e)`
+     - Min/Max prec_resistor width xhrpoly_2p85
+     - 
+     - 2.850
+   * - :drc_rule:`(rpm.1f)`
+     - Min/Max prec_resistor width xhrpoly_5p73
+     - 
+     - 5.730
+   * - :drc_rule:`(rpm.1g)`
+     - Only 1 licon is allowed in xhrpoly_0p35 prec_resistor_terminal
+     - 
+     - 
+   * - :drc_rule:`(rpm.1h)`
+     - Only 1 licon is allowed in xhrpoly_0p69 prec_resistor_terminal
+     - 
+     - 
+   * - :drc_rule:`(rpm.1i)`
+     - Only 2 licons are allowed in xhrpoly_1p41 prec_resistor_terminal
+     - 
+     - 
+   * - :drc_rule:`(rpm.1j)`
+     - Only 4 licons are allowed in xhrpoly_2p85 prec_resistor_terminal
+     - 
+     - 
+   * - :drc_rule:`(rpm.1k)`
+     - Only 8 licons are allowed in xhrpoly_5p73 prec_resistor_terminal
+     - 
+     - 
+   * - :drc_rule:`(rpm.2)`
+     - Min spacing of rpm to rpm
+     - 
+     - 0.840
+   * - :drc_rule:`(rpm.3)`
+     - rpm must enclose prec_resistor by atleast
+     - 
+     - 0.200
+   * - :drc_rule:`(rpm.4)`
+     - prec_resistor must be enclosed by psdm by atleast
+     - 
+     - 0.110
+   * - :drc_rule:`(rpm.5)`
+     - prec_resistor must be enclosed by npc by atleast
+     - 
+     - 0.095
+   * - :drc_rule:`(rpm.6)`
+     - Min spacing, no overlap, of rpm and nsdm
+     - 
+     - 0.200
+   * - :drc_rule:`(rpm.7)`
+     - Min spacing between rpm and poly
+     - 
+     - 0.200
+   * - :drc_rule:`(rpm.8)`
+     - poly must not straddle rpm
+     - 
+     - 
+   * - :drc_rule:`(rpm.9)`
+     - Min space, no overlap, between prec_resistor and hvntm
+     - 
+     - 0.185
+   * - :drc_rule:`(rpm.10)`
+     - Min spacing of rpm to pwbm
+     - 
+     - N/A
+
+
+.. figure:: periphery/p029-rpm_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(varac.-)`
+---------------------
+
+.. list-table:: Function: Defines varactors
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(varac.1)`
+     - Min channel length (poly width) of Var_channel
+     - 
+     - 0.180
+   * - :drc_rule:`(varac.2)`
+     - Min channel width (tap width) of Var_channel
+     - 
+     - 1.000
+   * - :drc_rule:`(varac.3)`
+     - Min spacing between hvtp to Var_channel
+     - 
+     - 0.180
+   * - :drc_rule:`(varac.4)`
+     - Min spacing of licon on tap to Var_channel
+     - 
+     - 0.250
+   * - :drc_rule:`(varac.5)`
+     - Min enclosure of poly overlapping Var_channel by nwell
+     - 
+     - 0.150
+   * - :drc_rule:`(varac.6)`
+     - Min spacing between VaracTap and difftap
+     - 
+     - 0.270
+   * - :drc_rule:`(varac.7)`
+     - Nwell overlapping Var_channel must not overlap P+ diff
+     - 
+     - 
+
+
+.. figure:: periphery/p030-varac_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(photo.-)`
+---------------------
+
+.. list-table:: Function: Photo diode for sensing light
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(photo.1)`
+     - Rules dnwell.3 and nwell.5 are exempted for photoDiode
+     - 
+     - 
+   * - :drc_rule:`(photo.2)`
+     - Min/Max width of photoDiode
+     - 
+     - 3.000
+   * - :drc_rule:`(photo.3)`
+     - Min spacing between photoDiode
+     - 
+     - 5.000
+   * - :drc_rule:`(photo.4)`
+     - Min spacing between photoDiode and deep nwell
+     - 
+     - 5.300
+   * - :drc_rule:`(photo.5)`
+     - photoDiode edges must be coincident with :drc_tag:`areaid.po`
+     - 
+     - 
+   * - :drc_rule:`(photo.6)`
+     - photoDiode must be enclosed by dnwell ring
+     - 
+     - 
+   * - :drc_rule:`(photo.7)`
+     - photoDiode must be enclosed by p+ tap ring
+     - 
+     - 
+   * - :drc_rule:`(photo.8)`
+     - Min/Max width of nwell inside photoDiode
+     - 
+     - 0.840
+   * - :drc_rule:`(photo.9)`
+     - Min/Max enclosure of nwell by photoDiode
+     - 
+     - 1.080
+   * - :drc_rule:`(photo.10)`
+     - Min/Max width of tap inside photoDiode
+     - 
+     - 0.410
+
+
+.. figure:: periphery/p031-photo_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(npc.-)`
+-------------------
+
+.. list-table:: Function: Defines nitride openings to contact poly and Li1
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(npc.1)`
+     - Min width of NPC
+     - 
+     - 0.270
+   * - :drc_rule:`(npc.2)`
+     - Min spacing of NPC to NPC
+     - 
+     - 0.270
+   * - :drc_rule:`(npc.3)`
+     - Manual merge if less than minimum
+     - 
+     - 
+   * - :drc_rule:`(npc.4)`
+     - Spacing (no overlap) of NPC to Gate
+     - 
+     - 0.090
+
+
+.. figure:: periphery/p032-npc_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(n/ psd.-)`
+----------------------
+
+.. list-table:: Function: Defines opening for N+/P+ implants
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(n/ psd.1)`
+     - Width of nsdm(psdm)
+     - :drc_flag:`P`
+     - 0.380
+   * - :drc_rule:`(n/ psd.2)`
+     - Spacing of nsdm(psdm) to nsdm(psdm)
+     - :drc_flag:`P`
+     - 0.380
+   * - :drc_rule:`(n/ psd.3)`
+     - Manual merge if less than minimum
+     - 
+     - 
+   * - :drc_rule:`(n/ psd.5a)`
+     - Enclosure of diff by nsdm(psdm), except for butting edge
+     - 
+     - 0.125
+   * - :drc_rule:`(n/ psd.5b)`
+     - Enclosure of tap by nsdm(psdm), except for butting edge
+     - :drc_flag:`P`
+     - 0.125
+   * - :drc_rule:`(n/ psd.6)`
+     - Enclosure of diff/tap butting edge by nsdm (psdm)
+     - 
+     - 0.000
+   * - :drc_rule:`(n/ psd.7)`
+     - Spacing of NSDM/PSDM to opposite implant diff or tap (for non-abutting diff/tap edges)
+     - 
+     - 0.130
+   * - :drc_rule:`(n/ psd.8)`
+     - Nsdm and psdm cannot overlap diff/tap regions of opposite doping
+     - :drc_flag:`DE`
+     - 
+   * - :drc_rule:`(n/ psd.9)`
+     - Diff and tap must be enclosed by their corresponding implant layers. Rule exempted for\n- diff inside "advSeal_6um* OR cuPillarAdvSeal_6um*" pcell for SKY130P*/SP8P*/SKY130DI-5R-CSMC flows\n- diff rings around the die at min total L>1000 um and W=0.3 um\n- gated_npn \n- :drc_tag:`areaid.zer`.
+     - :drc_flag:`DE`
+     - 
+   * - :drc_rule:`(n/ psd.10a)`
+     - Min area of Nsdm (um^2)
+     - 
+     - 0.265
+   * - :drc_rule:`(n/ psd.10b)`
+     - Min area of Psdm (um^2)
+     - 
+     - 0.255
+
+
+.. figure:: periphery/p032-n_psd_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(licon.-)`
+---------------------
+
+.. list-table:: Function: Defines contacts between poly/diff/tap and Li1
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(licon.1)`
+     - Min and max L and W of licon (exempt licons inside prec_resistor)
+     - 
+     - 0.170
+   * - :drc_rule:`(licon.1b)`
+     - Min and max width of licon inside prec_resistor
+     - 
+     - 0.190
+   * - :drc_rule:`(licon.1c)`
+     - Min and max length of licon inside prec_resistor
+     - 
+     - 2.000
+   * - :drc_rule:`(licon.2)`
+     - Spacing of licon to licon
+     - :drc_flag:`P`
+     - 0.170
+   * - :drc_rule:`(licon.2b)`
+     - Min spacing between two slotted_licon (when the both the edges are 0.19um in length)
+     - 
+     - 0.350
+   * - :drc_rule:`(licon.2c)`
+     - Min spacing between two slotted_licon (except for rule licon.2b)
+     - 
+     - 0.510
+   * - :drc_rule:`(licon.2d)`
+     - Min spacing between a slotted_licon and 0.17um square licon
+     - 
+     - 0.510
+   * - :drc_rule:`(licon.3)`
+     - Only min. square licons are allowed except die seal ring where licons are (licon CD)*L
+     - 
+     - 0.170 *L
+   * - :drc_rule:`(licon.4)`
+     - Licon1 must overlap li1 and (poly or diff or tap)
+     - 
+     - 
+   * - :drc_rule:`(licon.5a)`
+     - Enclosure of licon by diff
+     - :drc_flag:`P`
+     - 0.040
+   * - :drc_rule:`(licon.5b)`
+     - Min space between tap_licon and diff-abutting tap edge
+     - :drc_flag:`P`
+     - 0.060
+   * - :drc_rule:`(licon.5c)`
+     - Enclosure of licon by diff on one of two adjacent sides
+     - :drc_flag:`P`
+     - 0.060
+   * - :drc_rule:`(licon.6)`
+     - Licon cannot straddle tap
+     - :drc_flag:`P`
+     - 
+   * - :drc_rule:`(licon.7)`
+     - Enclosure of licon by one of two adjacent edges of isolated tap
+     - :drc_flag:`P`
+     - 0.120
+   * - :drc_rule:`(licon.8)`
+     - Enclosure of poly_licon by poly
+     - :drc_flag:`P`
+     - 0.050
+   * - :drc_rule:`(licon.8a)`
+     - Enclosure of poly_licon by poly on one of two adjacent sides
+     - :drc_flag:`P`
+     - 0.080
+   * - :drc_rule:`(licon.9)`
+     - Spacing, no overlap, between poly_licon and psdm; In SKY130DIA/SKY130TMA/SKY130PIR-10 flows, the rule is checked only between (poly_licon outside rpm) and psdm
+     - :drc_flag:`P`
+     - 0.110
+   * - :drc_rule:`(licon.10)`
+     - Spacing of licon on (tap AND (nwell NOT hvi)) to Var_channel
+     - :drc_flag:`P`
+     - 0.250
+   * - :drc_rule:`(licon.11)`
+     - Spacing of licon on diff or tap to poly on diff (except for all FETs inside :drc_tag:`areaid.sc` and except s8spf-10r flow for 0.5um phv inside cell names "s8fs_gwdlvx4", "s8fs_gwdlvx8", "s8fs_hvrsw_x4", "s8fs_hvrsw8", "s8fs_hvrsw264", and "s8fs_hvrsw520" and for 0.15um nshort inside cell names "s8fs_rdecdrv", "s8fs_rdec8", "s8fs_rdec32", "s8fs_rdec264", "s8fs_rdec520")
+     - :drc_flag:`P`
+     - 0.055
+   * - :drc_rule:`(licon.11a)`
+     - Spacing of licon on diff or tap to poly on diff (for all FETs inside :drc_tag:`areaid.sc` except 0.15um phighvt)
+     - :drc_flag:`P`
+     - 0.050
+   * - :drc_rule:`(licon.11b)`
+     - Spacing of licon on diff or tap to poly on diff (for 0.15um phighvt inside :drc_tag:`areaid.sc`)
+     - :drc_flag:`P`
+     - 0.050
+   * - :drc_rule:`(licon.11c)`
+     - Spacing of licon on diff or tap to poly on diff (for 0.5um phv inside cell names "s8fs_gwdlvx4", "s8fs_gwdlvx8", "s8fs_hvrsw_x4", "s8fs_hvrsw8", "s8fs_hvrsw264", and "s8fs_hvrsw520")
+     - :drc_flag:`P`
+     - 0.040
+   * - :drc_rule:`(licon.11d)`
+     - Spacing of licon on diff or tap to poly on diff (for 0.15um nshort inside cell names "s8fs_rdecdrv", "s8fs_rdec8", "s8fs_rdec32", "s8fs_rdec264", "s8fs_rdec520")
+     - :drc_flag:`P`
+     - 0.045
+   * - :drc_rule:`(licon.12)`
+     - Max SD width without licon
+     - :drc_flag:`NC`
+     - 5.700
+   * - :drc_rule:`(licon.13)`
+     - Spacing (no overlap) of NPC to licon on diff or tap
+     - :drc_flag:`P`
+     - 0.090
+   * - :drc_rule:`(licon.14)`
+     - Spacing of poly_licon to diff or tap
+     - :drc_flag:`P`
+     - 0.190
+   * - :drc_rule:`(licon.15)`
+     - poly_licon must be enclosed by npc by…
+     - :drc_flag:`P`
+     - 0.100
+   * - :drc_rule:`(licon.16)`
+     - Every source_diff and every tap must enclose at least one licon1, including the diff/tap straddling areaid:ce. \nRule exempted inside UHVI.
+     - :drc_flag:`P`
+     - 
+   * - :drc_rule:`(licon.17)`
+     - Licons may not overlap both poly and (diff or tap)
+     - 
+     - 
+   * - :drc_rule:`(licon.18)`
+     - Npc must enclose poly_licon
+     - 
+     - 
+
+
+.. figure:: periphery/p034-licon_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(li.-.-)`
+--------------------
+
+.. list-table:: Function: Defines local interconnect to diff/tap and poly
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(li.1.-)`
+     - Width of LI (except for li.1a)
+     - :drc_flag:`P`
+     - 0.170
+   * - :drc_rule:`(li.1a.-)`
+     - Width of LI inside of cells with name s8rf2_xcmvpp_hd5_*
+     - :drc_flag:`P`
+     - 0.140
+   * - :drc_rule:`(li.2.-)`
+     - Max ratio of length to width of LI without licon or mcon
+     - :drc_flag:`NC`
+     - 10.000
+   * - :drc_rule:`(li.3.-)`
+     - Spacing of LI to LI (except for li.3a)
+     - :drc_flag:`P`
+     - 0.170
+   * - :drc_rule:`(li.3a.-)`
+     - Spacing of LI to LI inside cells with names s8rf2_xcmvpp_hd5_*
+     - :drc_flag:`P`
+     - 0.140
+   * - :drc_rule:`(li.5.-)`
+     - Enclosure of licon by one of two adjacent LI sides
+     - :drc_flag:`P`
+     - 0.080
+   * - :drc_rule:`(li.6.-)`
+     - Min area of LI
+     - :drc_flag:`P`
+     - 0.0561
+
+
+.. figure:: periphery/p035-li_dotdash_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(ct.-)`
+------------------
+
+.. list-table:: Function: Defines contact between Li1 and met1
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(ct.1)`
+     - Min and max L and W of mcon
+     - :drc_flag:`DNF`
+     - 0.170
+   * - :drc_rule:`(ct.2)`
+     - Spacing of mcon to mcon
+     - :drc_flag:`DNF`
+     - 0.190
+   * - :drc_rule:`(ct.3)`
+     - Only min. square mcons are allowed except die seal ring where mcons are…
+     - 
+     - 0.170*L
+   * - :drc_rule:`(ct.4)`
+     - Mcon must be enclosed by LI by at least …
+     - :drc_flag:`P`
+     - 0.000
+   * - :drc_rule:`(ct.irdrop.1)`
+     - For 1 <= n <= 10 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
+     - :drc_flag:`CU` :drc_flag:`IR`
+     - 0.2
+   * - :drc_rule:`(ct.irdrop.2)`
+     - For 11 <= n <= 100 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
+     - :drc_flag:`CU` :drc_flag:`IR`
+     - 0.3
+
+
+.. figure:: periphery/p035-ct_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(capm.-)`
+--------------------
+
+.. list-table:: Function: Defines MIM capacitor
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(capm.1)`
+     - Min width of capm
+     - 
+     - N/A
+   * - :drc_rule:`(capm.2a)`
+     - Min spacing of capm to capm
+     - 
+     - N/A
+   * - :drc_rule:`(capm.2b)`
+     - Minimum spacing of capacitor bottom_plate to bottom plate
+     - 
+     - N/A
+   * - :drc_rule:`(capm.3)`
+     - Minimum enclosure of capm (top_plate) by met2
+     - 
+     - N/A
+   * - :drc_rule:`(capm.4)`
+     - Min enclosure of via2 by capm
+     - 
+     - N/A
+   * - :drc_rule:`(capm.5)`
+     - Min spacing between capm and via2
+     - 
+     - N/A
+   * - :drc_rule:`(capm.6)`
+     - Maximum Aspect Ratio (Length/Width)
+     - 
+     - N/A
+   * - :drc_rule:`(capm.7)`
+     - Only rectangular capacitors are allowed
+     - 
+     - N/A
+   * - :drc_rule:`(capm.8)`
+     - Min space, no overlap, between via and capm
+     - 
+     - N/A
+   * - :drc_rule:`(capm.10)`
+     - capm must not straddle nwell, diff, tap, poly, li1 and met1 (Rule exempted for capm overlapping capm_2t.dg)
+     - :drc_flag:`TC`
+     - N/A
+   * - :drc_rule:`(capm.11)`
+     - Min spacing between capm to (met2 not overlapping capm)
+     - 
+     - N/A
+
+
+.. figure:: periphery/p036-capm_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(vpp.-)`
+-------------------
+
+.. list-table:: Function: Defines VPP capacitor
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(vpp.1)`
+     - Min width of capacitor:dg
+     - 
+     - 1.430
+   * - :drc_rule:`(vpp.1b)`
+     - Max width of capacitor:dg; Rule not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5 and vpp_with_noLi
+     - 
+     - 11.350
+   * - :drc_rule:`(vpp.1c)`
+     - Min/Max width of cell name "s8rf_xcmvpp1p8x1p8_m3shield "
+     - 
+     - 3.880
+   * - :drc_rule:`(vpp.3)`
+     - capacitor:dg must not overlap (tap or diff or poly); (one exception: Poly is allowed to overlap  vpp_with_Met3Shield and vpp_with_Met5PolyShield); (not applicable for vpp_over_Moscap or "s8rf2_xcmvppx4_2xnhvnative10x4" or vpp_with_LiShield)
+     - 
+     - 
+   * - :drc_rule:`(vpp.4)`
+     - capacitor:dg must not straddle (nwell or dnwell)
+     - 
+     - 
+   * - :drc_rule:`(vpp.5)`
+     - Min spacing between (capacitor:dg edge and (poly or li1 or met1 or met2)) to (poly or li1 or met1 or met2) on separate nets (Exempt area of the error shape less than 2.25 (um^2) and run length less than 2.0um); Rule not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5 and vpp_with_noLi
+     - 
+     - 1.500
+   * - :drc_rule:`(vpp.5a)`
+     - Max pattern density of met3.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5)
+     - 
+     - 0.25
+   * - :drc_rule:`(vpp.5b)`
+     - Max pattern density of met4.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_Met5 and vpp_over_MOSCAP)
+     - 
+     - 0.3
+   * - :drc_rule:`(vpp.5c)`
+     - Max pattern density of met5.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_Met5 and vpp_over_MOSCAP and vpp_with_noLi); (one exception: rules does apply to cell "s8rf2_xcmvpp11p5x11p7_m1m4" and "s8rf2_xcmvpp_hd5_atlas*")
+     - 
+     - 0.4
+   * - :drc_rule:`(vpp.8)`
+     - Min enclosure of capacitor:dg by nwell
+     - 
+     - 1.500
+   * - :drc_rule:`(vpp.9)`
+     - Min spacing of capacitor:dg to nwell (not applicable for vpp_over_MOSCAP)
+     - 
+     - 1.500
+   * - :drc_rule:`(vpp.10)`
+     - vpp capacitors must not overlap; Rule checks for capacitor.dg overlapping more than one pwell pin
+     - 
+     - 
+   * - :drc_rule:`(vpp.11)`
+     - Min pattern density of (poly and diff) over capacitor.dg; (vpp_over_Moscap only)
+     - 
+     - 0.87
+   * - :drc_rule:`(vpp.12a)`
+     - Number of met4 shapes inside capacitor.dg of cell "s8rf2_xcmvpp8p6x7p9_m3_lim5shield"  must overlap with size 2.01 x 2.01 (no other met4 shapes allowed)
+     - 
+     - 9.00
+   * - :drc_rule:`(vpp.12b)`
+     - Number of met4 shapes inside capacitor.dg of cell "s8rf2_xcmvpp11p5x11p7_m3_lim5shield"  must overlap with size 2.01 x 2.01 (no other met4 shapes allowed)
+     - 
+     - 16.00
+   * - :drc_rule:`(vpp.12c)`
+     - Number of met4 shapes inside capacitor.dg of cell "s8rf2_xcmvpp4p4x4p6_m3_lim5shield"  must overlap with size 1.5 x 1.5 (no other met4 shapes allowed)
+     - 
+     - 4.00
+   * - :drc_rule:`(vpp.13)`
+     - Min space of met1 to met1inside VPP capacitor
+     - :drc_flag:`CU`
+     - 0.160
+
+
+.. figure:: periphery/p037-vpp_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(m1.-)`
+------------------
+
+.. list-table:: Function: Defines first level of metal interconnects, buses etc;
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(m1.-)`
+     - Algorithm should flag errors, for met1, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm1 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. NOTE: Required for IP, Recommended for Chip-level.
+     - :drc_flag:`RC`
+     - 
+   * - :drc_rule:`(m1.1)`
+     - Width of metal1
+     - 
+     - 0.140
+   * - :drc_rule:`(m1.2)`
+     - Spacing of metal1 to metal1
+     - 
+     - 0.140
+   * - :drc_rule:`(m1.3a)`
+     - Min. spacing of features attached to or extending from huge_met1 for a distance of up to  0.280 um to metal1 (rule not checked over non-huge met1 features)
+     - 
+     - 0.280
+   * - :drc_rule:`(m1.3b)`
+     - Min. spacing of huge_met1 to metal1 excluding features checked by m1.3a
+     - 
+     - 0.280
+   * - :drc_rule:`(m1.4)`
+     - Mcon must be enclosed by Met1 by at least …(Rule exempted for cell names documented in rule m1.4a)
+     - :drc_flag:`P`
+     - 0.030
+   * - :drc_rule:`(m1.4a)`
+     - Mcon must be enclosed by Met1 by at least (for cell names "s8cell_ee_plus_sseln_a", "s8cell_ee_plus_sseln_b", "s8cell_ee_plus_sselp_a", "s8cell_ee_plus_sselp_b", "s8fpls_pl8", and "s8fs_cmux4_fm")
+     - :drc_flag:`P`
+     - 0.005
+   * - :drc_rule:`(m1.5)`
+     - Mcon must be enclosed by Met1 on one of two adjacent sides by at least …
+     - :drc_flag:`P` :drc_flag:`AL`
+     - 0.060
+   * - :drc_rule:`(m1.6)`
+     - Min metal 1 area [um2]
+     - 
+     - 0.083
+   * - :drc_rule:`(m1.7)`
+     - Min area of metal1 holes [um2]
+     - 
+     - 0.140
+   * - :drc_rule:`(m1.pd.1)`
+     - Min MM1_oxide_Pattern_density
+     - :drc_flag:`RR` :drc_flag:`AL`
+     - 0.7
+   * - :drc_rule:`(m1.pd.2a)`
+     - Rule m1.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …
+     - :drc_flag:`A` :drc_flag:`AL`
+     - 700
+   * - :drc_rule:`(m1.pd.2b)`
+     - Rule m1.pd.1 has to be checked by dividing the chip into steps of …
+     - :drc_flag:`A` :drc_flag:`AL`
+     - 70
+   * - :drc_rule:`(m1.11)`
+     - Max width of metal1after slotting
+     - :drc_flag:`CU` :drc_flag:`NC`
+     - 4.000
+   * - :drc_rule:`(m1.12)`
+     - Add slots and remove vias and contacts if met1 wider than…..
+     - :drc_flag:`CU`
+     - 3.200
+   * - :drc_rule:`(m1.13)`
+     - Max pattern density (PD) of met1
+     - :drc_flag:`CU`
+     - 0.77
+   * - :drc_rule:`(m1.14)`
+     - Met1 PD window size
+     - :drc_flag:`CU`
+     - 50.000
+   * - :drc_rule:`(m1.14a)`
+     - Met1 PD window step
+     - :drc_flag:`CU`
+     - 25.000
+
+
+.. figure:: periphery/p038-m1_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(via.-)`
+-------------------
+
+.. list-table:: Function: Defines contact between met1  and met2
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(via.1a)`
+     - Min and max L and W of via outside :drc_tag:`areaid.mt`
+     - :drc_flag:`AL`
+     - 0.150
+   * - :drc_rule:`(via.1b)`
+     - Three sizes of square Vias allowed inside areaid:mt: 0.150um, 0.230um and 0.280um
+     - :drc_flag:`AL`
+     - 
+   * - :drc_rule:`(via.2)`
+     - Spacing of via to via
+     - :drc_flag:`AL`
+     - 0.170
+   * - :drc_rule:`(via.3)`
+     - Only min. square vias are allowed except die seal ring where vias are (Via CD)*L
+     - 
+     - 0.2*L
+   * - :drc_rule:`(via.4a)`
+     - 0.150 um Via must be enclosed by Met1 by at least …
+     - 
+     - 0.055
+   * - :drc_rule:`(via.4b)`
+     - Inside :drc_tag:`areaid.mt`, 0.230 um Via must be enclosed by met1 by atleast
+     - :drc_flag:`AL`
+     - 0.030
+   * - :drc_rule:`(via.4c)`
+     - Inside :drc_tag:`areaid.mt`, 0.280 um Via must be enclosed by met1 by atleast
+     - :drc_flag:`AL`
+     - 0.000
+   * - :drc_rule:`(via.5a)`
+     - 0.150 um Via must be enclosed by Met1 on one of two adjacent sides by at least …
+     - 
+     - 0.085
+   * - :drc_rule:`(via.5b)`
+     - Inside :drc_tag:`areaid.mt`, 0.230 um Via must be enclosed by met1 on one of two adjacent sides by at least …
+     - :drc_flag:`AL`
+     - 0.060
+   * - :drc_rule:`(via.5c)`
+     - Inside :drc_tag:`areaid.mt`, 0.280 um Via must be enclosed by met1 on one of two adjacent sides by at least …
+     - :drc_flag:`AL`
+     - 0.000
+   * - :drc_rule:`(via.11)`
+     - Min and max L and W of via outside :drc_tag:`areaid.mt`
+     - :drc_flag:`CU`
+     - 0.180
+   * - :drc_rule:`(via.12)`
+     - Min spacing between vias
+     - :drc_flag:`CU`
+     - 0.130
+   * - :drc_rule:`(via.13)`
+     - Max of 5 vias within …
+     - :drc_flag:`CU`
+     - 0.350
+   * - :drc_rule:`(via.14)`
+     - 0.180 um Via must be enclosed by parallel edges of Met1 by at least …
+     - :drc_flag:`CU`
+     - 0.040
+   * - :drc_rule:`(via.irdrop.1)`
+     - For 1 <= n <= 2 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
+     - :drc_flag:`CU` :drc_flag:`IR`
+     - 0.0
+   * - :drc_rule:`(via.irdrop.2)`
+     - For 3 <= n <= 15 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
+     - :drc_flag:`CU` :drc_flag:`IR`
+     - 0.6
+   * - :drc_rule:`(via.irdrop.3)`
+     - For 16 <= n <= 30 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
+     - :drc_flag:`CU` :drc_flag:`IR`
+     - 0.8
+   * - :drc_rule:`(via.irdrop.4)`
+     - For n > 30 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
+     - :drc_flag:`CU` :drc_flag:`IR`
+     - 0.9
+
+
+.. figure:: periphery/p039-via_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(m2.-)`
+------------------
+
+.. list-table:: Function: Defines second level of metal interconnects, buses etc
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(m2.-)`
+     - Algorithm should flag errors, for met2, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm2 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. Required for IP, Recommended for Chip-level.
+     - :drc_flag:`RC`
+     - 
+   * - :drc_rule:`(m2.1)`
+     - Width of metal 2
+     - 
+     - 0.140
+   * - :drc_rule:`(m2.2)`
+     - Spacing of metal 2 to metal 2
+     - 
+     - 0.140
+   * - :drc_rule:`(m2.3a)`
+     - Min. spacing of features attached to or extending from huge_met2 for a distance of up to  0.280 um to metal2 (rule not checked over non-huge met2 features)
+     - 
+     - 0.280
+   * - :drc_rule:`(m2.3b)`
+     - Min. spacing of huge_met2 to metal2 excluding features checked by m2.3a
+     - 
+     - 0.280
+   * - :drc_rule:`(m2.3c)`
+     - Min spacing between floating_met2 with AR_met2_A >= 0.05 and AR_met2_B =< 0.032, outside areaid:sc must be greater than
+     - :drc_flag:`RR`
+     - 0.145
+   * - :drc_rule:`(m2.4)`
+     - Via must be enclosed by Met2 by at least …
+     - :drc_flag:`P` :drc_flag:`AL`
+     - 0.055
+   * - :drc_rule:`(m2.5)`
+     - Via must be enclosed by Met2 on one of two adjacent sides by at least …
+     - :drc_flag:`AL`
+     - 0.085
+   * - :drc_rule:`(m2.6)`
+     - Min metal2 area [um2]
+     - 
+     - 0.0676
+   * - :drc_rule:`(m2.7)`
+     - Min area of metal2 holes [um2]
+     - 
+     - 0.140
+   * - :drc_rule:`(m2.pd.1)`
+     - Min MM2_oxide_Pattern_density
+     - :drc_flag:`RR`
+     - 0.7
+   * - :drc_rule:`(m2.pd.2a)`
+     - Rule m2.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …
+     - :drc_flag:`A`
+     - 700
+   * - :drc_rule:`(m2.pd.2b)`
+     - Rule m2.pd.1 has to be checked by dividing the chip into steps of …
+     - :drc_flag:`A`
+     - 70
+   * - :drc_rule:`(m2.11)`
+     - Max width of metal2
+     - :drc_flag:`CU`
+     - 4.000
+   * - :drc_rule:`(m2.12)`
+     - Add slots and remove vias and contacts if met2 wider than…..
+     - :drc_flag:`CU`
+     - 3.200
+   * - :drc_rule:`(m2.13)`
+     - Max pattern density (PD) of metal2
+     - :drc_flag:`CU`
+     - 0.77
+   * - :drc_rule:`(m2.14)`
+     - Met2 PD window size
+     - :drc_flag:`CU`
+     - 50.000
+   * - :drc_rule:`(m2.14a)`
+     - Met2 PD window step
+     - :drc_flag:`CU`
+     - 25.000
+
+
+.. figure:: periphery/p040-m2_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(via2.-)`
+--------------------
+
+.. list-table:: Function: Via2 connects met2 to met3 in the SKY130T*/SKY130P*/SP8Q/SP8P* flows and met2/capm to met3 in the SKY130DI* flow.
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(via2.X.1)`
+     - Via2 connects met2 to met3 in the SKY130T*/SKY130P*/SP8Q/SP8P* flow and met2/capm to met3 in the SKY130DI* flow.
+     - 
+     - 
+   * - :drc_rule:`(via2.1a)`
+     - Min and max L and W of via2 (except for rule via2.1b/1c/1d/1e/1f)
+     - :drc_flag:`AL`
+     - 0.200
+   * - :drc_rule:`(via2.1b)`
+     - Three sizes of square Vias allowed inside areaid:mt: 0.280um, 1.2 um and 1.5 um
+     - :drc_flag:`AL`
+     - N/A
+   * - :drc_rule:`(via2.1c)`
+     - Two sizes of square Vias allowed inside areaid:mt: 1.2 um and 1.5 um
+     - :drc_flag:`AL`
+     - N/A
+   * - :drc_rule:`(via2.1d)`
+     - Four sizes of square Vias allowed inside areaid:mt: 0.2um, 0.280um, 1.2 um and 1.5 um
+     - :drc_flag:`AL`
+     - 
+   * - :drc_rule:`(via2.1e)`
+     - Three sizes of square Vias allowed inside areaid:mt: 0.8um, 1.2 um and 1.5 um
+     - :drc_flag:`AL`
+     - N/A
+   * - :drc_rule:`(via2.1f)`
+     - Two sizes of square Vias allowed outside areaid:mt: 0.8um and 1.2 um
+     - :drc_flag:`AL`
+     - N/A
+   * - :drc_rule:`(via2.2)`
+     - Spacing of via2 to via2
+     - :drc_flag:`AL`
+     - 0.200
+   * - :drc_rule:`(via2.3)`
+     - Only min. square via2s are allowed except die seal ring where via2s are (Via2 CD)*L
+     - :drc_flag:`AL`
+     - 0.2*L
+   * - :drc_rule:`(via2.4)`
+     - Via2 must be enclosed by Met2 by at least …
+     - :drc_flag:`AL`
+     - 0.040
+   * - :drc_rule:`(via2.4a)`
+     - Inside :drc_tag:`areaid.mt`, 1.5 um Via2 must be enclosed by met2 by atleast
+     - 
+     - 0.140
+   * - :drc_rule:`(via2.5)`
+     - Via2 must be enclosed by Met2 on one of two adjacent sides by at least …
+     - :drc_flag:`AL`
+     - 0.085
+   * - :drc_rule:`(via2.11)`
+     - Min and max L and W of via2
+     - :drc_flag:`CU`
+     - 0.210
+   * - :drc_rule:`(via2.12)`
+     - Min spacing between via2's
+     - :drc_flag:`CU`
+     - 0.180
+   * - :drc_rule:`(via2.13)`
+     - Min spacing between via2 rows
+     - :drc_flag:`CU`
+     - 0.200
+   * - :drc_rule:`(via2.14)`
+     - Via2 must be enclosed by met2 by atleast
+     - :drc_flag:`CU`
+     - 0.035
+   * - :drc_rule:`(via2.irdrop.1)`
+     - For 1 <= n <= 2 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
+     - :drc_flag:`CU` :drc_flag:`IR`
+     - 0.0
+   * - :drc_rule:`(via2.irdrop.2)`
+     - For 3 <= n <= 4 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
+     - :drc_flag:`CU` :drc_flag:`IR`
+     - 0.6
+   * - :drc_rule:`(via2.irdrop.3)`
+     - For 5 <= n <= 30 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
+     - :drc_flag:`CU` :drc_flag:`IR`
+     - 0.79
+
+
+.. figure:: periphery/p041-via2_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(m3.-)`
+------------------
+
+.. list-table:: Function: Defines third level of metal interconnects, buses etc
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(m3.-)`
+     - Algorithm should flag errors, for met3, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm3 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. NOTE: Required for IP, Recommended for Chip-level.
+     - :drc_flag:`RC`
+     - 
+   * - :drc_rule:`(m3.1)`
+     - Width of metal 3
+     - 
+     - 0.300
+   * - :drc_rule:`(m3.2)`
+     - Spacing of metal 3 to metal 3
+     - 
+     - 0.300
+   * - :drc_rule:`(m3.3a)`
+     - Min. spacing of features attached to or extending from huge_met3 for a distance of up to 0.480 um to metal3  (rule not checked over non-huge met3 features)
+     - 
+     - N/A
+   * - :drc_rule:`(m3.3b)`
+     - Min. spacing of huge_met3 to metal3 excluding features checked by m3.3a
+     - 
+     - N/A
+   * - :drc_rule:`(m3.3c)`
+     - Min. spacing of features attached to or extending from huge_met3 for a distance of up to 0.400 um to metal3  (rule not checked over non-huge met3 features)
+     - 
+     - 0.400
+   * - :drc_rule:`(m3.3d)`
+     - Min. spacing of huge_met3 to metal3 excluding features checked by m3.3a
+     - 
+     - 0.400
+   * - :drc_rule:`(m3.4)`
+     - Via2 must be enclosed by Met3 by at least …
+     - :drc_flag:`AL`
+     - 0.065
+   * - :drc_rule:`(m3.5)`
+     - Via2 must be enclosed by Met3 on one of two adjacent sides by at least …
+     - 
+     - N/A
+   * - :drc_rule:`(m3.5a)`
+     - Via2 must be enclosed by Met3 on all sides by at least …(Rule not checked on a layout when it satisfies both rules m3.4 and m3.5)
+     - 
+     - N/A
+   * - :drc_rule:`(m3.6)`
+     - Min area of metal3
+     - 
+     - 0.240
+   * - :drc_rule:`(m3.7)`
+     - Min area of metal3 holes [um2]
+     - :drc_flag:`CU`
+     - 0.200
+   * - :drc_rule:`(m3.pd.1)`
+     - Min MM3_oxide_Pattern_density
+     - :drc_flag:`RR`
+     - 0.7
+   * - :drc_rule:`(m3.pd.2a)`
+     - Rule m3.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …
+     - :drc_flag:`A`
+     - 700
+   * - :drc_rule:`(m3.pd.2b)`
+     - Rule m3.pd.1 has to be checked by dividing the chip into steps of …
+     - :drc_flag:`A`
+     - 70
+   * - :drc_rule:`(m3.11)`
+     - Max width of metal3
+     - :drc_flag:`CU`
+     - 4.000
+   * - :drc_rule:`(m3.12)`
+     - Add slots and remove vias and contacts if wider than…..
+     - :drc_flag:`CU`
+     - 3.200
+   * - :drc_rule:`(m3.13)`
+     - Max pattern density (PD) of metal3
+     - :drc_flag:`CU`
+     - 0.77
+   * - :drc_rule:`(m3.14)`
+     - Met3 PD window size
+     - :drc_flag:`CU`
+     - 50.000
+   * - :drc_rule:`(m3.14a)`
+     - Met3 PD window step
+     - :drc_flag:`CU`
+     - 25.000
+
+
+.. figure:: periphery/p042-m3_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(via3.-)`
+--------------------
+
+.. list-table:: Function: Via3 connects met3 to met4 in the SKY130Q*/SKY130P*/SP8Q/SP8P* flow 
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(via3.1)`
+     - Min and max L and W of via3 (except for rule via3.1a)
+     - :drc_flag:`AL`
+     - 0.200
+   * - :drc_rule:`(via3.1a)`
+     - Two sizes of square via3 allowed inside :drc_tag:`areaid.mt`: 0.200um and 0.800um
+     - :drc_flag:`AL`
+     - 
+   * - :drc_rule:`(via3.2)`
+     - Spacing of via3 to via3
+     - :drc_flag:`AL`
+     - 0.200
+   * - :drc_rule:`(via3.3)`
+     - Only min. square via3s are allowed except die seal ring where via3s are (Via3 CD)*L
+     - 
+     - 0.2*L
+   * - :drc_rule:`(via3.4)`
+     - Via3 must be enclosed by Met3 by at least …
+     - :drc_flag:`AL`
+     - 0.060
+   * - :drc_rule:`(via3.5)`
+     - Via3 must be enclosed by Met3 on one of two adjacent sides by at least …
+     - :drc_flag:`AL`
+     - 0.090
+   * - :drc_rule:`(via3.11)`
+     - Min and max L and W of via3
+     - :drc_flag:`CU`
+     - 0.210
+   * - :drc_rule:`(via3.12)`
+     - Min spacing between via2's
+     - :drc_flag:`CU`
+     - 0.180
+   * - :drc_rule:`(via3.13)`
+     - Via3 must be enclosed by Met3 by at least …
+     - :drc_flag:`CU`
+     - 0.055
+   * - :drc_rule:`(via3.14)`
+     - Min spacing between via3 rows
+     - :drc_flag:`CU`
+     - 0.350
+   * - :drc_rule:`(via3.irdrop.1)`
+     - For 1 <= n <= 2 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
+     - :drc_flag:`CU` :drc_flag:`IR`
+     - 0.0
+   * - :drc_rule:`(via3.irdrop.2)`
+     - For 3 <= n <= 15 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
+     - :drc_flag:`CU` :drc_flag:`IR`
+     - 0.6
+   * - :drc_rule:`(via3.irdrop.3)`
+     - For 16 <= n <= 30 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
+     - :drc_flag:`CU` :drc_flag:`IR`
+     - 0.8
+
+
+
+:drc_rule:`(nsm.-)`
+-------------------
+
+.. list-table:: Function: Defines Nitride Seal Mask (FIXME)
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(nsm.1)`
+     - Min. width of nsm
+     - 
+     - 3.000
+   * - :drc_rule:`(nsm.2)`
+     - Min. spacing of nsm to nsm
+     - 
+     - 4.000
+   * - :drc_rule:`(nsm.3)`
+     - Min spacing, no overlap, between NSM_keepout to diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5). Exempt the following from the check: (a) cell name "nikon*" and (b) diff ring inside :drc_tag:`areaid.sl`
+     - :drc_flag:`AL`
+     - 1.000
+   * - :drc_rule:`(nsm.3a)`
+     - Min enclosure of diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5) by :drc_tag:`areaid.ft`. Exempt the following from the check: (a) cell name "s8Fab_crntic*"  (b)  blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)
+     - 
+     - 3.000
+
+
+
+:drc_rule:`(indm.-)`
+--------------------
+
+.. list-table:: Function: Defines third level of metal interconnects, buses and inductor; top_indmMetal is met3 for SKY130D* flows; Similarly top_padVia is Via2 for SKY130D*
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(indm.1)`
+     - Min width of top_indmMetal
+     - 
+     - N/A
+   * - :drc_rule:`(indm.2)`
+     - Min spacing between two top_indmMetal
+     - 
+     - N/A
+   * - :drc_rule:`(indm.3)`
+     - top_padVia must  be enclosed by top_indmMetal by atleast
+     - 
+     - N/A
+
+
+.. figure:: periphery/p043-indm_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(m4.-)`
+------------------
+
+.. list-table:: Function: Defines Fourth level of metal interconnects;
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(m4.-)`
+     - Algorithm should flag errors, for met4, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm4 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. Required for IP, Recommended for Chip-level.
+     - :drc_flag:`RC`
+     - 
+   * - :drc_rule:`(m4.1)`
+     - Min width of met4
+     - 
+     - 0.300
+   * - :drc_rule:`(m4.2)`
+     - Min spacing between two met4
+     - 
+     - 0.300
+   * - :drc_rule:`(m4.3)`
+     - via3 must  be enclosed by met4 by atleast
+     - :drc_flag:`AL`
+     - 0.065
+   * - :drc_rule:`(m4.4)`
+     - Min area of met4 (rule exempted for probe pads which are exactly 1.42um by 1.42um)
+     - 
+     - N/A
+   * - :drc_rule:`(m4.4a)`
+     - Min area of met4
+     - 
+     - 0.240
+   * - :drc_rule:`(m4.5a)`
+     - Min. spacing of features attached to or extending from huge_met4 for a distance of up to  0.400 um to metal4 (rule not checked over non-huge met4 features)
+     - 
+     - 0.400
+   * - :drc_rule:`(m4.5b)`
+     - Min. spacing of huge_met4 to metal4 excluding features checked by m4.5a
+     - 
+     - 0.400
+   * - :drc_rule:`(m4.7)`
+     - Min area of meta4 holes [um2]
+     - :drc_flag:`CU`
+     - 0.200
+   * - :drc_rule:`(m4.pd.1)`
+     - Min MM4_oxide_Pattern_density
+     - :drc_flag:`RR`
+     - 0.7
+   * - :drc_rule:`(m4.pd.2a)`
+     - Rule m4.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …
+     - :drc_flag:`A`
+     - 700
+   * - :drc_rule:`(m4.pd.2b)`
+     - Rule m4.pd.1 has to be checked by dividing the chip into steps of …
+     - :drc_flag:`A`
+     - 70
+   * - :drc_rule:`(m4.11)`
+     - Max width of metal4
+     - :drc_flag:`CU`
+     - 10.000
+   * - :drc_rule:`(m4.12)`
+     - Add slots and remove vias and contacts if wider than…..
+     - :drc_flag:`CU`
+     - 10.000
+   * - :drc_rule:`(m4.13)`
+     - Max pattern density (PD) of metal4; met4 overlapping pdm areas are excluded from the check
+     - :drc_flag:`CU`
+     - 0.77
+   * - :drc_rule:`(m4.14)`
+     - Met4 PD window size
+     - :drc_flag:`CU`
+     - 50.000
+   * - :drc_rule:`(m4.14a)`
+     - Met4 PD window step
+     - :drc_flag:`CU`
+     - 25.000
+   * - :drc_rule:`(m4.15)`
+     - Via3 must be enclosed by met4 by at least…
+     - :drc_flag:`CU`
+     - 0.060
+
+
+.. figure:: periphery/p044-m4_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(via4.-)`
+--------------------
+
+.. list-table:: Function: Via4 connects met4 to met5 in the SKY130P*/SP8P* flow 
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(via4.1)`
+     - Min and max L and W of via4
+     - 
+     - 0.800
+   * - :drc_rule:`(via4.2)`
+     - Spacing of via4 to via4
+     - 
+     - 0.800
+   * - :drc_rule:`(via4.3)`
+     - Only min. square via4s are allowed except die seal ring where via4s are (Via4 CD)*L
+     - 
+     - 0.8*L
+   * - :drc_rule:`(via4.4)`
+     - Via4 must be enclosed by Met4 by at least …
+     - 
+     - 0.190
+   * - :drc_rule:`(via4.irdrop.1)`
+     - For 1 <= n <= 4 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
+     - :drc_flag:`CU` :drc_flag:`IR`
+     - 0.0
+   * - :drc_rule:`(via4.irdrop.2)`
+     - For 5 <= n <= 10 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
+     - :drc_flag:`CU` :drc_flag:`IR`
+     - 0.2
+   * - :drc_rule:`(via4.irdrop.3)`
+     - For 11 <= n <= 100 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
+     - :drc_flag:`CU` :drc_flag:`IR`
+     - 0.5
+
+
+
+:drc_rule:`(m5.-)`
+------------------
+
+.. list-table:: Function: Defines Fifth level of metal interconnects;
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(m5.1)`
+     - Min width of met5
+     - 
+     - 1.600
+   * - :drc_rule:`(m5.2)`
+     - Min spacing between two met5
+     - 
+     - 1.600
+   * - :drc_rule:`(m5.3)`
+     - via4 must  be enclosed by met5 by atleast
+     - 
+     - 0.310
+
+
+
+:drc_rule:`(pad.-)`
+-------------------
+
+.. list-table:: Function: Opens the passivation
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(pad.2)`
+     - Min spacing of pad:dg to pad:dg
+     - 
+     - 1.270
+
+
+
+:drc_rule:`(rdl.-)`
+-------------------
+
+.. list-table:: Function: Defines the Cu Inductor. Connects to met5 through the pad opening
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(rdl.1)`
+     - Min width of rdl
+     - 
+     - 10
+   * - :drc_rule:`(rdl.2)`
+     - Min spacing between two rdl
+     - 
+     - 10
+   * - :drc_rule:`(rdl.3)`
+     - Min enclosure of pad by rdl, except rdl interacting with bump
+     - 
+     - 10.750
+   * - :drc_rule:`(rdl.4)`
+     - Min spacing between rdl and outer edge of the seal ring
+     - 
+     - 15.000
+   * - :drc_rule:`(rdl.5)`
+     - (rdl OR ccu1m.mk) must not overlap :drc_tag:`areaid.ft`. Exempt the following from the check: (a)  blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)
+     - 
+     - 
+
+
+
+:drc_rule:`(mf.-)`
+------------------
+
+.. note::
+
+    For SKY130D* and SKY130TM* CADflow use MM2 for Metal Fuse
+
+    For SP8P*/SKY130P* (PLM) CADflow use MM4 for Metal Fuse
+
+
+.. list-table:: Function: Defines metal fuses
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(mf.1)`
+     - Min. and max width of fuse
+     - 
+     - 0.800
+   * - :drc_rule:`(mf.2)`
+     - Length of fuse
+     - 
+     - 7.200
+   * - :drc_rule:`(mf.3)`
+     - Spacing between centers of adjacent fuses
+     - 
+     - 2.760
+   * - :drc_rule:`(mf.4)`
+     - Spacing between center of fuse and fuse_metal (fuse shields are exempted)
+     - 
+     - 3.300
+   * - :drc_rule:`(mf.5)`
+     - Max. extension of fuse_metal beyond fuse boundary
+     - 
+     - 0.830
+   * - :drc_rule:`(mf.6)`
+     - Spacing (no overlapping) between fuse center and Metal1
+     - 
+     - 3.300
+   * - :drc_rule:`(mf.7)`
+     - Spacing (no overlapping) between fuse center and LI
+     - 
+     - 3.300
+   * - :drc_rule:`(mf.8)`
+     - Spacing (no overlapping) between fuse center and poly
+     - 
+     - 2.660
+   * - :drc_rule:`(mf.9)`
+     - Spacing (no overlapping) between fuse center and tap
+     - 
+     - 2.640
+   * - :drc_rule:`(mf.10)`
+     - Spacing (no overlapping) between fuse center and diff
+     - 
+     - 3.250
+   * - :drc_rule:`(mf.11)`
+     - Spacing (no overlapping) between fuse center and nwell
+     - 
+     - 3.320
+   * - :drc_rule:`(mf.12)`
+     - Size of  fuse_shield
+     - 
+     - 0.5x2.4
+   * - :drc_rule:`(mf.13)`
+     - Min. spacing of center of fuse to fuse_shield
+     - 
+     - 2.200
+   * - :drc_rule:`(mf.14)`
+     - Max. spacing of center of fuse to fuse_shield
+     - 
+     - 3.300
+   * - :drc_rule:`(mf.15)`
+     - Fuse_shields are only placed between periphery metal (i.e., without fuse:dg) and non-isolated edges of fuse as defined by mf.16
+     - 
+     - 
+   * - :drc_rule:`(mf.16)`
+     - The edge of a fuse is considered non-isolated if wider than or equal to mf.2 and spaced to fuse_metal by less than …
+     - 
+     - 4.000
+   * - :drc_rule:`(mf.17)`
+     - Offset between fuse_shields center and fuse center
+     - :drc_flag:`NC`
+     - 0.000
+   * - :drc_rule:`(mf.18)`
+     - Min and max space between fuse_shield and fuse_metal (opposite edges). Rule checked within 1 gridpoint.
+     - 
+     - 0.600
+   * - :drc_rule:`(mf.19)`
+     - Spacing (no overlapping) between fuse center and Metal2
+     - 
+     - 3.300
+   * - :drc_rule:`(mf.20)`
+     - Only one fuse per metal line allowed
+     - 
+     - 
+   * - :drc_rule:`(mf.21)`
+     - Min spacing , no overlap, between metal3 and fuse center
+     - 
+     - 3.300
+   * - :drc_rule:`(mf.22)`
+     - Min spacing between fuse_contact to fuse_contact
+     - 
+     - 1.960
+   * - :drc_rule:`(mf.23)`
+     - Spacing (no overlapping) between fuse center and Metal4
+     - 
+     - N/A
+   * - :drc_rule:`(mf.24)`
+     - Spacing (no overlapping) between fuse center and Metal5
+     - 
+     - 3.300
+
+
+.. figure:: periphery/p046-mf_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(hvi.-)`
+-------------------
+
+.. list-table:: Function: Defines thick oxide for high voltage devices
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(hvi.1)`
+     - Min width of Hvi
+     - :drc_flag:`P`
+     - 0.600
+   * - :drc_rule:`(hvi.2a)`
+     - Min spacing of Hvi to Hvi
+     - :drc_flag:`P`
+     - 0.700
+   * - :drc_rule:`(hvi.2b)`
+     - Manual merge if space is below minimum
+     - 
+     - 
+   * - :drc_rule:`(hvi.4)`
+     - Hvi must not overlap tunm
+     - 
+     - 
+
+
+.. figure:: periphery/p047-hvi_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(hvnwell.-)`
+-----------------------
+
+* All nwell connected to voltages greater than 1.8V must be enclosed by hvi
+* Nets connected to LV nwell or nwell overlapping hvi but connected to LV voltages (i.e 1.8V) should be tagged "lv_net" using text.dg
+* This tag should be only on Li layer
+
+.. list-table:: Function: Defines rules for HV nwell.
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(hvnwell.8)`
+     - Min space between HV_nwell  and any nwell on different nets
+     - 
+     - 2.000
+   * - :drc_rule:`(hvnwell.9)`
+     - (Nwell overlapping hvi) must be enclosed by hvi
+     - 
+     - 
+   * - :drc_rule:`(hvnwell.10)`
+     - LVnwell and HnWell should not be on the same net (for the purposes of this check, short the connectivity through resistors); Exempt HnWell with li nets tagged "lv_net" using text.dg and Hnwell connected to nwell overlapping :drc_tag:`areaid.hl`
+     - :drc_flag:`TC`
+     - 
+
+
+.. figure:: periphery/p047-hvnwell_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(hvdifftap.-)`
+-------------------------
+
+.. list-table:: Function: Defines rules for HV diff/tap
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(hvdifftap.14)`
+     - Min width of diff inside Hvi, except HV Pdiff resistors (difftap.14a)
+     - :drc_flag:`P`
+     - 0.290
+   * - :drc_rule:`(hvdifftap.14a)`
+     - Min width of diff inside Hvi, HV Pdiff resistors only
+     - :drc_flag:`P`
+     - 0.150
+   * - :drc_rule:`(hvdifftap.15a)`
+     - Min space of Hdiff to Hdiff
+     - :drc_flag:`P`
+     - 0.300
+   * - :drc_rule:`(hvdifftap.15b)`
+     - Min space of n+diff to non-abutting p+tap inside Hvi
+     - :drc_flag:`P`
+     - 0.370
+   * - :drc_rule:`(hvdifftap.16)`
+     - Min width tap butting diff on one or two sides inside Hvi (rule exempted inside UHVI)
+     - 
+     - 0.700
+   * - :drc_rule:`(hvdifftap.17)`
+     - P+ Hdiff or Pdiff inside areaid:hvnwell must be enclosed by Hv_nwell by at least ….[Rule exempted inside UHVI]
+     - :drc_flag:`DE` :drc_flag:`NE`
+     - 0.330
+   * - :drc_rule:`(hvdifftap.18)`
+     - Spacing of N+ diff to HV_nwell (rule exempted inside UHVI)
+     - :drc_flag:`DE` :drc_flag:`NE`
+     - 0.430
+   * - :drc_rule:`(hvdifftap.19)`
+     - N+ Htap must be enclosed by Hv_nwell by at least …Rule exempted inside UHVI.
+     - :drc_flag:`NE`
+     - 0.330
+   * - :drc_rule:`(hvdifftap.20)`
+     - Spacing of P+ tap to HV_nwell (Exempted for p+tap butting pwell.rs; rule exempted inside UHVI)
+     - 
+     - 0.430
+   * - :drc_rule:`(hvdifftap.21)`
+     - Diff or tap cannot straddle Hvi
+     - :drc_flag:`P`
+     - 
+   * - :drc_rule:`(hvdifftap.22)`
+     - Min enclosure of Hdiff or Htap by Hvi. Rule exempted inside UHVI.
+     - :drc_flag:`P`
+     - 0.180
+   * - :drc_rule:`(hvdifftap.23)`
+     - Space between diff or tap outside Hvi and Hvi
+     - :drc_flag:`P`
+     - 0.180
+   * - :drc_rule:`(hvdifftap.24)`
+     - Spacing of nwell to N+ Hdiff (rule exempted inside UHVI)
+     - :drc_flag:`DE` :drc_flag:`NE`
+     - 0.430
+   * - :drc_rule:`(hvdifftap.25)`
+     - Min space of N+ Hdiff inside HVI across non-abutting P+_tap
+     - :drc_flag:`NC`
+     - 1.070
+
+
+.. figure:: periphery/p048-hvdifftap_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(hvpoly.-)`
+----------------------
+
+.. list-table:: Function: Defines rules for HV poly
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(hvpoly.13)`
+     - Min width of poly over diff inside Hvi
+     - :drc_flag:`P`
+     - 0.500
+
+
+.. figure:: periphery/p049-hvpoly_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(hvntm.-)`
+---------------------
+
+.. list-table:: Function: Defines tip implants for the HV NMOS
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(hvntm.X.1 )`
+     - Hvntm can be drawn inside HVI. Drawn layer will be OR-ed with the CL and rechecked for CLDRC
+     - 
+     - 
+   * - :drc_rule:`(hvntm.1)`
+     - Width of hvntm
+     - :drc_flag:`P`
+     - 0.700
+   * - :drc_rule:`(hvntm.2)`
+     - Spacing of hvntm to hvntm
+     - :drc_flag:`P`
+     - 0.700
+   * - :drc_rule:`(hvntm.3)`
+     - Min. enclosure of (n+_diff inside Hvi) but not overlapping :drc_tag:`areaid.ce` by hvntm
+     - :drc_flag:`P`
+     - 0.185
+   * - :drc_rule:`(hvntm.4)`
+     - Space, no overlap, between n+_diff outside Hvi and hvntm
+     - :drc_flag:`P`
+     - 0.185
+   * - :drc_rule:`(hvntm.5)`
+     - Space, no overlap, between p+_diff  and hvntm
+     - :drc_flag:`P` :drc_flag:`DE`
+     - 0.185
+   * - :drc_rule:`(hvntm.6a)`
+     - Space, no overlap, between p+_tap and hvntm (except along the diff-butting edge)
+     - :drc_flag:`P`
+     - 0.185
+   * - :drc_rule:`(hvntm.6b)`
+     - Space, no overlap, between p+_tap and hvntm along the diff-butting edge
+     - :drc_flag:`P`
+     - 0.000
+   * - :drc_rule:`(hvntm.7)`
+     - hvntm must enclose ESD_nwell_tap inside hvi by atleast
+     - :drc_flag:`P`
+     - 0.000
+   * - :drc_rule:`(hvntm.9)`
+     - Hvntm must not overlap :drc_tag:`areaid.ce`
+     - 
+     - 
+
+
+.. figure:: periphery/p049-hvntm_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(denmos.-)`
+----------------------
+
+.. list-table:: Function: Defines rules for the 16V Drain extended NMOS devices
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(denmos.1)`
+     - Min width of de_nFet_gate
+     - 
+     - 1.055
+   * - :drc_rule:`(denmos.2)`
+     - Min width of de_nFet_source not overlapping poly
+     - 
+     - 0.280
+   * - :drc_rule:`(denmos.3)`
+     - Min width of de_nFet_source overlapping poly
+     - 
+     - 0.925
+   * - :drc_rule:`(denmos.4)`
+     - Min width of the de_nFet_drain
+     - 
+     - 0.170
+   * - :drc_rule:`(denmos.5)`
+     - Min/Max extension of de_nFet_source over nwell
+     - 
+     - 0.225
+   * - :drc_rule:`(denmos.6)`
+     - Min/Max spacing between de_nFet_drain and de_nFet_source
+     - 
+     - 1.585
+   * - :drc_rule:`(denmos.7)`
+     - Min channel width for de_nFet_gate
+     - 
+     - 5.000
+   * - :drc_rule:`(denmos.8)`
+     - 90 degree angles are not permitted for nwell overlapping de_nFET_drain
+     - 
+     - 
+   * - :drc_rule:`(denmos.9a)`
+     - All bevels on nwell are 45 degree, 0.43 um from corners
+     - :drc_flag:`NC`
+     - 
+   * - :drc_rule:`(denmos.9b)`
+     - All bevels on de_nFet_drain are 45 degree, 0.05 um from corners
+     - :drc_flag:`NC`
+     - 
+   * - :drc_rule:`(denmos.10)`
+     - Min enclosure of de_nFet_drain by nwell
+     - 
+     - 0.660
+   * - :drc_rule:`(denmos.11)`
+     - Min spacing between p+ tap and (nwell overlapping de_nFet_drain)
+     - 
+     - 0.860
+   * - :drc_rule:`(denmos.12)`
+     - Min spacing between nwells overlapping de_nFET_drain
+     - 
+     - 2.400
+   * - :drc_rule:`(denmos.13)`
+     - de_nFet_source must be enclosed by nsdm by
+     - 
+     - 0.130
+
+
+.. figure:: periphery/p050-denmos_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(depmos.-)`
+----------------------
+
+.. list-table:: Function: Defines rules for the 16V Drain extended NMOS devices
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(depmos.1)`
+     - Min width of de_pFet_gate
+     - 
+     - 1.050
+   * - :drc_rule:`(depmos.2)`
+     - Min width of de_pFet_source not overlapping poly
+     - 
+     - 0.280
+   * - :drc_rule:`(depmos.3)`
+     - Min width of de_pFet_source overlapping poly
+     - 
+     - 0.920
+   * - :drc_rule:`(depmos.4)`
+     - Min width of the de_pFet_drain
+     - 
+     - 0.170
+   * - :drc_rule:`(depmos.5)`
+     - Min/Max extension of de_pFet_source beyond nwell
+     - 
+     - 0.260
+   * - :drc_rule:`(depmos.6)`
+     - Min/Max spacing between de_pFet_drain and de_pFet_source
+     - 
+     - 1.190
+   * - :drc_rule:`(depmos.7)`
+     - Min channel width for de_pFet_gate
+     - 
+     - 5.000
+   * - :drc_rule:`(depmos.8)`
+     - 90 degree angles are not permitted for nwell hole overlapping de_pFET_drain
+     - 
+     - 
+   * - :drc_rule:`(depmos.9a)`
+     - All bevels on nwell hole are 45 degree, 0.43 um from corners
+     - :drc_flag:`NC`
+     - 
+   * - :drc_rule:`(depmos.9b)`
+     - All bevels on de_pFet_drain are 45 degree, 0.05 um from corners
+     - :drc_flag:`NC`
+     - 
+   * - :drc_rule:`(depmos.10)`
+     - Min enclosure of de_pFet_drain by nwell hole
+     - 
+     - 0.860
+   * - :drc_rule:`(depmos.11)`
+     - Min spacing between n+ tap and (nwell hole enclosing de_pFET_drain)
+     - 
+     - 0.660
+   * - :drc_rule:`(depmos.12)`
+     - de_pFet_source must be enclosed by psdm by
+     - 
+     - 0.130
+
+
+.. figure:: periphery/p051-depmos_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(extd.-)`
+--------------------
+
+.. list-table:: Function: Defines rules :drc_tag:`areaid.en`
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(extd.1)`
+     - Difftap cannot straddle areaid:en
+     - 
+     - 
+   * - :drc_rule:`(extd.2)`
+     - DiffTap must have 2 or 3 coincident edges with areaid:en if enclosed by areaid:en
+     - 
+     - 
+   * - :drc_rule:`(extd.3)`
+     - Poly must not be entirely overlapping difftap in areaid:en
+     - 
+     - 
+   * - :drc_rule:`(extd.4)`
+     - Only cell name "s8rf_n20vhv1*" is a valid cell name for n20vhv1 device  (Check in LVS as invalid device)
+     - 
+     - N/A
+   * - :drc_rule:`(extd.5)`
+     - Only cell name "s8rf_n20vhviso1" is a valid cell name for n20vhviso1 device  (Check in LVS as invalid device)
+     - 
+     - N/A
+   * - :drc_rule:`(extd.6)`
+     - Only cell name "s8rf_p20vhv1" is a valid cell name for p20vhv1 device  (Check in LVS as invalid device)
+     - 
+     - N/A
+   * - :drc_rule:`(extd.7)`
+     - Only cell name "s8rf_n20nativevhv1*" is a valid cell name for n20nativevhv1 device  (Check in LVS as invalid device)
+     - 
+     - N/A
+
+
+.. figure:: periphery/p052-extd_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(hv.-.-)`
+--------------------
+
+.. note::
+
+    High voltage rule apply for an operating voltage range of 5.5 - 12V; Nodes switching between 0 to 5.5V do not need to follow these rules
+
+
+.. list-table:: Function: Defines High Voltage Rules (FIXME)
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(hv.X.1)`
+     - High voltage source/drain regions must be tagged by diff:hv
+     - 
+     - 
+   * - :drc_rule:`(hv.X.3)`
+     - High voltage poly can be drawn over multiple diff regions that are ALL reverse-biased by at least 300 mV (existence of reverse-bias is not checked by the CAD flow).  It can also be drawn over multiple diffs when all sources and all drain are shorted together. In these case, the high voltage poly can be tagged with the text:dg label with a value “hv_bb”.  Exceptions to this use of the hv_bb label must be approved by technology.  Under certain bias conditions, high voltage poly tagged with hv_bb can cross an nwell boundary. The poly of the drain extended device crosses nwell by construction and can be tagged with the "hv_bb" label. Use of the hv_bb label on high voltage poly crossing an nwell boundary must be approved by technology. All high voltage poly tagged with hv_bb will not be checked to hv.poly.1, hv.poly.2, hv.poly.3 and hv.poly.4.
+     - 
+     - 
+   * - :drc_rule:`(hv.X.4)`
+     - Any piece of layout that is shorted to hv_source/drain becomes a high voltage feature.
+     - 
+     - 
+   * - :drc_rule:`(hv.X.5)`
+     - In cases where an hv poly gate abuts only low voltage source and drain, the poly gate can be tagged with the text:dg label with a value "hv_lv".  In this case, the "hv_lv" tagged poly gate and its extensions will not be checked to hv.poly.6, but is checked by rules in the poly.-.- section.  The use of the hv_lv label must be approved by technology.
+     - 
+     - 
+   * - :drc_rule:`(hv.X.6)`
+     - Nwell biased at voltages >= 7.2V must be tagged with text "shv_nwell"
+     - :drc_flag:`NC`
+     - 
+   * - :drc_rule:`(hv.nwell.1)`
+     - Min spacing of nwell tagged with text "shv_nwell" to any nwell on different nets
+     - 
+     - 2.500
+   * - :drc_rule:`(hv.diff.1a)`
+     - Minimum hv_source/drain spacing to diff for edges of hv_source/drain and diff not butting tap
+     - 
+     - 0.300
+   * - :drc_rule:`(hv.diff.1b)`
+     - Minimum spacing of (n+/p+ diff resistors and diodes) connected to hv_source/drain to diff
+     - 
+     - 0.300
+   * - :drc_rule:`(hv.diff.2)`
+     - Minimum spacing of nwell connected to hv_source/drain to n+ diff
+     - :drc_flag:`DE`
+     - 0.430
+   * - :drc_rule:`(hv.diff.3a)`
+     - Minimum n+ hv_source/drain spacing to nwell
+     - 
+     - 0.550
+   * - :drc_rule:`(hv.diff.3b)`
+     - Minimum spacing of (n+ diff resistors and diodes) connected to hv_source/drain to nwell
+     - 
+     - 0.550
+   * - :drc_rule:`(hv.poly.1)`
+     - Hv poly feature hvPoly (including hv poly resistors) can be drawn over only one diff region and is not allowed to cross nwell boundary except (1) as allowed in rule .X.3 and (2) nwell hole boundary in depmos
+     - 
+     - 
+   * - :drc_rule:`(hv.poly.2)`
+     - Min spacing of hvPoly (including hv poly resistor) on field to diff (diff butting hvPoly are excluded)
+     - 
+     - 0.300
+   * - :drc_rule:`(hv.poly.3)`
+     - Min spacing of hvPoly (including hv poly resistor) on field to n-well (exempt poly stradding nwell in a denmos/depmos)
+     - 
+     - 0.550
+   * - :drc_rule:`(hv.poly.4)`
+     - Enclosure of hvPoly (including hv poly resistor) on field by n-well (exempt poly stradding nwell in a denmos/depmos)
+     - 
+     - 0.300
+   * - :drc_rule:`(hv.poly.6a)`
+     - Min extension of poly beyond hvFET_gate (exempt poly extending beyond diff along the S/D direction in a denmos/depmos)
+     - 
+     - 0.160
+   * - :drc_rule:`(hv.poly.6b)`
+     - Extension of hv poly beyond FET_gate (including hvFET_gate; exempt poly extending beyond diff along the S/D direction in a denmos/depmos)
+     - 
+     - 0.160
+   * - :drc_rule:`(hv.poly.7)`
+     - Minimum overlap of hv poly ring_FET and diff
+     - 
+     - 
+
+
+.. figure:: periphery/p054-hv_dotdash_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(vhvi.-.-)`
+----------------------
+
+.. list-table:: Function: Identify nets working between 12-16V
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(vhvi.vhv.1)`
+     - Terminals operating at nominal 12V (maximum 16V) bias must be tagged as Very-High-Voltage (VHV) using vhvi:dg layer
+     - :drc_flag:`NC`
+     - 
+   * - :drc_rule:`(vhvi.vhv.2)`
+     - A source or drain of a drain-extended device can be tagged by vhvi:dg. A device with either source or drain (not both) tagged with vhvi:dg serves as a VHV propagation stopper
+     - :drc_flag:`NC`
+     - 
+   * - :drc_rule:`(vhvi.vhv.3)`
+     - Any feature connected to VHVSourceDrain becomes a very-high-voltage feature
+     - :drc_flag:`NC`
+     - 
+   * - :drc_rule:`(vhvi.vhv.4)`
+     - Any feature connected to VHVPoly becomes a very-high-voltage feature
+     - :drc_flag:`NC`
+     - 
+   * - :drc_rule:`(vhvi.vhv.5)`
+     - Diffusion that is not a part of a drain-extended device (i.e., diff not areaid:en) must not be on the same net as VHVSourceDrain. Only diffusion inside :drc_tag:`areaid.ed` and LV diffusion tagged with vhvi:dg are exempted.
+     - 
+     - 
+   * - :drc_rule:`(vhvi.vhv.6)`
+     - Poly resistor can act as a VHV propagation stopper. For this, it should be tagged with text "vhv_block"
+     - :drc_flag:`NC`
+     - 
+   * - :drc_rule:`(vhvi.1.-)`
+     - Min width of vhvi:dg
+     - 
+     - 0.020
+   * - :drc_rule:`(vhvi.2.-)`
+     - Vhvi:dg cannot overlap areaid:ce
+     - 
+     - 
+   * - :drc_rule:`(vhvi.3.-)`
+     - VHVGate must overlap hvi:dg
+     - 
+     - 
+   * - :drc_rule:`(vhvi.4.-)`
+     - Poly connected to the same net as a VHVSourceDrain must be tagged with vhvi:dg layer
+     - 
+     - 
+   * - :drc_rule:`(vhvi.5.-)`
+     - Vhvi:dg cannot straddle VHVSourceDrain
+     - 
+     - 
+   * - :drc_rule:`(vhvi.6.-)`
+     - Vhvi:dg overlapping VHVSourceDrain must not overlap poly
+     - 
+     - 
+   * - :drc_rule:`(vhvi.7.-)`
+     - Vhvi:dg cannot straddle VHVPoly
+     - 
+     - 
+
+
+
+:drc_rule:`(uhvi.-.-)`
+----------------------
+
+.. list-table:: Function: Identify nets working between 20V
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(uhvi.1.-)`
+     - diff/tap can not straddle UHVI
+     - 
+     - N/A
+   * - :drc_rule:`(uhvi.2.-)`
+     - poly can not straddle UHVI
+     - 
+     - N/A
+   * - :drc_rule:`(uhvi.3.-)`
+     - pwbm.dg must be enclosed by UHVI (exempt inside :drc_tag:`areaid.lw`)
+     - 
+     - N/A
+   * - :drc_rule:`(uhvi.4.-)`
+     - dnw.dg can not straddle UHVI
+     - 
+     - N/A
+   * - :drc_rule:`(uhvi.5.-)`
+     - UHVI must enclose :drc_tag:`areaid.ext`
+     - 
+     - N/A
+   * - :drc_rule:`(uhvi.6.-)`
+     - UHVI must enclose dnwell
+     - 
+     - N/A
+   * - :drc_rule:`(uhvi.7.-)`
+     - natfet.dg must be enclosed by UHVI layer by at least
+     - 
+     - N/A
+   * - :drc_rule:`(uhvi.8.-)`
+     - Minimum width of natfet.dg
+     - 
+     - N/A
+   * - :drc_rule:`(uhvi.9.-)`
+     - Minimum Space spacing of natfet.dg
+     - 
+     - N/A
+
+
+
+:drc_rule:`(ulvt-.-)`
+---------------------
+
+.. list-table:: Function: Identify dnwdiodehv_Psub(BV~60V)
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(ulvt-.1)`
+     - :drc_tag:`areaid.low_vt` must enclose dnw for the UHV dnw-psub diode texted "condiodeHvPsub"
+     - 
+     - NA
+   * - :drc_rule:`(ulvt-.2)`
+     - :drc_tag:`areaid.low_vt` must enclose pwbm.dg for the UHV dnw-psub diode texted "condiodeHvPsub"
+     - 
+     - NA
+
+
+
+:drc_rule:`(pwres.-.-)`
+-----------------------
+
+.. list-table:: Function: Identify pwell resistors
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(pwres.1.-)`
+     - Pwell resistor has to be enclosed by the res layer
+     - :drc_flag:`NC`
+     - 
+   * - :drc_rule:`(pwres.2.-)`
+     - Min/Max width of pwell resistor
+     - 
+     - 2.650
+   * - :drc_rule:`(pwres.3.-)`
+     - Min length of pwell resistor
+     - 
+     - 26.500
+   * - :drc_rule:`(pwres.4.-)`
+     - Max length of pwell resistor
+     - 
+     - 265.00
+   * - :drc_rule:`(pwres.5.-)`
+     - Min/Max spacing of tap inside the pwell resistor to nwell
+     - 
+     - 0.220
+   * - :drc_rule:`(pwres.6.-)`
+     - Min/Max width of tap inside the pwell resistor
+     - 
+     - 0.530
+   * - :drc_rule:`(pwres.7a.-)`
+     - Every pwres_terminal must enclose 12 licon1
+     - 
+     - 
+   * - :drc_rule:`(pwres.7b.-)`
+     - Every pwres_terminal must enclose 12 mcons if routed through metal1
+     - 
+     - 
+   * - :drc_rule:`(pwres.8.-)`
+     - Diff or poly is not allowed in the pwell resistor.
+     - 
+     - 
+   * - :drc_rule:`(pwres.9.-)`
+     - Nwell surrounding the pwell resistor must have a full ring of contacted tap strapped with metal.
+     - 
+     - 
+   * - :drc_rule:`(pwres.10.-)`
+     - The res layer must abut pwres_terminal on opposite and parallel edges
+     - 
+     - 
+
+
+.. figure:: periphery/p056-pwres_dotdash_dotdash.svg
+    :width: 100%
+    :align: center
+
+
+
+:drc_rule:`(rfdiode.-.-)`
+-------------------------
+
+.. list-table:: Function: Identify RF diodes; Used for RCX
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - :drc_rule:`Name`
+     - Description
+     - :drc_flag:`Flags`
+     - Value
+   * - :drc_rule:`(rfdiode.1.-)`
+     - Only 90 degrees allowed for :drc_tag:`areaid.re`
+     - 
+     - 
+   * - :drc_rule:`(rfdiode.2.-)`
+     - :drc_tag:`areaid.re` must be coincident with nwell for the rf nwell diode
+     - 
+     - 
+   * - :drc_rule:`(rfdiode.3.-)`
+     - :drc_tag:`areaid.re` must be coincident with innwer edge of the nwell ring for the rf pwell-deep nwell diode
+        Allowed PNP layout
+        Layout: pnppar
+        Allowed NPN layout
+     - 
+     - 
+
+
+.. figure:: periphery/p057-rfdiode_dotdash_dotdash.svg
+    :width: 100%
+    :align: center
+
+
diff --git a/docs/rules/periphery.rst b/docs/rules/periphery.rst
new file mode 100644
index 0000000..3d002ef
--- /dev/null
+++ b/docs/rules/periphery.rst
@@ -0,0 +1,4 @@
+Periphery Rules
+===============
+
+.. include:: periphery-rules.rst
diff --git a/docs/rules/periphery/p018-x_dotdash.csv b/docs/rules/periphery/p018-x_dotdash.csv
new file mode 100644
index 0000000..cd22507
--- /dev/null
+++ b/docs/rules/periphery/p018-x_dotdash.csv
@@ -0,0 +1,52 @@
+Name,Description,Flags,Value
+(x.1a),"p1m.md (OPC), DECA and AMKOR layers (pi1.dg, pmm.dg, rdl.dg, pi2.dg, ubm.dg, bump.dg) and mask data for p1m, met1, via, met2 must be on a grid of [mm]",,0.001
+(x.1b),Data for SKY130 layout and mask on all layers except those mentioned in 1a must be on a grid of [mm] (except inside Seal ring),,0.005
+(x.2),Angles permitted on: diff,,N/A
+(x.2),"Angles permitted on: diff except for:\n- diff inside ""advSeal_6um* OR cuPillarAdvSeal_6um*"" pcell, \n- diff rings around the die at min total L>1000 um and W=0.3 um",,n x 90
+(x.2),"Angles permitted on: tap (except inside :drc_tag:`areaid.en`), poly (except for ESD flare gates or gated_npn), li1(periphery), licon1, capm, mcon, via, via2. Anchors are exempted.",,n x 90
+(x.2),Angles permitted on: via3 and via4. Anchors are exempted.,,n x 90
+(x.2a),Analog circuits identified by :drc_tag:`areaid.analog` to use rectangular diff and tap geometries only; that are not to be merged into more complex shapes (T's or L's),,
+(x.2c),"45 degree angles allowed on diff, tap inside UHVI",,
+(x.3),Angles permitted on all other layers and in the seal ring for all the layers,,
+(x.3a),"Angles permitted on all other layers except WLCSP layers (pmm, rdl, pmm2, ubm and bump)",,n x 45
+(x.4),Electrical DR cover layout guidelines for electromigration,NC,
+(x.5),"All ""pin""polygons must be within the ""drawing"" polygons of the layer",AL,
+(x.6),All intra-layer separation checks will include a notch check,,
+(x.7),Mask layer line and space checks must be done on all layers (checked with s.x rules),NC,
+(x.8),"Use of areaid ""core"" layer (""coreid"") must be approved by technology",NC,
+(x.9),"Shapes on maskAdd or maskDrop layers (""serifs"") are allowed in core only. Exempted are: \n- cfom md/mp inside ""advSeal_6um* OR cuPillarAdvSeal_6um*"" pcell \n- diff rings around the die at min total L>1000 um and W=0.3 um, and PMM/PDMM inside areaid:sl",,
+(x.9),"Shapes on maskAdd or maskDrop layers (""serifs"") are allowed in core only. PMM/PDMM inside areaid:sl are excluded.",,N/A
+(x.10),"Res purpose layer for (diff, poly) cannot overlap licon1",,
+(x.11),Metal fuses are drawn in met2,LVS,N/A
+(x.11),Metal fuses are drawn in met3,LVS,N/A
+(x.11),Metal fuses are drawn in met4,LVS,
+(x.\n12a\n12b\n12c),"To comply with the minimum spacing requirement for layer X in the frame:\n- Spacing of :drc_tag:`areaid.mt` to any non-ID layer\n- Enclosure of any non-ID layer by :drc_tag:`areaid.mt`\n- Rules exempted for cells with name ""*_buildspace""",F,
+(x.12d),- Spacing of :drc_tag:`areaid.mt` to huge_metX (Exempt met3.dg),F,N/A
+(x.12d),- Spacing of :drc_tag:`areaid.mt` to huge_metX (Exempt met5.dg),F,
+(x.12e),- Enclosure of huge_metX by :drc_tag:`areaid.mt` (Exempt met3.dg),F,N/A
+(x.12e),- Enclosure of huge_metX by :drc_tag:`areaid.mt` (Exempt met5.dg),F,
+(x.13),Spacing between features located across areaid:ce is checked by …,,
+(x.14),Width of features straddling areaid:ce is checked by …,,
+(x.15a),"Drawn compatible, mask, and waffle-drop layers are allowed only inside areaid:mt (i.e., etest modules), or inside areaid:sl (i.e., between the outer and inner areaid:sl edges, but not in the die) or inside areaid:ft (i.e., frame, blankings). Exception: FOM/P1M/Metal waffle drop are allowed inside the die",P,
+(x.15b),"Rule X.15a exempted for cpmm.dg inside cellnames ""PadPLfp"", ""padPLhp"", ""padPLstg"" and ""padPLwlbi"" (for the SKY130di-5r-gsmc flow)",EXEMPT,
+(x.16),"Die must not overlap :drc_tag:`areaid.mt` (rule waived for test chips and exempted for cellnames ""*tech_CD_*"", ""*_techCD_*"", ""lazX_*"" or ""lazY_*"" )",,
+(x.17),"All labels must be within the ""drawing"" polygons of the layer; This check is enabled by using switch ""floating_labels""; Identifies floating labels which appear as warnings in LVS. Using this check would enable cleaner LVS run; Not a gate for tapeout",,
+(x.18),"Use redundant mcon, via, via2, via3 and via4 (Locations where additional vias/contacts can be added to existing single vias/contacts will be identified by this rule).\nSingle via under :drc_tag:`areaid.core` and :drc_tag:`areaid.standarc` are excluded from the single via check",RR,
+(x.19),"Lower left corner of the seal ring should be at origin i.e (0,0)",,
+(x.20),"Min spacing between pins on the same layer (center to center); Check enabled by switch ""IP_block""",,
+(x.21),prunde.dg is allowed only inside :drc_tag:`areaid.mt` or :drc_tag:`areaid.sc`,,
+(x.22),"No floating interconnects (poly, li1, met1-met5) or capm allowed; Rule flags interconnects with no path to poly, difftap or metal pins. Exempt floating layers can be excluded using poly_float, li1_float, m1_float, m2_float, m3_float, m4_float and m5_float text labels. Also flags an error if these text labels are placed on connected layers (not floating) and if the labels are not over the appropriate metal layer.  \nIf floating interconnects need to be connected at a higher level (Parent IP or Full chip), such floating interconnects can be exempted using poly_tie, li1_tie, m1_tie, m2_tie, m3_tie, m4_tie and m5_tie text labels.\nIt is the responsibility of the IP owner and chip/product owner to communicate and agree to the node each of these texted lines is connected to, if there is any risk to how a line is tied, and to what node.\nOnly metals outside :drc_tag:`areaid.stdcell` are checked.\n
+The following are exempt from x.22 violations: _techCD_ , inductor.dg, modulecut, capacitors and s8blerf
+The 'notPublicCell' switch will deactivate this rule",RC,
+(x.23a),:drc_tag:`areaid.sl` must not overlap diff,,N/A
+(x.23b),diff cannot straddle :drc_tag:`areaid.sl`,,
+(x.23c),":drc_tag:`areaid.sl` must not overlap tap, poly, li1 and metX",,
+(x.23d),":drc_tag:`areaid.sl` must not overlap tap, poly",,N/A
+(x.23e),"areaid:sl must not overlap li1 and metX for pcell ""advSeal_6um""",,N/A
+(x.23f),"areaid:SubstrateCut (:drc_tag:`areaid.st`, local_sub) must not straddle p+ tap",RR,
+(x.24),condiode label must be in iso_pwell,,
+(x.25),"pnp.dg must be only within cell name ""s8rf_pnp"", ""s8rf_pnp5x"" or ""s8tesd_iref_pnp"", ""stk14ecx_*""",,
+(x.26),"""advSeal_6um"" pcell must overlap diff",,
+(x.27),"If the sealring is present, then partnum is required.  To exempt the requirement, place text.dg saying ""partnum_not_necessary"".\n""partnum*block"" pcell should be used instead of ""partnum*"" pcells",RR,N/A
+(x.28),Min width of :drc_tag:`areaid.sl`,,N/A
+(x.29),nfet must be enclosed by dnwell. Rule is checked when switch nfet_in_dnwell is turned on.,,
diff --git a/docs/rules/periphery/p018-x_dotdash.svg b/docs/rules/periphery/p018-x_dotdash.svg
new file mode 100644
index 0000000..5556d7e
--- /dev/null
+++ b/docs/rules/periphery/p018-x_dotdash.svg
@@ -0,0 +1,113 @@
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diff --git a/docs/rules/periphery/p020-dnwell_dotdash.csv b/docs/rules/periphery/p020-dnwell_dotdash.csv
new file mode 100644
index 0000000..6e2def5
--- /dev/null
+++ b/docs/rules/periphery/p020-dnwell_dotdash.csv
@@ -0,0 +1,10 @@
+Name,Description,Flags,Value
+(dnwell.2),Min width of deep nwell,,3.000
+(dnwell.3),Min spacing between deep nwells. Rule exempt inside UHVI.,,6.300
+(dnwell.3a),Min spacing between deep nwells on same net inside UHVI.,,N/A
+(dnwell.3b),Min spacing between deep-nwells inside UHVI and deep-nwell outside UHVI,,N/A
+(dnwell.3c),Min spacing between deep-nwells inside UHVI and nwell outsideUHVI,,N/A
+(dnwell.3d),Min spacing between deep-nwells inside UHVI on different nets,,N/A
+(dnwell.4),Dnwell can not overlap pnp:dg,,
+(dnwell.5),P+_diff can not straddle Dnwell,,
+(dnwell.6),RF NMOS must be enclosed by deep nwell (RF FETs are listed in $DESIGN/config/tech/model_set/calibre/fixed_layout_model_map of corresponding techs),,
diff --git a/docs/rules/periphery/p020-dnwell_dotdash.svg b/docs/rules/periphery/p020-dnwell_dotdash.svg
new file mode 100644
index 0000000..9c458fb
--- /dev/null
+++ b/docs/rules/periphery/p020-dnwell_dotdash.svg
@@ -0,0 +1,711 @@
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diff --git a/docs/rules/periphery/p021-nwell_dotdash.csv b/docs/rules/periphery/p021-nwell_dotdash.csv
new file mode 100644
index 0000000..78b2206
--- /dev/null
+++ b/docs/rules/periphery/p021-nwell_dotdash.csv
@@ -0,0 +1,12 @@
+Name,Description,Flags,Value
+(nwell.1),Width of nwell,,0.840
+(nwell.2a),Spacing between two n-wells,,1.270
+(nwell.2b),Manual merge wells if less than minimum,,
+(nwell.4),All n-wells will contain metal-contacted tap  (rule checks only for licon on tap) . Rule exempted from high voltage cells inside UHVI,,
+(nwell.5),"Deep nwell must be enclosed by nwell by atleast... Exempted inside UHVI or :drc_tag:`areaid.lw`
+Nwells can merge over deep nwell if spacing too small (as in rule nwell.2)",TC,0.400
+(nwell.5a),min enclosure of nwell by dnwell inside UHVI,,N/A
+(nwell.5b),nwell inside UHVI must not be on the same net as nwell outside UHVI,,N/A
+(nwell.6),Min enclosure of nwell hole by deep nwell outside UHVI,TC,1.030
+(nwell.7),"Min spacing between nwell and deep nwell on separate nets
+Spacing between nwell and deep nwell on the same net is set by the sum of the rules nwell.2 and nwell.5. By default, DRC run on a cell checks for the separate-net spacing, when nwell and deep nwell nets are separate within the cell hierarchy and are joined in the upper hierarchy. To allow net names to be joined and make the same-net rule applicable in this case, the ""joinNets"" switch should be turned on.",TC,4.500
diff --git a/docs/rules/periphery/p021-nwell_dotdash.svg b/docs/rules/periphery/p021-nwell_dotdash.svg
new file mode 100644
index 0000000..b0a06ad
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diff --git a/docs/rules/periphery/p022-pwbm_dotdash.csv b/docs/rules/periphery/p022-pwbm_dotdash.csv
new file mode 100644
index 0000000..bf3b98c
--- /dev/null
+++ b/docs/rules/periphery/p022-pwbm_dotdash.csv
@@ -0,0 +1,5 @@
+Name,Description,Flags,Value
+(pwbm.1),Min width of pwbm.dg,,N/A
+(pwbm.2),Min spacing between two pwbm.dg inside UHVI,,N/A
+(pwbm.3),Min enclosure of dnwell:dg by pwbm.dg inside UHVI (exempt pwbm hole inside dnwell),,N/A
+(pwbm.4),dnwell inside UHVI must be enclosed by pwbm (exempt pwbm hole inside dnwell),,N/A
diff --git a/docs/rules/periphery/p022-pwbm_dotdash.svg b/docs/rules/periphery/p022-pwbm_dotdash.svg
new file mode 100644
index 0000000..18ee42b
--- /dev/null
+++ b/docs/rules/periphery/p022-pwbm_dotdash.svg
@@ -0,0 +1,1079 @@
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diff --git a/docs/rules/periphery/p022-pwdem_dotdash.csv b/docs/rules/periphery/p022-pwdem_dotdash.csv
new file mode 100644
index 0000000..08036af
--- /dev/null
+++ b/docs/rules/periphery/p022-pwdem_dotdash.csv
@@ -0,0 +1,6 @@
+Name,Description,Flags,Value
+(pwdem.1),Min width of pwdem.dg,,N/A
+(pwdem.2),Min spacing between two pwdem.dg inside UHVI on same net,,N/A
+(pwdem.3),Min enclosure of pwdem:dg by pwbm.dg inside UHVI,,N/A
+(pwdem.4),pwdem.dg must be enclosed by UHVI,,N/A
+(pwdem.5),pwdem.dg inside UHVI must be enclosed by deep nwell,,N/A
diff --git a/docs/rules/periphery/p022-pwdem_dotdash.svg b/docs/rules/periphery/p022-pwdem_dotdash.svg
new file mode 100644
index 0000000..7dc48ff
--- /dev/null
+++ b/docs/rules/periphery/p022-pwdem_dotdash.svg
@@ -0,0 +1,256 @@
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diff --git a/docs/rules/periphery/p023-hvtp_dotdash.csv b/docs/rules/periphery/p023-hvtp_dotdash.csv
new file mode 100644
index 0000000..21da7fd
--- /dev/null
+++ b/docs/rules/periphery/p023-hvtp_dotdash.csv
@@ -0,0 +1,6 @@
+Name,Description,Flags,Value
+(hvtp.1),Min width of hvtp,,0.380
+(hvtp.2),Min spacing between hvtp to hvtp,,0.380
+(hvtp.3),Min enclosure of pfet by hvtp,P,0.180
+(hvtp.4),Min spacing between pfet and hvtp,P,0.180
+(hvtp.5),Min area of hvtp (um^2),,0.265
diff --git a/docs/rules/periphery/p023-hvtp_dotdash.svg b/docs/rules/periphery/p023-hvtp_dotdash.svg
new file mode 100644
index 0000000..4b6eed4
--- /dev/null
+++ b/docs/rules/periphery/p023-hvtp_dotdash.svg
@@ -0,0 +1,410 @@
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diff --git a/docs/rules/periphery/p024-hvtr_dotdash.csv b/docs/rules/periphery/p024-hvtr_dotdash.csv
new file mode 100644
index 0000000..d1892ef
--- /dev/null
+++ b/docs/rules/periphery/p024-hvtr_dotdash.csv
@@ -0,0 +1,3 @@
+Name,Description,Flags,Value
+(hvtr.1),Min width of hvtr,,0.380
+(hvtr.2),Min spacing between hvtp to hvtr,,0.380
diff --git a/docs/rules/periphery/p024-lvtn_dotdash.csv b/docs/rules/periphery/p024-lvtn_dotdash.csv
new file mode 100644
index 0000000..ca24ad5
--- /dev/null
+++ b/docs/rules/periphery/p024-lvtn_dotdash.csv
@@ -0,0 +1,10 @@
+Name,Description,Flags,Value
+(lvtn.1a),Min width of lvtn,,0.380
+(lvtn.2),Min space lvtn to lvtn,,0.380
+(lvtn.3a),Min spacing of lvtn to gate. Rule exempted inside UHVI.,P,0.180
+(lvtn.3b),Min spacing of lvtn to pfet along the S/D direction,P,0.235
+(lvtn.4b),Min enclosure of gate by lvtn. Rule exempted inside UHVI.,P,0.180
+(lvtn.9),"Min spacing, no overlap, between lvtn and hvtp",,0.380
+(lvtn.10),Min enclosure of lvtn by (nwell not overlapping Var_channel) (exclude coincident edges),,0.380
+(lvtn.12),Min spacing between lvtn and (nwell inside :drc_tag:`areaid.ce`),,0.380
+(lvtn.13),Min area of lvtn (um^2),,0.265
diff --git a/docs/rules/periphery/p024-lvtn_dotdash.svg b/docs/rules/periphery/p024-lvtn_dotdash.svg
new file mode 100644
index 0000000..e878847
--- /dev/null
+++ b/docs/rules/periphery/p024-lvtn_dotdash.svg
@@ -0,0 +1,743 @@
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diff --git a/docs/rules/periphery/p025-ncm_dotdash.csv b/docs/rules/periphery/p025-ncm_dotdash.csv
new file mode 100644
index 0000000..a0fd78e
--- /dev/null
+++ b/docs/rules/periphery/p025-ncm_dotdash.csv
@@ -0,0 +1,11 @@
+Name,Description,Flags,Value
+(ncm.X.2),Ncm overlapping areaid:ce is checked for core rules only,,
+(ncm.X.3),Ncm overlapping core cannot overlap N+diff in periphery,TC,
+(ncm.1),Width of ncm,,0.380
+(ncm.2a),Spacing of ncm to ncm,,0.380
+(ncm.2b),Manual merge ncm if space is below minimum,,
+(ncm.3),Min enclosure of P+diff by Ncm,P,0.180
+(ncm.4),Min enclosure of P+diff within (areaid:ed AndNot areaid:de) by Ncm,P,0.180
+(ncm.5),"Min space, no overlap, between ncm and (LVTN_gate) OR (diff containing lvtn)",P,0.230
+(ncm.6),"Min space, no overlap, between ncm and nfet",P,0.200
+(ncm.7),Min area of ncm (um^2),,0.265
diff --git a/docs/rules/periphery/p025-ncm_dotdash.svg b/docs/rules/periphery/p025-ncm_dotdash.svg
new file mode 100644
index 0000000..7b2fa82
--- /dev/null
+++ b/docs/rules/periphery/p025-ncm_dotdash.svg
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+ </g>
+ <path id="dq" d="m55.559 12.719h22.441v0.83985h-22.441zm0.60157 2.1602-3.6016-1.8008 3.6016-1.7969zm21.238-3.5977 3.6016 1.7969-3.6016 1.8008"/>
+</svg>
diff --git a/docs/rules/periphery/p026-difftap_dotdash.csv b/docs/rules/periphery/p026-difftap_dotdash.csv
new file mode 100644
index 0000000..d60873a
--- /dev/null
+++ b/docs/rules/periphery/p026-difftap_dotdash.csv
@@ -0,0 +1,15 @@
+Name,Description,Flags,Value
+(difftap.1),Width of diff or tap,P,0.150
+(difftap.2),"Minimum channel width (Diff And Poly) except for FETs inside :drc_tag:`areaid.sc`: Rule exempted in the SP8* flows only, for the cells listed in rule difftap.2a",P,0.420
+(difftap.2a),"Minimum channel width (Diff And Poly) for cell names ""s8cell_ee_plus_sseln_a"", ""s8cell_ee_plus_sseln_b"", ""s8cell_ee_plus_sselp_a"", ""s8cell_ee_plus_sselp_b"" , ""s8fpls_pl8"", ""s8fpls_rdrv4"" , ""s8fpls_rdrv4f"" and ""s8fpls_rdrv8""",P,NA
+(difftap.2b),Minimum channel width (Diff And Poly) for FETs inside :drc_tag:`areaid.sc`,P,0.360
+(difftap.3),"Spacing of diff to diff, tap to tap, or non-abutting diff to tap",,0.270
+(difftap.4),Min tap bound by one diffusion,,0.290
+(difftap.5),Min tap bound by two diffusions,P,0.400
+(difftap.6),Diff and tap are not allowed to extend beyond their abutting edge,,
+(difftap.7),Spacing of diff/tap abutting edge to a non-conciding diff or tap edge,NE,0.130
+(difftap.8),Enclosure of (p+) diffusion by N-well. Rule exempted inside UHVI.,DE NE P,0.180
+(difftap.9),Spacing of (n+) diffusion to N-well outside UHVI,DE NE P,0.340
+(difftap.10),Enclosure of (n+)  tap by N-well. Rule exempted inside UHVI.,NE P,0.180
+(difftap.11),Spacing of (p+) tap to  N-well. Rule exempted inside UHVI.,,0.130
+(difftap.12),ESD_nwell_tap is considered shorted to the abutting diff,NC,
diff --git a/docs/rules/periphery/p026-difftap_dotdash.svg b/docs/rules/periphery/p026-difftap_dotdash.svg
new file mode 100644
index 0000000..73bcc63
--- /dev/null
+++ b/docs/rules/periphery/p026-difftap_dotdash.svg
@@ -0,0 +1,2149 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+ <metadata id="aob">
+  <rdf:RDF>
+   <cc:Work rdf:about="">
+    <dc:format>image/svg+xml</dc:format>
+    <dc:type rdf:resource="http://purl.org/dc/dcmitype/StillImage"/>
+    <dc:title/>
+   </cc:Work>
+  </rdf:RDF>
+ </metadata>
+ <defs id="aoc">
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diff --git a/docs/rules/periphery/p027-tunm_dotdash.csv b/docs/rules/periphery/p027-tunm_dotdash.csv
new file mode 100644
index 0000000..49328b3
--- /dev/null
+++ b/docs/rules/periphery/p027-tunm_dotdash.csv
@@ -0,0 +1,8 @@
+Name,Description,Flags,Value
+(tunm.1),Min width of tunm,,0.410
+(tunm.2),Min spacing of tunm to tunm,,0.500
+(tunm.3),Extension of tunm beyond (poly and diff),,0.095
+(tunm.4),Min spacing of tunm to (poly and diff) outside tunm,,0.095
+(tunm.5),(poly and diff) may not straddle tunm,,
+(tunm.6a),Tunm outside deep n-well is not allowed,TC,
+(tunm.7),Min tunm area,,0.672
diff --git a/docs/rules/periphery/p027-tunm_dotdash.svg b/docs/rules/periphery/p027-tunm_dotdash.svg
new file mode 100644
index 0000000..49e90b5
--- /dev/null
+++ b/docs/rules/periphery/p027-tunm_dotdash.svg
@@ -0,0 +1,3114 @@
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diff --git a/docs/rules/periphery/p028-poly_dotdash.csv b/docs/rules/periphery/p028-poly_dotdash.csv
new file mode 100644
index 0000000..f77d8ee
--- /dev/null
+++ b/docs/rules/periphery/p028-poly_dotdash.csv
@@ -0,0 +1,17 @@
+Name,Description,Flags,Value
+(poly.X.1),All FETs would be checked for W/Ls as documented in spec 001-02735  (Exempt FETs that are pruned; exempt for W/L's inside :drc_tag:`areaid.sc` and inside cell name scs8*decap* and listed in the MRGA as a decap only W/L),,
+(poly.X.1a),Min & max dummy_poly L is equal to min L allowed for corresponding device type (exempt rule for dummy_poly in cells listed on Table H3),,
+(poly.1a),Width of poly,,0.150
+(poly.1b),Min channel length (poly width) for pfet overlapping lvtn (exempt rule for dummy_poly in cells listed on Table H3),,0.350
+(poly.2),Spacing of poly to poly except for poly.c2 and poly.c3; Exempt cell: sr_bltd_eq where it is same as poly.c2,,0.210
+(poly.3),Min poly resistor width,,0.330
+(poly.4),Spacing of poly on field to diff (parallel edges only),P,0.075
+(poly.5),Spacing of poly on field to tap,P,0.055
+(poly.6),Spacing of poly on diff to abutting tap (min source),P,0.300
+(poly.7),Extension of diff beyond poly (min drain),P,0.250
+(poly.8),Extension of poly beyond diffusion (endcap),P,0.130
+(poly.9),Poly resistor spacing to poly or spacing (no overlap) to diff/tap,,0.480
+(poly.10),Poly can't overlap inner corners of diff,,
+(poly.11),No 90 deg turns of poly on diff,,
+(poly.12),"(Poly NOT (nwell NOT hvi)) may not overlap tap; Rule exempted for cell name ""s8fgvr_n_fg2"" and gated_npn and inside UHVI.",P,
+(poly.15),Poly must not overlap diff:rs,,
diff --git a/docs/rules/periphery/p028-poly_dotdash.svg b/docs/rules/periphery/p028-poly_dotdash.svg
new file mode 100644
index 0000000..3bed614
--- /dev/null
+++ b/docs/rules/periphery/p028-poly_dotdash.svg
@@ -0,0 +1,1044 @@
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diff --git a/docs/rules/periphery/p029-rpm_dotdash.csv b/docs/rules/periphery/p029-rpm_dotdash.csv
new file mode 100644
index 0000000..3223d2c
--- /dev/null
+++ b/docs/rules/periphery/p029-rpm_dotdash.csv
@@ -0,0 +1,21 @@
+Name,Description,Flags,Value
+(rpm.1a),Min width of rpm,,1.270
+(rpm.1b),Min/Max prec_resistor width xhrpoly_0p35,,0.350
+(rpm.1c),Min/Max prec_resistor width xhrpoly_0p69,,0.690
+(rpm.1d),Min/Max prec_resistor width xhrpoly_1p41,,1.410
+(rpm.1e),Min/Max prec_resistor width xhrpoly_2p85,,2.850
+(rpm.1f),Min/Max prec_resistor width xhrpoly_5p73,,5.730
+(rpm.1g),Only 1 licon is allowed in xhrpoly_0p35 prec_resistor_terminal,,
+(rpm.1h),Only 1 licon is allowed in xhrpoly_0p69 prec_resistor_terminal,,
+(rpm.1i),Only 2 licons are allowed in xhrpoly_1p41 prec_resistor_terminal,,
+(rpm.1j),Only 4 licons are allowed in xhrpoly_2p85 prec_resistor_terminal,,
+(rpm.1k),Only 8 licons are allowed in xhrpoly_5p73 prec_resistor_terminal,,
+(rpm.2),Min spacing of rpm to rpm,,0.840
+(rpm.3),rpm must enclose prec_resistor by atleast,,0.200
+(rpm.4),prec_resistor must be enclosed by psdm by atleast,,0.110
+(rpm.5),prec_resistor must be enclosed by npc by atleast,,0.095
+(rpm.6),"Min spacing, no overlap, of rpm and nsdm",,0.200
+(rpm.7),Min spacing between rpm and poly,,0.200
+(rpm.8),poly must not straddle rpm,,
+(rpm.9),"Min space, no overlap, between prec_resistor and hvntm",,0.185
+(rpm.10),Min spacing of rpm to pwbm,,N/A
diff --git a/docs/rules/periphery/p029-rpm_dotdash.svg b/docs/rules/periphery/p029-rpm_dotdash.svg
new file mode 100644
index 0000000..214a2c0
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diff --git a/docs/rules/periphery/p030-varac_dotdash.csv b/docs/rules/periphery/p030-varac_dotdash.csv
new file mode 100644
index 0000000..1877d93
--- /dev/null
+++ b/docs/rules/periphery/p030-varac_dotdash.csv
@@ -0,0 +1,8 @@
+Name,Description,Flags,Value
+(varac.1),Min channel length (poly width) of Var_channel,,0.180
+(varac.2),Min channel width (tap width) of Var_channel,,1.000
+(varac.3),Min spacing between hvtp to Var_channel,,0.180
+(varac.4),Min spacing of licon on tap to Var_channel,,0.250
+(varac.5),Min enclosure of poly overlapping Var_channel by nwell,,0.150
+(varac.6),Min spacing between VaracTap and difftap,,0.270
+(varac.7),Nwell overlapping Var_channel must not overlap P+ diff,,
diff --git a/docs/rules/periphery/p030-varac_dotdash.svg b/docs/rules/periphery/p030-varac_dotdash.svg
new file mode 100644
index 0000000..0234b0d
--- /dev/null
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diff --git a/docs/rules/periphery/p031-photo_dotdash.csv b/docs/rules/periphery/p031-photo_dotdash.csv
new file mode 100644
index 0000000..cfa8467
--- /dev/null
+++ b/docs/rules/periphery/p031-photo_dotdash.csv
@@ -0,0 +1,11 @@
+Name,Description,Flags,Value
+(photo.1),Rules dnwell.3 and nwell.5 are exempted for photoDiode,,
+(photo.2),Min/Max width of photoDiode,,3.000
+(photo.3),Min spacing between photoDiode,,5.000
+(photo.4),Min spacing between photoDiode and deep nwell,,5.300
+(photo.5),photoDiode edges must be coincident with :drc_tag:`areaid.po`,,
+(photo.6),photoDiode must be enclosed by dnwell ring,,
+(photo.7),photoDiode must be enclosed by p+ tap ring,,
+(photo.8),Min/Max width of nwell inside photoDiode,,0.840
+(photo.9),Min/Max enclosure of nwell by photoDiode,,1.080
+(photo.10),Min/Max width of tap inside photoDiode,,0.410
diff --git a/docs/rules/periphery/p031-photo_dotdash.svg b/docs/rules/periphery/p031-photo_dotdash.svg
new file mode 100644
index 0000000..012bc77
--- /dev/null
+++ b/docs/rules/periphery/p031-photo_dotdash.svg
@@ -0,0 +1,601 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+ <metadata id="bk">
+  <rdf:RDF>
+   <cc:Work rdf:about="">
+    <dc:format>image/svg+xml</dc:format>
+    <dc:type rdf:resource="http://purl.org/dc/dcmitype/StillImage"/>
+    <dc:title/>
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diff --git a/docs/rules/periphery/p032-n_psd_dotdash.csv b/docs/rules/periphery/p032-n_psd_dotdash.csv
new file mode 100644
index 0000000..3f58053
--- /dev/null
+++ b/docs/rules/periphery/p032-n_psd_dotdash.csv
@@ -0,0 +1,12 @@
+Name,Description,Flags,Value
+(n/ psd.1),Width of nsdm(psdm),P,0.380
+(n/ psd.2),Spacing of nsdm(psdm) to nsdm(psdm),P,0.380
+(n/ psd.3),Manual merge if less than minimum,,
+(n/ psd.5a),"Enclosure of diff by nsdm(psdm), except for butting edge",,0.125
+(n/ psd.5b),"Enclosure of tap by nsdm(psdm), except for butting edge",P,0.125
+(n/ psd.6),Enclosure of diff/tap butting edge by nsdm (psdm),,0.000
+(n/ psd.7),Spacing of NSDM/PSDM to opposite implant diff or tap (for non-abutting diff/tap edges),,0.130
+(n/ psd.8),Nsdm and psdm cannot overlap diff/tap regions of opposite doping,DE,
+(n/ psd.9),"Diff and tap must be enclosed by their corresponding implant layers. Rule exempted for\n- diff inside ""advSeal_6um* OR cuPillarAdvSeal_6um*"" pcell for SKY130P*/SP8P*/SKY130DI-5R-CSMC flows\n- diff rings around the die at min total L>1000 um and W=0.3 um\n- gated_npn \n- :drc_tag:`areaid.zer`.",DE,
+(n/ psd.10a),Min area of Nsdm (um^2),,0.265
+(n/ psd.10b),Min area of Psdm (um^2),,0.255
diff --git a/docs/rules/periphery/p032-n_psd_dotdash.svg b/docs/rules/periphery/p032-n_psd_dotdash.svg
new file mode 100644
index 0000000..331eb7c
--- /dev/null
+++ b/docs/rules/periphery/p032-n_psd_dotdash.svg
@@ -0,0 +1,706 @@
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diff --git a/docs/rules/periphery/p032-npc_dotdash.csv b/docs/rules/periphery/p032-npc_dotdash.csv
new file mode 100644
index 0000000..2468d14
--- /dev/null
+++ b/docs/rules/periphery/p032-npc_dotdash.csv
@@ -0,0 +1,5 @@
+Name,Description,Flags,Value
+(npc.1),Min width of NPC,,0.270
+(npc.2),Min spacing of NPC to NPC,,0.270
+(npc.3),Manual merge if less than minimum,,
+(npc.4),Spacing (no overlap) of NPC to Gate,,0.090
diff --git a/docs/rules/periphery/p032-npc_dotdash.svg b/docs/rules/periphery/p032-npc_dotdash.svg
new file mode 100644
index 0000000..158dd6f
--- /dev/null
+++ b/docs/rules/periphery/p032-npc_dotdash.svg
@@ -0,0 +1,1492 @@
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diff --git a/docs/rules/periphery/p034-licon_dotdash.csv b/docs/rules/periphery/p034-licon_dotdash.csv
new file mode 100644
index 0000000..964de4f
--- /dev/null
+++ b/docs/rules/periphery/p034-licon_dotdash.csv
@@ -0,0 +1,31 @@
+Name,Description,Flags,Value
+(licon.1),Min and max L and W of licon (exempt licons inside prec_resistor),,0.170
+(licon.1b),Min and max width of licon inside prec_resistor,,0.190
+(licon.1c),Min and max length of licon inside prec_resistor,,2.000
+(licon.2),Spacing of licon to licon,P,0.170
+(licon.2b),Min spacing between two slotted_licon (when the both the edges are 0.19um in length),,0.350
+(licon.2c),Min spacing between two slotted_licon (except for rule licon.2b),,0.510
+(licon.2d),Min spacing between a slotted_licon and 0.17um square licon,,0.510
+(licon.3),Only min. square licons are allowed except die seal ring where licons are (licon CD)*L,,0.170 *L
+(licon.4),Licon1 must overlap li1 and (poly or diff or tap),,
+(licon.5a),Enclosure of licon by diff,P,0.040
+(licon.5b),Min space between tap_licon and diff-abutting tap edge,P,0.060
+(licon.5c),Enclosure of licon by diff on one of two adjacent sides,P,0.060
+(licon.6),Licon cannot straddle tap,P,
+(licon.7),Enclosure of licon by one of two adjacent edges of isolated tap,P,0.120
+(licon.8),Enclosure of poly_licon by poly,P,0.050
+(licon.8a),Enclosure of poly_licon by poly on one of two adjacent sides,P,0.080
+(licon.9),"Spacing, no overlap, between poly_licon and psdm; In SKY130DIA/SKY130TMA/SKY130PIR-10 flows, the rule is checked only between (poly_licon outside rpm) and psdm",P,0.110
+(licon.10),Spacing of licon on (tap AND (nwell NOT hvi)) to Var_channel,P,0.250
+(licon.11),"Spacing of licon on diff or tap to poly on diff (except for all FETs inside :drc_tag:`areaid.sc` and except s8spf-10r flow for 0.5um phv inside cell names ""s8fs_gwdlvx4"", ""s8fs_gwdlvx8"", ""s8fs_hvrsw_x4"", ""s8fs_hvrsw8"", ""s8fs_hvrsw264"", and ""s8fs_hvrsw520"" and for 0.15um nshort inside cell names ""s8fs_rdecdrv"", ""s8fs_rdec8"", ""s8fs_rdec32"", ""s8fs_rdec264"", ""s8fs_rdec520"")",P,0.055
+(licon.11a),Spacing of licon on diff or tap to poly on diff (for all FETs inside :drc_tag:`areaid.sc` except 0.15um phighvt),P,0.050
+(licon.11b),Spacing of licon on diff or tap to poly on diff (for 0.15um phighvt inside :drc_tag:`areaid.sc`),P,0.050
+(licon.11c),"Spacing of licon on diff or tap to poly on diff (for 0.5um phv inside cell names ""s8fs_gwdlvx4"", ""s8fs_gwdlvx8"", ""s8fs_hvrsw_x4"", ""s8fs_hvrsw8"", ""s8fs_hvrsw264"", and ""s8fs_hvrsw520"")",P,0.040
+(licon.11d),"Spacing of licon on diff or tap to poly on diff (for 0.15um nshort inside cell names ""s8fs_rdecdrv"", ""s8fs_rdec8"", ""s8fs_rdec32"", ""s8fs_rdec264"", ""s8fs_rdec520"")",P,0.045
+(licon.12),Max SD width without licon,NC,5.700
+(licon.13),Spacing (no overlap) of NPC to licon on diff or tap,P,0.090
+(licon.14),Spacing of poly_licon to diff or tap,P,0.190
+(licon.15),poly_licon must be enclosed by npc by…,P,0.100
+(licon.16),"Every source_diff and every tap must enclose at least one licon1, including the diff/tap straddling areaid:ce. \nRule exempted inside UHVI.",P,
+(licon.17),Licons may not overlap both poly and (diff or tap),,
+(licon.18),Npc must enclose poly_licon,,
diff --git a/docs/rules/periphery/p034-licon_dotdash.svg b/docs/rules/periphery/p034-licon_dotdash.svg
new file mode 100644
index 0000000..5377c77
--- /dev/null
+++ b/docs/rules/periphery/p034-licon_dotdash.svg
@@ -0,0 +1,1910 @@
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diff --git a/docs/rules/periphery/p035-ct_dotdash.csv b/docs/rules/periphery/p035-ct_dotdash.csv
new file mode 100644
index 0000000..18db78d
--- /dev/null
+++ b/docs/rules/periphery/p035-ct_dotdash.csv
@@ -0,0 +1,7 @@
+Name,Description,Flags,Value
+(ct.1),Min and max L and W of mcon,DNF,0.170
+(ct.2),Spacing of mcon to mcon,DNF,0.190
+(ct.3),Only min. square mcons are allowed except die seal ring where mcons are…,,0.170*L
+(ct.4),Mcon must be enclosed by LI by at least …,P,0.000
+(ct.irdrop.1),"For 1 <= n <= 10 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.2
+(ct.irdrop.2),"For 11 <= n <= 100 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.3
diff --git a/docs/rules/periphery/p035-ct_dotdash.svg b/docs/rules/periphery/p035-ct_dotdash.svg
new file mode 100644
index 0000000..784fb5c
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diff --git a/docs/rules/periphery/p035-li_dotdash_dotdash.csv b/docs/rules/periphery/p035-li_dotdash_dotdash.csv
new file mode 100644
index 0000000..a0e6e6b
--- /dev/null
+++ b/docs/rules/periphery/p035-li_dotdash_dotdash.csv
@@ -0,0 +1,8 @@
+Name,Description,Flags,Value
+(li.1.-),Width of LI (except for li.1a),P,0.170
+(li.1a.-),Width of LI inside of cells with name s8rf2_xcmvpp_hd5_*,P,0.140
+(li.2.-),Max ratio of length to width of LI without licon or mcon,NC,10.000
+(li.3.-),Spacing of LI to LI (except for li.3a),P,0.170
+(li.3a.-),Spacing of LI to LI inside cells with names s8rf2_xcmvpp_hd5_*,P,0.140
+(li.5.-),Enclosure of licon by one of two adjacent LI sides,P,0.080
+(li.6.-),Min area of LI,P,0.0561
diff --git a/docs/rules/periphery/p035-li_dotdash_dotdash.svg b/docs/rules/periphery/p035-li_dotdash_dotdash.svg
new file mode 100644
index 0000000..61e0c49
--- /dev/null
+++ b/docs/rules/periphery/p035-li_dotdash_dotdash.svg
@@ -0,0 +1,334 @@
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diff --git a/docs/rules/periphery/p036-capm_dotdash.csv b/docs/rules/periphery/p036-capm_dotdash.csv
new file mode 100644
index 0000000..1ff01d2
--- /dev/null
+++ b/docs/rules/periphery/p036-capm_dotdash.csv
@@ -0,0 +1,12 @@
+Name,Description,Flags,Value
+(capm.1),Min width of capm,,N/A
+(capm.2a),Min spacing of capm to capm,,N/A
+(capm.2b),Minimum spacing of capacitor bottom_plate to bottom plate,,N/A
+(capm.3),Minimum enclosure of capm (top_plate) by met2,,N/A
+(capm.4),Min enclosure of via2 by capm,,N/A
+(capm.5),Min spacing between capm and via2,,N/A
+(capm.6),Maximum Aspect Ratio (Length/Width),,N/A
+(capm.7),Only rectangular capacitors are allowed,,N/A
+(capm.8),"Min space, no overlap, between via and capm",,N/A
+(capm.10),"capm must not straddle nwell, diff, tap, poly, li1 and met1 (Rule exempted for capm overlapping capm_2t.dg)",TC,N/A
+(capm.11),Min spacing between capm to (met2 not overlapping capm),,N/A
diff --git a/docs/rules/periphery/p036-capm_dotdash.svg b/docs/rules/periphery/p036-capm_dotdash.svg
new file mode 100644
index 0000000..d4f64cd
--- /dev/null
+++ b/docs/rules/periphery/p036-capm_dotdash.svg
@@ -0,0 +1,1586 @@
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diff --git a/docs/rules/periphery/p037-vpp_dotdash.csv b/docs/rules/periphery/p037-vpp_dotdash.csv
new file mode 100644
index 0000000..1253d28
--- /dev/null
+++ b/docs/rules/periphery/p037-vpp_dotdash.csv
@@ -0,0 +1,18 @@
+Name,Description,Flags,Value
+(vpp.1),Min width of capacitor:dg,,1.430
+(vpp.1b),Max width of capacitor:dg; Rule not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5 and vpp_with_noLi,,11.350
+(vpp.1c),"Min/Max width of cell name ""s8rf_xcmvpp1p8x1p8_m3shield """,,3.880
+(vpp.3),"capacitor:dg must not overlap (tap or diff or poly); (one exception: Poly is allowed to overlap  vpp_with_Met3Shield and vpp_with_Met5PolyShield); (not applicable for vpp_over_Moscap or ""s8rf2_xcmvppx4_2xnhvnative10x4"" or vpp_with_LiShield)",,
+(vpp.4),capacitor:dg must not straddle (nwell or dnwell),,
+(vpp.5),Min spacing between (capacitor:dg edge and (poly or li1 or met1 or met2)) to (poly or li1 or met1 or met2) on separate nets (Exempt area of the error shape less than 2.25 (um^2) and run length less than 2.0um); Rule not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5 and vpp_with_noLi,,1.500
+(vpp.5a),Max pattern density of met3.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5),,0.25
+(vpp.5b),Max pattern density of met4.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_Met5 and vpp_over_MOSCAP),,0.3
+(vpp.5c),"Max pattern density of met5.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_Met5 and vpp_over_MOSCAP and vpp_with_noLi); (one exception: rules does apply to cell ""s8rf2_xcmvpp11p5x11p7_m1m4"" and ""s8rf2_xcmvpp_hd5_atlas*"")",,0.4
+(vpp.8),Min enclosure of capacitor:dg by nwell,,1.500
+(vpp.9),Min spacing of capacitor:dg to nwell (not applicable for vpp_over_MOSCAP),,1.500
+(vpp.10),vpp capacitors must not overlap; Rule checks for capacitor.dg overlapping more than one pwell pin,,
+(vpp.11),Min pattern density of (poly and diff) over capacitor.dg; (vpp_over_Moscap only),,0.87
+(vpp.12a),"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp8p6x7p9_m3_lim5shield""  must overlap with size 2.01 x 2.01 (no other met4 shapes allowed)",,9.00
+(vpp.12b),"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp11p5x11p7_m3_lim5shield""  must overlap with size 2.01 x 2.01 (no other met4 shapes allowed)",,16.00
+(vpp.12c),"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp4p4x4p6_m3_lim5shield""  must overlap with size 1.5 x 1.5 (no other met4 shapes allowed)",,4.00
+(vpp.13),Min space of met1 to met1inside VPP capacitor,CU,0.160
diff --git a/docs/rules/periphery/p037-vpp_dotdash.svg b/docs/rules/periphery/p037-vpp_dotdash.svg
new file mode 100644
index 0000000..aa4239c
--- /dev/null
+++ b/docs/rules/periphery/p037-vpp_dotdash.svg
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diff --git a/docs/rules/periphery/p038-m1_dotdash.csv b/docs/rules/periphery/p038-m1_dotdash.csv
new file mode 100644
index 0000000..35a908b
--- /dev/null
+++ b/docs/rules/periphery/p038-m1_dotdash.csv
@@ -0,0 +1,19 @@
+Name,Description,Flags,Value
+(m1.-),"Algorithm should flag errors, for met1, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm1 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. NOTE: Required for IP, Recommended for Chip-level.",RC,
+(m1.1),Width of metal1,,0.140
+(m1.2),Spacing of metal1 to metal1,,0.140
+(m1.3a),Min. spacing of features attached to or extending from huge_met1 for a distance of up to  0.280 um to metal1 (rule not checked over non-huge met1 features),,0.280
+(m1.3b),Min. spacing of huge_met1 to metal1 excluding features checked by m1.3a,,0.280
+(m1.4),Mcon must be enclosed by Met1 by at least …(Rule exempted for cell names documented in rule m1.4a),P,0.030
+(m1.4a),"Mcon must be enclosed by Met1 by at least (for cell names ""s8cell_ee_plus_sseln_a"", ""s8cell_ee_plus_sseln_b"", ""s8cell_ee_plus_sselp_a"", ""s8cell_ee_plus_sselp_b"", ""s8fpls_pl8"", and ""s8fs_cmux4_fm"")",P,0.005
+(m1.5),Mcon must be enclosed by Met1 on one of two adjacent sides by at least …,P AL,0.060
+(m1.6),Min metal 1 area [um2],,0.083
+(m1.7),Min area of metal1 holes [um2],,0.140
+(m1.pd.1),Min MM1_oxide_Pattern_density,RR AL,0.7
+(m1.pd.2a),Rule m1.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A AL,700
+(m1.pd.2b),Rule m1.pd.1 has to be checked by dividing the chip into steps of …,A AL,70
+(m1.11),Max width of metal1after slotting,CU NC,4.000
+(m1.12),Add slots and remove vias and contacts if met1 wider than…..,CU,3.200
+(m1.13),Max pattern density (PD) of met1,CU,0.77
+(m1.14),Met1 PD window size,CU,50.000
+(m1.14a),Met1 PD window step,CU,25.000
diff --git a/docs/rules/periphery/p038-m1_dotdash.svg b/docs/rules/periphery/p038-m1_dotdash.svg
new file mode 100644
index 0000000..efedcab
--- /dev/null
+++ b/docs/rules/periphery/p038-m1_dotdash.svg
@@ -0,0 +1,500 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+ <metadata id="ce">
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diff --git a/docs/rules/periphery/p039-via_dotdash.csv b/docs/rules/periphery/p039-via_dotdash.csv
new file mode 100644
index 0000000..33f407e
--- /dev/null
+++ b/docs/rules/periphery/p039-via_dotdash.csv
@@ -0,0 +1,19 @@
+Name,Description,Flags,Value
+(via.1a),Min and max L and W of via outside :drc_tag:`areaid.mt`,AL,0.150
+(via.1b),"Three sizes of square Vias allowed inside areaid:mt: 0.150um, 0.230um and 0.280um",AL,
+(via.2),Spacing of via to via,AL,0.170
+(via.3),Only min. square vias are allowed except die seal ring where vias are (Via CD)*L,,0.2*L
+(via.4a),0.150 um Via must be enclosed by Met1 by at least …,,0.055
+(via.4b),"Inside :drc_tag:`areaid.mt`, 0.230 um Via must be enclosed by met1 by atleast",AL,0.030
+(via.4c),"Inside :drc_tag:`areaid.mt`, 0.280 um Via must be enclosed by met1 by atleast",AL,0.000
+(via.5a),0.150 um Via must be enclosed by Met1 on one of two adjacent sides by at least …,,0.085
+(via.5b),"Inside :drc_tag:`areaid.mt`, 0.230 um Via must be enclosed by met1 on one of two adjacent sides by at least …",AL,0.060
+(via.5c),"Inside :drc_tag:`areaid.mt`, 0.280 um Via must be enclosed by met1 on one of two adjacent sides by at least …",AL,0.000
+(via.11),Min and max L and W of via outside :drc_tag:`areaid.mt`,CU,0.180
+(via.12),Min spacing between vias,CU,0.130
+(via.13),Max of 5 vias within …,CU,0.350
+(via.14),0.180 um Via must be enclosed by parallel edges of Met1 by at least …,CU,0.040
+(via.irdrop.1),"For 1 <= n <= 2 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.0
+(via.irdrop.2),"For 3 <= n <= 15 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.6
+(via.irdrop.3),"For 16 <= n <= 30 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.8
+(via.irdrop.4),"For n > 30 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.9
diff --git a/docs/rules/periphery/p039-via_dotdash.svg b/docs/rules/periphery/p039-via_dotdash.svg
new file mode 100644
index 0000000..8047c35
--- /dev/null
+++ b/docs/rules/periphery/p039-via_dotdash.svg
@@ -0,0 +1,258 @@
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diff --git a/docs/rules/periphery/p040-m2_dotdash.csv b/docs/rules/periphery/p040-m2_dotdash.csv
new file mode 100644
index 0000000..596399f
--- /dev/null
+++ b/docs/rules/periphery/p040-m2_dotdash.csv
@@ -0,0 +1,19 @@
+Name,Description,Flags,Value
+(m2.-),"Algorithm should flag errors, for met2, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm2 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. Required for IP, Recommended for Chip-level.",RC,
+(m2.1),Width of metal 2,,0.140
+(m2.2),Spacing of metal 2 to metal 2,,0.140
+(m2.3a),Min. spacing of features attached to or extending from huge_met2 for a distance of up to  0.280 um to metal2 (rule not checked over non-huge met2 features),,0.280
+(m2.3b),Min. spacing of huge_met2 to metal2 excluding features checked by m2.3a,,0.280
+(m2.3c),"Min spacing between floating_met2 with AR_met2_A >= 0.05 and AR_met2_B =< 0.032, outside areaid:sc must be greater than",RR,0.145
+(m2.4),Via must be enclosed by Met2 by at least …,P AL,0.055
+(m2.5),Via must be enclosed by Met2 on one of two adjacent sides by at least …,AL,0.085
+(m2.6),Min metal2 area [um2],,0.0676
+(m2.7),Min area of metal2 holes [um2],,0.140
+(m2.pd.1),Min MM2_oxide_Pattern_density,RR,0.7
+(m2.pd.2a),Rule m2.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700
+(m2.pd.2b),Rule m2.pd.1 has to be checked by dividing the chip into steps of …,A,70
+(m2.11),Max width of metal2,CU,4.000
+(m2.12),Add slots and remove vias and contacts if met2 wider than…..,CU,3.200
+(m2.13),Max pattern density (PD) of metal2,CU,0.77
+(m2.14),Met2 PD window size,CU,50.000
+(m2.14a),Met2 PD window step,CU,25.000
diff --git a/docs/rules/periphery/p040-m2_dotdash.svg b/docs/rules/periphery/p040-m2_dotdash.svg
new file mode 100644
index 0000000..0a752e2
--- /dev/null
+++ b/docs/rules/periphery/p040-m2_dotdash.svg
@@ -0,0 +1,508 @@
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diff --git a/docs/rules/periphery/p041-via2_dotdash.csv b/docs/rules/periphery/p041-via2_dotdash.csv
new file mode 100644
index 0000000..99f3805
--- /dev/null
+++ b/docs/rules/periphery/p041-via2_dotdash.csv
@@ -0,0 +1,20 @@
+Name,Description,Flags,Value
+(via2.X.1),Via2 connects met2 to met3 in the SKY130T*/SKY130P*/SP8Q/SP8P* flow and met2/capm to met3 in the SKY130DI* flow.,,
+(via2.1a),Min and max L and W of via2 (except for rule via2.1b/1c/1d/1e/1f),AL,0.200
+(via2.1b),"Three sizes of square Vias allowed inside areaid:mt: 0.280um, 1.2 um and 1.5 um",AL,N/A
+(via2.1c),Two sizes of square Vias allowed inside areaid:mt: 1.2 um and 1.5 um,AL,N/A
+(via2.1d),"Four sizes of square Vias allowed inside areaid:mt: 0.2um, 0.280um, 1.2 um and 1.5 um",AL,
+(via2.1e),"Three sizes of square Vias allowed inside areaid:mt: 0.8um, 1.2 um and 1.5 um",AL,N/A
+(via2.1f),Two sizes of square Vias allowed outside areaid:mt: 0.8um and 1.2 um,AL,N/A
+(via2.2),Spacing of via2 to via2,AL,0.200
+(via2.3),Only min. square via2s are allowed except die seal ring where via2s are (Via2 CD)*L,AL,0.2*L
+(via2.4),Via2 must be enclosed by Met2 by at least …,AL,0.040
+(via2.4a),"Inside :drc_tag:`areaid.mt`, 1.5 um Via2 must be enclosed by met2 by atleast",,0.140
+(via2.5),Via2 must be enclosed by Met2 on one of two adjacent sides by at least …,AL,0.085
+(via2.11),Min and max L and W of via2,CU,0.210
+(via2.12),Min spacing between via2's,CU,0.180
+(via2.13),Min spacing between via2 rows,CU,0.200
+(via2.14),Via2 must be enclosed by met2 by atleast,CU,0.035
+(via2.irdrop.1),"For 1 <= n <= 2 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.0
+(via2.irdrop.2),"For 3 <= n <= 4 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.6
+(via2.irdrop.3),"For 5 <= n <= 30 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.79
diff --git a/docs/rules/periphery/p041-via2_dotdash.svg b/docs/rules/periphery/p041-via2_dotdash.svg
new file mode 100644
index 0000000..d75d99d
--- /dev/null
+++ b/docs/rules/periphery/p041-via2_dotdash.svg
@@ -0,0 +1,342 @@
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diff --git a/docs/rules/periphery/p042-m3_dotdash.csv b/docs/rules/periphery/p042-m3_dotdash.csv
new file mode 100644
index 0000000..d5e119c
--- /dev/null
+++ b/docs/rules/periphery/p042-m3_dotdash.csv
@@ -0,0 +1,21 @@
+Name,Description,Flags,Value
+(m3.-),"Algorithm should flag errors, for met3, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm3 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. NOTE: Required for IP, Recommended for Chip-level.",RC,
+(m3.1),Width of metal 3,,0.300
+(m3.2),Spacing of metal 3 to metal 3,,0.300
+(m3.3a),Min. spacing of features attached to or extending from huge_met3 for a distance of up to 0.480 um to metal3  (rule not checked over non-huge met3 features),,N/A
+(m3.3b),Min. spacing of huge_met3 to metal3 excluding features checked by m3.3a,,N/A
+(m3.3c),Min. spacing of features attached to or extending from huge_met3 for a distance of up to 0.400 um to metal3  (rule not checked over non-huge met3 features),,0.400
+(m3.3d),Min. spacing of huge_met3 to metal3 excluding features checked by m3.3a,,0.400
+(m3.4),Via2 must be enclosed by Met3 by at least …,AL,0.065
+(m3.5),Via2 must be enclosed by Met3 on one of two adjacent sides by at least …,,N/A
+(m3.5a),Via2 must be enclosed by Met3 on all sides by at least …(Rule not checked on a layout when it satisfies both rules m3.4 and m3.5),,N/A
+(m3.6),Min area of metal3,,0.240
+(m3.7),Min area of metal3 holes [um2],CU,0.200
+(m3.pd.1),Min MM3_oxide_Pattern_density,RR,0.7
+(m3.pd.2a),Rule m3.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700
+(m3.pd.2b),Rule m3.pd.1 has to be checked by dividing the chip into steps of …,A,70
+(m3.11),Max width of metal3,CU,4.000
+(m3.12),Add slots and remove vias and contacts if wider than…..,CU,3.200
+(m3.13),Max pattern density (PD) of metal3,CU,0.77
+(m3.14),Met3 PD window size,CU,50.000
+(m3.14a),Met3 PD window step,CU,25.000
diff --git a/docs/rules/periphery/p042-m3_dotdash.svg b/docs/rules/periphery/p042-m3_dotdash.svg
new file mode 100644
index 0000000..7293420
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diff --git a/docs/rules/periphery/p042-via3_dotdash.csv b/docs/rules/periphery/p042-via3_dotdash.csv
new file mode 100644
index 0000000..ceef81d
--- /dev/null
+++ b/docs/rules/periphery/p042-via3_dotdash.csv
@@ -0,0 +1,14 @@
+Name,Description,Flags,Value
+(via3.1),Min and max L and W of via3 (except for rule via3.1a),AL,0.200
+(via3.1a),Two sizes of square via3 allowed inside :drc_tag:`areaid.mt`: 0.200um and 0.800um,AL,
+(via3.2),Spacing of via3 to via3,AL,0.200
+(via3.3),Only min. square via3s are allowed except die seal ring where via3s are (Via3 CD)*L,,0.2*L
+(via3.4),Via3 must be enclosed by Met3 by at least …,AL,0.060
+(via3.5),Via3 must be enclosed by Met3 on one of two adjacent sides by at least …,AL,0.090
+(via3.11),Min and max L and W of via3,CU,0.210
+(via3.12),Min spacing between via2's,CU,0.180
+(via3.13),Via3 must be enclosed by Met3 by at least …,CU,0.055
+(via3.14),Min spacing between via3 rows,CU,0.350
+(via3.irdrop.1),"For 1 <= n <= 2 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.0
+(via3.irdrop.2),"For 3 <= n <= 15 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.6
+(via3.irdrop.3),"For 16 <= n <= 30 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.8
diff --git a/docs/rules/periphery/p043-indm_dotdash.csv b/docs/rules/periphery/p043-indm_dotdash.csv
new file mode 100644
index 0000000..9eb7b0e
--- /dev/null
+++ b/docs/rules/periphery/p043-indm_dotdash.csv
@@ -0,0 +1,4 @@
+Name,Description,Flags,Value
+(indm.1),Min width of top_indmMetal,,N/A
+(indm.2),Min spacing between two top_indmMetal,,N/A
+(indm.3),top_padVia must  be enclosed by top_indmMetal by atleast,,N/A
diff --git a/docs/rules/periphery/p043-indm_dotdash.svg b/docs/rules/periphery/p043-indm_dotdash.svg
new file mode 100644
index 0000000..1731ec9
--- /dev/null
+++ b/docs/rules/periphery/p043-indm_dotdash.svg
@@ -0,0 +1,275 @@
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+  <rdf:RDF>
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diff --git a/docs/rules/periphery/p043-nsm_dotdash.csv b/docs/rules/periphery/p043-nsm_dotdash.csv
new file mode 100644
index 0000000..bb38dfd
--- /dev/null
+++ b/docs/rules/periphery/p043-nsm_dotdash.csv
@@ -0,0 +1,5 @@
+Name,Description,Flags,Value
+(nsm.1),Min. width of nsm,,3.000
+(nsm.2),Min. spacing of nsm to nsm,,4.000
+(nsm.3),"Min spacing, no overlap, between NSM_keepout to diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5). Exempt the following from the check: (a) cell name ""nikon*"" and (b) diff ring inside :drc_tag:`areaid.sl`",AL,1.000
+(nsm.3a),"Min enclosure of diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5) by :drc_tag:`areaid.ft`. Exempt the following from the check: (a) cell name ""s8Fab_crntic*""  (b)  blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)",,3.000
diff --git a/docs/rules/periphery/p044-m4_dotdash.csv b/docs/rules/periphery/p044-m4_dotdash.csv
new file mode 100644
index 0000000..5853cfb
--- /dev/null
+++ b/docs/rules/periphery/p044-m4_dotdash.csv
@@ -0,0 +1,19 @@
+Name,Description,Flags,Value
+(m4.-),"Algorithm should flag errors, for met4, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm4 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. Required for IP, Recommended for Chip-level.",RC,
+(m4.1),Min width of met4,,0.300
+(m4.2),Min spacing between two met4,,0.300
+(m4.3),via3 must  be enclosed by met4 by atleast,AL,0.065
+(m4.4),Min area of met4 (rule exempted for probe pads which are exactly 1.42um by 1.42um),,N/A
+(m4.4a),Min area of met4,,0.240
+(m4.5a),Min. spacing of features attached to or extending from huge_met4 for a distance of up to  0.400 um to metal4 (rule not checked over non-huge met4 features),,0.400
+(m4.5b),Min. spacing of huge_met4 to metal4 excluding features checked by m4.5a,,0.400
+(m4.7),Min area of meta4 holes [um2],CU,0.200
+(m4.pd.1),Min MM4_oxide_Pattern_density,RR,0.7
+(m4.pd.2a),Rule m4.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700
+(m4.pd.2b),Rule m4.pd.1 has to be checked by dividing the chip into steps of …,A,70
+(m4.11),Max width of metal4,CU,10.000
+(m4.12),Add slots and remove vias and contacts if wider than…..,CU,10.000
+(m4.13),Max pattern density (PD) of metal4; met4 overlapping pdm areas are excluded from the check,CU,0.77
+(m4.14),Met4 PD window size,CU,50.000
+(m4.14a),Met4 PD window step,CU,25.000
+(m4.15),Via3 must be enclosed by met4 by at least…,CU,0.060
diff --git a/docs/rules/periphery/p044-m4_dotdash.svg b/docs/rules/periphery/p044-m4_dotdash.svg
new file mode 100644
index 0000000..cf0beed
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+++ b/docs/rules/periphery/p044-m4_dotdash.svg
@@ -0,0 +1,496 @@
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diff --git a/docs/rules/periphery/p044-m5_dotdash.csv b/docs/rules/periphery/p044-m5_dotdash.csv
new file mode 100644
index 0000000..1851b99
--- /dev/null
+++ b/docs/rules/periphery/p044-m5_dotdash.csv
@@ -0,0 +1,4 @@
+Name,Description,Flags,Value
+(m5.1),Min width of met5,,1.600
+(m5.2),Min spacing between two met5,,1.600
+(m5.3),via4 must  be enclosed by met5 by atleast,,0.310
diff --git a/docs/rules/periphery/p044-via4_dotdash.csv b/docs/rules/periphery/p044-via4_dotdash.csv
new file mode 100644
index 0000000..57b812b
--- /dev/null
+++ b/docs/rules/periphery/p044-via4_dotdash.csv
@@ -0,0 +1,8 @@
+Name,Description,Flags,Value
+(via4.1),Min and max L and W of via4,,0.800
+(via4.2),Spacing of via4 to via4,,0.800
+(via4.3),Only min. square via4s are allowed except die seal ring where via4s are (Via4 CD)*L,,0.8*L
+(via4.4),Via4 must be enclosed by Met4 by at least …,,0.190
+(via4.irdrop.1),"For 1 <= n <= 4 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.0
+(via4.irdrop.2),"For 5 <= n <= 10 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.2
+(via4.irdrop.3),"For 11 <= n <= 100 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.5
diff --git a/docs/rules/periphery/p045-pad_dotdash.csv b/docs/rules/periphery/p045-pad_dotdash.csv
new file mode 100644
index 0000000..070e41b
--- /dev/null
+++ b/docs/rules/periphery/p045-pad_dotdash.csv
@@ -0,0 +1,2 @@
+Name,Description,Flags,Value
+(pad.2),Min spacing of pad:dg to pad:dg,,1.270
diff --git a/docs/rules/periphery/p045-rdl_dotdash.csv b/docs/rules/periphery/p045-rdl_dotdash.csv
new file mode 100644
index 0000000..be0d2b7
--- /dev/null
+++ b/docs/rules/periphery/p045-rdl_dotdash.csv
@@ -0,0 +1,6 @@
+Name,Description,Flags,Value
+(rdl.1),Min width of rdl,,10
+(rdl.2),Min spacing between two rdl,,10
+(rdl.3),"Min enclosure of pad by rdl, except rdl interacting with bump",,10.750
+(rdl.4),Min spacing between rdl and outer edge of the seal ring,,15.000
+(rdl.5),(rdl OR ccu1m.mk) must not overlap :drc_tag:`areaid.ft`. Exempt the following from the check: (a)  blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption),,
diff --git a/docs/rules/periphery/p046-mf_dotdash.csv b/docs/rules/periphery/p046-mf_dotdash.csv
new file mode 100644
index 0000000..41272d2
--- /dev/null
+++ b/docs/rules/periphery/p046-mf_dotdash.csv
@@ -0,0 +1,25 @@
+Name,Description,Flags,Value
+(mf.1),Min. and max width of fuse,,0.800
+(mf.2),Length of fuse,,7.200
+(mf.3),Spacing between centers of adjacent fuses,,2.760
+(mf.4),Spacing between center of fuse and fuse_metal (fuse shields are exempted),,3.300
+(mf.5),Max. extension of fuse_metal beyond fuse boundary,,0.830
+(mf.6),Spacing (no overlapping) between fuse center and Metal1,,3.300
+(mf.7),Spacing (no overlapping) between fuse center and LI,,3.300
+(mf.8),Spacing (no overlapping) between fuse center and poly,,2.660
+(mf.9),Spacing (no overlapping) between fuse center and tap,,2.640
+(mf.10),Spacing (no overlapping) between fuse center and diff,,3.250
+(mf.11),Spacing (no overlapping) between fuse center and nwell,,3.320
+(mf.12),Size of  fuse_shield,,0.5x2.4
+(mf.13),Min. spacing of center of fuse to fuse_shield,,2.200
+(mf.14),Max. spacing of center of fuse to fuse_shield,,3.300
+(mf.15),"Fuse_shields are only placed between periphery metal (i.e., without fuse:dg) and non-isolated edges of fuse as defined by mf.16",,
+(mf.16),The edge of a fuse is considered non-isolated if wider than or equal to mf.2 and spaced to fuse_metal by less than …,,4.000
+(mf.17),Offset between fuse_shields center and fuse center,NC,0.000
+(mf.18),Min and max space between fuse_shield and fuse_metal (opposite edges). Rule checked within 1 gridpoint.,,0.600
+(mf.19),Spacing (no overlapping) between fuse center and Metal2,,3.300
+(mf.20),Only one fuse per metal line allowed,,
+(mf.21),"Min spacing , no overlap, between metal3 and fuse center",,3.300
+(mf.22),Min spacing between fuse_contact to fuse_contact,,1.960
+(mf.23),Spacing (no overlapping) between fuse center and Metal4,,N/A
+(mf.24),Spacing (no overlapping) between fuse center and Metal5,,3.300
diff --git a/docs/rules/periphery/p046-mf_dotdash.svg b/docs/rules/periphery/p046-mf_dotdash.svg
new file mode 100644
index 0000000..36504c9
--- /dev/null
+++ b/docs/rules/periphery/p046-mf_dotdash.svg
@@ -0,0 +1,1605 @@
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diff --git a/docs/rules/periphery/p047-hvi_dotdash.csv b/docs/rules/periphery/p047-hvi_dotdash.csv
new file mode 100644
index 0000000..869cd60
--- /dev/null
+++ b/docs/rules/periphery/p047-hvi_dotdash.csv
@@ -0,0 +1,5 @@
+Name,Description,Flags,Value
+(hvi.1),Min width of Hvi,P,0.600
+(hvi.2a),Min spacing of Hvi to Hvi,P,0.700
+(hvi.2b),Manual merge if space is below minimum,,
+(hvi.4),Hvi must not overlap tunm,,
diff --git a/docs/rules/periphery/p047-hvi_dotdash.svg b/docs/rules/periphery/p047-hvi_dotdash.svg
new file mode 100644
index 0000000..0dd2197
--- /dev/null
+++ b/docs/rules/periphery/p047-hvi_dotdash.svg
@@ -0,0 +1,663 @@
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diff --git a/docs/rules/periphery/p047-hvnwell_dotdash.csv b/docs/rules/periphery/p047-hvnwell_dotdash.csv
new file mode 100644
index 0000000..372fb01
--- /dev/null
+++ b/docs/rules/periphery/p047-hvnwell_dotdash.csv
@@ -0,0 +1,4 @@
+Name,Description,Flags,Value
+(hvnwell.8),Min space between HV_nwell  and any nwell on different nets,,2.000
+(hvnwell.9),(Nwell overlapping hvi) must be enclosed by hvi,,
+(hvnwell.10),"LVnwell and HnWell should not be on the same net (for the purposes of this check, short the connectivity through resistors); Exempt HnWell with li nets tagged ""lv_net"" using text.dg and Hnwell connected to nwell overlapping :drc_tag:`areaid.hl`",TC,
diff --git a/docs/rules/periphery/p047-hvnwell_dotdash.svg b/docs/rules/periphery/p047-hvnwell_dotdash.svg
new file mode 100644
index 0000000..a6e3484
--- /dev/null
+++ b/docs/rules/periphery/p047-hvnwell_dotdash.svg
@@ -0,0 +1,238 @@
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diff --git a/docs/rules/periphery/p048-hvdifftap_dotdash.csv b/docs/rules/periphery/p048-hvdifftap_dotdash.csv
new file mode 100644
index 0000000..6685179
--- /dev/null
+++ b/docs/rules/periphery/p048-hvdifftap_dotdash.csv
@@ -0,0 +1,15 @@
+Name,Description,Flags,Value
+(hvdifftap.14),"Min width of diff inside Hvi, except HV Pdiff resistors (difftap.14a)",P,0.290
+(hvdifftap.14a),"Min width of diff inside Hvi, HV Pdiff resistors only",P,0.150
+(hvdifftap.15a),Min space of Hdiff to Hdiff,P,0.300
+(hvdifftap.15b),Min space of n+diff to non-abutting p+tap inside Hvi,P,0.370
+(hvdifftap.16),Min width tap butting diff on one or two sides inside Hvi (rule exempted inside UHVI),,0.700
+(hvdifftap.17),P+ Hdiff or Pdiff inside areaid:hvnwell must be enclosed by Hv_nwell by at least ….[Rule exempted inside UHVI],DE NE,0.330
+(hvdifftap.18),Spacing of N+ diff to HV_nwell (rule exempted inside UHVI),DE NE,0.430
+(hvdifftap.19),N+ Htap must be enclosed by Hv_nwell by at least …Rule exempted inside UHVI.,NE,0.330
+(hvdifftap.20),Spacing of P+ tap to HV_nwell (Exempted for p+tap butting pwell.rs; rule exempted inside UHVI),,0.430
+(hvdifftap.21),Diff or tap cannot straddle Hvi,P,
+(hvdifftap.22),Min enclosure of Hdiff or Htap by Hvi. Rule exempted inside UHVI.,P,0.180
+(hvdifftap.23),Space between diff or tap outside Hvi and Hvi,P,0.180
+(hvdifftap.24),Spacing of nwell to N+ Hdiff (rule exempted inside UHVI),DE NE,0.430
+(hvdifftap.25),Min space of N+ Hdiff inside HVI across non-abutting P+_tap,NC,1.070
diff --git a/docs/rules/periphery/p048-hvdifftap_dotdash.svg b/docs/rules/periphery/p048-hvdifftap_dotdash.svg
new file mode 100644
index 0000000..4289bbe
--- /dev/null
+++ b/docs/rules/periphery/p048-hvdifftap_dotdash.svg
@@ -0,0 +1,1163 @@
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diff --git a/docs/rules/periphery/p049-hvntm_dotdash.csv b/docs/rules/periphery/p049-hvntm_dotdash.csv
new file mode 100644
index 0000000..90b6126
--- /dev/null
+++ b/docs/rules/periphery/p049-hvntm_dotdash.csv
@@ -0,0 +1,11 @@
+Name,Description,Flags,Value
+(hvntm.X.1 ),Hvntm can be drawn inside HVI. Drawn layer will be OR-ed with the CL and rechecked for CLDRC,,
+(hvntm.1),Width of hvntm,P,0.700
+(hvntm.2),Spacing of hvntm to hvntm,P,0.700
+(hvntm.3),Min. enclosure of (n+_diff inside Hvi) but not overlapping :drc_tag:`areaid.ce` by hvntm,P,0.185
+(hvntm.4),"Space, no overlap, between n+_diff outside Hvi and hvntm",P,0.185
+(hvntm.5),"Space, no overlap, between p+_diff  and hvntm",P DE,0.185
+(hvntm.6a),"Space, no overlap, between p+_tap and hvntm (except along the diff-butting edge)",P,0.185
+(hvntm.6b),"Space, no overlap, between p+_tap and hvntm along the diff-butting edge",P,0.000
+(hvntm.7),hvntm must enclose ESD_nwell_tap inside hvi by atleast,P,0.000
+(hvntm.9),Hvntm must not overlap :drc_tag:`areaid.ce`,,
diff --git a/docs/rules/periphery/p049-hvntm_dotdash.svg b/docs/rules/periphery/p049-hvntm_dotdash.svg
new file mode 100644
index 0000000..59beef1
--- /dev/null
+++ b/docs/rules/periphery/p049-hvntm_dotdash.svg
@@ -0,0 +1,3480 @@
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diff --git a/docs/rules/periphery/p049-hvpoly_dotdash.csv b/docs/rules/periphery/p049-hvpoly_dotdash.csv
new file mode 100644
index 0000000..0453e91
--- /dev/null
+++ b/docs/rules/periphery/p049-hvpoly_dotdash.csv
@@ -0,0 +1,2 @@
+Name,Description,Flags,Value
+(hvpoly.13),Min width of poly over diff inside Hvi,P,0.500
diff --git a/docs/rules/periphery/p049-hvpoly_dotdash.svg b/docs/rules/periphery/p049-hvpoly_dotdash.svg
new file mode 100644
index 0000000..2e8ab5c
--- /dev/null
+++ b/docs/rules/periphery/p049-hvpoly_dotdash.svg
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diff --git a/docs/rules/periphery/p050-denmos_dotdash.csv b/docs/rules/periphery/p050-denmos_dotdash.csv
new file mode 100644
index 0000000..f743bec
--- /dev/null
+++ b/docs/rules/periphery/p050-denmos_dotdash.csv
@@ -0,0 +1,15 @@
+Name,Description,Flags,Value
+(denmos.1),Min width of de_nFet_gate,,1.055
+(denmos.2),Min width of de_nFet_source not overlapping poly,,0.280
+(denmos.3),Min width of de_nFet_source overlapping poly,,0.925
+(denmos.4),Min width of the de_nFet_drain,,0.170
+(denmos.5),Min/Max extension of de_nFet_source over nwell,,0.225
+(denmos.6),Min/Max spacing between de_nFet_drain and de_nFet_source,,1.585
+(denmos.7),Min channel width for de_nFet_gate,,5.000
+(denmos.8),90 degree angles are not permitted for nwell overlapping de_nFET_drain,,
+(denmos.9a),"All bevels on nwell are 45 degree, 0.43 um from corners",NC,
+(denmos.9b),"All bevels on de_nFet_drain are 45 degree, 0.05 um from corners",NC,
+(denmos.10),Min enclosure of de_nFet_drain by nwell,,0.660
+(denmos.11),Min spacing between p+ tap and (nwell overlapping de_nFet_drain),,0.860
+(denmos.12),Min spacing between nwells overlapping de_nFET_drain,,2.400
+(denmos.13),de_nFet_source must be enclosed by nsdm by,,0.130
diff --git a/docs/rules/periphery/p050-denmos_dotdash.svg b/docs/rules/periphery/p050-denmos_dotdash.svg
new file mode 100644
index 0000000..b70a189
--- /dev/null
+++ b/docs/rules/periphery/p050-denmos_dotdash.svg
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diff --git a/docs/rules/periphery/p051-depmos_dotdash.csv b/docs/rules/periphery/p051-depmos_dotdash.csv
new file mode 100644
index 0000000..fe7ac8a
--- /dev/null
+++ b/docs/rules/periphery/p051-depmos_dotdash.csv
@@ -0,0 +1,14 @@
+Name,Description,Flags,Value
+(depmos.1),Min width of de_pFet_gate,,1.050
+(depmos.2),Min width of de_pFet_source not overlapping poly,,0.280
+(depmos.3),Min width of de_pFet_source overlapping poly,,0.920
+(depmos.4),Min width of the de_pFet_drain,,0.170
+(depmos.5),Min/Max extension of de_pFet_source beyond nwell,,0.260
+(depmos.6),Min/Max spacing between de_pFet_drain and de_pFet_source,,1.190
+(depmos.7),Min channel width for de_pFet_gate,,5.000
+(depmos.8),90 degree angles are not permitted for nwell hole overlapping de_pFET_drain,,
+(depmos.9a),"All bevels on nwell hole are 45 degree, 0.43 um from corners",NC,
+(depmos.9b),"All bevels on de_pFet_drain are 45 degree, 0.05 um from corners",NC,
+(depmos.10),Min enclosure of de_pFet_drain by nwell hole,,0.860
+(depmos.11),Min spacing between n+ tap and (nwell hole enclosing de_pFET_drain),,0.660
+(depmos.12),de_pFet_source must be enclosed by psdm by,,0.130
diff --git a/docs/rules/periphery/p051-depmos_dotdash.svg b/docs/rules/periphery/p051-depmos_dotdash.svg
new file mode 100644
index 0000000..7ca8704
--- /dev/null
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diff --git a/docs/rules/periphery/p052-extd_dotdash.csv b/docs/rules/periphery/p052-extd_dotdash.csv
new file mode 100644
index 0000000..8052ab7
--- /dev/null
+++ b/docs/rules/periphery/p052-extd_dotdash.csv
@@ -0,0 +1,8 @@
+Name,Description,Flags,Value
+(extd.1),Difftap cannot straddle areaid:en,,
+(extd.2),DiffTap must have 2 or 3 coincident edges with areaid:en if enclosed by areaid:en,,
+(extd.3),Poly must not be entirely overlapping difftap in areaid:en,,
+(extd.4),"Only cell name ""s8rf_n20vhv1*"" is a valid cell name for n20vhv1 device  (Check in LVS as invalid device)",,N/A
+(extd.5),"Only cell name ""s8rf_n20vhviso1"" is a valid cell name for n20vhviso1 device  (Check in LVS as invalid device)",,N/A
+(extd.6),"Only cell name ""s8rf_p20vhv1"" is a valid cell name for p20vhv1 device  (Check in LVS as invalid device)",,N/A
+(extd.7),"Only cell name ""s8rf_n20nativevhv1*"" is a valid cell name for n20nativevhv1 device  (Check in LVS as invalid device)",,N/A
diff --git a/docs/rules/periphery/p052-extd_dotdash.svg b/docs/rules/periphery/p052-extd_dotdash.svg
new file mode 100644
index 0000000..71fcb0e
--- /dev/null
+++ b/docs/rules/periphery/p052-extd_dotdash.svg
@@ -0,0 +1,450 @@
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diff --git a/docs/rules/periphery/p054-hv_dotdash_dotdash.csv b/docs/rules/periphery/p054-hv_dotdash_dotdash.csv
new file mode 100644
index 0000000..dea777f
--- /dev/null
+++ b/docs/rules/periphery/p054-hv_dotdash_dotdash.csv
@@ -0,0 +1,19 @@
+Name,Description,Flags,Value
+(hv.X.1),High voltage source/drain regions must be tagged by diff:hv,,
+(hv.X.3),"High voltage poly can be drawn over multiple diff regions that are ALL reverse-biased by at least 300 mV (existence of reverse-bias is not checked by the CAD flow).  It can also be drawn over multiple diffs when all sources and all drain are shorted together. In these case, the high voltage poly can be tagged with the text:dg label with a value “hv_bb”.  Exceptions to this use of the hv_bb label must be approved by technology.  Under certain bias conditions, high voltage poly tagged with hv_bb can cross an nwell boundary. The poly of the drain extended device crosses nwell by construction and can be tagged with the ""hv_bb"" label. Use of the hv_bb label on high voltage poly crossing an nwell boundary must be approved by technology. All high voltage poly tagged with hv_bb will not be checked to hv.poly.1, hv.poly.2, hv.poly.3 and hv.poly.4.",,
+(hv.X.4),Any piece of layout that is shorted to hv_source/drain becomes a high voltage feature.,,
+(hv.X.5),"In cases where an hv poly gate abuts only low voltage source and drain, the poly gate can be tagged with the text:dg label with a value ""hv_lv"".  In this case, the ""hv_lv"" tagged poly gate and its extensions will not be checked to hv.poly.6, but is checked by rules in the poly.-.- section.  The use of the hv_lv label must be approved by technology.",,
+(hv.X.6),"Nwell biased at voltages >= 7.2V must be tagged with text ""shv_nwell""",NC,
+(hv.nwell.1),"Min spacing of nwell tagged with text ""shv_nwell"" to any nwell on different nets",,2.500
+(hv.diff.1a),Minimum hv_source/drain spacing to diff for edges of hv_source/drain and diff not butting tap,,0.300
+(hv.diff.1b),Minimum spacing of (n+/p+ diff resistors and diodes) connected to hv_source/drain to diff,,0.300
+(hv.diff.2),Minimum spacing of nwell connected to hv_source/drain to n+ diff,DE,0.430
+(hv.diff.3a),Minimum n+ hv_source/drain spacing to nwell,,0.550
+(hv.diff.3b),Minimum spacing of (n+ diff resistors and diodes) connected to hv_source/drain to nwell,,0.550
+(hv.poly.1),Hv poly feature hvPoly (including hv poly resistors) can be drawn over only one diff region and is not allowed to cross nwell boundary except (1) as allowed in rule .X.3 and (2) nwell hole boundary in depmos,,
+(hv.poly.2),Min spacing of hvPoly (including hv poly resistor) on field to diff (diff butting hvPoly are excluded),,0.300
+(hv.poly.3),Min spacing of hvPoly (including hv poly resistor) on field to n-well (exempt poly stradding nwell in a denmos/depmos),,0.550
+(hv.poly.4),Enclosure of hvPoly (including hv poly resistor) on field by n-well (exempt poly stradding nwell in a denmos/depmos),,0.300
+(hv.poly.6a),Min extension of poly beyond hvFET_gate (exempt poly extending beyond diff along the S/D direction in a denmos/depmos),,0.160
+(hv.poly.6b),Extension of hv poly beyond FET_gate (including hvFET_gate; exempt poly extending beyond diff along the S/D direction in a denmos/depmos),,0.160
+(hv.poly.7),Minimum overlap of hv poly ring_FET and diff,,
diff --git a/docs/rules/periphery/p054-hv_dotdash_dotdash.svg b/docs/rules/periphery/p054-hv_dotdash_dotdash.svg
new file mode 100644
index 0000000..3f63d6b
--- /dev/null
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diff --git a/docs/rules/periphery/p055-uhvi_dotdash_dotdash.csv b/docs/rules/periphery/p055-uhvi_dotdash_dotdash.csv
new file mode 100644
index 0000000..553a0a3
--- /dev/null
+++ b/docs/rules/periphery/p055-uhvi_dotdash_dotdash.csv
@@ -0,0 +1,10 @@
+Name,Description,Flags,Value
+(uhvi.1.-),diff/tap can not straddle UHVI,,N/A
+(uhvi.2.-),poly can not straddle UHVI,,N/A
+(uhvi.3.-),pwbm.dg must be enclosed by UHVI (exempt inside :drc_tag:`areaid.lw`),,N/A
+(uhvi.4.-),dnw.dg can not straddle UHVI,,N/A
+(uhvi.5.-),UHVI must enclose :drc_tag:`areaid.ext`,,N/A
+(uhvi.6.-),UHVI must enclose dnwell,,N/A
+(uhvi.7.-),natfet.dg must be enclosed by UHVI layer by at least,,N/A
+(uhvi.8.-),Minimum width of natfet.dg,,N/A
+(uhvi.9.-),Minimum Space spacing of natfet.dg,,N/A
diff --git a/docs/rules/periphery/p055-ulvt-_dotdash.csv b/docs/rules/periphery/p055-ulvt-_dotdash.csv
new file mode 100644
index 0000000..39ce63b
--- /dev/null
+++ b/docs/rules/periphery/p055-ulvt-_dotdash.csv
@@ -0,0 +1,3 @@
+Name,Description,Flags,Value
+(ulvt-.1),":drc_tag:`areaid.low_vt` must enclose dnw for the UHV dnw-psub diode texted ""condiodeHvPsub""",,NA
+(ulvt-.2),":drc_tag:`areaid.low_vt` must enclose pwbm.dg for the UHV dnw-psub diode texted ""condiodeHvPsub""",,NA
diff --git a/docs/rules/periphery/p055-vhvi_dotdash_dotdash.csv b/docs/rules/periphery/p055-vhvi_dotdash_dotdash.csv
new file mode 100644
index 0000000..9cede56
--- /dev/null
+++ b/docs/rules/periphery/p055-vhvi_dotdash_dotdash.csv
@@ -0,0 +1,14 @@
+Name,Description,Flags,Value
+(vhvi.vhv.1),Terminals operating at nominal 12V (maximum 16V) bias must be tagged as Very-High-Voltage (VHV) using vhvi:dg layer,NC,
+(vhvi.vhv.2),A source or drain of a drain-extended device can be tagged by vhvi:dg. A device with either source or drain (not both) tagged with vhvi:dg serves as a VHV propagation stopper,NC,
+(vhvi.vhv.3),Any feature connected to VHVSourceDrain becomes a very-high-voltage feature,NC,
+(vhvi.vhv.4),Any feature connected to VHVPoly becomes a very-high-voltage feature,NC,
+(vhvi.vhv.5),"Diffusion that is not a part of a drain-extended device (i.e., diff not areaid:en) must not be on the same net as VHVSourceDrain. Only diffusion inside :drc_tag:`areaid.ed` and LV diffusion tagged with vhvi:dg are exempted.",,
+(vhvi.vhv.6),"Poly resistor can act as a VHV propagation stopper. For this, it should be tagged with text ""vhv_block""",NC,
+(vhvi.1.-),Min width of vhvi:dg,,0.020
+(vhvi.2.-),Vhvi:dg cannot overlap areaid:ce,,
+(vhvi.3.-),VHVGate must overlap hvi:dg,,
+(vhvi.4.-),Poly connected to the same net as a VHVSourceDrain must be tagged with vhvi:dg layer,,
+(vhvi.5.-),Vhvi:dg cannot straddle VHVSourceDrain,,
+(vhvi.6.-),Vhvi:dg overlapping VHVSourceDrain must not overlap poly,,
+(vhvi.7.-),Vhvi:dg cannot straddle VHVPoly,,
diff --git a/docs/rules/periphery/p056-pwres_dotdash_dotdash.csv b/docs/rules/periphery/p056-pwres_dotdash_dotdash.csv
new file mode 100644
index 0000000..20d1b7f
--- /dev/null
+++ b/docs/rules/periphery/p056-pwres_dotdash_dotdash.csv
@@ -0,0 +1,12 @@
+Name,Description,Flags,Value
+(pwres.1.-),Pwell resistor has to be enclosed by the res layer,NC,
+(pwres.2.-),Min/Max width of pwell resistor,,2.650
+(pwres.3.-),Min length of pwell resistor,,26.500
+(pwres.4.-),Max length of pwell resistor,,265.00
+(pwres.5.-),Min/Max spacing of tap inside the pwell resistor to nwell,,0.220
+(pwres.6.-),Min/Max width of tap inside the pwell resistor,,0.530
+(pwres.7a.-),Every pwres_terminal must enclose 12 licon1,,
+(pwres.7b.-),Every pwres_terminal must enclose 12 mcons if routed through metal1,,
+(pwres.8.-),Diff or poly is not allowed in the pwell resistor.,,
+(pwres.9.-),Nwell surrounding the pwell resistor must have a full ring of contacted tap strapped with metal.,,
+(pwres.10.-),The res layer must abut pwres_terminal on opposite and parallel edges,,
diff --git a/docs/rules/periphery/p056-pwres_dotdash_dotdash.svg b/docs/rules/periphery/p056-pwres_dotdash_dotdash.svg
new file mode 100644
index 0000000..f234b5b
--- /dev/null
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diff --git a/docs/rules/periphery/p057-rfdiode_dotdash_dotdash.csv b/docs/rules/periphery/p057-rfdiode_dotdash_dotdash.csv
new file mode 100644
index 0000000..e4ca78f
--- /dev/null
+++ b/docs/rules/periphery/p057-rfdiode_dotdash_dotdash.csv
@@ -0,0 +1,7 @@
+Name,Description,Flags,Value
+(rfdiode.1.-),Only 90 degrees allowed for :drc_tag:`areaid.re`,,
+(rfdiode.2.-),:drc_tag:`areaid.re` must be coincident with nwell for the rf nwell diode,,
+(rfdiode.3.-),":drc_tag:`areaid.re` must be coincident with innwer edge of the nwell ring for the rf pwell-deep nwell diode
+Allowed PNP layout
+Layout: pnppar
+Allowed NPN layout",,
diff --git a/docs/rules/periphery/p057-rfdiode_dotdash_dotdash.svg b/docs/rules/periphery/p057-rfdiode_dotdash_dotdash.svg
new file mode 100644
index 0000000..5cfbb68
--- /dev/null
+++ b/docs/rules/periphery/p057-rfdiode_dotdash_dotdash.svg
@@ -0,0 +1,1267 @@
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q+jItCNgyBPfEgMC784A4D2J0QL5dGhYzi9Z8X2WRbpWyiZRyd6l5SNDa2vPicVXqQnVnlnhDPiDk1/vXYl0p2p5NaXvzL5cUb/nt8fiobdIiP8enEeSBeHs2AeLoLII7DwUHoBBjNhHgGc/7zIpvSs46VugJJ6J7WdFwv3rh9YWuU1jdqlYZgs+V6IT651wA0ivLZeqMpzovFo1Yx28AO2Xps8o8lK/H6pK3RlkxWkqPnYkcvPpvqjoTRdkbZzlgP6ZhYr4FvKIF4WAIcFri6LtDJrwfx6Rnm/OdFNjEdS8+akEwlCS0vvuXFx6Vj8UmRoC3cEPgoWTDVtsweWKVRHxbKqNEUxdChbD0dxT4X1A2Zs/xgXt6wA9MZPwUzfZ4+82QZNdkbBfZUNo1B/DAMHYntwC6LI7FLizys3EXe7H1GINfdOWqZnjNqJrgCWR3zuGLMKErxvXv2txZXS2qJmmSyazSabBZDyMwqq4N4LNh58XgxWPsnT2HLi9dsO7uW0uWHEAwhIzvqCSQL4m9Ux4KIwCAxEKeGwfJtKAuDWhvi5QRCLsMHF4VT8mTUUMnQ46PAqQAnqCXFWb8r8APz4rf5aUKm9QbEL5sXfwL5fn5ef/26ZIT3Tfd7eH//t3u9XqFwuVxwF8r3e4jxSutlt9+/P7qux/rT6RRCABOCeqPp8Yjn858QQoxXY8IaDcPACs4y7AJNGBeo7y+320f4Xotco9F0u8VhGKTA2a4s9/0lxqtcS1FZq2FNqE7nM+8ZYwIVOp1Ot9sg9Y3W3++h70/ncw8JjrLz798f5/OfGK99f6GaiXS/h/P59PdvorshhNstvb+H6/UKpxJlCMf8778/2i7U3G4xhND3/Z8/f+Rh2S4OfbvxQ4Xvk8sUcppahm/lDCGgQKQmBF1JHo8YcroXnq0PbbzvTzj6TKMI86wyW5OlrGQkwqBKaE2aVYYc+hlWCaqCKjpKoyidJ+f1gV6g0kKBGpyDZNGasJLWdyW3h7hkKgTWIVufcrfSo+4Jq4w/MmlyMmXdc2drGvu2wWQaHZeR/9WnVHJeZFOaF6hJk+LRWVUp2gIgFKmltGiPJWqSya5RWt+oVdpHZmXDi9eolqRJphlZFpQUqqZ9e4hNeH8dW9IkYbHPS9w7aXJHMvJ5dp8DFTKK139eZJNhlTCiDW1S95KisbElTeasUqLfqFXuCfGMqBsSzaRJutW6oRBRt9Iz+htNMuCVBVNtiypClYZ1yNanhbx4eZGjazSamG5RllF9Ssf04hehDT5TM210KuTUkiZL1FJatMcSs5KhZkXXKK1v1CqTQD+7XC/EJ3Pe7G5I64YnTCsbTaVePN3OJ/9YshItxFiXsXxN4JqQ07dmL7LwYF7eUDgVEtPeSsal6rTICaLnvdQVCCWWyFoDMYrktg7KssjCRy0xKxnPGp1WKdFv1Crrgvg4LxZPV2WX2a488hwvfo4izmcZ1QBbmNNYZsrKyYKm3shJFJ7Scgqp6VipXjlZJqjK9iyaZAwgsjGqe75sTDDeGiEeC56kyfS8bL/Usk1JSCfrxc9JZ9yGZVQDcHdBFuOOx7kWD0uD+FKi/i8Tpue8aCx+V2AyC9MoTVWca9mAJbtMGkB3ApEBSljvFLIB8csmTRZDfJoai/dILStcOcqhvXgbso2mRVgmyMrJ0iC+lNbz4m1XQDZpZdvGJ6vK9iyaZIqASJaZWLLyMcq4ECdVHYu3JTUqXGOUaRaylyKOakCRBTpZZsrKydJoGi2ukJqOleqVwVLkxS+iXTNZDMloQDSKUVmxMPQbtUpcjodaLL4urcqyjGqALcxpLFt68Y1KaXGF1HRsDe9hmqpsz6JJxgAiG6O6HMoXGe/+EL9sXrxfatkmNkqpF+/JWN+GJSux9KxzHiEXsUzw4tlaPCyNppFTu+R50bppCmMrSRGL9OJn5sWvzWIsuQiIDFDCev/ls9sX4hkhxKcWi5/BMqoBRtMiLBNk9Uose533LVk0HSvVK4PluF48W0vXYvFIFOKTOW92N5S+T8niKD/HQvZSxFENKLJAJ8tMWb0Sy17nfUsWTcdK9cpgkV78Ic57VjJdi8UDxRaLX4JlVANsYU5jaV787ud9SxZNx9bwHo513qVkuqn+e5dDeb9gU81efGx58S0v/rAsbPclWfyuQMuL75aL0mC9U8gGxLe8eO5fSHUf3RZ1XpBl1DMymhZhmSCrV2LZ67xvyaLpWKleGSzH9eLZWrpyd5OWmViy8jHKuBAntVh8XVqVZRnVgCILdLLMlNUrsex13rdk0XSsVK8MliIvvp7znpVM5wsXy3JWLAz9jHKNEB9bLH42y6gG2MKcxtK8+N3P+5Ysmo6t4T0c67xLyXRT/fcuh/J+waYavPiWF78GS1Zi6VnnPEIuYpngxU/Iiz8Ey2jnF2DRFMZWkiIW6cW3vHis918+cWJOarF471mHVezCMqoBRtMiLBNk9Uose533LVk0HSvVK4PluF48W0tX7m7SMhNLVj5GGRfipBaLr0ursiyjGlBkgU6WmbJ6JZa9zvuWLJqOleqVwSK9+EOc96xkOl+4WJazYmHoZ5RrhPjYYvGzWUY1wBbmNJbmxe9+3rdk0XRsDe/hWOddSqab6r93OZT3CzZt6MX/n/9jGvDn5fd7eDyuIYTz+XS7pRDC29sphIDl2y3d7wHrsQlZ4H/HjTKw0CY2ChDU4Chvb6dhGGilvd2Fhc48Kz2UGLJo3Saw0CkVraWxHIhF0zGpGKMKo7HcbskzJedaFmT5+zdltyGEv3/T/R6w8n4PwzAMw6ABURjDq/f3gIfCUQD92CisG5QN+vy8/vp1sXoUkfP6QAM1xq1KEp4jNnV1xOL3JXonlIRUWc+isr9bo9cmQ8fSQnpVp0YZOJC+vXhnlCYLRLKcnqEvCfSzyzhhJ1Udi5fd8BqjlY2mOCkWXwnEJ9O0Si3Qw1KnQTZaiWwdM5r8LHVq1KjtZ/HXQBgPEIUQKPRpUTJZrhHi47xYPG2SkmIsWhM9AUmcwqW8eHaLY3dzHhMoC7tr++91GmSjlUjTsTW8h1KaYDJ+8njxo3jFXMxsk8ZuH5mV94f4ZfPiGQu7HtI+dhPUl3rxNDfWJRQHxMs+nhPA7ARZ/JA9gWWCQU5QpsZSCYumMLJpMovUKOdaKIAuvvxR2zfczfSMMAb4ZOtbXvzIzZFEf6Mprh+LtyE+PJPzmCi6RRzzySyNXp4MHUsL6dVML36y+djk8eKz7mYSCAMFzSvV2JNAP7tcL8Qnc96xPBafrTeaSr34VBiL1/RPKugEiE+maZVaoIelQfyPIlvHjCY/y4IQvyDQj9p+Fn8pZDOEST68otAX64vFn1JKwZGmg1k+kDoJiVM0bYiWtyEcEZOijKwp3HqOfDqdoJC+lRJrJCVdcSWBoGiBlY2mySysc6PXJk3HQijTKydLERl2FL5NCfoUmRWQgQPhG7KmTLqQNFRk5fv9K0HcCUphcjKl8/pAXUL/p8w1lmDGuShLECGwEP5lL6VnL97zzWhG2YVT4TgFaFM2gG47TQuyGD5XPRHkxrIUi98Zn8xS5MXTtZTiUtEoTi8eyxrCIItskiyB+PXGKLLe8OJr/148K2tRGiPO5QmB0QOuF4tv1KjRLuQ0VUqTY/EhhzBGE60Pz7F4v+9bY6CG3ppdr9fL5XK9XkMIl8sFarLlbNPjEf/778/pdDqfezzm7RYTCYxkm/Am7n4PMV5LdCbcbkNpoKZRo0Z7USp0tt7eTufzYHTo+0uMV4ZRv39/hGeEochjNEH9798fXdcHE+6y5b6/7ByomZw0yeqzLDB09v7IbrIDNdp2ctJko0aNdqGsYdafNKmNIsubefG7BWqAtJsgo2nLQE1aKBZPReePrReV/d0avTYZOpYW0qvJGjUT4m2aHKhJAmGg4InnUPbkQHZarhfik3sNQKMon603muLmSZMLQnwyTavUAj0sDeJ/FNk6ZjT5WVaCeNpnwsFHbV96h3HppMnkRvkaIZ6e2m6JDxgkHb61piSycdLKXny2fibEp5UtkJUbxP8o0nRsDe+hlDx+0hyIH/Xi/e6m0WSzJB/Kbwbx/x63atIH6roLfEMYC85ytul8Hm63AevP5yHG1PenEMLtNlAW1tR1l74/Ud41CB/awGS0VqOPRpMlNoclhLCerBrVRhvo1WTrk49DpflAn9ttKHq0+Pl5HYZh9GPCNDn98bgOw/B4BESYlP71CSHIJskSQogxIYs2SvblIe1xq/ZYdaO8+LRQLN6Ic3lCYLt48aV9JPk9o8V9+UY/hAwdSwvp1SJevN1ngsfq8eIlRmkIYzTR+tBi8Z5ueNYlC2vCIE/c4wMG2Z7OYwJJC9ngbrpB/I8iW8eMJj/LTIj39JkG8dpW8w6NUIwzSkPR34+K3Q+JxU8WLhtlFy9+GmVhd23/vUH8jyJNx9bwHtagVb14v7tpI3uW3T4yK28G8eof+8m4D/vwBXxmYfQvrICFdvv7N51Op74/xe94Fj3U4/ElxGwT1ONfi7FvUGiROPafZ6X0+/fHf//9Cd8vL8yhvr+Qg1zI21uX5ze5tKYpLIvMvNFRSNexsJRePQ+xGOHbQxqNBqMN25d/rUdRhSEMHC0LPtn60VGK/thvYXJeH9g1XAuyy/JoZCbUnRdPaRimXEUp+T2jxX35Rj+EDB1LC+nVGhqFxgWmt2UsPgmEgYIWf9fYk89//ymxeAblsmw0xZ1i8YtAfDJNa4276QbxP4psHTOa/CzVQry2dcbiGcJ4gCi0WHzRsqexHMuLZ4W0ggWycoP4H0Wajq3hPSxI23jxflRxdpvMUiPEY2H+x4Tns2S9+DU+JkwJtPB87ukuEtZLwiZmJ9l6o2kai2GQc9bSWOpk0RTGaCpliXH5tdDW87kvhbPJHxOW9duwGBD/Ch8Tns+yqhevyaTF4hvVT4aOpYX0alUvHmizWLxWdnabw1KpF093d5RU1ou3t5VAfDJNq9QCPSwN4n8U2TpmNPlZqoV4bat5hzbCeLpNZqkR4uOPicVrMmmx+Eb1k6Zja3gPC9I2XrwfVZzdJrPsD/Grfi9+PkuRF1/6vXhYPkpACyamXAiSxesZxVwAdBiGWBgzLWKBJpyYNjdjLS/Dkm16MRZNYZjOeHRMY4FCdmK2/hssHohf43vxsrwNy/4Qz4gphH89pVEaJ8txvfhFHPPJLI1engwdSwvp1XG9eD8QObvNYakX4tOay3ayFHnxqcXiG/0YsnXMaPKzVAvx2lbzDm2E8XSbzLIZxBf8dysQfL0APiFAv43JvpO5AeGI+Oqw8Q0D+qkDJ0mZwD/Wzpkzfv6B/hcu+19crWkyC+vc6LVJ07EQyvTKybIUMeOa8OFcAwfCN2QtO+csaajIyve7+jFhjTb6mHB0ZKzTeg8LK4+yaF78UnnxWlPLi28s9bNoCmM0lbLElhevsEhf/gXz4tnd0BqxeCbHFosv6tbotcnQsbSQXlUbqNk9Fl8UCzpqLD7GBSTVYvF2tyKWBvE/imwdM5r8LNVCvLbdLBYf3XmZNUI8PbXdrnnxh/biWSGtYIGs3CD+R5GmY2t4DwtSy4sfpVq+F3+7jX8vfsIn5ikLzGfV78XTP7PF78VLok2nU9kQ21CMX8KB/8st4m0sR2SBv1LAMjzT+/7T1Avs0iatbLDQIdjEwvffsWafIkpTgu/OO7MY1vhevAZK01gY+r3m9+LZ3RALPNE7FKPMbmSyN0SpMi9+w5NWQEx6RbJ6PZbS4x+RRbsP1gzWKNs2PnpGimiXWHwREMkyE0tWPkYZJ+ykqmPxtqRGhWuM4reQUrWbBvFFQ6xKMJ+u8E3g7PZlWEqPf0QWDWXYrqesNTGNkmek1NbSfrF4DYhGMSorFn8sqEaIj/Ni8ZqkRoUrj1yzF180xKrUvHgNgF6bRUOZ0siyk8U4I0W0SyzeACKjSUN5Q0o7xuKDk5neiUzIi/dLLduUhHSynum+efF1Qrx9x3M+91CGtcj6F2NhKvGSLMxesN5oKmWJUZ0YnTbbo0AAACAASURBVBtQ5XnxRUBkgBLWZ0eRoxsQf9S8eI/UssKVozQv3kPNi8+e/Zdn0bxvzWCNsm3j2hmhz4H8NNmLx7EMfdAkUwREsszEkpWPUcYJO2n1DxjQV5bhbWP6NBzL93uAv2nHp+TX6/V2G+jTdrvMdh+PeLvFlNLv3x+3WwzfWSLP/xM/TrfbsOoHDCCjJlXz3BXmMwxD319KZdXouASnm1klNGUN1ihrTWjjWcKctyJbmPwBA7Q7SBszekrJADmBiJUfjwCg1HV9+BYRQz9DyH1/2fkDBpM/JrxeoCb8A/eyx63bfEyYypMdx778wv3v+dzTWyVjPshlHxnmg7IahqHrAgyUlZKsfz2WbNOLsWQjMPTLwFnjLWIBjcpODPFd2kJa52PCONao7RvRFScQaaBEYz5OF77eWHzaL1BDMesQgRpU6Ntt0Hih6XYbzuceVic7ZA1DXoG0+bRADW5Lj39Elhao0WS1RqCGmlhWPrsHaoKTmUHP6NWJsoxKalS4cDRUnVIvPqViaWZlUgTxDNb7Pu+k00r5HxdZfMe146wM7wbFmOoAoH1ZSo9/RBYNZdiup6w1MY1iZ2RHiNe2hmQ0IBrFqPQNSlQsDP2Mco0QH3dKmqTIntK/QE1yqHtWBZ00E+L7/ikrAG9I7REpC6xddhuGJ9y/3Ya+72W35sVnz/7Ls2goU+S/+1nkGanZi2fzN4DIaIIyBSUcxS/kGiEeC9snTVK0Mrz4qpImWdRFA2JjxL7v8dutrN5zJfDc8dSTzrgNC1OJl2RhVrl90iSD+LWTJmGs7ZMmmeuJ9dlR5OgGxC+bNPm/0GgFyn6DIsZosNBH/LT/5+f18bi+vZ2wQ/Y4m371olGjRkch5/WBOpIsGkUvTWxLu3kujNnrZ/hOpKEXwMoDNXi3QY+GrZLALQoh0Ce09Aj0gCEE6cUzTz8VBmrma1HWbyrabsBSevzFWWbK2TOKFmDRDNYo2zaunRGqFX464uNWHJraqUewKVlevEYv+7gVCEcJR3jcWgrxso/s33VfF4BQAvEoxmTKKgvWBo4b0FMJmBo6sCPLZCGn7+SN0VE0lEkkdoeH9ZRDzscyzgids58O97g1KxaGfka5RoiPOz1upUdDhavci08iFs+ekRoHAS4J8Zhvcz73dCbRjMUntxffPWM9BW6jKQnoMUaxtxuwlB5/cRYEayZJ2kETMqvRRtFQhuERhW/ajdZ7bFyeET/E0z4axI8eh0K8fUakZAwg8uAVE4UhpeydEB7ESQvH4ukH04He37++EY+7+AVkKONHk2k9ZTmf//1DrlFmu3i0vj9RFaQfhrb/lXv+9+K1bkbTMAyPx7+DPB6x73vP0PAWcfY1NjhC3/ePRyRHvtL3TRiB8OHFv7e3U9/3fd9n/78Y6ikvY6FN32fkqx4PZY+CLLRmS5Zs05YsICspZCpMTchYY4+Cp5JaaIzXGK8xJmiipgTdZD2w0CY8Gqwiu3z7/VK0l9PpBG+lXq9X+RSKEXaWoMRIs32UDMUrqNGAyGiCMoISQp9EP6O8HTmvD9Qh1S5i9D5IhvP810btUgkTjkeIxcOcaQqNZ3SWNMnyLLWjaRn3OJ/mxVOJ7csSNvHis/4jnGVmSnjMbD1rSsK6s2eEYUtWLWUfw4vP9mcHxNGNMyIlUwREsszEkpWPUcYJO+llY/F4NDzNMhqYdKNicOCn+W+3xpjgFXCZXgkH//7qRa995wCaYkzy8wZQA8c35tOR+1NDVmgkzJwoS7YJ6isEU0MHdmQBWUlJ0g6akFmNNoqGMongETUl2o3VsyZp49kzosFxyBG2OiFeHllKRjsjWcloQOSM0jCxaFEyWa4R4uNOsXimduEgsXgqOpuoYLUORfVsPk4vHojWM7symuQBdwfT7Lb0+IuzTBYynCPPKBrK+JHdw2KcEQnEQSfsUwTxlJdqoH1GpGQMIBrFKykWKXOjXCPEY6G9+kR3/4nyWWV3J1RBw4vHN1ao2WC9tCitqZv9UtI2LEwltmeZLGQ4R/NffaKmhKNo9bQJyqWvPvHlCUJ11V59Gj0CUHv1SaNiiE9TY/G0WyiJANKm9Hw/oam7sfXTj/pePBKtZ1ZkNMkD+s/Iliylx1+cZbKQ4Rx5RpEog7KSppQUE6OjswuA1Ch2RnYhWx8MydA10vpRyUixZOVjlDWI16jqWLzNgudJsrAmVFPDM9W2PxPiu5YXX9OFZ7KQU0le/AY/44zwJW1Fo2cki7/ILnFMa6L1Qbieo3CXvq831UE8XgNxiskB39mmIG4AU4lwmxfvIZyP04tnWE9txmhKLaOmhCV8gzWTJO2gCTm4vXjNEikeefBLw6bjevGjeEWP6bwY0FGcqJhq8OKX/UsQxoKSwtND0d9oikf7S5AdCSUJsrL/RiOETPyXsUiLwno8VPtLEJslfIdcmJA7Jf7O6j2jRMf/e0gTk/VZlkTu1D1/CRLGaPQvQUaPQCUjt6N/CRJEhIAeM9sk62v+S5Apf+x3vwf8SyqohzcLoLxZVj+OC28c2G8/0RdDnPQaf+yX0tM50mT1eISuC3//JuACghpkyTZBfUqZd3ycZ8RgoSPWQ3KxUse0JpCVlCSyGEJmNdoo8IYOs0oQ7+MRYkzv71+6EWPq+xMcE7qx+hCemkCXgKhGsZP4ePwTFBSM84h9tD/2s3UAhQknJShaB7KirzWtR4CBUv6yvPMf+zFCL57ujl6pgDzdSlmKvPiUii+YWZl4AjW1UXfkvPg6yalpTi+escgmWu8ZJRtxRhVN7igNPSMy6GycRDr/UQPRjGvUi2eH9ZwRTTIawni6TWbZP1DDaNlY/LIstlGxrZ9eA+KdskJiuE/JaJIHLMX3LAsevBLSFpuEjmlNk4UsL6XaKHYsHsgZZc42+WPxhgxlHz/EGyfFPiOeWDxlKQWiIpYaIR4Ldl58yi17cZasZ1pDXnxtZN/xVJ4Xj+NWQrjY9IPz4kGjZv4lCOuTfHnxxkmZnBcv67dhMSC+9rx4z7Lns1ToxWeJTQA9oOw9Y+d75yJbDjkXTEpPkxUFa6yXOK41yQP6z4jBYhj2LqQtNgkd05omCxnOkWcUeR88R6868e7hTC+eyRPLthfvPCn2GSmKEDi7zWHBCTuplrz4tImkDM9U224P8WCTdBqI7BJ/UQVLrTF+v06dlRhA/6issmBt4LgBTP4zMspSJ8Q7NS27nSzkVJIXn4RezUH5kEsAN06iH+Ip7fW9eK1c5JVOYKkR4mOLxZdDPFO+rGdNrXGCBXYdt0Aci/pftqyQPQvcRlNaMy++TohP5deq9CwrKcn0vOSskFmNNsri3kNWr7TRO3JlKpLtLn/PbZSd3Saz7A/xk/PiU8myJ7MUefHb5MXTPvj3TMwsI/nKB64Lso8ZZBeVO3HFxS9T4hxG8+LnEB5q2ST3OiF+dC3ZpkRWNJk8o8TnvPj5ejUnL55R1l7svPjRSioZuR3Ni5flbVj2h3hGCPGpxeLdJJUvbh6Ll3Pwy2p3lixSwNWXKqRB8hPNUJP9CLP2SWckG01wW7rwZVnkffAcverWjMVT2saL9wORs9scFpywk1os3oUgfloK4uk0mB9E19U93xr7rdG+4so5eGTFtnuxSKSgd1Q2yt9umX9S7L5vd1iZHhkuANljSmEamla0XZCFeQ9ZyC4qpzHrYydxR4i3ZZX1q7RykVc6gaVGiI8tFl9xLF4eLZbE4u3tXiwMKWguHfbJUhbf2d/hnr//CzcJWB/9I61RHStd/oIsa3sPh/bi/aji7DaZpUaIx0LLi6e7SBJT0OmTOctgJ2vETBPRoTTmxdfzJfcsC0MKDEZh5ywQR+X/ygHikaXvezyDff908cAAsXZC7bUwxdv4q/TMXubrFT3aUnnxSdiLlhc/SjBWy4tX5eNkpraUvbZrZWe3UpbjevF0/gtaozxafK1YvATu87nPnpG+/3LP5QWAyop9Qo52vt0G+k+5xgnNbksXviyLvA+eo1edQPlDe/F+IHJ2m8OCE3ZSi8W7EMRPLRa/OwtFChZmSc+RFib28/ff4XZdYGcNZEUrY8xAfBahpDANTSvaLsjCvIcuB9lF5TRmfewk7gjxtqyyfpVWLvJKJ7BsBvHqlybppyXlLn6/7Xq9hhDgE3G/f390XQ9lWs92F2Hp+0uM1+CjxyN2XX+7Df6Put3v4fH4kgkKR35pUpMb1MM38GgaWd9fhuGj7/u+v7y/f62r68KvXxf4Tl4I4XweQgi3r3/uHi/D7uVyoVL6+PgYhj/47cBhGEAIMcYQQt/3cskxRla/OwuIDlX0fB4SQZDfvz9CCP/994eyQLcYE6jr/R76/oS7IYTr9Xq7DfjNxWwfORYQO6HaWrJNm7GgjoEmgF6BwoQSvUIWGAUtse8vIYQYr9mJhRButwi7UoBZewkhgC1kvzTJOlMUAqJfmsQ50ymBrEAyABoSVSTCjHabyVL1lyZboMZJIGHmQIH0cIsdFrmhlgPJORzox1QUy0BZL15267qA3fB1AcAm1KVQ6MXX/GuBGrlN347z7uGHJM6Lc5lFMqE0BeLTmst2srxAoIZaAjVOvwUi4eq0QE3RtOshOvkoYvHsGSmQcSVgaTZdFzDgziB+GDIJOekgwmyBGrll1pd8COPpNpmlRojHNeAUUwWSStV78XQC1LNGotZYZIGMpA7FeAxU0ohNHrUOWzUuuovpGczrpxeDYXh640nL6DiEMBF/GcqXIntUHvMc2ov3o4qz22SWGiEeCy1pku4ieZImOSp/a+c0P8s4Gm5tY/OvZRcWNnmavR6jys5SHtFVR/XAXTxCjP+6Jd0boPOpU2JJiQaUeg90lx7NkzQJKF+6lpY0ifQKSZPUgc2WjSZ5t2VcvbPXcyct68UbNNkaDYrPsfiiaddDcvLgbiPEAGWDM9ANg+/IDq/Fynej4JjsyKPzqZDkffCyKD/qxadyW0v7xeLnABEOjTrmRMVUsxdPdz3r8XRj8G00AWbFQ8XiRwmnF6fG4o0jY+GINHPyTGlH6+2m+fPZhpgPlIXsonISBsusT1rilhCPNGr70jvMIgyuUWtiKE9Zkg8VqYT9CzxSLD6I62EqES4bxbh6Z1XQSZtBPLXGIgv0U9G066HaJl/bfLKE+MtQvhTZ49RYfCq3tbQQxNsXHikZWc4aZjIvBnQUP8rvD/GsBsHdmHc26pRlQUlJyLab8LJZ5MXf9viYcAEAb0I4MS2ea6xlLxaYefY4uxCbj7aWbNNmLFF8yqL7/sxvtqmUBaE/+zHh3fTbJANzg4gQIJfsptXfKv6YsPrqEyP60gFN2od6eBMKyvAuwwaE48LLHVAY3fqPL2UiX30yCN7IqITS7C/C70L4VsveE/mi2uaTJXyZiFol2og0WKOcZQGi1ke3j8de67YopfT2drrdtjhxgIEeIdf76lNyXJ0oi31DNO1GqciLT0eIxaP0NInJculZPhzVNvna5pOlbMQZqMjNNFiMWHxtIoL5sLuQ9IwqGsIkH15RsXhiQennxOKTIkFbuLKPEYPLRuWctGBGjY2/k8N5o4elt5ZHpNomX9t8sqShTJH3YLBI66Pb2kSE8+n0WLxhiQayzzTeGiEeC6MZ63LZjCWYcS7KEkQILOhefOV58RpRUaCUPDFTA9zT82VAW+Ox8uJ3JzqfOiWWdIUxmopYopkXX+cpyy5TQ5j0bYmySbJQlJfoZ6ClAfHL5sWvEoun0ahst74/dd2/eghxxpignrKwJi0aGOqLxYfnDyTBBG631Pcn1s0Aa5tGD3U+f8VGU93hY42qep6BVLkwt3kYZsfi6xERtUGIxTO8yiIMYJ3WROvh4MjC0O9Hx+KTftdjNOElNOvF29u9AjV0Guhfs1OAa/TcD2YvCXYwp2jaS9H8oYu1eRNaSj4rEb2Hk5YY3LmAdMm29dFtbSKC+TDrS47lO6M0ocXis01BudNJPuHGo8XicQJMA6SiJJ/VMfgevXwWTXspqs3at6QdF66hDIuRenRM0yVmfXSbPem3sf89T9/fk9D+khciHlku+8jUBj34S65rL5IX/39BIXlTQO9EwnduEN6j3e9hGAa4G6L14fvOEcIpcK/UdeF8PsWY4FblfP66h8JvprMmvAfEm6MQAgu/GPEZmJi2Um35WP79+wM/Sg5ffC6i6/V6Pg+wDSFAOYQQwgXyiGO8xphivEI9aDksM8ZrCBdgkfXAjk30yKQ8cdpL0Y5D70VwXk6n01J54iw8iAFDqpmU+r5HqwQT+P6Q+iWEwEwJDBlYaP33/zFcWBPY+NvbCUfB7fk8yCXjJD8/r1qo8/dv+BOF/naL4EjRVgjtns89QyTPkYGYNGg5fIMSlBF5gsAlA5QQYRj6GeXtyHl9oJfWmHvnLZGrE63Hpq78yxhsFJgwvZ84ohdv3NZQLnYPaNQn8fiaHTkIr8qg0jUaVDr0yxAzrplUekY0HfPoEqvPNqUSL55+OS4p/3vOarouSNOTb8Z5jpyEF88kUwREspyeTS8J9LPL23jxUyA+mfOOuVi8E9ltlEfLicePxbMaVBR/lIYKnBmqtEz/nBvEz6fdIT7lNCE5YqSsXmuK7li883/PKbEvx2Elg/gJ/6ielYwGRKMYhWKhluiJBaVXjcX7UZ7tMrVDJUsCvj1bP20Qi5f240d2g0V288+5Qfx82h3iDUuc4D0w62NHZlu2cHq1SPr/nlPKYpGEeOeRqQ1KyThdzGxZSkzK3ChvBvH/C256f/8K20GcmsbiaTmEp3r6SQOMbdlltot6xr6OQOOANOauReSzi6IxdyfBX4YGEWXGekY0ahnCk8Sg/v396UpGm+A/Re36EELfn+jRqPyXXYvR1FjqYcnqGDUfp47JpvAdmL5er9S4qIYjZSPOMUZtCfe7tcA5R85aHzw20IDIaKJlMD04rEQ/fEIp0dKgCaBkkfP6QC+Y7FYlrRyLD0pyUjqmF5+9tuMa6TKTL2aKo2hHDqFg4c2Ln0/MuGbS4rH4Ih3LNjm9+Oj+U1zsD9/vG43F+49MbVBKpgiIZJmZXlY+RnkbL34KxCdz3uxuKM2OxaOeJYKGOArKaBTf94J4Og1NA3CNpVGa2GLx9dHuEJ9ympCeH+z7dWzU+uh2DsQD0XdraeUciDesTwOiUYySFz+Jfka5RoiPO8Xik1C7Q3vxWSmhoiQ3stMVGfJvEL897Q7xhiWi1+n0HmQTOzLbsoUzIB6U/z1n85eiG43Fa0emNigl43ExjTIThZS5Ud4M4tVYvIwHZcN5MuoUlo7F3+/h8QinEw9Ay1j8ennxWjfZBEFtWs/y92XEHPLiod4Zf4/xivXQxM4FjiInVhrnXZvldDqdTqdtJmYfbUGW0kMVHQ0fnGgsio5dMZju1DGqZtgEpqTlxbOZDMPwePwzpccj9n0/ukDP3y0UHTkbi4eaybF4BCWEvmwsXitvR87rA71gahcxeh9Er5OUxenLG5fK+LqxeMolwy9afTpsXrzUw0PQ6JyXXdSh8+Kj/r/nFFLYemWT9OKNI1OiNiglUwREssyEnAT62eVtvHj17VaD3t/D7Zbo93TYW1u0Pnxf9m+3p3fD7DLdtUfB67PhxRsZNRsQnQZ+pYi983Y68Ws7OE3yrxi0eu1tumW/5DXhWX+WRbp7C2cRbEIgW4gCZ6loUVO+MKVQVsdC+PdeK3Qb1bEQ8k1BNzemb+/vYRj+XK/Xvr/EeMWUG3hhFUaB17OHYei68HiEvr+wTLD7/Stbhn4MUTtyljTrM4AICtkmKEshs7Hsd1y3+X+SEEq8+Bpi8Sl3NT6WF5+VEj0jnvi7zSK7+edsr7HIj8gObevhIWh0/qWLsr+ycui8eDoro4ZiSynZjNQGf2YsvgDisTDhe/F+qXluiKKSUVP59+KlxLIff6dNgWRGavVogdlRbKyRa2FrlDLRJGb88yqyaPguZ+gfZXuW0VWw3dFRpFTpBKiazf9efJGOySbQ5/hC34ufjPJJQJ9EPwMtDYhf9nvxxRCfWizeTajuOAGpAYnE4qU6UjPT6qkFZo9cZHIrefEGLNYGCqM0upbSRS3uxWsAlJ7Ttzw6lm2a4MXvRdQGpWQmuJsGyqecfIyyBvEavWxevD0KymgU37eHeDquZiHMzFgTNTOtXlqgPLJ/wotD/LJoWAMtvqjFIT7lNCE9P9j36xhtQpXTDK22swnzMaxPA6JRjJKHkuhnlDeDePVfn+iTDbmLDzkhfws/bdp1PTwtofXh+4krPGSDW127THcvlwsb5Xz+E0L4/tjpOD0esev6223w/8HK/R4ejy+ZoHDkB0s1uWE9yyTr+8swfPR9D8eBdXVdiDE+HgGyvh6PGEK43WIIXzbz8fHR9z2tv92GX78uUA8s//33h0oJmkB0cEZwYkF5sgdzzq4RWdh66S7VEGCRz1R/GiVxPchKDJ/KZs+LPCOUUbLc7yGrY3B8+MSxU8eAhTUNwwBPOGPkeYqPR6THrIHg8S98qwCmHb5t5Hq93m6DBkTBgVHhGfpgCIZ+Wrnqf31qgRo/sQl4AjVAzL0aLUspoWTYHZhNe3nxL0lOQW0fqAHylGVTStz66LZo4RsQzidrfUVAJMvpWchJv4XKlrfx4qdAfDLn3QI1lNjlZ1QDnMpRxLIvxCcf1hdMcW+qH+JTThNSoV4ZLC1QY7ieTiHXCPExPp34pQBoAsuhvXh7+UbTNJYaIJ7uvjzE0w7OA26ZNLmsJcptnZR81reqJbJyjRCPhQlJkzZLyknKYNG8+NqSJnFcT9IknWS2aTKLAfEbJ00mHR/lQM5RtmcZXQKrqSppMttUyhLHkiZro+wybVCaxiKvi7snTaqPWxnRh2n0QQHUs5fHcAtPWbPdjPIoCxDWIMvoC67+JxtZmdj/D5klNgF4pW2zj1TAaYJXkZ1kr7HogQ886cqavXznVnbb9DseCmXlNjp57OCEPOMZeCjXum3kRq2PvUM+wdaCWOaER4sGDkArWp8HiELw4hVlYehns9T7uDUpF7Gkx+JtFlb2dMt68fa26J4oK5MFY/Fb3k1XEqjROmjd6LTpvUhWFf1lrYnd7hh3P/a0UwWBmjTVrJwsUY/Fp0m2Jpc5wWMdtX1NMgtaoj8WVGOgJrZY/KFi8ahw1UK83U1ibrZsNBWx0G2WZXTCrMOOEL+qJUrrS4olFtEiEG9fePz4CyxLWWK2vBnEr/Ux4dvtX0SF7nrKo92gD70RO9zHhAP56Cj7MrAUbPbbsKMs4fuDcWxiK32zl0nMzwKKmGWBtWD9/flPJZFFqiWtpyysibLQMlN+NjGYsLF8gwyWbT4mnP33R03HsiwwxJvyMeHz2bK1rL2wP5U0aFTImu2j9fmByI9XkuXFPybMykVeg5/luF689BnpulKJ1+C5m97di++nUoyJFugW69nuaNnZTY5VRMy4RmnjvHjZpJU1vTquFz/frBZk2caLnwLxac1lO1lii8W7WXaH+JSSZ8t2YdpYjjFTL7vZZaMJJclG9M8ft7tDfFrZEmOLxc9mqRHiYzWxeFY2rt5ZFXTS9rF4dLqLytq5iNXE4p3IyHYl5tIyW/40idEj0y2t988ft7tDvNSrGFOplChLEnqVjunF+1HF2W0yC2hIXRCPhWWT3KexxJwXf6C8eLATWj8fs9gouDUgfoO8+L7vb7chi4bn8xOs06bbbWCYixKbg/JsFycWn+8SYJSY8+I9a3FGQbfJi1/kWohHO5+/ToSWF5+ErTnthS2zFM48ts/WskZevJ/FgPjaPybsWfZ8luN68dJnXMQa5dGw9bhevOFlZyHbiVlMYlr05rhe/Koof2gv3g9Ezm6TWer14unujpLKevH2di+Ip9OgnrW8sE3ArKjcTdPyvhC/Uix+JmZ1XfghsXjjIucspzHrk5a4PcSjwA3bz/pVWrnIK53AUiPExxaLb7H4Fos/ghcv9WpB7yFW6cVTxNQuPLb1sbKz22SW/SGe1aC6G/PORp1WYmF+RFIUDra373/w8suFWp0WTEy52CiLZTOlj+QrH7gu+Mv5RTCLjoKYBQWcmBbPhfrsGmnUWFs+bQKWrBdPY9Y0rg0s0ouPJDIen6PnEyTGdulYkdwlwCjx24tnExtdiwHxWYmBsmnnRZ4RrMmyxPWf8UAfrMct/su2ZmtZe4HleCDewDjNi6e278TfbVj2h3hG1BPMXtu1ctGy/SzH9eKlz7iINcqjYetxvfgWi08tFu8jpxfvByJnt8ksVUN8Wm3ZfpYiLz4R5fNTi8VLWjYWH0yKuf8vxPqZmNV1fBQ6hNyV1GLxKWdoaZKtyWW2WLykFos/hhdvrGUOZsmjxepj8dCqQafE3ES87DmYBbs4FpRxS0fRMH10XftCvNSrBb2HeGQv3o8qzm6TWWqEeCy0vHi6i9Ty4lkNIqOWSw6tDOITyYtH5EW3GsLfsDtBYmwXJkZ9dpAYRv+zE8OZ07W0vHhqidTWtsmL93vxWG558U9EYSJ7bdfKfmQvYjmuF8/wl65rjjXKo2Hrcb14BHf0r9EDykK2E7OggMeko7BY/EG9+FVR/tBevB+InN0ms9TrxdPdHSWV9eLt7V4QT6dBPWt5YZuAWbHiWHzKPURNPi8+PSNsfM54AduYg1kA8XQUtH8cJevF05kb69oX4pPQqzkon8asT1riXhCfnRJbhROIirzSCSw1QnxssfgWiy+HeGPLvGPmAkvMpU1zMKv7jsXj0RKxf1afhG8uEZ9tacFDLRYvl7mGF8/OrI0qRtMoi2eU/SG+5cW3vHisn5YXn3JevIxZYz3G2Rny0rx4ZJkmMbZLjxZjwrg8TgDmzyaGVyYtLx5XrQmZSazlxctlLpsXLy/PowjjR3bJwsbKsuwP8YyoJ5i9tmvlIkn5WY7rxTOfka5rjjXKo2Hrcb14GRmP3xHzLGQ7MQsK9Gg4i60zxAAAIABJREFUCg6N15h0QC9+Qb1C/aF6dSAvnqM76WYjjNE0yuIZsWqIT5OWvSxLkRefiPL5qcXiJS0ei6dYSSsRYWVknEpsMmZ1HR8lPgff0a+XEXZ2ZZJbw4vXpNpi8YvH4g1KPoTxdMuyGOOyPnVBfGyx+BaLX9qLT6+YF5/29uKlXi3oPdTvxVvoTnTJRhWjaZTFM3qNEI+FlhdPd5FaXrysBH/2p+XFMy++5cXLhci1LJIX76TkQJhsk5PFP5MiUGqx+GN48Qx/00LWKI+Grcf14hHcw3PeC9jGBM+U7uIx6Sgy+i8nlqr34ldF+Zq9+MNRkaBaLH4E3/eCeDoN6lnLC9sEzIoHj8VrXnx6Rth4qLz4FotvEO8n/xqnQfz/tIHvd2ta5/MphPD3b7perzFeofz790eM1/v9q/79Pdzvge16yp5uIYTzebher7DFQnb7+/fH+TwUyZ0u//PzqnWTTcBI6+lkQggfHx8oMZDe5+f179/UdX2M1xivf/+mv3/T+TxgGZpo/TAMkoWei4+PDxydTUxbjlHvYWESw6bzuf/8vOL29+8PLIcQYoyYMgi356fTKcZ4Op3Ct/afz/3jcQ0hdF04nU59f0oESR+Pr+UPw4BlWn8+/6unTedzj0cDjHg8rr9/f+AoIQScG51YjBHWRddyvf5bI35I2S8xQ/6SkFFjoTqGCkN1xqljwMI09vu0Dh8fH9LQbFvL2osNNdmFzyS4YsFFRSsbTaMs/pmAq7EuOa8P/kCNdCKy3Yyyx4V/yUANZZl/03OIQE2YmjQZcn73aJnuhlxwBocOL5Q0mRa1xJoDNTDuKOjNMSubxQnxqebHrXTXvolrgZoklN4I1CTdOO3yaLeaAzUUK2klIqwMm6AVAUsRymfRPL100mRawRKrDdTQydgIO9+ssiwxjgyNLJtB/Amk8/l5/fXrYswMb5EgSPL2drrd0vt7eHs7/f2b7veglYFltFsRy+2WaJ+3t1MIAQqjW0v8zyRlcr1eLxdLSpLYBG63dD7/W+YGdD5/nSkn2Wsc1RNGHx8ff/780ban0ymlBDEZpL7vocMw/AkhQMAkkNSa9ajvTzGm9/evad/v/0anE8OZa+vChTvHhfCFJthSrdtGtaj10W0gllh0QLbMUk0DLeo6jgNMu4DgLNtAFEJw4pVkyQ6aUqIsdMLONZbK5N/AnusDvRMZTWek9R4WVh5l0bz4AyVNQlnWG02TWQwv/kBJk7hGjLHgEOlbYbL+O6YzysAOTZqUo8SXSJqk6YyjuuRkibUmTSbF9qWOjYJStmmUJYqn9EGJC9EmRrUnTbL7xNJ7Qw9LPH4svvTWeDJLt3egxtiCsTF7wA7xOWkyG2MpitLAlHA3kJhPdpT4KkmTaWlLZNaXFEssoi0/QzbfrDQWqlF4LcmyGBCvUYvF58+u7cUbtGos3liX1jSZZV+IH43FaxSfI+OyDEMUoXz2OqGNIt0xDfFbLD49W+JeEJ+dErtWLWVWWZaoPGOT5RohPsanE18qqW7qK4jyyIf24m2JGU3TWHaHeP+W7XqcdL//jkKYzOLf0oKH1v6AQVrNe5DbabYml7mGFy8lYwCRB6/SDOPdDOLVvHiZwfr+HiA5HXchUf3t7QTlYRjgeQutpyzw6G+0zHblKNBEH6rYT1lxYn6iy//9+0PrJpsgcZjWs4e9fd/jWqAeXiaAetYE5TksKEmcmLYco97DwiSGTexpZNf9qzmfe1pPm+BZJawF6qEMLFhPm4DRZmFNNgtMns3ZsxZ8KcEvMUP+kjA5XWPJKgzVGaeOaSwhhLe3E9RTQzufh/PZsrWsveByRmn01QHN9tH66JKhRgMiownKEvok+hnl7ch5faCeoHYRo/dB9DpJWZy+vHGpjC0WX8JyaC9+1MsuitLAlPwsx/XiNU1IJXo1auNH9OLlPa4fiGQ5CUuU8tHKdMJOqjoW70T2IpSXp9De7gXxdBqjGrDG3fS+ED8BGVeC7NLAToxl86fXqn7sScNelNx6BeSxPmmJe0F8dkoMQ5woXxqliS0W70d5+1Ipr8YMRu2tn1osXlKLxfuvVTth+Agt6z3I7TRbSy0W76BaPibMNCPNi9JkUV7z4ltevGGoWdo3L57mkmN/2EJefBKYS5PcKUuckRevsWS9eM9aKvfi/TqmNcWj5cVnl3n7/je+aSifBPRJ9DPQEiZcBEq158VPRnk5yqG9ePvabjRNY+mO7MV7YilaU7bs7EZ1uHQVyIKgUwnBfPx6NWrjBpiW2lpqsXgHtVj8CL7vBfF0GqMaUGSBTpZ9Ib4UGdNqkF0a2Ml68Z4t9eKLxLUq4Xzmew/M+qQl7gXx2SkxDHGi/ChGZcXC0M8o1wjxscXiWyy+xeIP7sUv6z3I7TRbSy0W76CFIZ7VsDuR7Lwh6hRXjsVDlLbIi8egm18uNOisBRNTLgDNYtlM6WMuADoMA9ZnBTuTBZpwYlqcHeqza6RfU9GWT5uQRQI3jVnTuDawSC8+PgfTafScsjBo1liiiOYbLOjFs4mNrqVmL97/jAe+F59tAuvDetwCi2FrWXsBlfNAvIFxmhdPbZ950LXRyPlrsfhkonwiFwMntVi8pBaLP7oXX3SPaNt41sSm2VraNha/C4KP0ugaWyx+BN/3gnjmxcu1sHVpTZNZ9oX4UmRMq0E2TsbJEpeOxcP9wagMh2E4n3vjRMBxWCUc2Tg+zme+98CsT1riXhCfnRLDkPj8jaMaqBaIjy0W32LxLRY/1YuP8Z9s7W8CA0x3XcCjMeq6wI4QI33tPs8Frct6D3JbuRcPuw3iM4TqHltevBKab3nxshJQ+CfnxaMoqPrBEFJc9EzF5z8XpKdAPlDxOB/Mz/XomNYUD54XXznEt7x47l8cy4ufdms8meXQXrwnlqI1ZcvOblSHS1eBLNRuAa+pZDwQIzUW5M8gHgB39CzDfIruEW0br82LN3AgPVtf5RCvUYvFj+D7XhBPpyEtZMKtcSnLvhBfioxpNcguDexkvXjPVnrxEF6nksl66JSyt19ZiD+fv8aC66JGrx2Lz04m68XHFovPUmyx+BaLb7H4qV68DK2EEAxhxpjOZ47XNJQv4zwQpTSQ4rVj8XL0rBcPu1lIhSDkqLFoj7Wj/iwdm0afhI8OPdonc3CNueXFt7x4rG958Vk09+fFl0L8jfypLNZg2TiJnXgSS0cMr5sXnxy2j/OXkEpt3ED5qDzWjuazdGTRxFKLF0/LGrKwLe02GeXlKIf24qfdGk9mqdmLDybF5/9uzZb9zjj617hrH5nVSDLWlWZ78UAAmlLyBsRHEfSnI+I1w6ljto0f0YuHmTNIZU93jclr1kFZYlRdH42qg/hkKkfMxeJtllQOc0VefCKn308tFi9p2Vg8w0paiWCEMM3q0SSKUJ7ujo4Sn2PxDOKNdUkvHn18pBDGzwskz0Ahe5nJHsGG+LSEJcbXisUzSWomE5XH2vKyyq4foyd6VYg/wQCfn9dfvy55dyWEEJ7+zy+E8PZ2ut3S+/vXv9bd70ErA8totyIW+IctrIf/07L/24/+tZ6TpEyu1+vlYklJEpvA7ZbO53/L3IDgT8jgrHnIXuOonjDK/h8ebk+nU0rpdDpRlr7vocMw/Akh9P1Xq+1TL0J9f4oxvb9/Tft+/zc6nRjOXFsXLDzGGEJAAwYWKN/vAdTAng/8j50UOPw93n///clyaWcQ5LyUGKn10W0gllh0QDbtUk0LIRg4EL4hC8QOooDTAWc5kXvK378/uq6XMvz9++N2iyGEvu+H4Q/a1PV6fTwiPR2n05cifX5ez+chhAA3ZNqK6HwMmiCTEIiXYV8K8EIUJ+XF2yysPMqiefEHyouP33Fh7dZ4fl48lZVG++bFg7VIhey/8+LDc7gmfkfMA3G7sjF3Wj+aF48HDyFQFoaGODGcOV0Ly4tn9pWevblhGH/H1TgLMmkSybgJw/n4dSzbBLKqLS/eY/u4FgZ99DQlMw6GA7Eza0fh4HYw6KE5pipHzYtPY8juZ4nHj8VrEZvkltIoC56mfQM1xjbkPBfsEJ9j8VRiFPSTO0oDU8LdQGI+OAplYRAvZ+55xkClAfjILpMUYuB8wQXAOBEUU2CS+E6scS5wmWmeJUrrS4olFtFesfhSiMejYR/ngxZ6FWQkVSVLLRY/gu97QTydhrwLkevSlqyVR7vtC/F2LF7z4pMSGaf1MEQRyrNYPD2avGBkvXg6c2NdWYhPwo4k2XddBtco4XyW8h5SztDS0WLx0yA+kvi7/1l60B+fVAHxVPkQOIzr/Nq/JE7hIbx427SMplIWNMV9Id7YMu+YucASc2kTMPr9dxRC9mhJ2H8QsSDtUuT34vclmM9870FaX1IssYg28+Kli8BOE4TjRoejFwm8R8SmrNFpj15XhXj1cSs829R2395O5/MATySu12sI4XK53O8hxq8y1rPdpVj6/gKMHno8Ytf1t9vgfwR0v4fH40smKBz5IEuTG9aDoLC17y+Px/XxCH1/AXnis5rPz+vjEbLLxyas97B03ZeIYCycWMg9wcO1ZNeILGy9dJdqCLJ8fHzgu5dAMUb0c0Ey4EbBw8m+71FcMSY4BXC0rrvcbh8hhNst3m4DPQ6dHpShAGU4lawPjghHw27n8wATvt0iTADnTM8jTJvO4fEIXRfouoDS2DO0zQie6d1uA9OloOtYCIGqGTRBpkCMV3YKQgjAYtha1l5CCO/vrsetDIUYMVvDKXXd1yTBEK7X6zAMgZwaTB4Bog/GDaITdj5L//37I/uQvK7HrXR3qajLBJb4coEa6nfjrqcczUcju3vxowENrEnPUQ4tbEIl5pcSlnGXjUKHCPOSJqV91UAwnwkSSy8dqIGxcPT4nNVObYeW5aNjbKXP0tlDF80SnapSUaAmPWuDp9scFgaj9tZP2wdq5mCWPNohAjXJfNwqwyaI+BKySyUWyMPV8PxQVwZzwhKPW/clhPiZ3sOhAzWwK08N4HKMT9OIz8/5g/lYO/ssvesChH3sTyPUAvFYWDYDchpL1os/dNLkfMz6aUmTEyTGdldKmqwf4id7D6+XNGkTsx3bW8q2ehwseVeR7VZL0iQr+5G9iOW4XjzDX7quOSgvj4atx/XiEdypM5W+vxwrIduJWVDAY9JR6LPZl/Tip0ksPevVcb14esZLj78e1eXF010PFju7lbJkvXh7uxfE02lQz1pe2CZgVjx4LF7z4pNIbonPSZOTr4W4iz47HYKOnvXi6cyNdVVLC3oPSQfTvSBe2zLrA1GUHn89cs6nxeKP4cUba5mDWfJo8Qix+DA1aVJCdqnE6NGSsH+sTznfPLi9+NpovvdwaC8edkEUpcdfj5zzmQbx/9NUAXPLkN7fA+Te4e79/vVFCCgPw4BlrJfdFmEJz59/sT9Ngyx+osuHT4JkSTZBFhqtZ9/K6PseJoPrivFKP1kDX5Xxl2GXSQl8yff3gN1wYtpyjHoPC5MYNrFPuHTdvxrogPXQRI8Pa8F6xF+6riKJ0V16NJD/x8cHfKYGj/zx8YFzZmtnazmfe7aukDNaDEDTPvCEQ3v+ARl+9IDad2uhTzSf8RRJDHZBY9ESofXt7QT11NDO5+F8tmwtay+YKj1KEpQYabaP1ocf0vlB5Lw+UE9wNDKQnj1TT7dSluN68cxnpOua45nKo2Hrcb14GRmP3xFz5mYW+e8dicWH5/g7Dh2W8OKzMpHHsb89QCHeOCyd/IJ6hfpD9eq4Xjw9y6XHX4+c82mx+BF83wvi6TQQrWTEZhpmaXfTtLwvxI/GrLEmPQeyWZQmkqB5mh3XAoino8Tn4HtcIi+eSSPkKJVDvIYIdEVMr9bwHpIOpntBvLZl1tcgPkOxxeJbLL7lxRdm1KAcshg9E+IlLqCgVvUeDu3FdyQWXxuNLrDlxbe8+KdR6B2DRi0vvl8zLx6EMGrYUqpUmDbE40HwQxHMXubrFT3aK+XF10Z0Ldoai2QCVAzxqcXiS4hNILZYvDvzhII724Yw0TOlu/Ro2TKDeGmQi2TUpHlevKTYYvG6Fw8zL5LnZjS6wBaLH8H3vSCeToN61vLCNgGz4pFj8WzLdmHaNBZP62diVtcFNgraPxvRP38tar8xMe/BuMjN9B6SDqZ7Qby2ZdaXfAjj6TaZhZqtk1os/hhevLGWOZgljxarj8WzLduVmEvLczALZUKPTLe0vnQVaW8ncW3v4dBevB9VnN0ms+wP8awG1d2YdzZ6vhIL8yOSonCwBZZSaaIEtGBiygWgWSybqV38jphTO4H//F0Es+goqElQwIkZfxenrRFZjJAxbUIWCdw0Zk1j9MAivfhIIuPx+d/7JkiM7dKxIrlLgFHitxfPJja6liJETiV58fZxEOLXfsYDfbAet8MwDINla1l7AZXzQLyNcaO278TfbVj2h3hG1BPMXtu1ctGy/SzH9eKlz7iINcqjYetxvXjDy85CthOzmMSydwmJ6PxkLx7YnRCvyXAU4rEnQvyCetUJ7+HQXrwfiJzd5rDUC/FpzWU7WYq8+JSKpZmVSYvFt1i8ZyvBN+lAn2ZAPOuJEJ+EXs1B+TRmfdIS94J4bcusL/kQxtNtMkuNEI9rSAQ4dpdUOpoXb6xlDmbJo6Ep7gvx/u3rxeKlQBaEeO3ga3sP8chevB9VnN0ms9QI8VhoefF0F6nlxctKAG4tL57FuGnT7fsvFJiXjSzTJMZ2aWQ/krsEjP7LC49nLQyFpcRGId7Oi9fkT734BfWKHu018uKTA2HWZjEgvuXFJ1aDLJ6tn7aPxVMWv8S0JjxNx/XiR71s6XTbZWc3OlbpKtLYN2qQJnjxngNG5T54KUs8tBc/36wWZNEgXqNpEP9/2XtAm+A7f+/vX99QxG8cZsshuLqVsgTxBUfjS5P7fl6OTgP+X5jOX67LKSU/y14LB4IvL3q2chfLw/AnWzaaSlmG4Q9+b1Ky+Fchv0mpUXKnV/p7AtHvs65hiUE3N2gqmu2CZNg+tb5FzGomC/1U6rrkvD7Eklj8Nr+k+A6Ve/H2td1oKmVBR35HL34OUX1L4j6S9SwqZ5uY5y5Z/MSMa5RGvfiicTUdK9UrjeXoXvxmuGSXN/Pil/9ePLaez18ff6e7rPx4XGX9KAsM8WLfi4f67Cfy++cPdjtZQh3fi5/DAmvB+vv9iwXroUmqJa2nLKyJstAyU/7StRhksBhqxgg/sK6xZBWG6oxTx7IsMMRBvxevoYoEpdFuWZYQuGC18nbkvD4w76bTQ3t0a3Qzyh7n4rhefFZKiUi4VGJaU6wgFj+HcNqGl72I/66Vj+vFTzMrJ8vRvXh7yWmeJWp2nS1v48UvH4sPz/E7ttti8XgNx+3tlmgN3fWUNZbwKv9xIyVGie56ynY3dNA29bNWIKkwQVE5o5xlAWqx+CwLSubFY/Hp+Zrv6VbEcmgv3l6+0TSN5dBe/OKO+RwWPzHjGqVjxeJZ+Vhe/FJmNZ9lMy++AOKxMJqxLpe9bF48RiHS8yk8UF48lGW90TSZxYCqtfPikWsCSzYygywSsnEUg4U12SxZuXnW4vSf6Jd/7Lz4bL08GkJ8yilMcuiSkyW2vHiFRV4XXzAvnm5pt678nQttlEN78fZFzmiaxtId2YtnBVle1X8/rhfvxyy7bNu4AaaltiaXuU0svgiIZDkJS5TyMcoaxGtUyzdqYuTL9iN7EcrLU2hv94J4Og1NA6hxIkA4y7Br6NPRId4oO7tNYzkuxCfdFfDrFQ3nSpWzwXQviNe2hvVpQDSKUfJQEv1sq6wO4uO8WLwf5e1LpbwaG1fvrAo6actYPGI07mZvurP18mjpWYOPC/G7o/w02h3iDUuEWTl1LNvEjpwF070g3r7wSMk4XUwnyifTEll5M4g/pZRCCJ+f11+/LvS6jdkF2V3Igb1cLuE7S/dyudzvIcZr31+gJ6a7Xi6X6/V6uw0hhPN5CCHYZbYLj+npKN8qeA0+ejxi1/W324BZvaN0v4fH40smKJzr9QpLRtLkhvUgKGzt+8vjcX08AqwFjvl4xBBC3/dQPwwDxFVvtzgMw+Vy+fy8Ph5P9edz/99/f6AeWOA8opSwCQaFRAKYWAiBzZmuJbtGZGHrpbtUQ0ZH8bBg64KjyCUYLNkJeEY5nU5QSOKt1CwLpntnR5FnRJsYjBtj0nTsv//+/P790XW9U8eAhTV1Xd/3lxivMcb++eP4MIpha1l7CSG8v/NlZmXOTiUjZms4pa77miQYAtpI+E7+cQIRKwOsBQJ9OEQIT6Nky/d7gDx6PyhpejhCzutD1gnSnAVan1qgxheowXXhqfG48LEFalZz4Y/rxaeSQE3SdUxrii1Q0wI1dNmpBWocgZpSZDdY0rMGHxfid0f5abQ7xBuWOMF7oE3oiyTFxKbZmlxmC9RIqjpp0i+1bFMS0ok5L/7QSZMUF7CJ+lxaPVpgS5qUTbElTT5nQBbpmGwK4cskXyZpcjLKJwF9Ev0MtDQgftmkSTUWz4hGwWgUCerZq5u4pe+VAUsI4XZLo2W6K0cBwhocZfQFV3/YKysTGRUdJTYBeKWNSezt7fR4hBhT359CCF33b8kYXe37k1YPA6WUORcgGXgV2Un2Gp1fYlmEuu4C3yPCgiwH8s0ioxuWnd2gzBjXJs0A/VqHWhFyOha+TcnQJVmfbaKaln2PtNTW5DInxJ0NHIBWaX1FQCTLTMghcPTLIiQbvcXif0osPug5DGEs7SFsFYvfktYLuThZiuS2HhWdEVQVqQmJxOJTiY7RJlQ5zdBSi8W3WPxome1SPctCIYNRe+unljS5L8m4SrZsNC3LsheVnhFNx9CZSCXeg2xiR86C6V4Qb194pGScLma2XGqJrLwZxK/yMWFaT1nO538f3zHKbBel0/cnqoL0RuxwHxMWX21N+GVgukz6oVdazz4m3Penu/Jt2M0+JrwGi/wyMKv3fEyY1ttHC8oHyErXsiyLpDkfEw4h+HWMqhk2gSm9HfNjwuzTvkEHIqMJyghKCH0S/YzyduS8PjDvplNuVdiWdnNeG+UuHg0mTO8njujFZ6/tgaSp4TJDyC+f1adcngPzU/xUlRfPCrK8qv9+XC9e04Q0pkusPtuUEre+pFjinGUe5QMG1PSSQD+7vI0XPwXikzlvdjeUlovF42UpvmIsPn1Ljy6TdtPqpaGy8tEh3ig7u01jOS7Ep5wmJOJMOHVMa2LWJy1xL4jXtob1aUA0ilEoFmqJUcSCtHKNEB8riMWn7wdKzI8YxfdEVNBJLS9+X3I66UbTsix70eKx+FLvgVkfO3IWTPeCePvCIyXjdDGzZSmx5EB2LNcI8VjYPi8epJm+1VH6EVBoefGGbWepNC/eaFqchfpcQNHMi882RTMv3mbJym2z5WPZnxcPBU3HElGz5NMx2QROa2x58bnrokQ/Ay0NiP9xHxNGPaPSOa4Xn70uUluiTdTMtHpqgfLI3ZG9eFaQ5VX99+N68ZomJBFbSGM6lm06rhfPJFMERBrKJ6GrTl9eg3iNXjYWzy6Vhhdvb/eCeDoNTQNwjaxJegqyXlogKx8d4o2ys9s0luNCfMppQiLmk0p0bNT6pCXuBfHa1rA+DYhGMUpzPUeRPZGo0QYQX/DfrfhNuPCdNlT0F4jAAi902WUo4C68DwaZRvj1xPCcIBV8b7f6F7sgsbdbNSl13b8X5B6Pf+8csuXLerqr/Z9kEfmT2Falvv/3Ab8QQggXpWw0zWLp+0sloiglwxJPJ0uXWH34fheUWh/7+1Pt7dYdF2683cokE8gLqwyIjCYog8FS0wshGEjIytvlTWrXB1bD7kSyVyeIOsUVYvHpOZpR6sVj0M1/6aOfDdGCiSkXG2WxbOnFy4j5MAxYT5cZ9JhplkUbBZpwYv7Q8L4s6HPJiDku3xN/pyzZJo0FC6Vr2ZdF0zGQQAgFOkbVLBCnFawPR8EtsBi2ll0LLMfjxdtu7KjtZ7GrCIg0UKJh/VH/PY3F4jWqPRZPu+EFRgYZRpvi68bigUaXz+rTonnx9ZCEWlk2mrJlZzeqw4cjTcc8usTqs00pcetLiiUW0S6x+PRsO3T5Tuuj7OlZc0ZRfhuILwjUIME7k0ZkgNaH3G1j/P5+FrwyJz8xZjTRt+zYjViFURo2MfxK0e32tSIoQ0+oQQ2DAnbT6qGGHg3L+y58KaL/zsHKIahN2bKz29bvH65AWR0b1SVWn22iNq6FRDZZYobs8BFan4ZXQIgwGviwetbHE6V5e3t6jXZdcl4fqO+cyEM8z/2IbApjzw+1pvSiefF0ek7BjrLgzeDRvVHczZaNpmVZjkKajpXqlcYirS8pllhEu+TFJ/2Bs9FksySfkDfz4gsgHgsT8uIZS3gOLITnyCBlYU3xVfLi43dcmNXjrieV3mbBrQFVRWvZmIWuAijWlBdfocSgoCmM0VTEAmJ8mbx4iTDIIpskC0V5iX4GWhoQf9S8eNotlEcAKYv0Iw7kxWellIiEi/wsgwVP03G9UVaQ5QnOuJ/luHLLKkypXmks0vqSYolFtGMsXiIMkNZE6+mFIT1rzqiQt/HiV4nFaxFADA7G8gggZQE6dCw+KDG7ELxJV36WvRa+FLVYfCnJiLP2VMwuayxBN7dQdyw+iKcUWYSZ/FQstFh8EpGZIOJcRhPO+bhevC0xo6mUJbZY/KIsRyFNx0r1SmM5tBc/umSKjVrTIsa7mRevQvzkvPjkWDZKSkK23YQ3TfHgefHUTliSu5TYaCp9lgU1CQotLz62vPiSZzwaC7oOr5EXTyGbuZ6ym1Y/Ooos7w/xjJg9+NdjXyqjEucymlDPEjmRB/Li6fyZWDrfOxfZsjxabLF4UXZ2o2fncCS97zl6hfpD9eq4XnzW3UwCYaCQBR9Zn4iqFKF8vRCf3GsA8qC8LBtNiF/p+RTa270gnk6D+UFULKiCpdbNA2CiAAAgAElEQVQ4esU9LlSNlp3dprEcWm5Mr9bwHpIOpntBvLZl1pccQOTBKIb4flSkEvYvsPbvxdvd5rAYV++sCjpp+1j8NAvUzkU8fiw+VEl7C2aE1vYebC8eaC+Ity88tvWxsrPbZJYaIR4Ldl58yi17cZasF3/ovHgG2RNQ/vXy4vcEcp2qlRgUmL3M1yt6tNG8eBARtbXK8+Jl/TYsBsTXnhfvWfZ8luN68Qx/6brmWKM8GrayIx/lVy3E7y6ZUbmtivKH9uL9QOTsNocFJ+ykg8XiZ7JkvXh7W6p2rxSLL5UV2+7CEkkCQyVE8WtU04q2C7Iw7yEL2UXlNGZ9dLsvxNuyyvpVWrnIK53AUiPExxaLL4d4BgoS2dOzNU6wQO1csDuGSgDIz1ItxKcqr4iGjnWLeg+H9uL9qOLsNpllf4hfNS9+PkuRZ7pjXjwDhajnxTPILip3Ssw0EZ8LEpYhlzwrpWya844s1UL86FqyTZuxxPWf8UQ9L96G+Arz4mV5G5bNIP6UUgohfH5ef/26GPFH+gp4IH8MdLlccFcrO7sVsTz/H5CLbrcBXrB2kpTJ9XqF0f0Ef6CDqt/3F3ztPsYrWzLOM4RwPg/OMuyezwOTEoqo7y+lsqqB+v4CX5xOqZagPDubdRLqGNUrUJhQolfIAlZD9SoE1fpAOF0XimwtCOMaRSRJb28ntIgsMcnYCOPsNpml7y/wN1J+QU2QSQjfLlIL1EhqgZp9War14pNDx0qXvyBLC9RosmqBGotooKYlTdJdpGxCG2j87kmTGjQgi5YDtyNLFuJvt+F87iG0ZROE2mQ3qNfiAFoTEMUvYy1M8TzLX5CF2ct8vaJHa0mTS7EYEN+SJhOrkepubP20khfP8Jeua441hpBJbpPSK5LVviwS4vu+Bwju+x7XmyUKK7QbhRWmD9h0uw3aiT6KF784yuPCY0uaXI4FJ+ykljTpQhA/LQjxbBVZ/O2eb4391gi7aIFSYhNkxba7sDCIZ6ej60Lf91mZMx8QD973PVVjfNCXBKyznkjsgq1tSxe+LAvzHrKQXVSGqykuXFof3e4L8bassn6VVi7ySiew1AjxscXiK47FUwvEsfx3PDNJHnA+Zkkvnp0drYk5+KirrB6OD2W4P8Amiv7ybI6uxWiaKWfPKIt7D5peGYq0F8TbZ8S2PlZ2dpvMsj/Et6TJH5U0Gb4fGFBiLBLTsR4PtVnSJATlZT0FbjxHIOEsxGfRH2JB8uAMZydkQAK7FDIVpiZkrNklaRJFhBrVkibnsOwP8YyYbfjXU7RsP8txvXg6f7auOdaIFsh0yCkrnGTWZzSa0vf3VNkB/WdEY7EhHq9hjKR3j5+VBzzFeoR4if7aLQK7YBs6pjUBu5Qk7aAJmdVoo8QVYvE4c3pSNEUyIN6gFosfpRaLdyGInzaOxSPclFpjXCIWj5OUXiSyZJs6cnkoPSM2iwHxMebzl5IJ8dCEOnY+9xS2/BDv1DQNAbOSZBCZFTKr0UZh3kMWsovKKCJUlexFiLbuBfHaNisZu1zklU5gqRHiY4vFrxOLpwYzwQK7RWPx0lw9TfKA/jOisRgQb5wIA+LTc84l1m/sxU8TMpwjzyhSx7purveA8qGqkj37+0K8fUay1qeVnd0ms9QI8VhoefF0F2lCXnzGXMJXNxoAtetZUyI6lMbueFg6M5qrjAvbTd1WefFS7IyiiMWzR6m0G2p1eIb4YcgH+il+TUtynyzkRJ6X2KMwe8F6XLVfx5iaQROfcQh0YlREQC0vPltvQHztefHo76/9S+IUerZ+WjUWn7UT2pl2k046Mz801CR0KCWXrNjoDPdHm+QB/WdEY8lCvEfLu+4Jr9kRgMCXx91heHrjSYMYbbFJ6JjWNFnIcI48ozDroAA0qkuyPogLQE5nnyYZKvbit8GlrPxlWYN4jWqJxTNk0bpJBWJlo4mOMmpUDEH8tFIs3rAQaZy0SatHg5RCTvodD9viAWk9I6OpCOacyCghHoCYmpOWd4FnKuai9jInMsZEU2g0VdEW67+8TRYynuLRUTSUSQTNpZCN+vB8AeAzztFeEK9tDcmwNWLZg1Hsuqj5VYZV1gXxiCY4xeS4UmWbpKQYi6127LC2UbGtnxb34kcNA1icyE5XJF0w6s15ZJWdJGPJNqWtMmqyIQI8U1jGMwUXAwnl2scPsMk4yzho0bVKykpKknbQhBzcXry8cmxPmgw1qiQWT5fgvBbSUZyomGrw4ifnxTP8zbKgpFAbKPobTZEkujmNqqsgL95J3fPddCMg/1mzKYvsRX32lsTBSAqwwrz48PwkmZqe7KbV4yiaUyvL+0M8I6r6cSwWT+vtS6V0P0eb6P3EUbz4RnOoVObr0d6SOBKVynavvPgQMggDBc0r1diTQD+7XC/EJ8fVibKMony23mgq9eJTKpZmViY/DeKZeLNNUF8UrLDtMIkzXirz9Qjm49S07DaQZ5JUkrSDJmRWo42ioUwSry+FsVgEa4KyR3NKbS3tGovXEMaQTJZdop9RrhHi49Kx+KRI0Bau7FO/F89M16Zp18IQRu6rbFkx48was9EkD1iK75KlWohPhdcqKbcJQpaXUm0UDWX8yG6zGISte0G8fUY0yWSXb0vGYKHdjHKNEI+F0Yx1ueyu5J0L2YSmFc1YfP158ZZ9fBMsc35ePDVUDRqOmBe/I1H8annxUgeYiIAqz4svAiIJSoGgvEQ/Ay0NiD9AXjytx6bJKI96RqVzOC8+keufZiS0M96yyOWnXNAwCEcjW9ZkxUbPXpCMJnlA/xnRWKqF+FS9F589+1lTSmM6FsQFQGosHZ2uooh2icUXAZGG8onAo7xvNsoaxGtUdSzeiexZ4aKepW8dsj1TbbsjxDNZMROituS5H4y5uBZVNXZePLIyzNXTVARzTmSsFuJLr1VJyE3WjAo5VZkXrynSXhCvbQ3JaEA0ilFBXBcl+hnlGiE+zovF+1Ge7Sahdof24pmUmBknN7LTFUkXTNNpTVa2Adu2zaDHGMXest3R2529aHQtRlMIeUnSDqxJQqc9ioYyTElwlFHvIaux2uhsUX7aJRZvAJEHr9KzkJMD2ROxyp0hftm8eL/Usk3pW3viMfPiqZRkzJR+ZZsuExhjLmaKH9KiLNooIKvjfi++NhpdS7YJdTgr5E6Jv7N6zyiajlGdCT4dkyyJYOVrfC9+MsrjCY0tLz7NQ3k8GmhPPH4sPilnnZo386dGy0GgfLasyQonmcUyoymt6cV77GR0yXP8LKDStRhNICspSdpBEzKr0UbRxIJ4NEGvoJCEdWcViS7KT0eMxaeWFw/kR3Yb5anOFXnxKRVLMyuTZWPxi2CWh8UjqzCPimDOiYyLQzbVJadgDdQY1TQDASeTZxRNx0r1ymBhGiUVqdTW0gFj8UkESCX6jVplkaBeNhaP+o2XzXhkL35ZzPKwTJbVviyeq9dSmOVhKdKxHVk0HVvDe5DbfSHelpWUjAFERlPMpYHAKH4h1wjxWGh58XQXqeh78YkEQFMOsxZkMbz4aRnr27BkfS62Rlsysn5UmLQ+5rx4z1r2ZdHW6NElJ0uM6sQkxLe8eMMqi0DpZWPxQUlOSuIUerZ+2j4WD6Q1LcJSJKt9WTRvlJZLPdMiwR7Xi8+uq1SvRm08O3rlXjxbSxEQyTJ1PYGyfolWxgk76WVj8exSaXjx9rZU7X5ULL5CzFocskthLuvFe7b7smg6ViRYm4VpFN3+nFi85no6hVwjxMedYvH0aAj3kz1TP7VY/L4snqvXUpjlYSnSsR1ZNB1bw3uQ28q9eKk/oy6mUU4zjHd/iG958VvmxUeS5C4FO5MlOvLiu5KM9W1Y0BKM5fufWABLtkljQSUsXcu+LNryqc44JaaxxJYX/wxKNefFn1JKIYTPz+uvX5eg0/0e3t//7V6vVyhcLhfchfL9HmK80nok+Hee83kYLdPdxyOklH7//ggh3G4xpXS/g2SfDj5Kt9vw929BdqCUyfX6tS4/nU6nEP6pft9fQIxUYrRsNE1m6ftLqaxqIJz2zOUzVfQLFjR5q+UuRoaOhZLlj9p4dnRQ9a4LRbYWhHGNIpKkt7cTgIZGUjLX61UDojCGUX//foFS1/U4c4l+hlWezyc4jnOBE2QSQlC9eEaVBGpw6Bao8bO0QA2WiwTbAjUtUGOX0wzj3T9Qw4gGarZPmkxCOtlATUua1AxVg4aWNGmwUCMsWsu+LNoaPbrkZIktaTIHfV1LmhyVWla4cpRDe/HruZlOn8svq31ZNG+Ulks90yLBHteL1wCoaPmjNp4dvXIvnq2lCIhkmYklKx+jjBN20ssmTdqj+C2kVO1a0uS+LItDdinMZb14z3ZfFk3HigRrszCNkiex1NbSAZMms2Lx+CWJWGWRoFZ/3AoEzyve3k63W3p/D29vp79/EzyMzZaB5e3tFEK43RI8YbDLIQS6K48MfbAeDg6F0a3/KcWCj1u7LtDVbU8ozwOR1IRs2WhaluUotI2OjUpml8etQcGB8A1Z5/MTkoR5SsLgLnynpYyi4vt7uN/Dzo9bl02atFlY/ShLqRe/Y9KkpN1ZNK7aWNDnwnpUQpo0yZpslmyTxoKF0rXUyWLrzO4seyVNyvIcFv+NeNWBGuNWhW1LJeVkiceJxTeaTBJqZdloypad3agON9qGdonFG2VnN8aiRcmy5XohPo3h73xJOa+B6fkU2tsG8ceixSG7lKVB/Ja0VyxeKxd5pchSYSy+AOKp0nflefF2tyKW5sX/BHI66UbTsiyNVqVd8uKNsrPbZJbNIP5//qj9+/vXU4LPzyvs3u9fDzdoGZ453G4Jn9DSXU95tBv0oY9ToDAMg/GsNbsoWEsRwSttQby7i/WNZSkW0CsgKMt6o0nWjx6N1u++/MbiJzBkzfbxcagfiPx4JVkoKgIoSbQcXcti5Lw++GPxrFzkv/tZmhf/8tRi8T+KXiMWX8SyjRc/BeLTmst2srRY/MvT7lGaBvFb0mvE4v0sNUJ8PbF4Vm5e/EtSi8X/KGqx+FGq5WPCqWTZk1mKvPiWF5/2TnKfwIKW0PLiF2FpefFO/N2GZX+IZ8Tswb+e0iiNk6V58S9PEmpleVX/vXnxW1KLxY9Si8WP4HuD+GPR7lGaBvFbUovFj1KLxTcv/qXI6aQbTcuyNFqVWix+lGr5XnzKLXtxlqwXX+H34llTY/GzyGhJVCLpRhOr9xwN67MQX7PEDs2y1/fiZf02LAbE1/69eM+yMStfKxtN8m6refEvSdSrkJXJ7eZP9t+bF78l7RWLnwNE+GoRDW8kByqmDb34/5vwttT7O//GL75IJsshZLrF+MX+/h5iTH1/CiH0/QnqgSXb9PZ2gnJ4fruV7frfbi0l9oZeo/Wo7y9E2hfyZ6GX5z8O1ZrmsoR2uo9Ghu3Tr/hSjAKiCAPIA5XZJlrf9yd6KAMJWXm774o7rw9x0Vh8yDnmlEVrwjnv4sU32pKcTrrRtCxLoy1pr1g8xUYj9pBlt4/Mypt58SrEr5oXj5KSkG03Qb0Wi9e2S+XFS/Ln/9bDUnq0vVjQEoyIuT/JPX1fM1bNix9taixOls3y4ilkM9dTdtPqW178SCxeor/RROOkzYt/YZJQK8ur+u/Ni9+RtozFJ4EwUNC8Uo09OZCdluuF+OReA9Aoymfr7RulIi8+6Rk1BjWI35d2j9I0iN+RNsuLp5DNECb58MoOSmvlzSC+4HEr/hFrCOF8Pt1uyfNsIeQeQTweIZInGPd7eDy+/uYUpKY1vb+H0+nEnpn4/7vVv1ighb/q2aiEuu5yv4fHA0/BRSkbTbNYuu7SFOBYZPxjMzzhzKZ+9P2JIgwgTwgZ8NFAif53q/OJq/094SXJeX2gd83zk9yDGeeiLEGEwIIei182L16jxrINC7ulq4e2WX5jKWVxevFY1hAGWWSTZAnErzdGkfWGF/8iefFGnMsTAtsgFt9oX3oZiG+0DU2OxYccwhhNtD60WLynGxqPZGFNeAndIBbfaF9iN3Y1UG3zaURpciyeIUz69rK1Jlofqo/FF0B8/GF58Y32pQbxjYrI48X73U0b2bPs9pFZeX+Ib3nx/s6NZQ2WY0F8DRL74Syjtm+4m+kZYQzwydbXnBd/SimFED4/r79+XYJO8O4vEr7Yfbn8e89bK8um378/brcYQjif+xBC1/XYB55TG03nc//ff3/u9/D8Svo43W4DPPVudAi637/eIE+plrMGGljPfBpRens7nc+D0aHvLwBiFKNOp9MwDAxhoH8WfGQ9socxJKTlvr+cz6cQgh+URlE6T87rwxqBGlqP85EstCmJbJzUAjUvSsfy4hvtTpMDNQxhaPgh22SzJAcqpg0DNf/zXwze378+4gPJwjQ5nZZDCPd7uN3+JX7SXSiDjGg9XkIkC22630OMX/U07xUKwzCUJsVPSHxuLPuyfH5ePz+vdlrx5+f19++P61XtBmrMWuHIi+fC7y6xn8Oi2T7mrTMgyiIM1BtNNgtDRQAliZbLLt8i5/UB/fc0ljTJHltrl00tNN85kiaZp9+8+JekrBdPPz5OdZL1gU8M9X0fck43fow+e+TbbdC+Gi3n06ge8njx9nNBWm800foQnlgY+tnlbbz4KRCfzHmzuyGtW9LveowmDPIUPW5NLWnygCQhnv1TRPaEMkXtusB0G2OMlBis933mGpAaxNdNo7afxV+JMGlG0qQWC5LlGiF+8Vj8ZOE2L/4nkIR46gQkBawZMYf9fO6zHnrfP108hiHvyDeIr5k8Xrzf3bSRPctuH5mV94f4yUmTDH+zLNqdDqC/0QT1pV58S5o8IguDeNilHTS81oZA5UnC2WcXDwjyyKMZEF+DxH44y6jtG+5mekYYA3yy9TiK5tTK8v4Qz4gaQFwiFs+gnJWNpthi8a9O8jKfUrrdBgnxxvfHY+SBnWEYQggQpj+fe+qCSIjPQrkB8Y12J48XP+puFgERQ/wk0M8u1wvxyXF1oizO4FQRS5EXn1os/lC0IMQDpkNN1wXav+97cNUbxL8Gjdp+Ef768YqyeGJBadtY/HYfEw4hwN8Vesp0V/vbwwkfE17qH1wb1U/v7+H9/U8IH8MwwAsjj0eAHBug87k/n4cJ33RtWlQtlX5MOOhAZDRhmcFd+CEfE87G4uF6Ra9dRlk2sVE0L97+oGgSV/WfyUJ362QBzRyNxbNnpFmiXN1zdg113sOzFz8MQ/b+AObjPyP+5W/AIit/DgsUss8OuxIg6nRQwvrsKHJ0w4uv/WPCWizeI7WscOUoc2Lxmor8HJbS42/PkoV4aKJ6yBA/SzE+pdLTx7MU/YdhoCbAgvh0RGDZ/SROYKn/vK/Hkr6VJxsN7xZC+STQzy7jQpxUdSzeltSocI1RmrpPU/eaWTSIp9nrFLsNYm9IsaOh2seYaAqNZnjTvHjPtp33VVmgkMXfTgGiUYySh6ozFh+czHF2XrwmqVHhyiM3L36+utfMokF8+na3Y0zUH6dPRyFtBrrJN2DhwgC3zyzhEo7JjsyoefEHZYGCxN9uqv/e5VA+uf33VIMXv2xevF9q2SY2SqkXL+N0o2rxwix25xpYDIj3EPVFtA4TmpLpxdO1jC58FxZP51dl6b7RA5vmozw9VMuLb7H4ilhKj789y0yIX4+aF39QFihI/O3K3U1apocCysaCtDIuxEktFl+XVlXLUnr87Vkqh/gaTuJLnvf1WKCQxd/OFy6WZXkoiX5GuUaIjy0W/xIspcffnqVyiE8VnMQJLPWf9/VYoNBi8RbRO5GWF39oFrpbJ0vlEO8/I8m9/A1YZOXPYekIemC55cU/UYvFvwxL6fG3Z6kc4lMFJ/H/2zvD88ZVJgqj77mFaCuJUskqldiu5CqVLK5ktxN9P8hlMSB0ACONyXl/+MFCR4BmGI0ISQok8u3eTmIKXItPwbX4biS51z9eIjzESzBil3ZvJzEFrsWn4Fp8N5Lc6x8v8UK8NCQYsUu7t5OYAtfiU5fz3kSi/ea++JeQpE+WIDGRVGyI3x3L7sBPkSAn9yoZY/HK3sb6VRrui+davCBJ7vWPl2ThuV+6bL6WXV+UEbu0ezuJKXAtPgXX4ruR5F7/eElejG+MTCN2afd2ElPgWnwKrsV3I8m9/vESUcg0Ypd2bycxBa7Fp3DfRLgv/qUl7leZEhNbwRUV6xhpt1ydhCMrxHv9FLLJvUASHvw+kqgzcF/8AyeuxXuzvXItPmt6I3M+8RkerARspdHAtzqABKAsicE+xcEuIQnUiq3Fu0+C3FHgFvEkVYYButrUPSrt3nTg1iJh/M0KRGHZtu5mwKArys3i3a/RfntvQ1unuWVrqlDiVdmIH83ikc+oW2y5S+hJiD8l3B1sZauqJpiCrSQkWx2IfuJ3KZR4Fl+TcRl/Nbb3autS7vBti2Uxq0BSbBd7sMYiYCvRjrm1ZXZHWqlxS9cN0sHHHk9Uucdt65pr8W6VChLzNefmVmbxXyPfcJGt4yv8my+uJJxIYCvRjoGtJAYeDXO7w0934Ilhzt6l0Mpbayxp9/PK7vU9Qom9fkHMKgtzWXYJq2osEm0dmRdRV8m1u9qbF+mOgRZB4q/bEPgwcFvBXfH8EP/cffGexN6pcJamq/R//28zK4t31+msi7i4J28dt1VIK1binWblu61EOwa2Eu2YegwNWcN3OwAOP92ltMSdSFEfc9mdTu5iaPQ5kW4FjFP1m9xNW7hdwqp0K+nORFtH5oWhcpO7vSY4/LDn6VYSTqKCFYKoY6hkUOK++NTLkXqcpbtVunot/mvkDt4J0eNrkLDsfoYHrXy3lWjHwFYSA7f3Kmv46Q5EP/G7FEqsodPzxM633enk3iskHXP9LXcUuEVCu2fZJayqsUi0dWReRF0l1+678yLdMdAiW++FaxBh3A6EVVvyNYh+6bIdCEhZiB9MLz8/bz9/XtQ297t6e/v79Xa7XS6X2+2mlLpcLuaIKd/vSuubKRiJOdl8teVleTeXmudf0eOJqnn+pZTS+pbo8BbmH7/9d51pWfQ8T0opU1gWnTgeXqGgdaSVrarKps2VzTUTrYTHraSmA7ld1Xo11leBj9lyoqpeMgzDYUN2GwLtYo/YQr17eK2kO+B6bOVdQuZFomNg69N0eXtTYSAaxykaYcB4ZeUGE5d2fWyaLvM8KKV+/0Z/1r0bpeOAzwf3MYXsTlud52coUerhNPX4EuRKVPB+pNTfH22vj09pZKuZO/DRWcTwjnsn2yqloFbWx4zGSsBWoh1Tez9uTXcMbCUhURsrRdFP92vxpsldH3O/4psmQUn0nrfbAVnjluYgbpGwY8VuuT7m0elWtjrW2i2jVt6KMK5FvKpQopx3wUQrUVccN7J46ZsmvXK0SiVfghJV9njNQo11i/Bg4rj6b7ESbys8CLayVQW2kh548fC3OoCEuSyJNfquj4FvxO69wiW5Q861SDTMlbnlCqxXIO5R5jBubZndW7ulKWwt1KhYhElUucdN62HCgZTHjRC/hZRNk14ZOc2aKpR4VcYbNDdN5gdTsJWEZKsD0U/8LoUSz+IJ58lyxfExewDdsixmFUhq3NIcrLFIsVuue1k8YvfWbunaNx187PFElXtcOdE/yxUlhngtZtOk10rWpDLylT9uzRl+ugNPDHP2LqmNTZNeGZxOtgye5t6K3FHgFgntnmWXsKrGItHWkXkRdZVcu+/Oi3THQIsg74VuQ+DDwG0Fd8XzQ3zxpskVGLa9U9Y13eifqNLJtfitT26adGdRugPR424HwOGnu5SWuBMp7WNbrrglAWcgN02aVpB5YeCmyXQrYfn8EO/hLtToZ6zFG/TGOleiKpz5+KRamcW/VBaPzJO0+3ll8DTX33JHgVsktHuWXcKqGotEW0fmRdRVcu2+Oy/SHQMtEnUYI4+mnqEzRIPS6oRH3BVFh/g1Z55sVVmDlb0oZWXx7qd1ERfvhOhxW4W3tTWRkFaiHSuYuqE83YHo8XQHop/4XQolUetHy1muaO8VKDHdKItZBRLVJosHLRJtfdcxwklRZnd7BXD4Yc8Ri0TfC5UTsm0T4cPArdqSZ7mixBCvn70Wv27cwfTNNTauyeLD+eA60NZxOwdqwhzYylYV2Ep64MXD3+rAE8Oce5eQOQNOJ1sGT3OHnzsK3CJhmCt2yxVIZhH3KHMYt7bM7q3dcnWiamhxe50we4hWpSWgj0kM8bbAffG5MYv74rMkpq1ozuWV3a/cF49bJOxYsVuuj0+XdCtbHWvtllErc1/8A+5Cjea+eKyt8CDYylYV2Ep64MXD3+oAEuayJNbouz6W9WrsejIiyR1yrkWiYa7MLVdm8YBFog5jnU09RphElXvctF7wjig3i3e/IuNBTrOmCiVelfEGzX3x+cEUbCUh2epA9BO/S6HEs3jCebJccXzMHkC3LItZBZIatzQHayxS7JbrXhaP2L21W7r2RZZcNPfFj9wXXxTmlJNzpVuJdgxsJTFwe6+yhp/uwBPDnL1L6luuxWfZJayqsUi0dWReRF0l1+678yLdMdAiyHuh2xD4MHBbwV3x/BB/5L54r5yo0sm1+K3PcM2xBqSVdcPdK5sGW4l27CmAN3nXImmJaSuac/W9L76FdfB98TXU74t/+sDdVhIWVxWByJa5L/75b9PFWXyuI/Ynyb3+WRIk58ryK3OvsvIssUbs2O4tJNajGr3wlUlGsSF+bTlsUJKVxYefMh3xSHeXL3l6yB4r8ixpRuzY7i0krn1x6+N+VSCRGOL189binyuhuzcNDWdJEE/I8iv3XhVIRBmxY7u3kFiPwq2f5SQFEokh3hbq98XXS6JZfM2O9e8jcb9KliA5l/v16fvio1l8u33xrSXhwe8jiVo5bf3WkkSI72FffL2EWXyxJPf6Z0mQnKt1niXWiB3bvYXEetQxL3ygZJSZxbtfT09c4a0AAAgPSURBVLxT0Swe/5TpiEe6u3xJi7fpLFeMZvFCjNix3VtIXPvi1sf9qkAiMcRrrsV3Icm9/lkSxBOy/Mq9VwUSUUbs2O4tJNajcOtnOUmB5PwQ33RffL0kK4sv3kvepSR9shxJNOc6cl98VhZfvy++tQQ5uVfJrsVD67eWnB/iPdyFGs21+FeW5F7/LAmSc7XOs8QasWO7t5BYjzrmhQ+UjGJD/Npy2KAkK4sPP2U64pHuLl/S4m06yxWzsnjaXbLEtS9ufdyvCiQSQ7zmWnwXktzrnyVBPCHLr9x7VSARZcSO7d5CYj0Kt36WkxRIJIZ4W+C++JeWuF8lS5Ccy/3KffH47f1ukqiVuS/+AXehRnMt/pUludc/S4LkXK3zLLFG7NjuLSTWo4554QMlo8ws3v164p2KZvH4p0xHPNLd5UtavE1nuWI0ixdixI7t3kLi2he3Pu5XBRKJIV5zLb4LSe71z5IgnpDlV+69KpCIMmLHdm8hsR6FWz/LSQok54d47ovvVZI+WY4kmnNxX3yxBDm5V8muxUPrt5acH+I93IUazbX4V5bkXv8sCZJztc6zxBqxY7u3kFiPOuaFD5SMh4T4fwr+x8rbm5rn6+Vy+fFjmOer1ur373WrrJRCTsuVTNNX6+bTSsBPpRR+cmeS3Ht1lkSpfYdRSuF+Ze8VKDE+JtOIHdu9hcTcK6WU1jfQ+oj71UiWpfZ/XaGAzwd3ocae7KX20XIjiXe+oeApR4lYiZdKJ8or7GPeV/rYt5JkWb+1JOpdBhGbJrPKLSSJG0T6IBpq0yF7twyeRh/rktYOUyNBOGHTJF5+uoTTr3tOn4H0sc7A3wsLHga5Eokh/oBhl0lIl4CekKg6Ps8ikkHeC6Pnt5CcH+LTmyaj5eiqUyNJ1g2SsxpICS6J5lyVPgbOQPpYl5Is67eWnB/iPQqS8Rr57mnMsLoHySqk5VlEMq0dpkaCwLV40hWnz0D6WGdE3wu3ygVJbZZEYog/YNhlEtIloCckqo7Ps4hkkPfC6PktJBJDvC1wXzwlB0jwnGuFfcz7Sh/7VpIs67eWJEI898VHTib9geRc0vIsIpnWDlMjQeBaPOmK02cgfawz8PfCgodBrkRiiD9g2GUS0iWgJySqjs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9rx6tcz9u5sI6dh6+P0n75hDrXjle59HYurGNnzXa1bL/kXt4L5ZhS2rmgH7/a9AzN47KLnf/4ZnyQbSxJz4IyrwL7Qr+el/l/HEf8blbKystFu1U7gi7Y//luKdLYv7Xz83uD0mg753dTnmCH6g/YuchSdlL9rmPn57tgLNuhT8aj7Vzk+D7drmDnwiH2Dz+195MPtSOXy7c/8bLj2C8Fvp1r2v/h2s8IfAoyPy+kItMqqJY3pa/auUXvvAiXseCQUOApMO0XOZ7do7Ds2ryXncBcq1l2rPULO3vZCX33o7udh6/Psv3A4na4PRzN9ZjZXGq/CIV1fOd0DbpiESFjk0NtBTic1sw0a3jc2qfvHoVSX3Nt3svOgTX+V9sp9el2guV+fMDOw9dnzX5gNTtyP0PRXI+h1n5KncJrvNPDOr73BCIhhHAaEYuTYehHGugNlml8QYsv88tzpZ5KevErWUqjt8Olp/bLND125PQj7KSaFeyU13CcnZOcNSTY0ZTXyw4t4yJ2vMr1vJ1I2sloO6eifziLs62G2lGWl+Oz7HiVK+lc+lv7l8E2+2ftHDMN90K0nHVG/406NGRK0XjWmdfUDdWFqKo34GLwUZ8nc+v/cbeWlv61Xp9ksN9+FilX7WT6UDtC+jKof8ZO+H1Jm8vlaCf8bgacnWrRBtkJpCUI5eK+NcIOLR1np3pBxtkJ6vZJ28xoO8GpP/Gy8/N4v0QdqxaKsy/4o7Ef+OtQQj826SHnTj+9bYd6PagXSTzPF/HSH4Zpv0hYb0132bV5LzsBa/ywg71HsDO4P+H0zE5CZz+z7H6RWeN7y+9oJgYi7pfpOI4Y40F2RPfwZL/Uj++ehgab6buXmD0BpDSZfv7+tUKWnrNT6tPtZHy6nYevz0l27y9ix6tcjnaye2QFO6b2ADsP9yfpIyunUPb/zfx4PCx4PseE9vfR9DhkMiJ/1IPP9x0E4fecWMkvBz4j311StR++nWNCm31a3u3slHU0zo6+Trn6creTdP01hx25DTxjx7d/cLHTcM1H2wnL9CcP9DNZPx9qY02ZrxfkYfRQLFE16IaxW95OUiKq3/7npcsf9SCQPWgy4u+NPLdpqKhJL9uPzHsgG/yBDh069L+pVz9KYvbpCH+4NOVXGoZmjdmGTzt1ZZHP8+yNRUY3FPlbnQjfiTWqyJxLP1S/Ls46/kCHDh36dnoUf/3E8Sx9JINRsz8yz77lhWiPRbiv6HU5UwpzgaMiymvTBacHXaZAfqMlp6cecpe7qlftl+mb7UOHDh06dI2efZSlz8gIfziefSvWYhEhvVLnUlrTm3Q5U4r2WMTFUY1B+aMeVCPlKi/bh0skrrRPi7/IEwZ06NCh76Vz/CRjwa2dK1mbP9l3OZ591wvREotwib30EuYCxyLW63GI6oLT+vKYEJr2i5h0lwouPx3dUKBDhw79ZTrXLSdRY4fjDf5wiLNjEcfrryzy2RaLjG4oegudCPb9IqdrJK7UY0ckDh06dOjQg3rmQ9YjCWhc/Cx5ltILUReLcMnadDlTCnOBfR3VpDyHXaZQzItYvb3VM9Jmh37aYwc6dOjQ/6weYxTSp09lO1Tp95N+Sv8N5Cn0Nr1S5z5t8FCvy5lS+MQiqRgayEb0mfYjWPaLnCMjcdk+rddFnjCgQ4cO/U16LMaCavoYY3O+8Xc/z/HMjhfiXSzCJYg6VDOSM6VwOOssKfRUrh/Xs/ofOOtMhubwFu4At8CXV+8qAAAA8Azo+JXhgYO/Zp11JoxT2SG21fE9/Uvt6MfuljPgM0etgcVqA/PtKXhBfCfClYbT6XfL9LHp1Felz+Dg4ODgiev7W6GfDwS3/X+mc2NE6WdYA0ftpYOhady/Rcu78TQZmxxqKwAXvlh1WvGpQYTi/QLh62eZXtCr9rn0en+gQ4cOHfogXejnA8Ft/5/pHOf8ofAa7/RomFDoWb740KugAZ2ZKRdrEs9maWgyYYln4hrNbaQc1O+DsPLbiJ4Wf5EnDHBwcPC9+MG8P6jkI/r5i6/8PhpubaWcHamO750BSuMazW3EdLu2dGvnYdCKr/K2NUJ58ew4jtt8rX6Cg4ODgzfzchNhOTCXnEuf6Uof5qI60cCN49VFnPQtfaYtazReUzeLBCKfz+eWZ+t8FzmKNcI2HRwcHBx8TZ712wkP9P9T0BBguYzvLbGIdfOpYyDitWZG9SwiVuqHfe8I9ohAhw4d+kZ62W9feKb/HzHeybBONHB6y/h+GhHF80WokiCnlC3fftSDEEJc43wR2QdafE16cHBwcPCMK/tbOf01qJnsJz3ufL5IqVA9dp8v0vub3lCsn11kiz0iFOd5Knnpv6AfxyGkV+bb5ic4ODg4uJVfoQDXb4diJqBhXLjlUyCseJR7V93H967f9AoZN+wp6fSkGZp1O+F8EVkPxr0m4ODg4OBzudDPBwJNeuF8kVs+HaP3iFDgfBHV2iGNlE1rhFX72DsCHTp06MvqQj8fCG77/x+cL6LHaUR1fSgp2RpSqVe/xRks0/giWPaLxKY1wtI+Tc99N+MR+0XAwcHB+7iyv5W/G1v3DpbfVfrpBXkYLUftjN+O7w2ZUvifL5ISuNh5DOd5ylzY8xFjTOXNeEqT0neuHWrSg4ODg4O3cWFG5OrMj+MQ+vy0wSIQWH2Yi3KcKjeFKO3oM22JRbymbhYJRD6Kk/uEdw1Qnhox1S+lJNV/OUzcTwMAAPAONPe31S8K/X9Kk40XpV5ybpnmGZTjcorDGsZ3w8h1GmGditHrmjUa39wDWUOx2knTVulfOlV1q2dm5Xz11wo6dOjQoVf1hv42UyIBp6dPZcuyn9fQ7HsduE8bPNTrcqYUPrGISwEEp/XlMSFY9otQPRZrh6kJZt/l9MyO7AMtviY9ODg4OHjGlf2tkF7Tz5djSjlemPL1wm0s4h6I3GZK0fub3vDsz37G4TxPJb/8T/q1dniV6NKPLyJ5r0HVjjLfNj/BwcHBwa08kl9NVtNw/Xw1vWBH4FPgMo43j+9Pny8i6J2eNEPzO2/ufBGrfvt7dHBwcHDwuVzon3v6eZwvImDI+SLPFIALX6x67DhfJHGlTiNlTb7QoUOHDv1hXXlelLWf5zjnD4XXeKfH0ysepxHxbk9Ksy4sLOnXnEwI3eeLVPX4RdI1XPAhYr8IODg4eB9X9rfCd+l4UfbzSefyimvvF9Ek9tJLOJ8vsu/ekfM8Zc79Xpz+7jyEEGP8qZ3Vf6Uvy3ubr9VPcHBwcPBmzs1wXCTNjlT7+Uhm0AOB1Ye5mLL1omWN5mWBiGm/SFCsBVr3joCDg4ODr8mt/XzwewfZFMwa31tikRfsEaG6HBFzunXvCPaIQIcOHfpeesMeQaUdjT8jxjsZMycaTiOqyz8ua0jCwpJ+zcmEYNkvQvW0npd0Ye2wqmd2ZB8i9ouAg4OD93Flfyuk1/Tz5ZhSjhemfL0gD6OX/6YvanT92N24X4SiXDPLPi3FFZZmMpznqeRZxHccRxYRZ2uHgh1lvm1+goODg4NbeeT3fNC+vdrPczMimZ1bPgXCng/NjEsKA9rG995YRMg46Vkx+je5+OJjeR9NuUaYGlzi9LuynhquxgdwcHBw8Gau72/LvR10LLD288nOFu+joTi+75T5Kd4sUx3fe/aADjlfJBhnPubuHdGs4dFIWb8WaNX1/kCHDh069EH6oH5enkEpdYpxe0Q4WMf3nkAkhBBOIyJ/HEgk4PTqtziDZRpfBMt+kWjc86HRuTQZj9gvAg4ODt7Hlf2tez+f9Lj2fhHu3/g9MUUe3xsypXA+XyQU521cCrenpDeS8sN5njKvrvlxa4FWXebW9ODg4ODgbZyb4QgEI/p5rs9/HqX/dLEm1MZ3zo4+U8/zRYLTz30fxkfxO2/T78WtOjg4ODj4mtyrn2/o/6fAOl57je+e54tY00/cI0J1OSLmdOwRgQ4dOvR363P3CI4Y72RYJxo4vWV8P42oLv+k9SSqcGtLshF9pv0Ilv0iVI8D9o4IPkTsFwEHBwfv48r+dlw/H9feL8IlqI7j2fgei/0lmkwpPM8XCST+2mKPCMV5nkrutXZ44HwRcHBw8MX4FQo49vOdewQfg7DikW0KGTG+d/2mV8i4YU9JpyfN0Kzb3b5TBntHwMHBwd/BB/XzW+wXoRi9R4QC54uo1g5ppDxr7RA6dOjQoT+gD+rnOc75QzFujwiHhgmFrhWP04jq+lBSsjWkUq9+izNYpvFFsOwXiQP2iHBpMh6xXwQcHBy8jyv7W/d+Pulx7f0i3L9x0/NFUgIXO4/hPE+ZC3s+4u93E1R5St+5dqhJDw4ODg7exrkZjkDGtds+v6Gf5/r851GOU+WmEKUdQ66nEQ0RkFKfNS9CL4KJlzMcKUIs9bMWKetnZay+gYODg4NT3tbfmvr5hhn0qp9U8YJyXsR3fNeP3Z7nizywycVrzYzq53kmXkbEnC6sBVZ17BGBDh069L10az+vt6PxZ8R4J8NrHG8Z35UxS0I1zHGJpIQASh9bmRC6I+WkcxGxS6RMi69JDw4ODg6ecf3MBJde08+XY0o5Xpjy9YI8jF7+m76o0fVjd+9vesOzP/sZh/M8lfzyP+nHccQYrxJd+vFF0jk7ynzb/AQHBwcHt/JIZrKrabh+vppesCPwKZi44hGeP19E0Ds9aYbmd97c+SJW/fb36ODg4ODgc7nQP/f08zhfRMCQ80X22juiWcOjkbJp7RDni0CHDh36XjrXb2fprf08xzl/KMbtEeHw9IrHaUQcs9tWSCB/1INg2S+SreEJevwi6Rou+BCxXwQcHBy8jyv7W+G7dLwo+/mkc3nFtfeLaBJ76SWczxfZd+/IeZ4y534vXv7u/Kd2Vv+Vvizvbb5WP8HBwcHBmzk3w3GRNDtS7ecjmUEPBFYf5mLK1ouWNZqXBSKm/SJBsRZo3TsCDg4ODr4mt/bzQTdeaHyYglnjO84XuYmIOd26dwR7RKBDhw59L71hj6DSjsafEeOdjJkTDacR1eUflzUkYWFJv+ZkQrDsF6F6Ws9LurB2WNUzO7IPEftFwMHBwfu4sr8V0mv6+XJMKccLU75ekIfRy3/TFzW6fuxu3C9CUa6ZZZ+W4gpLMxnO81TyLOI7jiOLiLO1Q8GOMt82P8HBwcHBrTzyez5o317t57kZkczOLZ8CYc+HZsYlhQFt43tvLCJknPSsGP2bXHzx+XxSI+C4sEaYGlzi9LuynhquxgdwcHBw8Gau72/LvR10LLD288kOZ5Pzczqu8T39pR9Vx/eePaBDzhcJxpmPuXtHNGt4NFLWrwVadb0/0KFDhw59kD6on5dnUEqdYtweEQ7W8b0nEAkhhNOIyB8HEgk4vfotzmCZxhfBsl8kGvd8aHQuTcYj9ouAg4OD93Flf+vezyc9rr1fhPs3fk9Mkcf3hkwpnM8XCcV5G5fC7SnpjaT8cJ6nzKtrftxaoFWXuTU9ODg4OHgb52Y4AsGIfp7r859H6T9drAm18Z2zo8/U83yR4PRz34fxUfzO2/R7casODg4ODr4m9+rnG/r/KbCO117ju+f5Itb0E/eIUF2OiDkde0SgQ4cO/d363D2CI8Y7GdaJBk5vGd9PI6rLP2k9iSrc2pJsRJ9pP4JlvwjV44C9I4IPEftFwMHBwfu4sr8d18/HtfeLcAmq43g2vsdif4kmUwrP80UCib+22CNCcZ6nknutHR44XwQcHBx8MX6FAo79fOcewccgrHhkm0JGjO+jzhdp2FPS6UkzPh3ni3zufo8u62lqTuPDdD6xjgAA2B1Xzz+xH9P3t779fNL3PV+kqnPp2/LqikUa1pYEO9ahzmsrjWYNj0bK5V4TL13vzyx9wQktAADWR+ruVujHbvVB/Xw5psj+UHiNd3o0TCh05XgaUV0fSgq3R4T7SDZYpvFFwPkiFq68VuDg4OAZt+7VWM0Hl/5/8f0i3L8R54s8ifM8Zb7I2qEm/SCe6m6iD+Dg4OBDeTlj8Uw/z/X5z6P0P83xcOM7Z0efaUssIgcQ1bUlTr+9Rq8AACAASURBVF8hEDHtFwnFWmAqF93/UepXhWV29tovAg4ODt7GV+jr2nyg/Xa2z0/o/8MXVTtKP6dAWPQJ/PjO2dGHIy2xiMuqVVsg4pUL1Wk0ql9TLOPElKaqV9cU91pDBQcHB2/j1VnVh/uxhv5W2PPB9f9KOxo/R4x3MqopaUndc/wfTiOqyz/WtSKTEfmjHoTu80WSntbMsu9yemZH9gH7RcDBwbfmO+4X0ffnVC/7yXK8MOXrhdv9Ii7j+Fnba6JB13t6LzwzIzIa53kq+eV/0q+I+CrRpR9fJJ2zo8y3zU9wcHBwcCunM9nVNFw/X00v2BH4FExc8QhtZ8D3OCSvRU3BR/FeAO58Eav+6Xg3ATg4ODj4A1zon3v6+S3eR0Px5ERDVyzy/GpW9i0XXbN2SCPl6rqgUqeR8mp7QbB3BBwc/JlZh8V1rt8OtXFBSM+NC0p/KLzGOz2eXvE4jUjLP+5rS4vvF6muNSr3iGi44AP2i4CDg2/Nd9wvUn6X9oHC3hEur8X3i2gSe+klnM8X2XfvyHmeMs/8zPSD7ND+qf0O+0pflvc2X6uf4/hR2wkPDg4O/ibOzXBcJM2OVPt5OoMeCKw+zMWUrRctazQvC0RM+0WCYi3QuncEHBwcHHxNbu3ng2680PgwBbPG95ZY5AV7RA7d77wF3bp3BHtEwMHBwVfox8b183o7Gn9GjHcyZk40nEZUl39c1pAW3y9C9bSel3Rh7ZDba3Jivwg4OPjf4DvuF9H351Qv+8lyvDDl64Xb/SIj9ojox26cL/JfnOep5AfOFwEHBwd/Kacz2dU0XD9fTS/YEfgUzN160bh3tZpxORFUnRrq3+Tii4/lfTTlGmFquNV3Exy/31/w+f1uglIHBwcHfx9foa/T+1Du7aBjAdfPJ52zs8X7aCgO8Z0ymf7DHxWvQVcsImRM9ds4Qy6wNXerrlnDo5Fyudck6Zn9Us/S3+a7sg4ODg6u5MfvX5qUaZbSO/v5TK/mpfGntNav60EtZAWpju+9OZ5GpOWfch0oEnB69VucwTKNL0L3+SInvwap0bFfBBwc/C/wHfeLaL5r0hffL8L9G78npsjje0OmFM7ni4TivI1QvM9QaedhnOcp88zPSy/9b9Nlbk0/iKe6m+gDODg4+FBezlg8089zff7zuJ37Kcd3zo4+U8/zRYLT5peH8VH8ztv0e3GrDg4ODg6+Jvfq5xv6/ynwWgyyju+e54tY0zcEItb4S6PLETGnH8zvxa26Nd+5Ojg4OPi4GYjVdK9+vq3/HzHeybBONHB6y/h+GlFd/knrSVTh1pZkI/pM+xG6zxfJ0nvpGcd+EXBw8K35jvtF3Pv5xfeLCHs+uD0isbbdk+Myen/TG5if9W6xR4TiPE8l91o7PHY7XwT7RcDBwV/Po/hOmef3CD4GYcWj/B2N+/jee9ZZw1qRdYlnNDTrdrfvlMHeEXBwcPB38EH9/Bb7RShG7xGh6IpFGtaWrHbkb7nomjU8Gilj7wg4ODh4G1+tH6vqg/p5jnP+UIzbI8KhYUKha8XjNKK6PpQUbo8I95FssEzji4DzRSwc+0XAwcHb+I77RTTfNemL7xfh/o04X+RJnOcp80XWDjXpB3HsFwEHB38952Y4AsGIfp7r859H6f8x/nyRllhEDiDK7C+lqq8QiHws76Oh+sG8gybU3llwVVhmJ6XX+AAODg6+KV+hr2vzgfbbx+/3iAn9f/iiakfp5xQIe0ECP75zdvThSEss4rKZpXmPiHvuNBrVrymWcWJKU9XLijl3e0cDODg4eBuvzqo+3I819Ldlvy3383o7Gj9HjHcyqil/+JfeeY7vpxHV5R/rWpHJiPxRD0L3+SJJT2tm2Xc5PbMj+4D9IuDg4FvzHfeL6Ptzqpf9ZDlemPL1wu1+EZdx/KztNdGg9ze94dmf/YzDeZ5Kfvmf9Csivkp06ccXSefsKPNt8xMcHBwc3MrpTHY1DdfPV9MLdgQ+BRNXPMLz54vIa1FT8FH8zps7X8Sqf+5+jw4ODg4OPpcL/XNPP4/zRQQMOV/ksb0jLrpm7ZBGytV1QaVOI+XV9oJg7wg4OPgzsw6L61y/HWrjgpCeGxeU/lB4jXd6PL3icRqRln/c15YW3y9SXWtU7hHRcMEH7BcBBwffmu+4X6T8Lu0Dhb0jXF6L7xfRJPbSSzifL7Lv3pHzPGWe+ZnpB9mh/VP7HfaVvizvbb5WP8fxo7YTHhwcHPxNnJvhuEiaHan283QGPRBYfZiLKVsvWtZoXhaImPaLBMVaoHXvCDg4ODj4mtzazwfdeKHxYQpmje8tscgL9ogcut95C7p17wj2iICDg4Ov0I+N6+f1djT+jBjvZMycaDiNqC7/uKwhLb5fhOppPS/pwtoht9fkxH4RcHDwv8F33C+i78+pXvaT5XhhytcLt/tFRuwR0Y/dOF/kvzjPU8kPnC8CDg4O/lJOZ7Krabh+vppesCPwKZi79aJx72o143IiqDo11L/JxRcfy/toyjXC1HCr7yY4fr+/4PP73QSlDg4ODv4+vkJfp/eh3NtBxwKun086Z2eL99FQHOI7ZTL9hz8qXoOuWETImOq3cYZcYGvuVl2zhkcj5XKvSdIz+6Wepb/Nd2UdHBwcXMmP3780KdMspXf285lezUvjT2mtX9eDWsgKUh3fe3M8jUjLP+U6UCTg9Oq3OINlGl+E7vNFTn4NUqNjvwg4OPhf4DvuF9F816Qvvl+E+zd+T0yRx/eGTCmczxcJxXkboXifodLOwzjPU+aZn5de+t+my9yafhBPdTfRB3BwcPChvJyxeKaf5/r853E791OO75wdfaae54sEp80vD+Oj+J236ffiVh0cHBwcfE3u1c839P9T4LUYZB3fPc8XsaZvCESs8ZdGlyNiTj+Y34tbdWu+c3VwcHDwcTMQq+le/Xxb/z9ivJNhnWjg9Jbx/TSiuvyT1pOowq0tyUb0mfYjdJ8vkqX30jOO/SLg4OBb8x33i7j384vvFxH2fHB7RGJtuyfHZfT+pjcwP+vdYo8IxXmeSu61dnjsdr4I9ouAg4O/nkfxnTLP7xF8DMKKR/k7Gvfxvfess4a1IusSz2ho1u1u3ymDvSPg4ODg7+CD+vkt9otQjN4jQtEVizSsLVntyN9y0TVreDRSxt4RcHBw8Da+Wj9W1Qf18xzn/KEYt0eEQ8OEQteKx2lEdX0oKdweEe4j2WCZxhcB54tYOPaLgIODt/Ed94tovmvSF98vwv0bcb7IkzjPU+aLrB1q0g/i2C8CDg7+es7NcASCEf081+c/j9L/A+eLPADNuh32iICDg4P/QT5xj+AUeO0RsY7vLfMiwuZTfXzUvEfE/TLJETGnpzgxFS3GKPOf4h0HNI0y37k6ODg4eAOvzqo+3I819Lepn7/E4zhu+3mNHaWfz4cFcsqx4/tpRHX5x7pWZDIif9SD0H2+SNLTmln2XU7P7Mg+YL8IODj41nzH/SL6/pzqZT9ZjhemfL1wu1/EZRw/a3tNNOj9TW949mc/43Cep5Jf/if9ipSvEl368UXSOTvKfNv8BAcHBwe38kh+NVlNw/Xz1fSCHYFPwZSlmYSnzxcR9E5PmqFZt+POF7HqPWuH4ODg4OAPcKF/7unnt9gvQvHkRMOQ80WeKYB+7UrWNWuHNFIu9VD8Hp3TaaS82l4Q7B0BBwd/ZtZhcZ3rt0NtXBDSc+OC0h8Kr/FOj4dXPD7WeaGUn3sgIpRk0LLO5/NJ02ufz/8uRcmvev33759GT40p6Vd0LHPBB1p82c+hXHmtFuHXtaV1AQ7+Mr7d/bivD6k/Sde87OeTfm1TrY4XPz8/Vj+9IA+j2acTJhpOIyL/crtOXdjkot//YkIg+4xk3PofCap61U5n7g9jETeUqHrr3m6VFQr97+iaPs1Ff8H9uKYPZTJ9P591+M0ONAzNGrPKTx3brb7eW2KRQTeY4PSgdhy+E2JU0XP63fjdQX2h1M+ihYXajusqj7rd16N5z7V6npfXlvO/R+f46HyhQ9/9flzWh6y/NfXzmc7ZufWTKl6Qh9FI4irT12VdP3abC+zrqCblOewyhWJexOotdSxBo2dmrdU5rhYEXd+qVkBzzZr0QS0T+r46d8+657v1/SiI4/SG/lbZn8cCt5ZlP2lUdJteqcsNZlC71bdSn1jEpQCC04Puuv5IOempCZYRblXP7Mg+0OKv/1SxCI/FU4ucpk1PN/BST8bQJ+oN93ubvu/9uIsP+v6c6mW9lOOFKV8vyMPo5b/pixpdzpTCXODS9IgC6D/qQWjaL5LxVIVJjwQnX8dC3Qu5T8QibihBq0NO0KMPuoGhQ7/VN70f1/ch68+zj4R+vpoL/VfvwJRYZISur/feWMSxAILTg9pxsO8XKdOn5lg+tSQ9+d/2ZBN10fRobr1Wc3nqINZ5YoYO3VHf8X7cwoesPz/F68/1/yU3+UkVL8jDaPVTYbxW6vqxu/E9vRfKXwFln5rsWH8P7fXjoqviL5znWdUvXvqZpTlq7yMo7Zd2uHxX1hfnx3GUNU6vv4te9eGBfKEvq5f39eh8t+DVvnGFfqyqc/UYxH4+6Vx7kMeFUqcY+GNaBslCdWiuil05KmOWhMjMRJ3FnFVVF+ImIYDSx1YmBO9I2aoro2ZafE36QXyFJxs9f+YJtbwmz+QLfVk9MnvL3PN9x/24iw8u9Rh1M9zZd70gD6PlqJ1xbhCvispMKRrPOqvGXMf3bbThd9BE05dTKelfIY7rD/GqoOd3yfCKSYXiN+T+MBZxQwmhiWpQba6lcbk96zPi7HeaGmSn2dQ4O22mRtjR9GnlE7OcEefn7vfjmj5UW+mI/l9wYO5ZZ9V+IxvH06epJcshwS1azoAXivTwJJILNO8FML1TxqqDP8PT9b9aXfaeiJ+fn0zvrN9b+8HYrvayk27tdez8fE/MHGqn5x0lpnYI/gz36ucb6nEKHg68ElpiES5ja/qGQITLpUen4WdUrykezDtlrLo137n6vvy6/tUyVvUyPWenzX4Q32FRLYvS/t+0cxR7d2bZsbYfTTvR+LkjX61/G9fPt/X/I8Y7GdaJBk5vGN9739PblnHzjIjLZarqVzSaPfFwPHvCbtZv87X6OVrflMtPwHq94YnHxf5qdpT2m2eYBtlxr8fOJ+PbGSlrvtvxWf2YrJftrbOfv62v0p8L48a7KprHZRc7Xb+jKTNO8dcPs7YU/ArsC+sTdvndBl2Zb5uf7jzV4wpPVD31Fb8vr8raZ9KVdk7x1zqh2DvF5atsJ+vYub51a4fOEIy2c5Hj+0uHiXZC0fU3t8Mf8Vc5m96P63NlO+nUZT4F1XH5IJtFaMqyHab0beN777wIl7HgkFDgKdBE8V57CN73ZLM4V17/0U/enP3mvQWw02YnONWX0s6T7RDckQ/q57fYL0JhHd+bA5HQGYtYA44GO/K3XHTNGh6NlLF3ZBd+PL5Hgatfr70pe9kp9el2gq6d9NiZsgdoI75aP1bVB/XzHOf8ofAa7/Swju89gUjoiUU6M+63Yw2DZP12DS9FuIN0Ll+rn4/p6/MpeyaEJ9c37UHx2uswYs/EUnY66/d2pmQ7vlo/Vuqz+nmql/DSlWgYlztzbNwvchsxHYPXltxxG9Fnfs5aO5z4ZHPsvz59uO6ZuE1/HIdmT4BgP8Frj8tjdn7EvQ7udlKdytdZU79edm714zhu7Qt7F15wP67JuRmOQDCin+f6/OdR+p9aLDe+c3b0meJ8kfYn7AN7RLbih25t3mtv0Cz7f9ZOMM4oDLLz2F4Z8Ge4Vz/fUI9TYB2vvcZ35/NFji/KTzO9LRCxxl8avW1N8fiuBaaiJR6+7ybI9B/sEZnHj2F7JtrsB5wv4mrnwPkiG/LV+rfbPR+afl5jR+nPiPFOhjwuC+O7yU4dpxFxzNv8hMTyRz0IIUT1+2ioHr/vC0h6/CL7LqdndmQfIt5HY+f02pbcq74i/zZgjX2uXWnyzexzfJYdr3Lp7dD2KdTvaDvW9tPcDuO29+MuPrTVV1kv3P2uzNcL8e59NFyCHl3OlKLxfTSy4qvLH/Xg0/Q+moxf5HYtrcyF0+XcJ2IRN5Sg1UHdVj4iVOvLVInWjIT7QmMnkC0Oo+388CvEpaln7AR7AUfbudXbmiLXsBfHCt4qfUgtU77fy36e63Bu7/Eyl39T30fjqBvqXRmzcGGOYyQlBFD62MqE8J0co4rMNZFyio5vI2Xlk40ymh7NV3iy0XPNEzB06PvqO96PW/iQ9eeneP25/r/kJj+p4gV5GK1+KozXSl0/dpsLHBXTL2264PSgy5Ra0m166mGmJwtJjwTp39IylzVXnb5Xu0HXt6oVoKzZTn1Qy4S+r87dv+75bnc/ZoRLME7v7G/jF9m/WfqMUDscL3MpY5H+6yA3mEHtVt9K22MR96YjOD3oruuPlKt6aqC3kXLVZslp8dd/qliEc9fWVy+vyTP5Ql9Wj79nMcfl+477cRcfyvu97OdPUi/ceNHgpxfkYTT7tHkcN2VKYS5wutAuDlFdcFpfHhNo25Jx638kqOpVO525P4xF3FCi6q17u334Boa+vq7p01z0F9yPa/pQJtP381mH3+zA3FjEsd3q670lFhl0gwlOD2rHwb5f5GSi1yiuHaaG2/ZkE3XR9Gjec62e5+W15fzv0Tk+Ol/o0He/H5f1IetvTf18pnN2bv2kihfkYTSSuMr0dVnXj93mAvs6qkl5DrtMoZgXsXpLHUvQ6JlZa3WOqwVB17eqFdBcsyZ9UMuEvq/O3bPu+W59PwriOL2hv1X257HArWXZTxoV3aZX6nKDGdRu9a3UJxZxKYDg9KC7rj9STnpqgmWEW9UzO7IPtPjrP1UswmPx1CKnadPTDbzUkzH0iXrD/d6m73s/7uKDvj+nelkv5XhhytcL8jB6+W/6okaXM6UwF7g0PaIA+o96EJr2i2Q8VWHSI8HJ17FQ90LuE7GIG0rQ6pAT9OiDbmDo0G/1Te/H9X3I+vPsI6Gfr+ZC/9U7MCUWGaHr673x3XgJjgekdHrSjM/nfwe+cVx4Z8TVbmT94tQmp4N78Wq9ZNe/Qb8aKq27f//+pdYLHbqghy/622Gmr89X6Ov0PgjXWdP/c3aUdZf8nA6v8V2DrlikPGEt+9RkxxqOeF0mWvGpQWR6anCZn1ma9FH5XWq/tMPlu7K+OD+Oo6xxev2b9enHRwJ7YVA7DMvcaxpe7RtX6MeqerV/Psg7aMrvUp3r5+VxodQpngwLMgvVobkqduV4GiHMEGZzVlW9+i3OYJnGF8H7JD6rzqXJOC2+Jv0grrxWi/AR9bVCucDfwfvb4Tvux118cOk34tr7Rbh/I9lsIIzvDZlSNM6LCDHX7Vn9SjsP4ySRaZVPfLKxph/Es6h/R95fX5vOEoFP5GWbcek3XnA/rskH1ZeJz0Xpf5rj4cZ3zo4+0/+zehkUgYgy/SKByOfzueXZOt9FjmKNsE0Hf4ajvsBX4GiHe3Gv+mqoxynwWgyyju8t8yLWzaeOgciIyyRHxJxergU26MdWa6h78eM4jtr6rgtfpIzgu/DjOP54O6z6/HA/1tDfuvTzgi77+XxYYJ1o4PSW8f00orr8E3//qOkU15ZkI/pM+xE8TuIboWc8Yr+IndNr+3B9gYMPbW8R54s84oN7vxHX3i8i7Pkox/FsfI/F/hJNphS9v+kNvyOgFNBtsUeE4iRRqsxL/5t1Zb5tfrrzHZ/GgvevGLgnG3BwjkfyK7xA0Nk+N70f1+eD6svkwxQIKx5Z1zdifG/ZL6LJ2DrVk5XnSZj2ixzz1g7BGzjqC3wFjna4Fx9UX1vsF6EYtxhUoisWaVhbstqRv+Wia9YOaaTMrSn263p/VtDX59d1HqeDgys52mHiq/VjVX1QP89xzh8Kr/FOj4YJha4Vj9OI6vpQUrI1pFKvfoszWKbxRcD5Ihb+jvVpLx0cvIf3t8N33I+7+ODSb8S194tw/0acL/IkThKZVvkia4ea9IP4C9an++tr31ki8Fmce2IOBA36C+7HNfmg+jLxuSj9P3C+yAMw7RcJA9YUwZ/hqC/wFTja4V7cq74a6nEKrOO11/jeEotYN586BiJea2YH82sI/Zpi/9phW75z9X3531ybB1+Ne7XDQ/0rvJX5av3buH6+rf8fMd7JsE40cHrD+P6hJdegmkeawNFYoFM9t5ZvP+rB5/OJMV6WP+KbGy8HPr/fvnh+p0mzt3FyvLSf7HD5lsWX/RzKlddqEU6vbcmH1hc4+G2bDN976uIN7XDf+3EXH9rqq6wXOl7QcUSZrxfkYfT4/naX++gW6bs0I/3Y7Xm+SHWFSUi/FGjFy7z0/2p8SU81l3TOjjLfNj/d+bHn+rRjff3gfBHw1qf/hnZYbW9l+hXK+CbO1VfqA4X6CkW9VO3c8imYsjST8PT5IoLe6UkzNOt23PkiVr1n7RC8gSuvP+oLHO0QXHOde+pri/0iFI8FImHQ+SLPFIALX6y6Zg2PRsqlHorfo3M6jZTXWRNt09fnB7/nI9NpfZnsgINrONphWcaVda7fDrVxQUjPjQtKfyi8xjs9ngxEQgjhNCLeHQfSrAs/RNb/RtmE0H2+SFVPv7dOuoYLPkScL2Ln3LXtqa8VygX+Dq5ph7fpFylLW3n38uH6Lr3mXH3F72kcpZ245/kiI/QSzueLPB1J+eEkkWmVc2t+D68datIP4i9Ynz6+e0Ga62vfWSLwWZx7Yj6O47Ydxru9C4uU8U2cq6+LpNkRa32Z+Fw4ju/6TD3PF9k0EDHtFwmKtUClPn1N9K9x1Bf4ChztcC9ura9gPI9K4FMwa3z3PF9koz0iR7E7/YJ+TfEw7h0p07flO1fflx/FWjutr1Iv04ODP98OSz3ZmV6Wfr5a/9bfz+vtaPwZMd7JmDnRcBpRXf5xWUMSFpb0a04mBMt+Eaqn9bykC2uHpjXgKo/YL2Ln3J6PtO47rr7AwZXtp6cd7ns/7uJDW32V9VKOF6Z8vSAPo5f/pi9qdP3Y3fub3rDt0kyGk0SjMs+ebI7jiN/DbS79+CLpnB1lvm1+glfrK3zXeoO9voQnG3Bwjkdmpu22HVbbG2bsZtVX4kJ9afofa5//GOZuvcD5Irb9Ita1Q26NsGHtELyBK68/6gsc7RBcc51xvkiDrgHOF8H5Io36+vz2yaYso+OTDTg4197+cjtcrR+r6ly/HWrjgpDetKek1Cm8xjs9ngxEQuh4H02ZsbLw5bc4g2UaX3ws76MJtXdDJD01oNv3ShzMe1IEH2jxZT+HcuW1WoRz1/Ywvo9GWUfg4A3ts6cdvuN+3MUHfX3F7899q+PFz8Lvo6Gf0n/bRnZNphTO54uE4ryN8PtleFmpBgUZDaAVX+WZn5x+QR853uZr9XMcT3U30YdO3h/p7ztLBD6Lc0/MoYCp33jB/bgmH1RfJj4X1XJx4/gP/1pc09yM5/kiwWnzy8PQrNuZ1m6tOvgzHPUFvgJHO9yLe9VXQz1OQX/gJescPM8XsaZvCESs8ZdGlyNiTj+YPR9W3ZrvXH1ffjBr7VYdHLyHe7XDA+eLPKJ79fNt/f+I8U6GdaKB01vG99OI6s+F4/cEfqokyClly7cf9SB0ny+SpffSMx5xvoid02v7cH2Bgw9tbxHnizzig3u/Ebc9X6Qcx7PxPTJniujH7sb9IhQ0Akrx1xZ7RChOEo3KnFsLbNCV+bb56c43XZ92rK9sZXSdMoKvzCP5FV4g6Gyfm96P6/NB9WXyYQqEFY+s6xsxvj99vkiwL/GMhmm/iHUt0KqD+3LUF/gKHO1wLz6ovrbYL0JhHd97JhqGnC8S+LUlqx35Wy66Zg2PRsqz1g5X09fnh9/aPPaOgPdwtMPEV+vHqvqgfp7jnD8UXuOdHg0TCl0rHqcR1fWhpGRrSKVe/RZnsEzji2DZL+K+diikyXjEfhE7H1FfK5QL/B28vx2+437cxQeXfiOuvV+E+zd+d3nK43tDphQ4X+S/OElkWuWLrB1q0g/iL1if7q+vfWeJwGdx7ok5EDToL7gf1+SD6svE56L0//juluPGd86OPlOcL2LbLxIGrCmCP8NRX+ArcLTDvbhXfTXU4xRYx2uv8R3ni9xExJzev3bYlu9cfV/+N9fmwVfjXu3wwPkij+he/Xxb/z9ivJNhnWjg9Ibxvf19NKWoLDCd6rm1fPtRDz6W99H8kPcIHN/3BRz299FQ+8kOl29ZfNnPoVx5rRbh9NqWfGh9gYPftsnwvacu3tAO970fd/Ghrb7KeqHjxc/C76MJfb9yTd+lGenHbs/zRaorTEL6pUArXual//H7MqRsLS3pnB1lvm1+uvNjz/Vpx/r6wfki4K1P/w3tsNreyvQrlPFNnKuv1AcK9RWKeqnaueVTMGVpJuHp80UEvdOTZmjW7bjzRax6z9oheANXXn/UFzjaIbjmOvfU1xb7RSgeC0TCoPNFnikAF75Ydc0aHo2USz0Uv0fndBopr7Mm2qavzw9+z0em0/oy2QEH13C0w7KMK+tcvx1q44KQnhsXlP5QeI13ejwZiIQQwmlEvDsOpFkXfois/42yCaH7fJGqnn5vnXQNF3yIOF/Ezrlr21NfK5QL/B1c0w5v0y9Slrby7uXD9V16zbn6it/TOEo7cc/zRUboJZzPF3k6kvLDSSLTKufW/B5eO9SkH8RfsD59fPeCNNfXvrNE4LM498R8HMdtO4x3excWKeObOFdfF0mzI9b6MvG5cBzf9Zl6ni+yaSBi2i8SFGuBSn36muhf46gv8BU42uFe3FpfwXgelcCnYNb47nm+yEZ7RI5id/oF/ZriYdw7UqZvy3euvi8/irV2Wl+lXqYHB3++HZZ6sjO9LP18tf6tv5/X29H4M2K8kzFzouE0orr847KGJCws6decTAiW/SJUT+t5SRfWDk1rwFUeln8LPwAAIABJREFUsV/Ezrk9H2ndd1x9gYMr209PO9z3ftzFh7b6KuulHC9M+XpBHkYv/01f1Oj6sbv3N71h26WZDCeJRmWePdkcxxG/h9tc+vFF0jk7ynzb/ASv1lf4rvUGe30JTzbg4ByPzEzbbTustjfM2M2qr8SF+tL0P9Y+/zHM3XqB80Vs+0Wsa4fcGmHD2iF4A1def9QXONohuOY643yRBl0DnC+C80Ua9fX57ZNNWUbHJxtwcK69/eV2uFo/VtW5fjvUxgUhvWlPSalTeI13ejwZiITQ8T6aMmNl4ctvcQbLNL74WN5HE2rvhkh6akC375U4mPekCD7Q4st+DuXKa7UI567tYXwfjbKOwMEb2mdPO3zH/biLD/r6it+f+1bHi5+F30dDP6X/to3smkwpnM8XCcV5G+H3y/CyUg0KMhpAK77KMz85/YI+crzN1+rnOJ7qbqIPnbw/0t93lgh8FueemEMBU7/xgvtxTT6ovkx8Lqrl4sbxH/61uKa5Gc/zRYLT5peHoVm3M63dWnXwZzjqC3wFjna4F/eqr4Z6nIL+wEvWOXieL2JN3xCIWOMvjS5HxJx+MHs+rLo137n6vvxg1tqtOjh4D/dqhwfOF3lE9+rn2/r/EeOdDOtEA6e3jO+nEdWfC8fvCfxUSZBTypZvP+pB6D5fJEvvpWc84nwRO6fX9uH6Agcf2t4izhd5xAf3fiNue75IOY5n43tkzhTRj92N+0UoaASU4q8t9ohQnCQalTm3FtigK/Nt89Odb7o+7Vhf2croOmUEX5lH8iu8QNDZPje9H9fng+rL5MMUCCseWdc3Ynx/+nyRYF/iGQ3TfhHrWqBVB/flqC/wFTja4V58UH1tsV+Ewjq+90w0dM2LNKwtCXas4YjXZdKs4dFIuXwy9tL1/qygL86P45j7ZLMCjzGmZvYy3nxNpvA/3g7P32/GrqZZSh/Uz5djiuwPxZNhwa2FETm2z4v0F7XTjssWm6SXkWmmpwh3kM7la/XzMX19vsKTzQr8rVjh2s5qhyuUq42v1o+V+qx+nuolvHQlGsblzhwbYxE5YrqCwYQr5aXr7TwMzZNNqR+P/DrD5Ce4wPvra7sn8vDtI970d9y1GjQ7lenP9BvgbXyF+pqLclzOxvFyfOfsGHI9jZB322bJsq22ZRru64JlR4Rvs6OKnvfvslbuhFfuvh7NV9gJr+fltXXZFb9IXSg5vQFf8zfrUla4zqb716UdCvqaXNnXreDD9PrKUnpBHkbTp2Wy8qaLv8F96zZTipZYhNM5X6tf51yXMxVyb9Bp67TasVZAVVeWS3+thur6VrUCmmu2TV8TWU/xmr/b1UKVc2mU+r4XQRbH6elfOX1ZX2V6L53zk0ZFt+mVutxghDRlY4sE1axvL3UJn1ikWoWZr1xK2fLtRz3YJVKmxV//qWIRTq/tw/W1Dqf34Gv+phKtc52V3Lcd7ns/7uKDe7+hbLdx0rwIl6D8KBKUxjkuo/3deKWiXxyqrjAJK0+DtpV8yPulZFAHMq7Mq7pXpqrLuU/EIm4oQZsldVtZZdX6+iG/qt8CqY0l5zXfoum5v3ofRtgJ3RvlngTXctqaItewF8cK3ip9EO70hirjxg7ZgenvxqO60j7X3yrr3fN8kR+C7N9Mr9rp9KQZpp3wB/+rin///qUy3v7y4njLrvjFuXCd/0J9Jee5gb96S94GIuUtzN3aI+xkH61wnQe1w3Qddm+H2/Hm+vphfk2T0pj8mY7rpuPG8VLsiTi7YhEhknLRb3N30aPxfJFSDyEo9ct+aYfLd2V9fX7wu9l/mF/HVNMLdhbnqVDpFhPCjjK98DfLggsvRtjJvrLCdb7lf7wdrtBfmXSu3w61cUFIz40LSn8ovMY7PZ4Zx/8H5VpOQnV9qJrAqgsLS/o1JxOCZb9IdS2wqqeFtKRruOADLb4m/SD+jvXpnvpaoVwmTtd0Yw1nsQ+j1Lm/s+wkZZ3r3MCjoh3epl+kLG3l3cuHWOzR4eorNdTq/djgpxeiOIxmn3KJvfQSzueLPB1J+eG8i+jlJ5vji/jdgEL1lL7tycbkJ7jAU10011fccJaoOvOR9EAeoaiumc+Q7QT1vIjJzpRr2MPLNpOemOV2eOnhLTMiu3CuvhJ/oL7mwnF812faEou8LBAx7RcJirVApT59TfSv8T9YX6kg2cCfKVQPigCiDFlKO8qwpsFOVroVrjPa4Yu5tb6C356zKZg1vrfEIhMDES7O6tE1T73Ck02ZpqqX6dvynavvy8snFVpfpd7/ZLMCTwWkt1sWCiToA4gyZCntKMOaBjtZ6Va4zuPaYaknO9PL0s9X69/6+3m9HY0/I8Y7GbMCkRBCOI2oLv+4rCEJC0v6NScTQvf5IkkX1g5Na8BVTouvST+I77s+XfKh9bUOT8UpOVXkNJq/pZ22vxo76dN1rrOS69sbp1M7cdv7cRcf2uqrrJdYjBemfL0QyThS/ZRL0KPLmVL0/qY3bLs0k+FUR/TZk80hrh2mklbtKPNt8xO8Wl8hhOb6Ep5sVublYkdg9ohk6W/nMwQ7pnkRk53p19PKIzPTdtsOq+2ttAPuy7n6SlyoL03/Y+3zH8O0GZEQgu/5Ip16pyfNMO0XOZzWejkd3Jcrr/9b6ys5X4YgF7KwIEsv/M2yqNoJuv0iVjvZV1a4zmiHL+PCde6pry32i1A8FogEnC8ScL5Iq74+v32yKcvo+GSzAk+FSrdYdqNVw4LbAKK8lbjwYoSd7CsrXOdb/sfb4Qr9lUnn+u1QGxeE9Ny4oPSHwmu80+PJQCSEEE4j0vKP+9qSsLCkX3MyIeB8EQt/x/p0T32tUC4TT0WjnOLE+SLLtM9UNH36RcrSVt69fIg4X8RVL/Gf0IRqBJQCMTlSo1/sjaT8cN5F9JmfNE2MMRU5/o58k36SSNmUr9XPcTwry448Pdk011dknmZW5vI8RChu2LZ5kdJOaJoX0djpvyZP8rLNpILctsNIZmQDwTvuxzU5V18Xqc6OaOrLxOci8z+7H/UzLra5mZtYpUB6KKl+lCWjDzHVNNzXBcuOCN+mQxU91z/BcLryyWaRp8AVnmz0vLy2/fV1LlMXSl6dV9j9b9alrHCdTfevSzsU9DW5sq9bwYfp9RWnzouUycqbLv4G963bTClaYhFO53ytfp1zXc5UyL1Bp63TasdaAVVdWS79tRqq61vVCmiu2TZ9TWQ9xWv+blcLVc6lUer7XgRZHKenf+X0ZX2V6b10zk8aFd2mV+pygxHSlI0tElSzvr3UJXxikWoVZr5yKWXLtx/1YJdImRZ//aeKRTi9tg/X1zqc3oOv+ZtKtM51VnLfdrjv/biLD+79hrLdxknzIlyC8qNIUBrnuAyHWIR6Q/2r6nKB9Zm6oJwX0Thg9V9fwZrcJ2IRN5So3iTVBCZ9u4tA3X7N3+1qIf3lPm3Qd7wIW/gwqL5MDkxcoyl1et9lXQrVq3b09d4bi2QXOnNX1jM7gtOD2nGw7xfh0rfpqVy3T7ca30Zz67Way9MNM+XJZhFe9h0v+Jv1FStc59v7170dCmnW5Mq+bgUfBtWXyc9FYpHqrZfdgFQpjciZUnTFIlk2VUdPvgyZHcFp4Vs9evj+Lus2fdknlikbdGW55OvzmK5vVStAWbNWfdOL8LK/29XCCH3TizCxH6t+VIq0sfnqmp7k8rOMRfqvg9xghPT0visvI6drMqVoj0Wqrt/6eltgOVNfTI+UuTQZp8Vf/6liET6ivlYol4nTm+41f1OJ1rnODby/Hb7jftzFB5d+Q9lu4wLzIvTf7NYrU5aiMlOKxlikmgF1KPOb6pyjgtP68pgQmvaLOOqduT+MRdxQgmui+sRVfbuLoBzg9/q7XS3cKg367hdhWR8G1ZfJgbmxSDlO0RswKVTnmqi+3ltiEc2Fjr/BpeG+Llh2RMD5Irs92eh5eW376+tcpi6UPOsv3vE361JWuM6m+9elHQr6mlzZ163gw/T6ilNjkTJZedPF3+C+dZspReO8SFXnfK1+nXNdzlTIvUEv50X0dqwVUNWV5dJfq6G6vlWtgOaabdPXRNZTvObvdrVQ5Vwapb7vRZDFcXr6V05f1leZ3kvn/KRR0W16pS43GCFN2dgiQTXr20tdwicWqVZh5iuXUrZ8+1EPdomUafHXf6pYhNNr+3B9rcPpPfiav6lE61xnJfdth/vej7v44N5vKNttnDQvwiUoP4oEpXGOy/ic5xks4F6hGSyHz1vf8jfotTWfzyfGqLFMHci4Mi/u9T3W3CdiETeUoM1SeLcCh2p9ca+KXRapjXHvf6mi4X00zdba7ATdjbMIuJbT1hS5hr04VvBW6YNwpzdUGTd2yA78+/fPOjRrzAq5c59ax7iyv1XW+/8ps+FAc/ohyP7N9KqdTk+a8fl8bvm/f/8ucrWSUr94KiOXJtnM7Gh8AG/gwnX+C/WVnOcG/uoteRuIlLcwd2uPsJN9tMJ1HtQO03XYvR1ux5vr69I5O9a6m47rpuPG8VLsiTi7YhEhknLRb3N30SPz5lWqR/L2xVIPISj1y35ph8t3ZX19fl3nappMp/VlsrM4T4VKt5gQdpTphb9ZFlx4McJO9pUVrvMt/+PtcIX+yqRz/XaojQtCem5cUPpD4TXe6fHMOP4/KNdyEqrrQ9UEVl1YWNKvOZkQus8XqeppIS3pGi74QIuvST+Iv2N9uqe+ViiXidM13VjDWezDKHXu7yw7SVnnOjfwqGiHt+kXKUtbeffyIRZ7dLj6Sg21ej82+OmFKA6j2adcYi+9ROO8yNwZkRE47yJ6+cnm+CJ+N6BQPaVve7Ix+Qku8FQXzfUVN5wlqs58JD2QRyiqa+YzZDtBPS9isjPlGvbwss2kJ2a5HV56eMuMyC6cq6/EH6ivuXAc3/WZtsQiLwtETPtFgmItUKlPXxP9a/wP1lcqSDbwZwrVgyKAKEOW0o4yrGmwk5VuheuMdvhibq2v4LfnbApmje8tscjEQISLs3p0zVOv8GRTpqnqZfq2fOfq+/LySYXWV6n3P9mswFMB6e2WhQIJ+gCiDFlKO8qwpsFOVroVrvO4dljqyc70svTz1fq3/n5eb0fjz4jxTsasQCSEEE4jqss/LmtIwsKSfs3JhNB9vkjShbVD0xpwldPia9IP4vuuT5d8aH2tw1NxSk4VOY3mb2mn7a/GTvp0neus5Pr2xunUTtz2ftzFh7b6KuslFuOFKV8vRDKOVD/lEvTocqYUvb/pDdsuzWQ41RF99mRziGuHqaRVO8p82/wEr9ZXCKG5voQnm5V5udgRmD0iWfrb+QzBjmlexGRn+vW08sjMtN22w2p7K+2A+3KuvhIX6kvT/1j7/McwbUYkhOB7vkin3ulJM0z7RQ6ntV5OB/flyuv/1vpKzpchyIUsLMjSC3+zLKp2gm6/iNVO9pUVrjPa4cu4cJ176muL/SIUjwUiAeeLBJwv0qqvz2+fbMoyOj7ZrMBTodItlt1o1bDgNoAobyUuvBhhJ/vKCtf5lv/xdrhCf2XSuX471MYFIT03Lij9ofAa7/R4MhAJIYTTiLT84762JCws6decTAg4X8TC37E+3VNfK5TLxFPRKKc4cb7IMu0zFU2ffpGytJV3Lx8izhdx1Uv8JzShGgGlQEyO1OgXeyMpP5x3EX3mJ00TY0xFjr8j36SfJFI25Wv1cxzPyrIjT082zfUVmaeZlbk8DxGKG7ZtXqS0E5rmRTR2+q/Jk7xsM6kgt+0wkhnZQPCO+3FNztXXRaqzI5r6MvG5yPzP7kf9jIttbuYmVimQHkqqH2XJ6ENMNQ33dcGyI8K36VBFz/VPMJyufLJZ5ClwhScbPS+vbX99ncvUhZJX5xV2/5t1KStcZ9P969IOBX1NruzrVvBhen3FqfMiZbLypou/wX3rNlOKlliE0zlfq1/nXJczFXJv0GnrtNqxVkBVV5ZLf62G6vpWtQKaa7ZNXxNZT/Gav9vVQpVzaZT6vhdBFsfp6V85fVlfZXovnfOTRkW36ZW63GCENGVjiwTVrG8vdQmfWKRahZmvXErZ8u1HPdglUqbFX/+pYhFOr+3D9bUOp/fga/6mEq1znZXctx3uez/u4oN7v6Fst3HSvAiXoPwoEpTGOS7DIRah3lD/qrpcYH2mLijnRTQOWP3XV7Am94lYxA0lqjdJNYFJ3+4iULdf83e7Wkh/uU8b9B0vwhY+DKovkwMT12hKnd53WZdC9aodfb33xiLZhc7clfXMjuD0oHYc7PtFuPRteirX7dOtxrfR3Hqt5vJ0w0x5slmEl33HC/5mfcUK1/n2/nVvh0KaNbmyr1vBh0H1ZfJzkVikeutlNyBVSiNyphRdsUiWTdXRky9DZkdwWvhWjx6+v8u6TV/2iWXKBl1ZLvn6PKbrW9UKUNasVd/0Irzs73a1MELf9CJM7MeqH5UibWy+uqYnufwsY5H+6yA3GCE9ve/Ky8jpmkwp2mORquu3vt4WWM7UF9MjZS5Nxmnx13+qWISPqK8VymXi9KZ7zd9UonWucwPvb4fvuB938cGl31C227jAvAj9N7v1ypSlqMyUojEWqWZAHcr8pjrnqOC0vjwmhKb9Io56Z+4PYxE3lOCaqD5xVd/uIigH+L3+blcLt0qDvvtFWNaHQfVlcmBuLFKOU/QGTArVuSaqr/eWWERzoeNvcGm4rwuWHRFwvshuTzZ6Xl7b/vo6l6kLJc/6i3f8zbqUFa6z6f51aYeCviZX9nUr+DC9vuLUWKRMVt508Te4b91mStE4L1LVOV+rX+dclzMVcm/Qy3kRvR1rBVR1Zbn012qorm9VK6C5Ztv0NZH1FK/5u10tVDmXRqnvexFkcZye/pXTl/VVpvfSOT9pVHSbXqnLDUZIUza2SFDN+vZSl/CJRapVmPnKpZQt337Ug10iZVr89Z8qFuH02j5cX+tweg++5m8q0TrXWcl92+G+9+MuPrj3G8p2GyfNi3AJyo8iQWmc4zIcYhHqDfWvqssF1mfqgnJeROOA1X99BWtyn4hF3FCiepNUE5j07S4Cdfs1f7erhfSX+7RB3/EibOHDoPoyOTBxjabU6X2XdSlUr9rR13vju/EShNcHB+bVOEL6Kfh8Pud5yvzfv38XOY4j8StN/L4k6d+/f6kU//79y/Sr1MnmZSel0fgAbuLx+5Iqx/qidlYo4y2/QF8pp/yrfD3eFDvhN1a4zre82n6ussjtMITw8/Ozezuk990WPnDX+dLl+rp41Y6y7pLN6TiKlzgmPdRGbS4e0OD/2r5WzfjnC8opAh+INBSAC1+sOq142olTPQ1sPz8/pR5CuPRUzEzP7Jd2uHxX1tfn13Wuprn0an2Z7CzOU6HSLVbeaKWuDCBu7QT7e3o1drL0K1znW97WDlNhd2+HK/RXJp3rt6/0XD+fdK6f5zjnD4XXeKcH7TTKcbxETyASgn0i6HaGcMSU46D5vdB9vkhVT3NWSddwwQdafE36QVx5rRbh3LXtqa8VymXi2ZxqibPYh1Hq3N9ZdpKyznVu4FHRDm/TL1KWtvLu5UMs9uhw9ZUaavV+bPDTC1EcRrNPucReeonGeREuAvLSn8d5F9HLTzbHFzHGFDkmPaVve7Ix+Qku8FQXzfUVN5wlKh9ZUpGzuVaqa+YzZDtBPS9isjPlGvbwss2kJ2a5HV56eMuMyC6cq6/EH6ivuXAc3/WZtsQiLwtEPp/PLc/W+S5yMGuBSl2TL7gj/4P1lQqSDfyZQvWgCCDKkKW0owxrGuxkpVvhOqMdvphb6yvoxgv9/fswZo3vLbHIxECEi7N6dM1Tr/BkU6ap6mX6tnzn6vvy8kmF1lep9z/ZrMBTAentloUCCfoAogxZSjvKsKbBTla6Fa7zuHZY6snO9LL089X6t/5+Xm9H48+I8U7GrEAkhBBOI6rLPy5rSMLCkn7NyYTQfb5I0oW1Q9MacJXT4mvSD+L7rk+XfGh9rcNTcUpOFTmN5m9pp+2vxk76dJ3rrOT69sbp1E7c9n7cxYe2+irrJRbjhSlfL0QyjlQ/5RL06HKmFF2/o7nwzIzIaJzqiD57sjnEtcNU0qodZb5tfoJX6yt8d8IHe30JTzYr83KxIzB7RLL0t/MZgh3TvIjJzvTraeWRmWm7bYfV9lbaAfflXH0lLtSXpv+x9vmPYdqMSAih8ze9DQ4JeqcnzTDtFzmc1no5HdyXK6//W+srOV+GIBeysCBLL/zNsqjaCbr9IlY72VdWuM5ohy/jwnXuqa8t9otQPBaIBN/zRdz129xddO5JNxbrf4d97VB4stHku7K+Pr99sinL6PhkswJPhUq3WHajVcOC2wCivJW48GKEnewrK1znW/7H2+EK/ZVJ5/rtUBsXhPTcuKD0h8JrvNPjyUAkhBBOI9Lyj/vakrCwpF9zMiHgfBELf8f6dE99rVAuE09Fo5zixPkiy7TPVDR9+kXK0lbevXyIOF/EVS+B80X+i/MuopefbI4vIs4XWZinumiur7jhLFF15iMUezIyXTOfIdsJ6nkRk50p17CHl20mPTHL7fDA+SIzOFdfiT9QX3PhOL7rM215H42cMZc91780OOCLj+V9NFQ/mHcTyDq1kxq9xgdwEy+v7fF9B9DxfQ+Itb5WKJeJX8gG/sDfqklXhiOyndC6DVa2k6VZ4Tqb+FHsIXh9O1ykr2vzwVpfQRwvSl3wcwrKcbnsOpTfqt6wLE4jhKkY+lE2v1p+vbQjTOYI3+rRQ/GeXr0dOm/crCvLpb9WQ3X9bNsKmD7luALSDfiyv9vVQpVzaZT6vhdBFsfp6V85fVlfZXovnfMzkDWd2/RKXW4wQpqysUWCata3l7qETyxSrcLMVy6lbPn2ox4Ey34Rqkf1mm6bnnFafE36QVx5rRbh9No+XF/rcHoPvuZvKtE611nJfdvhvvfjLj649xvKdpvZ8QIdR6qfcgnKjyJBaZzjMhxiEeoN9a+qywXWZ+qCcl5E44DVf30Fa3KfiEXcUKJ6k1QTmPTtLgJ1+zV/t6uF9Jf7tEHf8SJs4cOg+jI5MCUW4XR632VdCtWrdvT1/vT5IoE/UKXTk2Zofufd/Lt/qw7uy/94fSXnX/aXYoXrjHb4Mj6ovnC+iIAh54sEJuBosCN/y0WPHeeLnN9NSS663p8V9PX5wexm99LX538BK1znW/7H2+EK/ZVJH9TPc5zzh8JrvNPDOr73BCIh2CeChBnCbA6nqle/xRks0/gidJ8vcvatKXJpMk6Lr0k/iCuv1SJ8RH2tUC7wd/D+dviO+3EXH1z6jbj2fhHu31hbo6GfVkd2TaYULb/pDYqIiQZl9GCALFjrjaT8cJLItMozP08S+fbrMremH8RT3U30oZP319e+s0Tgszj3xBwIGvQX3I9r8kH1ZeJzUfp//D7gpxzfOTv6TFvWaLymbhYJREz7RcKANUXwZzjqC3wFjna4F/eqr4Z6nALreO01vrfEItbNp46BiNeaGdXliJjT+9cO2/Kdq+/L/+baPPhq3KsdHuq3fK/MV+vfxvXzbf3/iPFOhnWigdNbxvfTiOryT/z9I59TXFuSjegz7UfA+SIWvu/6NPaOgK/AfdvhvvfjLj649xtx7f0iwp4Pbo9IrG335LiMxv0iFDQCSvHXFntEKE4Sjcrca+1Q/2TT5qc7P/Zcn3asr2xldJ0ygq/MI/kVXiDobJ+b3o/r80H1ZfJhCoQVj6zrGzG+98YiwlpRYKaGrEs8o/GxvI+mXPNL02vCuwnSVfr8fjdBSqPxAdzEU4fiWF/UzgplBN+FV9vP8X0vktAOQwg/Pz8vaIcr9HV6H7jrfIjvoKF61c4W76OhSA9gZcARaqN2z0RDVyySZUxnRxo2uVjDkbZcSl2zhkcjZepnSpPFiZme2ZefsK1rirP0xfl1/5RPJKl/T2JWX6F44mx7sgEHT5xrP3I7DL9nT7duh+meWq0fq+pcv32l5/r5pHP9fDmmyP5QeI13eiQLmZ1ROZ5GVNeHqgmsurCwpF9zMiF0ny9S1dNCWtI1XPAhYr+InevXdPX1tUK5wN/BNe3wNv0iZWkr714+xGKPDldf8bsnsrQT194voknspZdwPl/k+djNCyeJTKtcfrKhUX91Le0kkbIpX6uf4/ix//p0espsrq9NZ4nAJ/KyzZRT31w7jPzehRfcj2tyrr4uQmdHTPVl4nPhOL7rM/U8X2TTQETzO2/TuwaUuiZfcEeO+gJfgaMd7sWt9RWM51EJfApmje+e54s8EIhwcVaPLkfEnH7w7xqo6mX6tnzn6vvyozingdZXqZfpwcGfb4elnuxML0s/X61/6+/n9XY0/owY72TMnGg4jagu/7isIQkLS/o1JxNC9/kiSRfWDk1rwFUesV/Ezrk9H2ndd1x9gYMr209PO9z3ftzFh7b6KuulHC9M+XpBHkYv/01f1Oj6sbvrPb0XNl2ayXCSaFTm2ZPNcRzxu7P60o8vks7ZUebb5id4tb4C2QlvrS/hyQYcnOORmWm7bYfV9oYZu1n1lbhQX5r+x9rnP4a5Wy96YxHHKZ1OT5ph2i9iXTvk1ggb1g7BG7jy+qO+wNEOwTXXuae+ttgvQvHkRENXLDJzbclvzYx70o3F+l/5ZJy4Utc8Ye+ir89vn2zKMjo+2YCDc+3tL7fD1fqxqs7126E2LgjpTXtKSp3Ca7zT48lAJIQQTiPS8o/72pKwsKRfczIh4HwRC3/H+nRPfa1QLvB3cE07vE2/SFnayruXDxHni7jqJXC+yH9xksi0yjM/M/1oPa/iNl+rn+P4sf95BgfOFwF/nHNPzNdug5Sm2g4jzhd5nHP1FXC+CM4XGQrTfpGgWAtU6tPXRP8aR32Br8DRDvfi1voKOF9E1Dm0zIsIEZBm7SoFkm17RNwvkxwRc3r1yYamr0bK9Dqcu72jYS/OzXDQJ5uUnquvQLBIucBYafC0AAAgAElEQVS35vJMW9kOAzMjm2b4FinXLa/O4jzcjzX0t2W/fVtfSjsaP58PC6opqT/ct0LxciXz+H4aUV3+SStkVEmQU8qWbz/qQeg+XyRL76VnPGK/iJ1r9nwMqi9w8KHtrdy7sE4ZOb7CvWP1wb3fWHy/iLDnoxzHs/E9G/2VmVJ0vaf3Ao2AUtxUXUsr06+Dk0SpMueemBt0Zb5tfrrz6pPN+tyxvoQnG3Bwjsszbc36pvfj+nxQfZl8mAJhxSPr+kaM70+fLxLEAk+Bab/IYfzdv1UH9+WoL/AVONrhXnxQfW2xX4Ri3GJQiSHniwQm4GiwI3/LRdesHdJImVsL7Nf1/qygr88P5jwGLx0cXMnRDhNfrR+r6oP6eY5z/lB4jXd6NEwodK14nEZU14eSkq0hlXr1W5zBMo0vQvf5ImffmqJy/TJiv4idj6ivFcoF/g7e3w7fcT/u4oNLvxHX3i/C/Ru/uzzl8b0hUwrn80VCcd5G2GTvyEki0ypfZO1Qk34Qf8H6dH997TtLBD6Lc0/MgaBBf8H9uCYfVF8mPhel/8d3txw3vnN29Jl6ni8SnF6u8zBM+0XCgDVF8Gc46gt8BY52uBf3qq+GepwC63jtNb63xCLWzaeOgYjXmtnB/BpCv6bYv3bYlu9cfV/+N9fmwVfjXu3w2O18kSpfrX8b18+39f8jxjsZ1okGTm8Z308jqss/aT2JKtzakmxEn2k/As4XsfB916exdwR8Be7bDve9H3fxwb3fiGvvFxH2fHB7RGJtuyfHZeB8kf/iJNGozL3WDvVPNm1+uvNjz/Vpx/r6wfki4HYecb7IVnxQfZl8mAJhxeMH54s8ANN+EetaoFUH9+WoL/AVONrhXnxQfW2xX4TCOr73TDR0zYvIGVvXqKzhiNdl0qzh0UiZ+hl/v49A4FfWmifsddZKZX1xfhxH9Ymkub4yO+Dgei7MjN72IWm/yNbtkJarmmYpvdo/K+uLpi/HC5M/FE+GBaWFcnSuKl05nkZU14eqCaz64vtFqmuBVT0tpCVdwwUfIvaL2Ll+TVdfXyuUC/wdXNMOb9MvUpa28u7lQyz26HD1Fb97Iks7ce39IprEXnoJ5/NFno/dvHCSyLTKuSeSbM0sxlhdSztJpGzK1+rnOH7svz59fPfoNNfXprNE4BN52WbSE/NtO4z83oUX3I9rcq6+LpJmR6z1ZeJz4Ti+6zP1PF9k00DEtF8kKNYClfr0NdG/xlFf4CtwtMO9uLW+gvE8KoFPwazx3fN8kQcCES7O6tHliJjTD/5dA1W9TN+W71x9X34U5zTQ+ir1Mj04+PPtsNSTnell6eer9W/9/bzejsafEeOdjJkTDacR1eUflzUkYWFJv+ZkQug+XyTpwtqhaQ24yiP2i9g5t+cjrfuOqy9wcGX76WmH+96Pu/jQVl9lvZTjhSlfL8jD6OW/6YsaXT929/6mN2y7NJPhJNGozLMnm+M4YoxXiS79+CLpnB1lvm1+glfrK3zXeoO9voQnG3Bwjkdmpu22HVbbG2bsZtVX4kJ9afofa5//GOZuvXj6fBFB7/SkGab9Ita1Q26NsGHtELyBK68/6gsc7RBcc5176muL/SIUT040dMUiM9eW/NbMuCfdWKz/lU/GiSt1zRP2Lvr6/PbJpiyj45MNODjX3v5yO1ytH6vqXL8dauOCkN60p6TUKbzGOz2eDERCCOE0Ii3/uK8tCQtL+jUnEwLOF7Hwd6xP99TXCuUCfwfXtMPb9IuUpa28e/kQcb6Iq14C54v8FyeJTKs88zPTj9bzKm7ztfo5jh/7n2dw4HwR8Mc598R87TZIaartMOJ8kcc5V18B54vgfJGhMO0XCYq1QKU+fU30r3HUF/gKHO1wL26tr4DzRUSdQ8u8iBABadauUiDZtkfE/TLJETGnV59saPpqpEyvw7nbOxr24twMB32ySem5+goEi5QLfGsuz7SV7TCI77JZp1y3vDqL83A/1tDflv32bX0p7Wj8fD4sqKak/nDfCr8basv4fhpRXf5JK2RUSZBTypZvP+pB6D5fJEvvpWc8Yr+InWv2fAyqL3Dwoe2t3LuwThk5vsK9Y/XBvd9YfL+IsOejHMez8T0b/ZWZUnS9p/cCjYBS3FRdSyvTr4OTRKky556YG3Rlvm1+uvPqk8363LG+hCcbcHCOyzNtzfqm9+P6fFB9mXyYAmHFI+v6RozvT58vEsQCT4Fpv8hh/N2/VQf35agv8BU42uFefFB9bbFfhGLcYlCJIeeLBCbgaLAjf8tF16wd0kiZWwvs1/X+rKCvzw/mPAYvHRxcydEOE1+tH6vqg/p5jnP+UHiNd3o0TCh0rXicRlTXh5KSrSGVevVbnMEyjS9C9/kiZ9+aonL9MmK/iJ2PqK8VygX+Dt7fDt9xP+7ig0u/EdfeL8L9G7+7POXxvSFTCufzRUJx3kbYZO/ISSLTKl9k7VCTfhB/wfp0f33tO0sEPotzT8yBoEF/wf24Jh9UXyY+F6X/x3e3HDe+c3b0mXqeLxKcXq7zMEz7RcKANUXwZzjqC3wFjna4F/eqr4Z6nALreO01vrfEItbNp46BiNea2cH8GkK/pti/dtiW71x9X/431+bBV+Ne7fDY7XyRKl+tfxvXz7f1/yPGOxnWiQZObxjfHX7TmzJ2KbAMl8tU1T+fz3mel35xqmc8RbhZeqt+m6/Vz6F6umFur886PPn879+/1D7//fvXo2d1AQ4u86wtebXDHe/HJ/urZr381WRnP1/OiNz6c2HceFeF10pFmx2cL/JfcJF7yUv/m3Vlvm1+uvNjz/Vp3ylHbkYNHJzj8fe7SzI065vej+vziPNFCA6cL/IYNOt2OF9kU476Al+Box3uxQfV1xb7RSi8AmgNuuZF5Iz14UX5xNmTu1XXrOHRSJn6GX+/j0DgV9Y0UuaesNdZK5X1xflxHHOfbMDBE0c7pP1hNc1SerV/Pr7vsbrt87l+vhxTZH8ongwLSgvl6FxVunI8jYh3x4E068IPkfW/UTYhdJ8vUtXT762TruGCDxHni9g5d229dHDwHt7fDt9xP+7iQyzeAVT28yepF268aPDTC/IwGvnzRUboJfLNMrdIsZ7v2qeQRv6oB5/P51rKvU156/9xt5aW/qV2lOUaVHwrFnFDiaq3/e3WOnsHACPaoZB4TazgbXN/q+/n6ac9Dvz79886NGvMyusYt2Nxgx70h7ArYxYa5gyKmGbNiwSPKDtFzdUZES5S1s/KWH0bwVd4stHz8tqOmCnRzHJBh/6kviZX9nUr+JD1t6Z+PtM5O7d+UsUL8jAa7xYo2nT92G0usK+jmpTnsMtEW6fVTnahI4FGz8xaq3NcLQi6vlWtgOaaNemDWib0fXXunnXPd+v7URDH6Q39rbI/jwVuLct+0qjoNr1SlxvMoHarb6U+sYhLAQSnB911/ZFy0lMTLCPcqp7ZkX2gxV//qWIRHounFjlNm55u4KWejKFP1Bvu9zZ93/txFx/0/TnVy3opxwtTvl6Qh9HLf9MXNbqcKYW5wKXpEQXQf9SDUMyLaBzIeKrCpEeCk69joe6F3CdiETeUoNUhJ+jRB93A0KHf6pvej+v7kPXn2UdCP1/Nhf6rd2BKLDJC19d7byziWADB6UHtONj3i5TpU3Msn1qSnvxve7KJumh6NLdeq7k8dRDrPDFDh+6o73g/buFD1p+f4vXn+v+Sm/ykihfkYbT6qTBeK3X92G0ucFREeW264PSgy5Ra0m166mGmJwtJjwTp39IylzVXnb5Xu0HXt6oVoKzZTn1Qy4S+r87dv+75bnc/ZoRLME7v7G/jF9m/WfqMUDscL3MpY5H+6yA3mEHtVt9K22MR96YjOD3oruuPlKt6aqC3kXLVZslp8dd/qliEc9fWVy+vyTP5Ql9Wj79nMcfl+477cRcfyvu97OdPUi/ceNHgpxfkYTT7tHkcN2VKYS5wutAuDlFdcFpfHhNC036Rqh4JqnrVTmfuD2MRN5Soeuvebh++gaGvr2v6NBf9Bffjmj6UyfT9fNbhNzswNxZxbLf6em85A37EQWcTUb41seTVtywexbsGrjak1D97vvl2F15e2+v6p1OJ5LehXgcZaepd0AX7iXvZSXfTA3bO75Het9fz5+fnGTvBUr9D7QjvrsrSp7K3tZO9+Ap9XZsP1n4+qO/rWz+nwHd81x8O2fJuvImBCFewHj01gmB5Z8HlP9UTr+pl+rZ85+r78uv6X/xqeLS+zvP8+fmhOk3P2ZF12X4o2olsX7aj9/MxO+nufsbO8X3rtWDnp3gn1Ag71vajaSeCn+X13Iiv1r/19/N6Oxp/Rox3MnwDEWWmF3rf00szPmq4Pi2VhkAk8KfJ9uvX2xF/vk+EmZ5xGuEex0HTpCebUhfsy7rez9H6prx8IkncpHN2RttfzY7SfvPbrQfZca9Hq52DmUHh7Fvz3Y7P6sdkvWxvZXpTP39bX6X9C+PGuyqEwCIU43g5vt/akdH1nl4h4x/+rP7mQGQorE/Yl0ILIlRkplufbNr8dOepHld4omqrrwtpCSZrn0lX2jnFtwEH8hIiOV/BfiDtZB076cFDtkNnCEbbCd8+cbqdoH4r7207/GHeFlutL3Df2ZrbdpJBn97a5z8GIRDJmuKI8b13XkRfMQlCgadAE8U3P5lZdXBfrrz+o5+8OfvWfGGn005wqi+lnSfbIbgjH9TPW+tuOqzje3MgEjpjEWvA0WBH/paLrlnDk/d8eOl6f1bQ1+fH3R6FsozV9JydQ5xB4daYuScwTb572Sn16XaCrp302GnYA9Rc3h35av1YVR/Uz8t7Skqdwmu808M6vvcEIqEnFunMuN+ONQyS9ds1vBThDtK5fK1+Pqavz6fsmRCeXN+0B8Vrr8OIPRNL2ems39uZku34av1Yqc/q56lewktXomFc7syxcb/IbcR0DF5bcsdtRJ/5Ka8FWnWZW9MP4sf+69OH656J2/THcWj2BAj2E7z2uDxm50fc6+BuJ9WpfJ019etl51Y/juPWvrB34QX345qcm+EIBCP6ea7Pfx6l/6nFcuM7Z0efacu8iBBAVHUu/SKBSPMT9oE9IlvxQ7c277U3aJb9P2snGGcUBtl5bK8M+DPcq59vqMcpsI7XXuO75/ki1vQNgYg1/tLobWuKB/aIbMWPYXsm2uyH1vNFbu3/TTtHMaMzy85je27C7Huqn6/Wv43r59v6/xHjnQxhXHaZgBDgeb7IuPQJLpepqstreBlPEW6W3qrf5mv1c7S+KVc+AbvPhHnZX83O4jMTj9Vj55PxiL0ye/FZ/Zisl+2ts5+/ra/SnwvjxrsqmsdlFzvO54uk+Otnhz0iFNYn7PK7Dboy3zY/3fmx5/p0ef1xvkinnR+cL8LbCThfZHNuPV+kTZf5FFTH5QPnizwGTRTvtRb+viebxbl8/dOoM+jJm7PfkO9qdrKy72In6GYavOx0tsPUK6LfeJgP6ue32C9CYR3fhXH/HqcRkX+bXyTg9Mi/cLL6UTUjQTTpIQTOpbNWUs7PZl1ZLvn6PKYLFbQglDXbqQ9qmdD31bn71z3f7e7HjHAJxumd/W2/zvHSz3Jo7r8OcoMR0qeCJJQO6y8vh/ZYpOq6BnqDZRpfXLFI4lTPeNk+Mj2VTuCpLFUu+ECLr0k/iCuv1SKcu7a+enlNnskX+rL61SQeyPcd9+MuPuj7+fgduUs7WdtQ+umFaIlF4u+wSYOGTCnMBU4X2pSxRhec1pfHBHo/y7j1P6uSUq/a6cz9YSzihhJVb93brbJCof8dXdOnuegvuB/X9KFMpu/nsw6/2YG5sYhju9XXe0ssMugGE5we1I7Dd5sSVfScfjeKsyCp4bY92URdND2a91yr53l5bTn/e3SOj84XOvTd78dlfcj6W1M/n+mcnVs/qeIFeRiNJK4yfV3W9WO3ucC+jmpSnsMuUyjmRazeUscSNHpm1lqd42pB0PWtagU016xJH9Qyoe+rc/ese75b34+COE5v6G+V/XkscGtZ9pNGRbfplbrcYAa1W30r9YlFXAogOD3oruuPlJOemmAZ4Vb1zI7sAy3++k8Vi/BYPLXIadr0dAMv9WQMfaLecL+36fvej7v4oO/PqV7WSzlemPL1gjyMXv6bvqjR5UwpzAUuTY8ogP6jHoSm/SIZT1WY9Ehw8nUs1L2Q+0Qs4oYStDrkBD36oBsYOvRbfdP7cX0fsv48+0jo56u50H/1DkyJRUbo+nrvjUUcCyA4PagdB/t+kTJ9ao7lU0vSk/9tTzZRF02P5tZrNZenDmKdJ2bo0B31He/HLXzI+vNTvP5c/19yk59U8YI8jFY/FcZrpa4fuz/neQYL6GEmXgehHL/fAaj8Yn/un8/nqvXb9NTDTL8Idw5dOq6OZnGQExU15ZKvz2N61zk2j+OYd3oeADyDve5HuRt5QA99/S3t7UOtn88KWB0vNKNnCOHfv3/Z0Nx/HeQOXJ/epBtGDWXMUoY5/RGT0qD8UQ+C3/kimU1lpKyMmmnxNekH8RWebMDBwXfkK8zi9PiQZkGSXvbzSefyimvvF9Ek9tJLNL6PZnQM+zzO85R55memH7V3SVD9Sl+W9zZfq5/j+IH3X4CDg7+dX6EA1Wl/fvS9q0jJ58J3LkqJlvfRvCwQMb2PJijeNaDUp79zARwcHBxc5tZ+Pvi9XXkKZo3vLbHIxECEi7N6dDki5vTLf6onXtXL9G35ztXBwcHBx81ArKZb+3m9HY0/I8Y7GRMnGrr2rmaissDVbUGc5duPevD5fK6ptounS1Hyy4GkXxHu+V22+PfvX2pMAi/tJztcvmXxZT+HcuW1AgcHB8+4sq9byocyvaafL/tJOl7QcUSZrxfkYfRg9vYGdShj2qJbonG/CEU1s+pamtW5J0ErXubUf1oQfYSY7CjzbfPTnR/YLwIODv52Lu/5aOjnO/cIPgYhEMnmGkaM7y1rNJqMBYf6N7n44qNYt7vd8+Glg4ODg4PP5YP6+S32i1A8sDST0BWLWAOOBjvyt1x0zRqevOfDS9f7s4IODg4O3jbrsLg+qJ+X95SUOoXXeKdHw4RC14rHaUTkjwOJBJxe/RZnsEzji+B9Ep9V59JkPOJ8EXBw8J25sq9b1geX/j/ueb5IJC8zEcb3hkwpnM8XCYoz6ZR2HsZ5njI3rQWOWzvUpB/EsV8EHBz89Zyb4QgEI/p5rs9/HqX/x+8zZMvxnbOjz9TzfJHg9HPfh6FZt8MeEXBwcPA/yCfuEZwCrz0i1vHd83wRa/qJe0SoLkfEnI49IuDg4OC+MxCr6XP3CI4Y72RYJxo4vWV8P42oLv+k9SSqcGtLshF9pv0IrW/KHbF3RPAB+0XAwcG35jvuF3Hv5xffLyLs+eD2iMTadk+Oy3A+XyTFX1vsEaE4z1PJvdYOD5wvAg4ODr4Yj8bzRdp0mU+BsOLxg/NFHoBm3Q7ni4CDg4P/ET6on99ivwjF6D0iFDhfBOeLNOrg4ODgbbMOi+uD+nmOc/5QjNsjwqFhQqFnxeNDr4IGdGam/NmPxkL1x0JVg2UaX3ws76MJtXfKJD01oNv30RzkXQMH3kcDDg7+B7iyr1vWh+u7mn7+6iereR1rv4+Gfkr/bRvZNZlSeJ4v8sO89E5waFCQ0QBa8VXOrflla2apIWZ6amSda4ea9IP4gf0i4ODgb+fcDEdQ9PPyXhM9n4vMfxqUWMd3faae54tsGohwa3WUm9YClbomX3BwcHDwidzazwfjeVQCn4JZ47vn+SIPBCJea2ZUlyNiTj/4tcCqXqZvy3euDg4ODj5uBmI13drP6+1o/Bkx3smYOdFwGlH9ubDwu+R+I/JHPQjd54skPf3YOvsup2d2ZB8izhcBBwffmSv7uqV80PfnVC/7yXK8MOXrBXkYvfw3fVGj68fu3t/0hm2XZjKc56nkl/9JP44jbeq89OOLpHN2lPm2+QkODg4ObuV0Jruahuvnq+kFOwKfgrlbL54+X8Rlk4svNOt21r0gzeeRgIODg4PP5UL/3NPPb7FfhOLJiYYh54vstXdEs4bH7fm4XTusrhFi7wg4OPjf5Kv1Y1Wd67cDsy9E2c/Le0pKnWLcHhEOT694nEbE2vnz1QRWffH9ItW1RuUeEQ0XfMB+EXBw8K35jvtFyu/SPlDYO8Lltfh+EU1iL72E5/kijvrzOM9T5pmfmX7gfBFwcHDw/Tk3w3GRNDtS7efpDHogsPowF1O2XuB8Edt+kaBYC7TuHQEHBwcHX5Nb+/mA80VEnQPOF7mJiDnduncEe0TAwcHBV+jHxvXzejsaf0aMdzJmTjScRlSXf1zWkBbfL0L1tJ6XdGHtkNtrcmK/CDg4+N/gO+4X0ffnVC/7yXK8MOXrhdv9IiP2iAzfL0JRrplln5biCkszGc7zVPIs4juOI4uIs7VDwY4y3zY/3Tn2i4CDg7+eC3s+aN9e7eeFvSYmH6ZA2POhmXFJYUDb+N4biwgZJz0rRv8mF198FG9rFNYIU4OrvgFS1lPD1fgADg4Ovilfoa/T+1Du7aBjgbWfT3Y4m5yf03GN7+kv/ag6vvfsAR1yvkgwznzM3TuiWcOT93x46Xp/VtDBwcHBrXy1fqyqD+rn5RmUUqcYt0eEg3V87wlEQgjhNCIt/5TrQJGA06vf4gyWaXwRus8XOfk1SI2uXL+M2C8CDg6+M1f2dcv64NL/L75fhPs3fk9Mkcf3hkwpnM8XCcV5G5fC7SnpjaT8cJ6nzKtrftxaoFWXuTX9II79IuDg4K/n+j0fvv081+c/j9J/ulgTauM7Z0efqef5IsHp574P46P4nbfp9+JWHRwcHBx8Te7Vzzf0/1NgHa+9xnfP80Ws6SfuEaG6HBFzOvaIgIODg/vOQKymz90jOGK8k2GdaOD0lvH9NKK6/JPWk6jCrS3JRvSZ9iN0ny+SpffSM479IuDg4FvzHfeLuPfzi+8XEfZ8cHtEYm27J8dleJ4vEkj8tcUeEYrzPJXca+3wwPki4ODg4IvxKL5T5vk9go9BWPHINoWMGN+7ftMrZNywp6TTk2Zo1u1u3ymDvSPg4ODg7+CD+vkt9otQjN4jQoHzRXC+SKMODg4O3jbrsLg+qJ/nOOcPxbg9IhwaJhS6VjxOI6rrQ0nh9ohwH8kGyzS+CDhfxMKxXwQcHLyN77hfRPNdk774fhHu37jp+SIpgYudx3Cep8yFPR/x97sJqjyl71w71KQfxLFfBBwc/PWcm+EIZFy77fMb+nmuz38e5ThVbgpR2tFn2hKLeE3dLBKIfCzvo6H6Qd5BcPx+v0xVL9cUU3qND+Dg4OCb8hX6ujYfyj0fcj8fxPGi1AU/p6Acl1Mc1jC+68MRz/NFHghEvNbMqJ4aQej73XniVR17RMDBwcFX6MfG9fN6Oxp/Rox3MrzG8Zbx/TSiuvxjXSsyGZE/6kHoPl8k6WnNLPsup2d2ZB+wXwQcHHxrvuN+EX1/TvWynyzHC1O+XpCH0YY9HxpdP3b3/qY3PPuzn3E4z1PJL/+TfhxHjPEq0aUfXySds6PMt81PcHBwcHArpzPZ1TRcP19NL9gR+BRMXPEIz58vIuidnjTjo/idN3e+iFX/3P0eHRwcHBx8Lhf6555+HueLCBhyvshee0c0a3jcno/btUPT79H1/qygg4ODg7fNOiyuc/12YPaFKPt5eU9JqVOM2yPC4ekVj9OItPzjvra0+H6R6lqjco+Ihgs+YL8IODj41nzH/SLld2kfKOwd4fJafL+IJrGXXsL5fJF9946c5ylz7vfi6fdO17/X2mEq14HzRcDBwcH34dwMx0XS7Ei1n6cz6IHA6sNcTNl60bJG87JAxLRfJCjWAq17R8DBwcHB1+TWfj7oxguND1Mwa3zH+SI3ETGnW/eOYI8IOPj/t3d2a5KCyhKlz7ffCx+95sk8F+5i0/ykmZCoVb3iKjoKA1AHciRFOPwJ49i6cV7vo2nPivlOxp0PGnYjmss/LmtID88XyfW0npd0Ye2wl2uyky8Ch8P/Bv/EfBH9eJ7r9ThZzxemer1wmi+yIkdkeb5IjnrNrPi1Fp+wNFNg33clLyK+bduKiLhYOxR8lPWOtdOdky8Ch8O/ngs5H/nY3hznhVwTUxtugZDzoXniksKAsfl9NhYRKk560Y35JBdf/Fi+R1OvEaYbLvH8WFlPN66mDXA4HP6h/Aljnb4NdW5HPhdYx/nk8xHfo8mxvb8p86q+LNOc32dyQJfsLxKMTz7uzR3RrOHJOR9eur49T9DhcDjcyp82jjX1ReO8/ASl1nOsyxHpwTq/zwQiIYSf/CxokK/IFBXXj2tqPVTdEAzrMr44ItDDWY6Ujy4MRMSy3itT8Lz7T/hfBQAAmPB6vW5/QqMcb03HmvRjJLfW5QV5Gq1zD/InH8Vzkeb8PhmgOO8vEqr9Ng4lDziUPhfjNKJvrvnV7R/TZW4tv4g/52IBAD4OT3gqM/bk5ppx3j34GEbzQUNvHq+Xb/Kj9JV67i8SnF73vRg/ive8Te+LW3U4HA6HP5N7jfMD4/8tsM7XXvO75/4i1vI35ojk+tia4vYnc0TQ0dHR/47uNc6Pjf8r5jsZ1gcNPX1kft+NaL4uHN878OdKglxSdj79aQZhen+RoryXXvDI/iJwOBw+x5Xj7bpxPn7s/iL1PF7M77Gzp4h+7vbcXyT8TmN5fo5Ijn3fldxr7XBjfxE4HA5/GI/9/UUcdZnfAmHFo85ddZ/fp97pFSoeyCmZbMkwNOt2p9+UIXcEDofDv4MvGuc/Il8kx+ockRzsL8L+Iujo6Ojo/9MXjfM93mtPjnU5Ij0MPFCYWvHYjWiuDyWlWEOq9eZRPcO6jC+CJV8kLsgR6ZUpeCRfBA6Hw+e4crx1H+eTHp+dL9L7M76zPOX5faDSHP77i6QCLj6XYd93mQs5H/H3twmaPNeTHP0AAB3LSURBVJWfXDvUlF/EyReBw+Ffz3tPOEI2r52O+QPjfG/Mvx71PFUnhSh99JWOxCJej24eEoj8KHbfa35HYKt2UE03cVOv1xRTeU0b4HA4HD7Mx8bbOudDHueDOF/UutDOW1DPyykOG5jf9eGI5/4iFwQiXmtmuZ5ugjD33nniTZ0cEXR0dPTP0q3jvN5H054V850Mr3l8ZH7fjWgu/1jXikwm8k8zCJZ8kVyP7/W8pKc1s+LYnl74yG2I5IvA4XD4HFeOt0J5zThfj5P1fGGq1wvyNHq033SgRtfP3bPv9IZrX/tZh33flfxof9K3bYvvD+wd+vZG0ns+ynrH2gmHw+FwK4/Zk+xmmd443ywv+Aj8Fty44hGu319E0CdbMowfxXvevf1FrPrP2fvocDgcDr+XC+PzzDjP/iICluwv8lm5I5o1vDxSNq0dmt5H17cHHR0dHX2R3hu3i/LWcb7He+3JsS5HpIerVzx2I9Lyj/vakrCwpF9zMiFY8kWKNTxBj28kXcOFNkTyReBwOHyOK8db4dh8DKzH+aT36orPzhfRFPbSazjvL/K5uSP7vsu89754et/p+DPG+Grt1X+Ur/t7Wq+1nev4xv4icDj823nvCcdB0tOR5jgfsyfoIYO1DffiltSLkTWaLwtETPkiQbEWaM0dgcPhcPgzuXWcD7r5QtOGW3DX/M7+IicRcU+35o6QI4KOjo7+WfpAjqDSR9OeFfOdjDsfNOxGNJd/XNaQhIUl/ZqTCcGSL5LraT0v6cLaYVMvfOQ2RPJF4HA4fI4rx1uhvGacr8fJer4w1esFeRo92m86UKPr5272F/kv9n1X8o39ReBwOPxLecyeZDfL9Mb5ZnnBR+C34N7Ui8Hc1WbF9YOg5qOh+SQXX/xYvkdTrxGmG/ffv3+pF4WeHsH9/P42Qa3D4XA4fAXXj7d1bkc+F/TG+aT3fD7iezQ5NvGbMoWeJ/MOYCoWESrO9dM4Q+6wtXarrlnDyyPlOtck6YV/rRflT+tFR0dHR79YnxznC71Zl6Y9tdu8rkfuUHSkOb/P1rgbkZZ/6nWgmKGnN4/qGdZlfBEs+SLRmPOh0XtlCh7JF4HD4fA5rhxv3cf5pMdn54v0/ozvHVPk+X2g0hzO+4uEar+N8PvRTfHwYz5288K+7zIv2nnodfvHdJlbyy/i6drd2AY4HA5fyusnFteM870x/3qcPvup5/eej75Sz/1FglPyy8X4UbznbXpf3KrD4XA4/Jnca5wfGP9vgddikHV+99xfxFp+IBCxxl8aXY6Ie/rWeV/cqlvrRUdHR0e/Rvca58fG/xXznQzrg4aePjK/70Y0l3/SelKu9NaWZBN9pfMIlnyRXI8LckeENkTyReBwOHyOK8fbdeN8fHa+SK9Acx4v5vdY5ZdoKs0x+05v6LzW+xE5Ijn2fVdyr7XD7dP2FyFfBA6Hfz0/QgHHcX4yR/AyCCse9Xs07vP77F5nA2tF1iWe1dCs251+U4bcETgcDv8Ovmic/4h8kRyrc0RyTMUiA2tLVh/5KBdds4aXR8p3rR2io6Ojo1+gLxrne7zXnhzrckR6GHigMLXisRvRXB9KSrGGVOvNo3qGdRlfBEu+SFyQI9IrU/BIvggcDofPceV46z7OJz0+O1+k92dkf5Erse+7zB+ydqgpv4iTLwKHw7+e955whAwrxvnemH896vZv6/cXGYlF5ACirv5QmvoTApEfy/docn3rfIMmtL5ZcFywwieV17QBDofD4cN8bLzNx+3t93fEhPE/vNH0UbbzFgi5IKE/v/d89OHISCzikswynCPiXnsejerXFOs4MZVp6vWF2bMnDY9aK0VHR0f/Pn1gvK3HbXmc1/to2rlivpPRLPnqf/TOc37fjWgu/1jXikwm8k8zCJZ8kVxP63lJT2tmxbE9vfCR2xDJF4HD4fA5rhxvhfKacb4eJ+v5wlSvF+Rp9Gi/6UCNrp+7Z9/pDde+9rMO+74r+dH+pB8R8dGjQ9/eSHrPR1nvWDvhcDgcbuUxe5LdLNMb55vlBR+B34IbVzzC9fuLyGtRt+BH8Z53b38Rq/5z9j46HA6Hw+/lwvg8M86zv4iAJfuLXJY74qJr1g7zSLm5LqjU80j5IWuo6Ojo6Oi53hu3i/LWcb7He+3J4TXf6XH1isduRFr+cV9bEhaW9GtOJgRLvkixhifo8Y2ka7jQhki+CBwOh89x5XgrHJuPgfU4n/ReXfHZ+SKawl56Def9RT43d2Tfd5kX7Sz0LcvQfrXewz7K1/09rdfaznW86AscDod/H+894ThIejrSHOdj9gQ9ZLC24V7cknoxskbzZYGIKV8kKNYCrbkjcDgcDn8mt47zQTdfaNpwC+6a30dikS/IEdl073kLujV3hBwRdHR09M/SB3IElT6a9qyY72Tc+aBhN6K5/OOyhiQsLOnXnEwIlnyRXE/reUkX1g6beuEjtyGSLwKHw+FzXDneCuU143w9TtbzhaleL8jT6NF+04EaXT93/2/rWSXqeOeCSGrRas7Pz0/MtgARkDeg4Adprh0CAAD4MtTjfDH+53NKb+4QcKzmWKdmja1Q+6J5XD93D+auNmuq5+DmrDyf5OKLH8v3aOo1wvheghG+TZAinp/f3yao9SY/TrKmnUt58S/k9vbA4XC4nuvH2xBCc6zbfn+TpTf+F2NmeOMjvkeTYxO/KVPor/5W8RpMxSJCxUVkpPGxhiNecZxmDS/dcK/WNwWSXj8xCu+M62b503rR0dHR0S/WreO8rDfr0rSndpvX9cgdio405/fZGncj0vJPvQ4UM/T05lE9w7qML4IlXyQacz7i2dqhcGzBI/kicDgcPseV4618bOzkDmrqis/OF+n9Gd87psjz+0ClOZz3FwmKtTSlz8XY913mRTsPvW5/oaf+yuVlbi2/iBd9gcPh8O/j9ROL03Feqev5vTh99lPP7z0ffaWe+4sEp9d9L8aP4j1v0/viVh0Oh8Phz+TFuJ1wwfh/C7wWg6zzu+f+ItbyA4GINf7S6HJE3NO3zvviVt1aLzo6Ojr6NXo9bh+4ZvxfMd/JsD5o6Okj8/tuRHP5J60n5UpvbUk20Vc6j2DJF8n1qF4jTP1Vlm/ySL4IHA6Hz3HleCuXPyY1k3/S47PzRXoFmvN4Mb/HKr9EU2mO2Xd6g32/jYcszRTY913JTWuE27YJ5ZX1jrXTnZMvAofDv54foYCQ83FB7sgtEFY86vdo3Of3kTUaTcUDOSWTLRmGZt3u9JsywloguSNwOBz+QVwY50MGTfnT79QI/HaszhHJccX+IkofazjidZo0a3gxxtQ8R35aLzo6Ojr6LXpz3A5ZRDIz5mvak+PKsODUYUmNuxHN9aGkFGtItd48qmdYl/FFsOSLxKE1wto/L987tuCRfBE4HA6f48rxVj42sr8I+4ssxb7vMh9bIyxyLObXDjXlF3HyReBw+Nfz+omFNRdkbJzvjfnXo25/Wrvoze89H32lI7GIHEDU1W+/9/BX+lyGH8v3aHK9XiO06unxXf39moJv7+/XCGUu4D/ZtxKe0B44HA7Xc814+2p9OyxUmB//e/NOHgxdD2HRJ/Tn956PIRzZjbA+itHrvZK7Yh1nTA/ZuoPVJ3ZeTi70goz5xNbjsrH2zOgHrq8XHR0dfV6PMQrl06+yT67MtzP/Nf/zmJqV5ZV679eBFup1udIcPrGISweERuv7Y0Kw5IvkerpXivK1ni6wXF72z6+rst4Ven2u7m0POjo6upeuHN9ijMP1xt/jfI8XPl6IZ7FIr8CMLleaw9zh2npFB/Q/zSBUz0U0DTC1X3mBZf+4JmK16kWB29uDjo6OrtebP105vvXK1IfcEous0JVd3udjkdU3inzUJMI7TSlXZN4rv1Q/Ts7t7enx288POjo6+qkexScfyvEtZpPRcHtkXhzlhWiPRXqH6HW50hzmDkdFlDemC41edJqOq64pn7ewd7qbetO/Lj/sf6VekNvbg46Ojq7Xi5+K8gVZ0Z4eL46KrVhEKK/UeyWt5U26XGmO8VjEpaEaQ/mnGTQj5Sav7w+XSFzpn3f/xv9hpH9aD/wfDzo6Orqs9/huGd+OYmPtKY7t8eJYL0RLLNIr7KXXMHc4XTCXBuW60Gh9f0wIQ/kiJt3lAte/rr5RmnqM8ZZ60dHR0ef13rCcRI1Pjw+0p4d4dyzieP6VXd7HYpHVN4reYRLBni+yu0biSj1OROLo6Ojo6MHpyW7MAhqXdta8KOmFqItFesXGdLnSHP/bYkUJr13xezu7yZX61n7sKpMXsLbWtK9cvm9d7XOBv9Kt55P/6tKe0N8np+l2gY/e6jKfMaulPgNWD/EJ2cbQq30G/qU8xKdwW+rjOJ5YW1X49PRF40z9a/7nv3//9n1XllfqvV8HWqjX5Upz+MQiLh0QGq3vjwm373A3gOMePXixC2quHzzd06flNT4x25FwxsfantjZCXGFz/7e6l72396x7AU+yv7mZZ7gc3qe3X2U9+cx4F7gk1/fyX8vXj55Hx/ic3qefX0+BXn7vXAaiwTjR+80umHuVj4/Sagfufg+0rH+NAN992NnLS2+sf9+xlXD5FkUE/zzAoJ/rgg+wlE1GfZp9q7nUx+41Oe0X3t1wi/wSQcKPr1urvApTHo+hb7UR9OvooOrffbfp3S4X44+6SjZp2m1yCcpcr96R1l9mh2R9UIc9u95NjEwNZ9Crl15/1h1fZf/TxWw9OH4SGeyJcP4+fk55ek7Atvvbwqc6gVPnkofr/KP9Qmdc3WXj/X64vNZPmHu36O7z8Xn57HjwMN98nEmx/B1LDx7/HYMzOPDKxiD3+ltVrxV3+A1+ejLN2sf1mP2+G7PHovl+sHrdqYyPb3p3/Op9f39qF9Zb88/9etRPofSPFd3+ZiuLz6n9//TfILl3+MFPhefH8fxxMvHq1+OPoIefmP4OobW/VPrObYLw4LCoe54T5yqUfn8pH7k0nxElj+zaurNo3qGdRlf5N2X+dFypZ56GlqZ23qfXvncvy4z43Na3sUn19OVFXx69a7w2d83m+yj6a+XT97Hh/h49et6n5jdJ6t9dsX4sGf3yQU+yv72+F0+Xv1Keq/8qf9hOOa/V9dIyb0QLWs0+Z+pRwlFyVpUVppjMHe1GXOlSDn8Dpry8sWB+Z9CHDcf4jWRf6lZxmnsKfQ3iRqfWg9V0D3sX0SyTZ9CP23MgE+wnLf81wt8wu9TOtwvR5/w+8z3fJpdW+QTsjtK6FfvqBU+ee96Ps0Tss4nqO/P/J5Z7ROcxhMvn5ffeKL0yRvW7FTPX2iPxj/0z0MN/dykh1x7/mt9e4fRcaOpNzGSLyJ0yXQB9BdmKUz5IuF5a7qXrT2Hznr56vYE1vjxIfcIn8XjSU8vfBImx5nH5otY52uv+X0kFhEiZVP5gUCkV8uMnoefUbGGt2drgbmeeFOvy/d8VvvLPrWefIrzMOxjbU/wOP+OPqvPc1PH5/TfS9Ddn5f53PLv91t9at19HOjphU/C5DijmXdWzHcyhHnZpA/M7yOxyHzFY4FIMJ4Ok35Eo6/3vgKFXnAhwj302qepn0b6Sp9T/0OvI/d7fbz6db3Pgef4XHx+lP71/1Dv9fHql97nwHN8nnlfPXZccu/vgXpOqX0O6OevMb3A8Lzs4jP1Hk1d8ZYtEya9CMq8OuyLPBqVedH+bdvie+Ojor+9aLfpI+iC/+u9VqfxP/V5/V5zLXya5Qd8cn1rrc33/C/wOcijfNL1fY7PcZTmfrjM5yDb+3+3T/A5sInjw6uVA7HUR+6X73ji5aMcT5Tnp3efa+7/zXWcEfgtKNp5IHU5vwTN/qbyTZ9TzD4X6VUsNEjo8C0w5Yts1+YoPHZt3ssndM7VXT7W64vPZ/mEuX+P7j4Xn5/HjgMP9+nlcAxfx8LzUfkiOazze0/XYGoP+K2K3BPv6aEVi2zvyLfXjeZP86fp571X92n5vIWF3mxwjeKE1D5Nf30Vsv+YVeGzdQJhq4+1PSH7j8hqnyL8l60e5VO4LfUZ6N1qnzD6j3Gdj97qMp8xq4ePS1af0BkHCrJinOnxopZX9l2IQu+V1+i9kqfl63+qvTuh9pcr/QXlu78Jkf1FfpeR9TixD4HG/0o96vbnQEdHR/84XTm+xdF9XOpjldwL8dn7i5g7nJrV/ClmgUXexNgJOOoOC5W6Q3+9rSda09+P0wduOHR0dPSP0JXjW4/PtKfGvbFIUTKdmaTHDHv/1AmntMZILKK8YEVzm2V6hwvOjjiutzVKNUXEPW71QUdHR0e/XY/ZfOzi3+S54oWoi0XqYvGNWkl686jTSnOYO9yzjmr0fIRGC0fN6PX11vsoL0BBhn2eoOeX7wntQUdHR/fSD5yWz5X5evNfcxxzk768Ru/9elom6tBsiVxpDp9YxOWUCY3W98cEfZR6NGAg8k0XWC4/7H+lnq7CQ9qDjo6O7qUrx7cY43C98fc4r+ReiGexSK/AjC5XmsPc4dp6RQf0P81Af701J7epKy/wsP+VelHg9vago6Oje+kXjG+9MjVuiUVW6IYuK8tZaxrQhUbr+2PCcb1NUWp8ZER/jd7jT2snOjo6ulVXjm8xm4yG6z3lueKFaI9FeofodbnSHOYOR0WUN6YLjV50mo7rrSmft7B3upt6ce/2yg/7X6kX5Pb2oKOjo3vpBVlRb4/XR9WxiFxeo/dKWsubdLnSHON7nc1vvaI0lH+aQb6fjMyP7Vz+/fsXYzx0OBwOh8NNvNjHTMO9YNrrzH1+P8Xg92iub+hq5Be+5sONfE4H5/FNfQEAgAHMD4PyXPMEOM7v+kpHvkfzZYGI5rsAcDgcDofnuLKuy3DX/D4Si9wYiPTirBk9j0bTIzV0dHR0dPRCz7G63hXznYw7HzQo80oSoiU/xaT3Css/zSDv/iKeWn5BXfQFDofDl/JY5Zau5l6Qp9EYo8s8vutSdGuMPBcp8KFLMwX2fYfD4XA4/HZ+C+5NvZiNRW5JcvHFE9Yg4XA4HP58nuPKum7BlQ8aBt+jaVZcxBPWNSprOOJ1mp6wBomOjo6O/nw9x+p6c1y//pAcmlNzU5yqcTciLf/U60AxQ09vHtUzrMv4Iu/+Iv5NORbf1Bc4HA4f4F+cL9L7M743bZPn94FKczjvLxLekVEeNB3PPJoR1nNyR/Z9X8FTfxf5X8m/qS9wOBz+WH4v6nk5rV305veej75Sz/1FglPyy8V4whokHA6Hw5/Pc1xZ12X4hv1FrOXZXwQdHR0d/YP0HKvrfc7+IqGfC/LE/UWKFabe2pJsoq90Hnn3F/FvyrH4pr7A4XD4AP/ifBEh56OXIxJb6Z49LmP823i1oswRCfZIatFqzgVPw3oBNQAAgE/Ev3//LqjFOjWfQp5G5e02iqSQ5vye/izerlXO3VPv9Ao1DeSUTLZkAO4X+7vxkPweAAAAF6C33caKHNCpvc4G1pasPvJR6Ojo6Ojo6Epdj83pJRUlxtdo6orzzgt7oAlLPBev0QATuAoAAPChkAfwrb+2slVPR5rz+2SAwv4iAAAAAPgvmg8aevN4cxEnHaWvlP1FAAAAABCCfb72mt+d9xfZ3qh/LfSxQORpa2/o6Ojo6OifqDdLyus4B079ZZ82lO/+yq8LC+8lz5vIP4HLwFUAAIAPxcz+IsO6ftYYeS6ijICsOgAAAABuwS1LMwmzsYhXQ/UPkQAAAACwGlc+aJiKRRwDEXJH0NHR0dHRl+p6bBeveCjXcurlH/e1JfJFHg6uAgAAfChO80U0hb30GoPPRbwiptlICgAAAAB+cJzf9ZWOxCIEIgAAAMD34a75fSQWIUcEHR0dHR39o/Vmydvmd+Vajrz8w/4ifwFcBQAA+FCwv4hWBwAAAMAtYH+R/+qTLQEAAACAF6580DAVi9y5tvS8tTd0dHR0dPQn63ps1654/Oz7bjog1VdXrOx8fVTPsC4DbgRXAQAAPhTyAF78mv85NrNrKs0x+FxEqOD1ehU/HX/WuuwDAAAAgIvRnJd787gc3+grHYlF5EBEX55ABAAAAHgOvJZmrPP7SCxiTT4lRwQdHR0dHf1RerOk6UFDTxd8ehjPF6nFrbPCVK9CCSb6SsHF4CoAAMCHQh7AjylbeNBQzOOJ1+mePS7jP5pCMpohSB5wFEEZUxoAAADwKMiBSBF/uM/vg7mrpxVbH/XoHyIBAAAAYDWs8/vMg4apWGRgbcnqIx+Fjo6Ojo6OrtT12JxeUlFi1f4ivbWlwP4iHwuuAgAAfCjkAbz4datyPk7n98kAZTBf5DRiKtq9kTsCAAAAPB7NBw29ebwIU4qj9JWOxCJej25Mgcj8EycwD64CAAB8Mazzdf3URNZ7GIlFrMmn84EIz04AAACApbA+aOjpAyseDu/0hiwCakYkvYjJpWoAAAAATOI0oUSpj83vnvuL9JJSe+UBAAAA8AS4pFgMz+9X7y8i6JMtAQAAAIAXLgtEwqL9Ra7sAAAAAAB8cfE8Ph6LEIgAAAAA34fr5/HBWIRABAAAAPg+3JJ6MRKLEIgAAAAA34e75nfP/UVm9COAIoMVAAAAuB7b+5O8zZ+WP2jYjYgxKkWTHt+Y9EFHR0dHR0c36THGFf69MjVGYpF1OO0YOjo6Ojo6uru+CM3qasw+F3ngCUVHR0dHR0c36fWv8/69kjWmYhHHE9H86ZkXDB0dHR0d/cv0ooCLf69wjfFYxPdE1L/efmHQ0dHR0dH/iN7jK+qtMRiLuDe0KPCEC4OOjo6Ojv5H9PSno3/vpxqDuavWBp3qPe7lj46Ojo6Ojt7TD8XXv/drDZ93euf19OdzLgw6Ojo6Ovof0WOM7v69AjV+9n037UfS3MPkEJU7lR0lC5PkUOvKhhU7pzUbeaVPbjW5Ra6XT7J6jk/o3A/JZ/K+GvBJbj2fMHpbrvPRW3n5NK2aGxhe5lNbDY8nXj6BccnSpAt8rh9PTn3CI8eTQjd5FuNJ07PG1Hd6hcoO5fV6nQ40p3rTZ8D/aT5ba5O7e33WXcdP8Un6o3yauNHnaefHdD/gI/swLj3QJ+lLfWox+F3HU8zGImOBxbxurVc40Xf5oB94lA/3yXfrgfsNXaEH7hNXXYOpWMR6AQQfk97z//QbbrWP1f8CnyZu9Hna+cHH0cdxPPHy+ejxhHHpMp+7/r14tUeD8VhksuJTH6v/03yC3wVbceHxwWf1v9+n+Xz0eMK4hM+VPl73gx4j3+kNiogpH0FeWfJOMbJoTkQ6pOfzUiQH5VbX+NQmtU9SLvBpujX7e5lPUN8Pwem++laf/IZ8iM9x1KN88j5e4PNiXHrkuJSO6vkE9f3wrT6O90NTb2LkucjpiVCWd9RN7bzAB91RDw971Mz99kw9cJ+gK/TAfXKr3sNILGI6EUJ5lwtv9cfns3wc7ysvn48Y4Fb7WP0v8GniRp+nnR98AuOJt4/VX4DDO70DFXtFUl7twSfpT/O55b56mk9gjR+fP+zDeHKNT5jO+Rhrz4HBfJFexemmeXmsUSXUPgP+T/PZWONX+OR9vMDn5bo27+VTm9Q+ITvzq32abs3+XuYT1PdDeNg48DSfzW888fJ5fex4ovQJv0+XfB3X+dRi8LuOp5h9LqI8QTlcdGu9wom+ywf9wKN8uE++Ww/cb+gKPXCfuOoaTMUi1gsg+Jj0nv+n33Crfaz+F/g0caPP084PPo4+juOJl89HjyeMS5f53PXvxas9Gox/j6auWPgnmqM+6iV+oUbfNvkE6a2u8dFbefk0rYozP9ykMZ/ayve+GvAprJr/wAaaNOOTWw1MkCt8ktVzfILiUbb+LLn4JLeeT2Bc6lgtGpeGrdb5jFmt8BG41VZuZxvKb+gV399b/TW/R329EB0dHR0d/bv19Kejf++nGiOxyIoT0eNe/ujo6Ojo6Og9/VB8/Xu/1hh8LuKupz+fc2HQ0dHR0dH/iB5jdPfvFajhE4vMdyAuiMjQ0dHR0dHR79J7ZWo4xCIuHYgxPuHEoaOjo6Oj/0G9+dOkf69YjdlY5IEnFB0dHR0dHd2k17/O+/dK1piKRRxPRPOnZ14wdHR0dHT0L9OLAi7+vcI1xmMR3xNR/3r7hUFHR0dHR/8jeo+vqLfGyF5npvIAAAAA+JtQ7nVmjkUAAAAAABwx+208AAAAAIAZEIsAAAAA4E78P3FGwotdY3j9AAAAAElFTkSuQmCC"/>
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OH6SdLb2/xFNOPJ3rRP3tOFvrJnVxZ/+7jR7IPGR7kJ7dsOz8z/STnIfeTu9rfT3IeWD9JuQv9JA2X/LDlLvGTf0pSHuRHOhUW/+x5Zs9/7kc6lGBtfFNsV8hgLI5fn5Kmg1jj5rWxOajNubGsfbL+B62tPsXPbmvYj8s58PKz23mGn7V+DuEaq30+7OZnk+feaD/u/hW+BGd9/GCPKwr5xXlh53meWaBz/sBSOb0Ud/0qrUE2rMHTsq7KnBuL/yf6key39XNw18ML/Gx1nu33BfwM8nMI11jV82E3P9J5eLqfCfU8uOfMjRHjrw49TsjjCsWSP2CZ52Fnfmp1yVg/1IykdVU8lNY47wor9rV64j+xWe7H0t6k3LV+8vOQ6/Gqe5mf5Hxu7ie2/U1+ws/1uYOfQK4rxc9Vej7M9JOch6K+vx+JG/0HMkRWPQ8lnwr3QiiN+JJBm84eLcc3vpWoPdQMY4flRceTRUEtJT33wx6iH9T9SzVc4ofaS36Schf6SRou+WHL3dYPex4SP9KnlviRTkXy7+P85E4SnbVf5UeyDxn28VNsV17i/n6S85B7kPznyP0n3qR/JcyPb/Tz2aCzBv87VNSujSm6XtAIGAtll9tYxa4X63Dr//79Cz/Ty8naKqvHXZhuPfxMM07wE6ut+CmWO83Pka3xW87D/n7a+neVn3hdKX4s1+1ufprP57Z+jiz3a62f3c5Pp58bcSxoGEeK9hKvcjsTXnGFsrx1HIe2f7FXYae6P6P0wc7S70eVUm5eK6oYrwnWP/VAD1V5Nvqf5oeemf39WDwcv3cUfY0f9npe5Ye9/hOxqjI7+JGuW3rGaiszzk/t5beDH/350PCUeIofVq/ynF/P9KmSf/D8+aadRAKKvVGXLKVDnSXyZtKEz5zpo+KhZhxkofdqyrlR9Ht6rWgvcVq9qnKhQ4cOHfqz9BBCp59AhlGXeio2Xgg1I75kbNdZS6ZVd2d0FpbrVa3tx/E7vtGLHtHe6/dFyRoPKhc6dOjQoT9Cz49KSoN/6VBitja+cTmfrMjHN/2F5bq9tS6I8Y0evd5XQG1ETCus2MeLcp9vEtChQ4cOfaYe1PEi/B6nWD+3k4b6xKJZm+tnnKKKF4JtxJfMXHSmVaxdf2GW1jo29eDmbyRlkB6vbNY+ue4n1Ac6dOjQoW+l06Pu/vNDuX34HWkV7Y26dJQeciyRPWSKb1wqYWmtI47K/JurJkK/PXdG+rF6O3zDgA4dOnToI/TQPV4Ebiyz+JFsFD9eCKURXzJo09mjTKtCFtw5VqL2UDOOmvwbS2WoLvHEnj0UxcnnGTp06NChz9clThXdj/SpYn0ks8Rmfnzjfp5Zg0J841gJvbXSoWYc5vybqz6ypudUsY9mxcjaWC506NChQ3+WHtTxIoRQ9BNaZ4BCNgblPPmUF0L9iN+jszZ1+9947esglVgU7Xrn/jd2y+azBAAAAAA39P11Gsap42n737DGOdgWOex/E37AiuwHgzp9VDzUjGPp/jfGqNlYN3BwcHDwh/LQvZKgzwA16IqNF6pG/Dx4SOIKxVIpjn8/gxJ5xdCJKjRINPqZjOu6WH53bV7P20bSD/Ut4gc5D1K513VZbMDBwcHB/xS3z5FI9lE3lrsWyezUTVziCj6+USay9Mq1VWIo6DuAWH6e579//2LrknepsPpBzoZkXywXHBwcHPz1nEKyScaafHxpGKfYd67lnI5r89EQP9jjisL7NZPC2BDHMbjpX/OLeuT0IqMdGXX7WqZdP8+zWC506NChQ3+9TiHZB5It6jgeWeoZzRzHX+Po7xLEHEruzpVBWdmiRFoby0XJreVQM46l+98E5N+Ag4ODg5vzb5Rxhx3LiuOUYqP48UJxxGcjDT2uYKMLydsl5d9Q5FnKh7w2xsaSO+C6LpbnEXfDGmeuI/8GHBwcHNzOlfEln4mpHad0Ph/FmRsprqjKxfm/tkpYFoYs+gR8Ph87v9c4i3qEZA8ODg4ODp5AsrGMO816Qz1Ho2pZqnkhTItvGtbGfHNxXHT7WuldT4seS5Tsq8qFDh06dOhv1SlGjEe63lZPr/HXDsVDe1xxZVBWs4prY/kHQ5a7I5Xoi6My/yYY1jKjfjdWsQ/IvwEHBwcHx/43hkN58JDEFYqlUhz2vwkH9r8BBwcHB9+D25djJPuoG8tdC1r/OCy6xBX8+lRtbo3jspQ7iuuODWucrH/k4oCDg4ODJ5xCsoljh1fOTcN4tAQN8YM9rqje/4aNcnKxOefGJb3ozLLNb7BrkFJ2+m0fD1EeDb7fL42gq8qFDh06dOiv1ykke7qSkIwj7BiU8MR/1XgUzRzHX+Por1vac3okS2aPxbxIl+YpLRkx0/P5eb9m/De2tMjvyJfq8YK4dft5BwAAAIBO0LEsH4++3y87fuVjWXG880JxxPcNp9ij1fvfNOtrIa07KpEvjY6ltUDptFpOwp4nCgAAAHBEz3AQFwqK45Gei6Pz+ZgzV+S//01V7s4EVK2Vnr/XLKU10eJaKTg4ODg4eALJxpJDM3o8mok5C2Et+9/MmdGRQqJa3b5Wemb7B0Ru1JPcHWO50KFDhw79rTrFuPEot++pp9f4a8eQuOLKEOT9b3p0yUA/1IzjOELf/jfhB0ad+gnY/wYcHBwcvHv/mzimNI9Hej0TGy9Ujfj98QZryc/frJ25GYHrulhOI99Ev2t+6+cPqC5F3FJZ4ODg4ODgOm8bj1g/xnLXYlxcUbf/zRODm+K6o7RmWbvGiVwccHBwcPCEU0g2tePLiPFoCYbGFYX84jmVoJ9y15MoONelNcvanJvOtU/o0KFDh/4+nUKypysJq8ajEeOvDseVIr6AK8OItTHFWD/UjKMy/4by/jXOgPwbcHBwcHBz/k3V+ELtQyl3R69nYuOF4ojvElfo3rD/TUj007z/DY24k7LO33sSsNxiAw4ODg7+F3g+jhwkh6Y4HkV71o/O58Nx5kaJN7D/zS9uXOPE/jfg4ODg4BZOIdlg/5tjwGSKNn+Tf5iGKcraW/6p7+93YVjg1VT7GmRez2S9M5m5OUrvrjKWCx06dOjQ36pTtI1H+ZiSj0f5+JXM+lTVc/66DW2pdPRGnLgql3hlUFaz4rIfK7IfjP8WV+N8cVTm3wTz2qdFD8i/AQcHBwfv3v9mhK7YeKFqxM+DhySuUCyV4vj5GyUyStb8jt/vYEqCr31yca7rYjmNfHP7Zh35N+Dg4ODgDdxxPDKWuxa0/nFYdIkr6va/KVaurRJDUVx3lNYsvXRwcHBw8D/LKSSb5v1sHMejJWiIH+xxRe/+N1JhbcGNZe2tVqdRKrsG+a3ZP6BWV8qFDh06dOiv1ykke7qSsGo8GjH+6nAJYrQSrwzKyhYl0tpYLkpuLYeacVTm31Aeutc4A/JvwMHBwcEH7H9j1yUbxY8XiiM+G2nocQUbXUjerob9b+5ASVobo/pWuK6L5VLkm3+2Skf+DTg4ODi4nfvmgFbVYT7m5Pj6738j+dELGoeqtVLk3ICDg4ODO3IKyWaHHNCZcEl3KU6maPFNw9rYhrk49jVIx7XPqnKhQ4cOHfpbdYr541FbPcfl3EhQPLTHFVcGZTWruDaWfzBkuTtSib44KvNvguvaZ0D+DTg4ODg49r8xHMqDhySuUCyV4rD/TTiw/w04ODg4+B7ccTwylrsWtP5xWHSJK/j4RsmtySeRFH2H4Obz+cSOZHm+Znn9BB///v2L7fr371+cyov69/vV/YCDg4OD/2VOIdko+9/k486RjUe5/9tPtFHqKS1RzYGey8suWtnjivLvp4qV8M25cSmFnhR6kbFrkF/uHVJHFj/Gz0adRsdUMZYLHTp06NBfr1NI9nQlIRlH4ndpZTxK/FeNR9HMcfw1jv6JJZ3Fcflh03FlMK5s1epVq3H9OCrzbyjP1yzjQqDdvliWxQYcHBwc/NE8eO9/k4xHQc7dkXwq/r1QHPFd4grdW/X+N836WlzXxfI84o6RbwwJQwjsWiCNuJOykH8DDg4ODm7neg5NcTyK9qwfnc/HnLki//1v6qaPxuNTswdAsvYprYkW3xUCDg4ODg6eQLKx7GczejyaiTkLYS3730zLxXHR7WulZ7Z/AF3jtOg04t5tDRg6dOjQoc/XKcaNR7l9Tz29xl87hsQVV4YRa2OKgX6oGUdl/k2+Thl+YNSpn4D8G3BwcHDw7v1v4pjSPB7p9UxsvFA14vfHG6wlP3+zduZmBK7rYjmNfBP9rvmtnz+guhRxS2WBg4ODg4PrvG08Yv0Yy12LcXEFH9+8KbgprjtKa5a1a5zIxQEHBwcHTziFZFM7vowYj5ZgaFxRyC+eUwn6KXc9iYJzXVqzrM256Vz7hA4dOnTo79MpJHu6krBqPBox/upwXCniC7gyjFgbU4z1Q804KvNvKO9f4wzIvwEHBwcHx/43wiGXuEL3hv1vQqKf2P8GHBwcHHwuz8eRA/vftOo3CvFN8uFkFqhqGspo6Y5PzbtC8jXOGMSw7/7I1zjtZYGDg4ODv55TSDb6O6TOn/chSuPRTfLxKH6BV+pJv+RPg7LMVFz2ip8tTqZo8Y3yYSno+f5+5wX1UxvieMVx9jVIWs+kgTRezvXcT1W50KFDhw79rTpFw3gkjTuW8ShZbbDXc/66TTLyJnFFYmYt8cqgrGbFZT9WZD8Y/y2uxvniqMy/Cea1T4sekH8DDg4ODt69/80IXbHxQtWInwcPSVyhWCrF8fM3xZmbfM4m13U/k3FdF8uDnEPToyP/BhwcHBy8gTuOR8Zy14LWny5C9ccVdfvfFCvXVomh+JR+95+vWfrq4ODg4OB/llNINs372TiOR0vQED/Y44re/W+kwtqCGyWEatZplMquQX5r9g+o1ZVyoUOHDh3663UKyZ6uJKwaj0aMvzpcghitxCuDsrJFibQ2louSW8uhZhyV+TeUh+41zoD8G3BwcHDwAfvf2HXJRvHjheKIz0YaelzBRheSt6th/5uY5MyujbF53Tvgui6WS5Fv/tkqHfk34ODg4OB27psDWlWH+ZiT41tYn6pdG+ufsHJH1Vopcm7AwcHBwR05hWSzQw7oTLikuxQnU5g9iGiglHz4JLnNuXgI8zen8Ht9vZYNoRXVP59P+L3PI2tPj0r1bNBvotcznxhz6Vq7vjDoBAAAmAb38aVKl7jux2U8UkbzaHAcx79//5JIwGV8qR3xD9v+NxUD6JVBWc0qro3lH8xzd6QSfXFg/5sSb85PAgcHB38Kt+SgDOXG/BtLnb10xcYLVSN+HjwouTiKhwTY/yYcf3X/m7z+4ODg4OBrueN4ZCx3LZL5rZu4xBV8fKNMZOWLGoq+Q3DzKb0f5OTeIRVn7WK74rs/qP79fnU/4ODg4OALeXxur6oDhWRjeYeUMh7l/s+fd1fZz88S6AtnbBKFPa4o/36qWIkqfU4p9KTQiyz/tdSRvTMr0WP8GD8bdRodU8VY7oY6ODg4+Mt4fCyveq5SSPZ0JSEZR+J3aWU8SvxXjUfRzHH8NY7+iWVDllLU+QKuDMaVrVp98/wbyvM1y7gQaLcvloX8G3BwcPDR/Cn5N1XjC7VXcnd2zr9xiSt0b9X73zTra3FdF8vziDtGvjTqZ9cCldwd5N+Ag4ODg9u5nkNTHI+iPetH5/MxZ67If/+buumj8fjU7AGQrH1Ka6LFd4WAg4ODg4MnkGws+9mMHo9mYs5CmBbfzF+NSz7lotvXSs/snR10jdOi04h7t9wa5NyAg4OD35j5vKUYNx7l9j319Bp/7RgSV1wZRqyNKQb6oWYc3fvfSDk3llwc5N+Ag4OD78Cfkn8j1TmOKc3jkV7PVfk3FmO7zlry8zdrZ25G4LoultPIN9Hvmt/6+QOqSxG3VNZunGKH+oCDg4ODt41HrB9juWsxLq7g45s3BTfFdUdpzbJ2jRO5OODg4ODgCaeQbGrHlxHj0RIMjSsK+cVzKkE/5a4nUXCuS2uWtTk3nWufO+jg4ODgb+WrnqsUkn0xh2bCeDRi/NXhuFLEF3BlGIJ5o4kAACAASURBVLE2phjrh5pxYP+bEkf+DTg4+Ov5U/JvqsYXal/M3dHruSr/xiWu0L1h/5uQ6Cf2vwEHBwcHn8vzceTA/jet+o1CfJN8OJkFqpqGMlq641PzrpB8jTMGMey7P/I1TntZ4ODg4OCjefwSu6oOFJKN/g6p8+d9iNJ4dJN8PLK0nX7JnwZlmam47BU/W5xM0eIb5cNS0PP9/c4L6qc2xPGK4+xrkLSeSQNpvJzruZ+qctfq4ODg4C/m7Ez5zOctRcN4JI07lvEoWW2w13P+uk0y8iZxRWJmLfHKoKxmxWU/VmQ/GP/dPP/GvvZp0ZF/Aw4ODr4Df0r+jaXOXrpi44WqET8PHpK4QrFUiuPnb4ozN/mcTa7rfibjui6WKzk0PTryb8DBwcHBG7jjeGQsdy1o/ekiVH9cUbf/TbFybZUYik/pd//5mqWvDg4ODg7+ZzmFZNO8n43jeLQEDfGDPa7o3f9GKqwtuFFCqGadRqnsGuS3Zv+AWl0pd0MdHBwc/K181XOVQrKnKwmrxqMR468OlyBGK/HKoKxsUaLn4ljcWg4143Dd/6ZWR/4NODg4+A78Kfk3I3Juds6/YSMNPa5gowvJ29Ww/01McmbXxti87h1wXRfLpcg3/2yVjvwbcHBwcHA7980BrarDfMzJ8S2sT9WujfVPWLmjaq0UOTfg4ODg4I6cQrLZIQd0JlzSXYqTKVp807A2tmEujn0N0nHts6rctTo4ODj4X+Mzn7cU88ejtnqOy7mRoHhojyuuDMpqVnFtLP9gyHJ3pBJ9cWD/mxJH/g04OPjr+VPybyx19tIVGy9Ujfh58KDk4igeEmD/m3Bg/5t1dQAHBwcHp9xxPDKWuxa0/nFYdIkr+PhGya3JJ5EUfYfg5lN6P0i+Znn9BB/sO6eo/v1+dT/g4ODg4At5fG6vqgOFZGN5h5QyHuX+z593V9nPzxLoubzsopU9rij/fqpYCd+cG5dS6EmhFxm7Bvnl3iF1ZPFj/GzUaXRMFWO5G+rg4ODgL+PxsbzquUoh2dOVhGQcid+llfEo8V81HkUzx/HXOPonlnQWx+WHTceVwbiyVatvnn9Deb5mGRcC7fbFspB/Aw4ODj6aPyX/pmp8ofZK7s7O+TcucYXurXr/m2Z9La7rYnkeccfIl0b97FqgkruD/BtwcHBwcDvXc2iK41G0Z/3ofD7mzBX5739TN300Hp+aPQCStU9pTbT4rhBwcHBwcPAEko1lP5vR49FMzFkIa9n/ZloujotuXys9s/0D6BqnRacR9265Nci5AQcHB78x83lLMW48yu176uk1/toxJK64MoxYG1MM9EPNOLr3v5Fybiy5OMi/AQcHB9+BPyX/RqpzHFOaxyO9nqvybyzGdp215Odv1s7cjMB1XSynkW+i3zW/9fMHVJcibqms3TjFDvUBBwcHB28bj1g/xnLXYlxcwcc3bwpuiuuO0ppl7RoncnHAwcHBwRNOIdnUji8jxqMlGBpXFPKL51SCfspdT6LgXJfWLGtzbjrXPnfQwcHBwd/KVz1XKST7Yg7NhPFoxPirw3GliC/gyjBibUwx1g8148D+NyWO/BtwcPDX86fk31SNL9S+mLuj13NV/o1LXKF7q9v/Jo+S2Lhph2WpBNd1sVyKfO/VzdwmhHBi/xtwcHBwcFeejyMH+TVucTyK9qwfnc8HOxMT26LPDNEP6itFhfhG+bAS9EjVWoJPzbtC4prl3bpEV+wbygIHBwcHH81jQLCqDhSSjfIOqdw+12+Sj0eWttOAaRpq4wpWL6bBtOx/Y6mc0Y9euotuX4OU1iwb9Kpy1+rg4ODgf43PfN5SzB+P2uo5LudGguKhPa64MiirWXHZjxXZD8Z/N8+/sa99WnTk34CDg4PvwJ+Sf2Ops5eu2HihasTPg4ckrlAsleL49anizA0Ntb7cuzCKfibjui6WKzk0PTryb8DBwcHBG7jjeGQsdy3YHF+XuKJu/5ti5doqMRSf0u/+8zVLXx0cHBwc/M9yCsmmeT8bx/FoCRrih3n730iFrc25oTqNUtk1SK+cG+x/Aw4ODr4tX/VcpZDs6UrCqvFoxPirwyWI0Uq8MigrW5TouTgWt5ZDzThc97+p1ZF/Aw4ODr4Df0r+zYicm53zb9hIQ48r2OhC8nbV7n9zkB+gs2tjVN8K13WxXIp8889W6ci/AQcHBwe3c98c0Ko6zMecHN/C+lTt2lj/hJU7qtZKkXMDDg4ODu7IKSSbHXJAZ8Il3aU4mYL9b/7THdc+q8pdq4ODg4P/NT7zeUsxfzxqq+e4nBsJiof2uOLKoKxmFdfG8g+GLHdHKtEXB/a/KXHk34CDg7+ePyX/xlJnL12x8ULViJ8HD0oujuIhQfX+N9HAou+Ti3NdF8uDsP9N+P2+D4knPvM1QqncC/k34ODg4OAZz3Nei+PR+/a/SQwkex18fOOyBrZJcPMpvR8kX7OMNvEdH7dNDGhu/T7pFj/g4ODg4Et4fG6vqgOFZKPsf5OMOwc3HuX+ExvL+VkCGickUV1/XNG7/41vcOO15kd1epGxa5DSmmWiR479b8DBwcEfx1c9Vykke7qSsGo8GjH+6vCKK8QSrwzGla1affP8G8rzNcu4EGi3L5aF/BtwcHDw0fwp+TdV4wu1V3J3ds6/cYkrdG/V+98062txXRfLpcj3PE+6xsn+/l7K3bmw/w04ODg4eA3Xc2iK41G0f/T+N77xRiG+GT59NB5Va6XJ2mdcvzTqm6w3v4zfF0+y3gwODr6c30/7fZ4VLI91fkT+DdXzPBtpPLqJkruzW/7NpBzfK0Oc55kwfaR8sLP042cByF4rqoTfuH6fFlanfuJRpZ6Jge/ZtuhKj2yFCWdmxBUIHfpC3X6/N+uPfoDM7B2J635iP1JC/41mVEn8FDvr/ngeCfSfB+XyGNEjrJkY38y8GUbcJ0dl/k3Sx4eccyPp1E8sWinXYjOUV52f3bh+/mv1vC98/UOHPlkPck6Gly7Z7MaX1zPpC4tNfp57xiO9nomNF0LNiC8Z23XWkmnVfbI6C8v1qtb24/gd3+hFSycrkOAsovgp9pBU9EIsr4ARI26GRE8MRlz/0KHP1C3P3k79uQ+QDSug9Fcy7kQl13OfxqLXxjcu1ycr8vFNf2G5bm+tC2J8U4yaAxfhJnrgIujEf26vlGu0Gcot52cHrpxnL93Sd9ChQ6d6fG7v86xg+fJ60gGuaM+eZ8t4xPqxtD3x4IVgG/ElMxedaRVr11+YpbWOTT24+RtJKeqBgP1Ubl+sZ/TGHpqgKz2yFSbcDCOuQOjQF+r6Pe6iP+4Bsk/v5Drtr/zplOiBgPUfdUvHhd/f2Nvqz5bOHr3G9Ah7yBTfjL4ZRtwnB/a/KfHm87OK289/rR5vyE2+GUOH3qlXPa989d348nqGjpUEtv7JeJT4p/aWtic2XiiO+JJBm84erdv/Jv+ZN/vD7/ftf0Ptsf/NZK6cZy/97u5x/qFDn6wf8n4qXjotC7yfK+c5H3ciP1+0/01si7ShzJm9bKvwE/E85KFxUMgmsiJYMTmU2OQ6W4oLDnP+DdVnfrN5xLeKHfjCb6LQoUOX9LB6BtrIl9cz+K0k1OqWtief8kLDiB/kuEKy0X0yexDFgCiPjGJUlQRQkX/JvoqJQyXOkkK5nq1+7m2LlHLzWkn1bNBvotcz+WBnexv0QuS7DZQWWT6e9K/kR/kyYSyis55efoztneOneIXXVmYHP8X7qKEy7n6M93vPeXv0A2Tm81biuh+X8ajYWefP7qlJJDB0fFEuRXqi4iFLi/jipBiKjYbyYCqJs/IPxn8borkeHN373/ToxqjZWLdBvPlbxQ6c/aZyw6W/cl3yHy97o/8eP17tneNH4o/2EwwzvlL/zvRj8d953iSfu/Hl9Uz6wmLTfz/a257YeCHUjPghCx4CgW6pFMfn3yiRVwydqEJDKqOfybhIcEp5GJPbcSL/xo8HW44Uex0a+/cU1rBjEf3++/14tXemn+L9cvy+F97h58iek2v9TGgvuCNv6Ee9f4vlrgWtf7zkXOKK/2NV9sNJGcXC7JUYis/no/Mze2eHrw7uy0/bu1eUd7JU6UX/R/bumLV+vNoFP4/2M62e4EVOIdl4Pa96xqMlaIgf7HEFH9/0F9YW3CghVLOuzwQcx/H9fqUZgn5dKXdDfX9+n2e2LUZd8tPs36uek9s7x4/XeX6WH9qnq/zMae+z+KrnKoVkT8/zqvFoxPirwyWIUUo0xTe1wUpbcHPITerX7yj11vOoOdFj5NupK+XuoOfnZ0/ePPMh6Q3feFz8d/rxau9ufnY7z9Oun1V+vM7b4/iq562xPl7jTsN4dGPc+MuiOU6o8HNlYNN5Io/5PoEkDrO67tZ4qBlHzfunLJWp0tuKnozlFTBCTyjTr0Nj/8ZPKbp0nSv3i68fr/ZO8yOdiuTfx/nJnSQ6a7/Qj6L3nDepiN2wvJ6WCnT2o6Qbi2YjgU4oRVsuKuk6lxrIOizM30iRkaJLfvSCxqEq0nf8JgTuyI3nv3kN+7B9c/Xy77XWDj97+lmeE7PqvIGznEKyWZVzI9VzNKrmfmrjkAgtvlE+7FI5HbWhkqQH8xrk6bf2WVXuWv0RXFr7N+YQ0P5idbbcXPfy3+bHq73w0+NHeg5Yyp3px+Lf/bw9iM983lLMH4/a6uk1/tqheGiOK8T4pi0ocfTjuxYorUHm31S+09c+V+kUO3zLcflmc4yZKXH/pjXIz/IZptp2Sfbw4+tnQj2fxfd5DrN88riTw0s3ojZOMNpX738TDSy6V5DUDz2Kz+sZfr/vQ+KJz+gn2ijfJCw2QznFDt+o7N+0Tux/8xA/yXnI/Ry/74V3+Dmw/w14B0/O83mexfFI799iuWtB2xublhhI9jrq9r/5crjtE6WqEkNhj5Rzm3///sUWJd9uY9Pe981mc56c59E5CkX/h+2b7jQ/Xu2Cn0f7mVZP8CKnkGws51kZj3L7hv5aAhon6HEF1Y3Oe/e/qdWLpbjrxTXIr7Bm+ZX3nxix9rmDvj8/5RyF4+fbzPk7/+lbmStT69+rnpPbO8eP5Tzn5+HpfqT+nelnTnufxVc9VymUe+dQx5EJ49GI8VfH6RRXiCVeGcL0n0wrh5px/P59OG1pkYffv5e7Xd2w2xfLstgM5c3nZxW3n/9aPVS++wk69M31queVr74bX17PYHv/VNXziton/qm9pe2JjReKI75k0KazR5lWBdsP6L10/VAzjt/xjb3oeLIoqKWk627bbIZieQWMGHEz5OLo6xw69Jfpz3qAbF6B4nmWxp2kIxI/xqLnxzfu1ydrUIhv5twMI66/GN9URdaBRMQ3j5dUYpPrrB+pXKPNUG45PzvwhvMMHTr00Xp8bu/zrGD58nrSAa7qs/Q86+NRzu1tTz7lhVA/4vforA3TqqAGRM16bWs7S6eXhbFWVAm/cf0+LaxO/cSjSj0TgxFdrutKj2yFCWdmxBUIHfpC3X6/N+uPfoDM7B2J635iP1JC/41mVEn8FDvr/nge3/SfB+XyGNEjrJkY38y8GUbcJ0dl/k3gIt+87xWd+olFv/JbxQ5cP/+1et4Xvv6hQ5+sB2Fm2rFcyWY3vryeSV9YbPLz3DMe6fVMbLwQakZ8ydius5ZMq+6T1VlYrle1th9HTf6NdLICCc4iip9iD0lFL8TyChgx4mZI9MRgxPUPHfpM3fLs7dSf+wDZsAJKfyXjTlRyPfdpLHptfONyfbIiH9/0F5br9ta64DDn3wQuwk30wEXQif/cXinXaDOUW87PDlw5z166pe+gQ4dO9fjc3udZwfLl9aQDXNGePc+W8Yj1Y2l74sELwTbiS2Yu+ue6ruM32J+Y9/9OXbKkhxx/Df/v378QQrEO589OrLpOf14fdfqp3J46lE7p4fQ6sTZd6ZGtkJ9n3caou9UPALaH8WlcpT/uATLnudqm02dyPnwcZNw5hPEo9ywNMbn/f//+Xdc1bXwZ0SMHO5ha4iCXSMoYzXnhwP43Jd58flbx0d9QwcFfycP4GdDlbVT48nqGjpUEtv7JeKT0r6Xtq+ZvfGdu2KP8+6cokhgzP5p/ZMOg/roult9dS/UYe8amUZuQvX8qjygv27ulLDZDeVLnbblynpt1et3u0EZw8Dnc8T5a3paXceU85+NO5Mk4IvWXzudDmhFMCGtQXBuJKMQ3yoeVoEeq1hJ8Pv+twRX5mb2FleqKfUNZ4A39MkgHB38xV95t1HMfxYF2hzYqfHk9KYp9lJ9n6XlI9Zvk/WVpOw2YpqE2rmB1Pbg59PdPWYIbi16shFS6i57P0Ej6Kbyzo0GvKnet/gj+7XuHlK6Dg7+b0xlQ3Ec3Zj5vKeaPR2319Bp/7VA8NMcV4vxNW1Di6McltDqymZjIv7/fwqrP3NTqMbVZKjePrIv27jrFJt+0WP7v37946dNvjZ36I9oODu7C7+eS+320vF3NfP7zVtcT7jUeWerDBhZe468RZ5Y2YLEvmvHxTXHmhtbjK+R12ysxAXRQp3xEbsdBzoNU7oX8GzMPht/B1er0Qt2hjeDgQ3nn/cLq53kub9crueN4ZCx3LWj945PZJa7g16eki7tYubZKDMXnZ21S4me2Zumrg/ty9As4eBXH820tpyj20cLxaAka4gd7XKHl3/QU1hbcKCFUs57P1iS6yxqnpCvlbqjvz88/mSsADt7DpefVX7uPVj1XKSR7upKwajwaMf7qcAlitBKvDPnvyKNCSURimYuSW8uhZhyu+9/U6gH73wzg/f2i6+Dgr+QB+9/sdP4lmxH9Yml7YuOF4ojPRhp6XMFGF5K3q3b/m+MnUJLWxr677op7XRfLpcg3/2yVfiL/xo/TbzZ5ndt0aYYPHPzd3PE+Wt6Wl3HfHNCqOsxHceZGiivOmlycwvpU7dpY/4SVO5Db8QK+cE0aHPzpfIfcjr/MKYp9dKzrl5lwSXcpTqZg/5v/dMe1z6py1+qP4C65ApIODv5uTmdAcR/dmPm8pZg/HrXV02v8tUPx0B5XXBmU1azi2lj+wZDl7kgl+uKozL/xXfsMyL8ZzL36Cxz89XxhbscOfHk9gy3/xlLnEc+9xMYLVSN+HjwkcYViqRRXvf9NNLDobTM3I3BdF8vpNxtqH36/70Piic98jVAq90L+jZlL5/k8T2Mfsf27vF3g4NO4kkNjedYlz7d92vVKnpzn8zyLfdSZI7UWtL1saNEcV/Dxjcsa2CbBzce8U2RuE9/xcf5+30p8m7zRD7gjT85z3i/H7/5Cv4D/ca6/Q+r+qtBwH0X7Hdqo8OX1pCj2kXKelfEo95/YWM7PEtA4IYnq+uOK3v1vfIMbrzU/qtOLjP3WLq1ZJnrkg9Y+d9D35/naP+0Xiw4O/te49Lyy30e5/RP5qucqhWRPz/Oq8WjE+KvDK64QS7wyGFe2avWq1bh+HK7738SFQLt9sSyLzVDefH5WcXu/1PYXOPiLeZBzO8JPvuCL76Pl9Qy2/Juq8YXaF/tXr2di44XiiO8SV+jeqve/adbX4roulkuRb5Lb8eV+f08j7qSsE/k3flw6z0q/RD2fyZN0cPC/wBvuI8nP8ra8jOs5NMXxSOrf2rFgDhxnbpR4w3//m7rpo/H4dOyzIq2JFveTAPfl0nmu7Rf0F/gf5LX3Be4jX05R7KOjvl+8xqOZmJPj27L/zZwZHa81P/sa5JmtWUprnMW1z6py1+qP4NLaf1XOzfmKHAJw8FpOZ0BxHyVtnKBTjBuPcvueenqNv3YMiSuuDCPWxhQD/VAzju79b3rWpAPybwbzt+YKgIO7857cjkvO53jKPbW8nqFv/5s4pjSPR3o9ExsvVI34/fEGa1m3/82cmZsRuK6L5TTypfahI7eD2kvlXsi/MXPpm815nsU1aaV/l7cLHHwaX5jbAV7L28Yjap/0b7HctRgXV/DrU28KbpDb8TI+eU0aHPzpfIfcjr/MKYp9tHA8WoKhcQX2v+FzaHJdWvukEXfP2ucO+v78xP434OCVXHpe2e+j3P6JfNVzlUKyp+d51Xg0YvzV4RVXSCUyeyzmLvJpsSLySigRz4iZns/nc8/dxX9jS4v8zHaHlDi1p35i0UpZFpuhnJ72VXVo6JfkHLL9kveR7gcc/MX8vtPZ67/2WUf9P+U+Wl7P5PxLNvp51vtI79+q8+OF4ojPRhoWz2x8whbXuP8NuxaY6FuBdh7lUuSbe7DrF/a/ceVSDk1tf1F7aYYPHPzdPLkvIm+4j5a35WXc8fmW6zqfDyVO0OOKJAbS4w3//W8kP3pB4/DpyO1o1sF9uVe/oL/A/yBvztXAfeTCKYp9dKzrl5nQg5sEtXFIRMv+N16V01EbKkm6fQ3yFNYsG/Sqctfqj+Ds2v8p5ATU6uDg7+Z6Ds3fvI9mPm8p5o9HbfX0Gn/tUDy0xxVXhiDvfxN/as+K7AfDY/e/6dED9r8ZzL36Cxz89fx+OLvfR0+5p5bXM/TtfzNCV2y8UDXi58FDElcolkpxdfvfHK5rYzNxXRfL6Teb3L5ZP5F/48elbyp5/e36o2ezwMFrue/zbZ92vZI7jkfGcteC1j8Oiy5xRd3+N8XKtVViKJDb8TKOfgEHr+J4vq3lFMU+WjgeLUFD/GCPK3r3v5EKawtuvNb8TuHXMey3dq+cm861zx30/XltToCkg4P/HS49r/7afbTquUoh2dOVhFXj0YjxV4dLEKOVeGVQVrYokdbGclFyaznUjKMy/4by/jVO5N+M4DPXpMHBX8MX5nbswJfX05h/M6JfLG1PbLxQHPHZSEOPK9joQvJ2Sfk3FEmEdQdK0trY94373zToJ/Jv/Dj9ZpPXuU2XZvjAwd/NHe+j5W15GV+YIzUfxZkbKa44a3JxsP/NL4416T35wjVpcPCn8x1yO/4ypyj20bGuX2bCJd2lOJmC/W/+0x3XPqvKXas/grvkCkg6OPi7OZ0BxX10Y+bzlmL+eNRWT6/x1w7FQ3Nc8aFNpR9jP2xsQ7KeFaeVpNq0BUA6PpXvnzpd320U8P6pwTyeZ7Zf8j7K+xcc/I/ws+/dRodwHz3lnlpez/tJW2WTn+ee8ajq/HihasSPUYfFMxufsMU17n9jtB8RuLSBdh7lUm7HHXzQ4CzXzyyHI7eXyr2Qf2Pm0jcVev6V/jqE/l3eLnDwaVzK1Th+P4uk+yh5vu3TrlfytvGI2if9Wyx3LWL9LSGLoueo2//micHNxym3o3kNG9yXG/ul2F/g4H+E9zzfcB/1c4piHy0cj5ZgaFzRu/+Nb3AjTU/16PpMwCHsf5PrkQ9a+9xB35+f2do/7ReLDg7+17j0vLLfR7n9E/mq5yqFZE/P86rxaMT4q8MrrhBLvDJIvy+3WCp68dfwvjhc97+Jv7y32xfLstgM5c3nZxW390ttf4GDv5gHef+bm7/7Plpez+C9/03SL8X+1euZ2HihOOK7xBW6t+r9b5r1tbiui+VS5HueZ3FNmkbcSVkn8m/8uHSelX4p5khJM3zg4O/mDfeR5Gd5W17GF+ZIzYfjzI0Sb/jvf1M3fTQeyO14ATeuMSNHChw85zvkdvxlTlHso6O+X7zGo5mYk+Pbsv/NnBkdrzU/+xrkma1ZSmucxbXPqnLX6o/g0tp/Vc7N+YocAnDwWk5nQHEfJW2coFOMG49y+556eo2/dgyJK64MI9bGFAP9UDOOyvwb+9qzZU06IP9mMH9rrgA4uDvvye245HyOp9xTy+sZbPk3Up3jmNI8Hun1TGy8UDXi98cbrGXd/jdzZm5G4LoultPIl9oH7H+zDZe+2ZznWVyTVvp3ebvAwafxhbkd4LW8bTyi9kn/Fstdi3FxBfa/wZr0w/jkNWlw8KfzHXI7/jKnKPbRwvFoCYbGFdj/hs+hyXVp7ZNG3D1rnzvo+/MT+9+Ag1dy6Xllv49y+yfyVc9VCsmenudV49GI8VeHV1whlfjJuyF3kU+LFZFXQol4Rsz0fCrfP0X52f1uo4D3Tw3g7Hlm+yXvI90POPiL+bnu3UY78OX1TM6/ZKOfZ72P9P6tOj9eKI74bKRh8czGJ2xxjfvfsGuBib4VaOdRLkW+uQe7fmH/G1cu5dDU9he1l2b4wMHfzZP7IvKG+2h5W17GHZ9vua7z+VDiBD2uSGIgPd7w3/9G8qMXNA6fjtyOZh3cl3v1C/oL/A/y5lwN3EcunKLYR8e6fpkJPbhJUBuHRLTsf+NVOR21oZKk29cgT2HNskGvKnet/gjOrv2fQk5ArQ4O/m6u59D8zfto5vOWYv541FZPr/HXDsVDe1xxZQjy/jfxp/asyH4wPHb/mx49YP+bwdyrv8DBX8/vh7P7ffSUe2p5PUPf/jcjdMXGC1Ujfh48JHGFYqkUV7f/zeG6NjYT13WxnH6zye2b9RP5N35c+qaS19+uP3o2Cxy8lvs+3/Zp1yu543hkLHctaP3jsOgSV9Ttf1OsXFslhgK5HS/j6Bdw8CqO59taTlHso4Xj0RI0xA/2uOKTB3Gs3/P3T7CS+Rtqdgi/olKqS926pBedPz+oK9YhaZeXnhhIp/QYvJWirm8SgBaRRPdDz8xukL5UAPtg/wvJ/jSu0h90E7mPL+46fSY7jkeHYa+W8+f34dPGF2WgjFzSD6FFrG7a36/2Om6+7qVP9et3lPr92W8m6neEm+jnT+TbqSvl7qDn52dPvsM3mx2++QF7YofrpIq/+H7R+arnrbE+XuNOw3h0Y9z4y8IrPlb8lOObPMKKyvf7/f68BijR+yvti9rcDmlN1K7vzyl2qI/eR179cqq/MtiN36C3Ff7u9neH66Q2t8NFX96Wl3GvfmF1nc+HEpR8v9+vEFfkHykESVeGJIc5OZSnNIcMrM9Vv5+ibcz5Plnr87nl/OzAR/z640Ftx9+d/4bVv4Ks4mH6r0R34MvrGStQ+9n+/rK0gDPIbwAAIABJREFUPWzw+6lcD78h2eg+tfgm/0BeWFIP6VNS8UrNLKdA0WPX6vb5CbLXX9Hzs5TXMz+Nur27rvTIVhhxBh7UdnqZ4e+efzeHXtVm/RFtv8aML1W6xHU/Uq9V6cXOCiEELr7pPw/K5SH1SHKiItjPSjqFmF/MTvuctmxH+kEpkygv0eLZjk/l+6dO13cbBbx/ajCP55ntl7yP8v59BKc3o/3uSz6V/93Hj8XDbn4S+/2vK6WePffRU+6p5fW8r5Yqm/w894xHVefHC1UjftsNWCyOz79RavblkOgWP5NBO4/yIOR2xOBD0UOWw5H72ZlT7FAfvY+ofmY5NEp/HUL/Lm+XsY+UO/9LskBye/sQPs6P7oEtd38/if0O10mRs8+lM8uhke6jJz7fnsvbxiNL/1rGgvmgtx5FrtywxxV1+9+46JNRzGY/bb8aaP4VD7gvN/ZLsb+ewqX7+SuEGpYhfJofS5CklLunH9bz8utE4T3Pt9fcRws5RbGPFo5HSzA0rjD9Pnx0Jein3PXit/av8GuabzZDoNif6q9ynqLvz095JsaoP46zwcfxe6iWdGkIn+bHEiQp5e7ph/W8/DpRuGWmWb+Pcvsn8lXPVQrJnp7nVePRiPFXh1dcIZZ4ZbAnClXptdlGnTgq3z9FeZJvdbvK87B0+2JZFpuhvPn8rOL2fqntr215+J3KmuTcFXXp7z5+cuzvJ1F2uE50fteWvf7Dzy+h2LZIeu5neRsVvryeyfmXbOznOemXYv/q9UxsvBBKI75k0KazR6v3v2nW1+IyR/Qx8j1/EH6vcVL9ePI3G4od6qP3EfuNU+qXqCv9u7xdxj5K5kti087fiyns7AL7d6Yfy3zJs/wc2fzNDteJnTfcR5Kf5W15GWfHkXielfEosW8Yj+Yjud3c9RuF+MaxEnpB44Dcjhdw6TzX9ssT+4sOpXl4odtIQ/gcP0dNkPQUP9LR5deJwnfI7fjLnGLnHKmZmBDcHHp841VYsRJS6S669E3d8s0+CGuckk4jbnu5a/VH8K/wjeRbk3NzPnOmjQ6lSXgRIdlIQ/gcP4d5vuRBfqSjy68ThRdnmv/CfXRw52SOTjFuPMrte+rpNf7akd9ubfovXBlGrI0pBvqhZhyV+Tf2tWfLmnQsWinXYjOUV52f3Xhbv+xTfyMPtkwR3XKVH4vP3GZ/P8nRHa4TnSv1zPXYWNZG4svbqPDl9Qy2/BupzmFwjlRi44VQM+JLxnadtazb/2ZIhDUFV+U3m9CR2yGVtRun2KE+eh9RPX5TYfvlMuRI5T735Ec2p3KQr0p0TuLgZhfYv9P8HDWLXA/yk9jvcJ0UOftcOg25HdHmeNrz7bmcfV4VxyOlf4vlrkW8lTr1HNj/5jixJv0obuyX1+RI0aGUIgk1WF0awqf50T0kYcRT/LCel18nCt8ht+Mvc4qdc6SWYGhcgf1vji/2v3kOP+WZGKP+OM4GH8fvoVrSpSF8mh9LkKSUu6cf1vPy60Thlplm/T7K7Z/IVz1XKSR7ep5XjUcjxl8dXnGFVKL4/ilWsdc7r4RUM/1QMz6V75+i/Ox+t1HA+6cGcPY8s/2S95HuZ1uuhxQsikP4Vn4sHnbzk9jvfy3dtWWv/9pn3fHA+2h5PZPzL9no51nvI71/q86PF4ojPhtpWDwXv4H8hytDkqdD/42pTFQPBPnHJbfGQ804fucX24vuT3RSjGtthmJ5BYxou650/UFtD78TWvF3w7+bg1ZSqnCD/oi2Xxv0kaUCjv3SUDQbCXRCKVq6eKgeCKg3qYGsw0J8k/uiReaipd56iV6I8Q3tuZwnNklPu+u1NkO55fzswO+Lx7dfHtR2/N35b/h5du1zzSg8uN5HT2n78nrGCtR+tr+/LG0PK+Kboh5+Q7LRfWrxTf6BvLCkHtKnpOKVmllOgaLHrtXt8xNkr7+i52cpr2d+GnV7d13pka0w4gw8qO30MsPfPf9uDr2qzfoj2n6NGV+qdInrfqReq9KLnRVCCFx8038elMtD6pHkREWwn5V0CjG+UWqQ+6V67fnVDzUjWZ/a8JuNxWYorzo/u3Gv/tqc03sKfzf8G55wXSn17NEf0fYd6nlfLVU2I/pLqkPYYP6G3lZRidAtleL4+EaqWdSTshOdLbKqtf04avJviu2t1e1FL8TyChhhvJSr9Ae1XRlc8XeTv5tDqmSn/oi2XxvU01IBauPYX8ai18Y38d9AIOlSo1hRW5/Kdak8ycbiVj/UjMOcfxMWfbOx2AzllvOzA0/q6dJfz2o7/m77N/w8u/a5Zow8TMnt2IEvr2esgMW+v1+obml7WBrfJJyiqBeLs8Y39K5OykvMEkvdbXKoquq6zs7fSIq7np8WtpKO7W3QlR7ZCtLNINn06LshuaHwd8+/myOvpFTtKv0Rbb/GjC/uun5RNeuWjgu/f3VRtDfqyuUh9UggkHSpRaxuim/y2hTrYXFrOdSMozL/5nKNoGPRr/lWsQPv7xdd35DnTz383epveMK1dNf2z95Hy+uZnH/JZkS/WNoeFs3f5AaBQNLZT0nFleMb+i8tIOpJwVKriq31BTt/Yym6tv6s3lb0ZCyvgBFt15WuP6jttML4u+ffzUErKVW4QX9E268N+shSAcd+aSh6fnzDHqV6IKDepAayDgvxTe6LFpmLlnrrJXrhwP43Ht8qduD3xePbLw9qO/7u/Df8PLv2uWYUHrD/zYo6xArUfra/vyxtD4vmb3Q9/IZko/vU3s8wY/vk3yUWRbseX4Cg29OjPTu1J57jUaWeyQc729ugKz2yFZQWWT6e9K/uczfcbXzHqwxe7MfykYVQqtrwSFcGiD0xYnyp0i1PHun53HlBFjvrzN4LUVtPvf5sbXsuxePnapRa+gtSDGWJsKr0hmiuB0f3/jcxcjTq1I8xajbWbRBv/laxA2/rl33qb+T6zAH9ctP8d5wfi8/cZn8/ydEdrhOdK/XM9dhY1kbiy9uo8OX1vK+WKpv8POf9cjk998IG8zeSsV1nLfn3h4+ObefjIsEp5XfXntzbdL8/LxO+ruv8AdXDz0vOos/cz86cYof66H1E9fPn7bhsvyT9dQj9u7xdxj6iX+Po3+Pne0x+tDg/McfPYZgvycvd309iv8N1UuTsc+lujvR8i/rx+75b3pbXc/Z5VRyPlP4tlrsW8Vbq1HPw8Y1LYfZKDMXn89H5eZ7//v0r6pEb7YvlgrdxY78U++spnA6lFEmowerSED7Nj+4hCSOe4of1vPw6UXjP8+0199FCTlHso4Xj0RIMjSv4+GZyJein3PXit/YvNxOT65Gz9ufPjIK93A31/fkpz8QY9cdxNvg4fg/Vki4N4dP8WIIkpdw9/bCel18nCrfMNOv3UW7/RL7quUoh2dPzvGo8GjH+6vCKK8QSrwwj1sYUY/1QMw7X/W9q1zhj0UpZFpuhvPn8rOL2fulfk96EB1suiKRLf/fxk2N/P4myw3Wi87Aut2MHvryeyfmXbOznOemXYv/q9UxsvBBKI75k0KazR8vzN3NmbkbjMkf0MfI9fxAqczuewil2qI/eR+w3Tqlfoq707/J2GfsomS+JTTu5HJHDPO8yx49lvuRZfo5s/maH68TOG+4jyc/ytryMs+NIPM/KeJTYN4xH85Hcbu76jUJ841gJvaBxQG7HC7h0nmv75Yn9RYfSPLzQbaQhfI6foyZIeoof6ejy60ThO+R2/GVOsXOO1ExMCG4OPb7xKqxYCal0F136pm75Zh+ENU5JpxG3vdy1+iP4V/hG8q3JuTmfOdNGh9IkvIiQbKQhfI6fwzxf8iA/0tHl14nCizPNf+E+OrhzMkenGDce5fY99fQaf+3Ib7c2/ReuDCPWxhQD/VAzDux/U+JV52c33tYv+9TfyIMtU0S3XOXH4jO32d9PcnSH60TnSj1zPTaWtZH48jYqfHk9gy3/RqpzwP43rR6w/81/kW+ixy98F/a/Wcql8xyw/w32v1nhJ7Hf4Topcva5dGL/my05+7wqjkdK/xbLXYt4K3XqObD/zXFiTfpR3Ngvr8mRokMpRRJqsLo0hE/zo3tIwoin+GE9L79OFL5Dbsdf5hQ750gtwdC44n9VlUjufHqU/is9AY2luOiRF7+1J+1K7OOh8Hu9M+o04q4qd0N9f573uNQvUU/s92mLkUu3HjsYH7YhfJqfYpD0RD+s/fLrROHSDOhNzixfML+P8vvuyn65sy1nn+Ezn6sUkj09z8k4QusvjUeJ/6rxKJrlveyrFy2Tuy+/GRU//IErg7KyRQldk6aWuSi5tRxqxuG6/02tHotWyrLYDOXN52cV7+8XXd+Qh76cGPwd/Tc84VoKcm7HCH03vryeyfmXbEb0i6XtiY0XQmnEzw0CgaSzn5KKK8c39F9aQNSTgqVWFVvriyS+sRddW39Wbyt6MpZXwIi260rXH9R2WmH83fPv5qCVlCrcoD+i7dcGfWSpgGO/NBQ9P75hj1I9EFBvUgNZh4X4JvdFi8xFS731Er0Q45ttv9lYbIZyy/nZgd8Xj2+/PKjt+Lvz3/Dz7NrnmlF4cL2PntL25fWMFaj9bH9/WdoeFs3f6Hr4DclG96nFN/kH8sKSekifkopXamY5BYoeu1a3z0+Qvf6Knp+lvJ75adTt3XWlR7bCiDPwoLbTywx/9/y7OfSqNuuPaPs1Znyp0iWu+5F6rUovdlYIIXDxTf95UC4PqUeSExXBflbSKcT4RqlB7pfqtedXP9SMozL/Jkz/ZmOxGcqrzs9u3Ku/Nuf0nsLfDf+GJ1xXSj179Ee0fYd63ldLlc2I/pLqEDaYv6G3VVQidEulOD6+kWoW9aTsRGeLrGptP46a/Jtie2t1e9ELsbwCRhgv5Sr9QW1XBlf83eTv5pAq2ak/ou3XBvW0VIDaOPaXsei18U38NxBIutQoVtTWp3JdKk+ysbjVDzXjMOffhEXfbCw2Q7nl/OzAk3q69Nez2o6/2/4NP8+ufa4ZIw9Tcjt24MvrGStgse/vF6pb2h6WxjcJpyjqxeKs8Q29q5PyErPEUnebHKqquq6z8zeS4q7np4WtpGN7G3SlR7aCdDNINj36bkhuKPzd8+/myCspVbtKf0TbrzHji7uuX1TNuqXjwu9fXRTtjbpyeUg9EggkXWoRq5vim7w2xXpY3FoONePA/jcl3nx+VvH+ftH1DXn+1MPfrf6GJ1xLd23/7H20vJ7J+ZdsRvSLpe1h0fxNbhAIJJ39lFRcOb6h/9ICop4ULLWq2FpfsPM3lqJr68/qbUVPxvIKGNF2Xen6g9pOK4y/e/7dHLSSUoUb9Ee0/dqgjywVcOyXhqLnxzfsUaoHAupNaiDrsBDf5L5okbloqbdeohcO7H/j8a1iB35fPL798qC24+/Of8PPs2ufa0bhAfvfrKhDrEDtZ/v7y9L2sGj+RtfDb0g2us/PdV3Hb9BXkyRvkTC+DyL/lP5GKvZQ5zsvPp9PCEEpN6+V/hoaFqz/+Fm9nvmrN4a++4Otp/EtIWuhtMjy8aR/dZ+74W6j/YK8UfV+paF+Gt739EQ/lo8shFLVhke6MkDsiRHjS5VuefJIz+fOC7LYWbf/f//+JZHA0PGl51I8fq5GqaW/IMVQlgirSm+I5npwdO9/EyNHo079GKNmY90G8eZvFTvwtn7Zp/5Grs8c0C83zX/H+bH4zG3295Mc3eE60blSz1yPjWVtJL68jQpfXs/7aqmyyc9z3i+X03MvbDB/Ixnbddby/w4Oo2Pb+bhIcEr53bV3PRP9rvmtnz+g+v1Z6jP3szOn2KE+eh9R/T7PIQS2X5L+OoT+Xd4uYx/Rr3Hn73dZxyYnR4vzE3P8HIb5krzc/f0k9jtcJ0XOPpfu5kjPt6gfv++75W15PWefV8XxSOnfYrlrEW+lTj0HH9+4FGavxFB8Ph+dn+f579+/oh650b5YLngbN/ZLsb+ewulQSpGEGqwuDeHT/OgekjDiKX5Yz8uvE4X3PN9ecx8t5BTFPlo4Hi3B0LiCj28mV4J+yl0vfmv/cjMxuR45a3/+zCjYy91Q35+f8kyMUX8cZ4OP4/dQLenSED7NjyVIUsrd0w/refl1onDLTLN+H+X2T+SrnqsUkj09z6vGoxHjrw6vuEIs8cowYm1MMdYPNeNw3f+mdo0zFq2UZbEZypvPzypu75f+NelNeLDlgki69HcfPzn295MoO1wnOg/rcjt24MvrmZx/ycZ+npN+KfavXs/ExguhNOJLBm06e7Q8fzNn5mY0LnNEHyPf8wehMrfjKZxih/rofcR+45T6JepK/y5vl7GPkvmS2LSTyxE5zPMuc/xY5kue5efI5m92uE7svOE+kvwsb8vLODuOxPOsjEeJfcN4NB/J7eau3yjEN46V0AsaB+R2vIBL57m2X57YX3QozcML3UYawuf4OWqCpKf4kY4uv04UvkNux1/mFDvnSM3EhODm0OMbr8KKlZBKd9Glb+qWb/ZBWOOUdBpx28tdqz+Cf4VvJN+anJvzmTNtdChNwosIyUYawuf4OczzJQ/yIx1dfp0ovDjT/Bfuo4M7J3N0inHjUW7fU0+v8deO/HZr03/hyjBibUwx0A8148D+NyVedX524239sk/9jTzYMkV0y1V+LD5zm/39JEd3uE50rtQz12NjWRuJL2+jwpfXM9jyb6Q6B+x/0+oB+9/8F/kmevzCd2H/m6VcOs8B+99g/5sVfhL7Ha6TImefSyf2v9mSs8+r4nik9G+x3LWIt1KnngP73xwn1qQfxY398pocKTqUUiShBqtLQ/g0P7qHJIx4ih/W8/LrROE75Hb8ZU6xc47UEgyNK/5XVYnkzqdH6b/SE9BYioseefFbe9KuxD4eCr/XO6NOI+6qcjfU9+d5j0v9EvXEfp+2GLl067GD8WEbwqf5KQZJT/TD2i+/ThQuzYDe5MzyBfP7KL/vruyXO9ty9hk+87lKIdnT85yMI7T+0niU+K8aj6JZ3su+etEyufvym1Hxwx+4MigrW5TQNWlqmYuSW8uhZhyu+9/U6rFopSyLzVDefH5W8f5+0fUNeejLicHf0X/DE66lIOd2jNB348vrmZx/yWZEv1janth4IZRG/NwgEEg6+ympuHJ8Q/+lBUQ9KVhqVbG1vkjiG3vRtfVn9baiJ2N5BYxou650/UFtpxXG3z3/bg5aSanCDfoj2n5t0EeWCjj2S0PR8+Mb9ijVAwH1JjWQdViIb3JftMhctNRbL9ELMb7Z9puNxWYot5yfHfh98fj2y4Pajr87/w0/z659rhmFB9f76CltX17PWIHaz/b3l6XtYdH8ja6H35BsdJ8t+98cQgKypNtX45JPueihY7+BZr2q3LX6I/i3Zh+OWn1zTvM/8He3vxHLrxOFB3X/Gy/9WXzm85Zi/njUVs/k8m7W7VA8NMcVYnxj+bAFzX5cQquo5xnjt55noSf2XnpS7g46xQ6/Muj59Ufzr+E2aeNWv2gAqrDDdVL7q0N3/XF8n+ew3l9zxp0cXroRtXGC0Z7//ZTy4Zh1T5WTZOM3VGICLN9scvtmPZ4H5ZuExWYoz+u/J5e+qeT1t+tPmc3a5PYBjNjhmpFmQPN6ej33wH2543hkLHctaP3jsOgSV/DzN9J0ULFybZUYCnyzeRlHv4CDV3E839ZyimIfLRyPlqAhfrDHFVr+TU9hbcGNEkI168U1yK9Tzg2rK+VuqO/Pzz+ZKwAO3sOl59Vfu49WPVcpJHu6krBqPBox/upwCWK0Eq8MeR5yVCjJE5upbnFrOdSMA/vflHjz+VnF+/tF18HBX8nDul+J7sCX1zM5/5LNiH6xtD2x8UJxxGcjDT2uYKMLydt1XeX9i5MI6w6UpLUxqm+F67pYLkW++Wer9BP5N36cfrPJ69ymSzN84ODv5o730fK2vIwvzJGaj+LMjRRXnDW5OIX1qdq1sf4JK3cgt+MFfOGaNDj40/kOuR1/mVMU++hY1y8z4ZLuUpxM0eZv9A/XrrHVhjgNoRWr29cgaT3Pnz1sYrVZzs4ExM8ay12rP4Ir3yAtfdTzzQYc/OlcmQHV753I7w8m99HyGWgjZ+s583lL0TAeWfro4MbZq/LdWxRe468ddOSVjlaXeGVQVrN69OJqnC+OyvwbNoeGXROVdOonIP9mMG/rl33qDw4+jVfdF/l9ZOHL26jw5fUMfTvpxzGleTzS65nYeKFqxO+PN1jLuv1v5sd0Xriui+XSN5sQArvmR3V25sb+zWb5tx+KVXWwcOM3G6m/DqF/l7cLHHwa13NoivdR8nzbp12v5G3jEbVP+rdY7lqMiyvq9r95YnDjldvRvIYN7suN/VLsL3DwP8J7nm+4j/o5RbGPFo5HSzA0rujd/8Y3uLGvvdl1fSbgEPa/yfXIWfsT+99M/GbDtsWog4P/NS49r+z3UW7/RL7quUoh2dPzvGo8GjH+6vCKK8QSrwwj1sYUY/1QMw7X/W9q1zgD8m8GcHu/9K9Jg4O/hi/M7diBL69nsOXfVI0v1L7Yv3o9ExsvFEd8l7hC91a9/02zvhbXdbFcinx7cjsu7H/jyqXzrPRLMUdKmuEDB383b7iPJD/L2/IyvjBHaj4cZ26UeMN//5u66aPxQG7HC7hxjRk5UuDgOd8ht+Mvc4piHx31/eI1Hs3EnBxfLb6ZE2Eppbvo9jXIM1uzlNY4i2ufVeWu1R/BpbX/qpyb8xU5BODgtZzOgOI+Sto4QacYNx7l9j319Bp/7RgSV1wZRqyNKQb6oWYc2P+mxKvOz278rbkC4ODuvCe345LzOZ5yTy2vZ8D+N6VD/fEGa4n9b8KB/W/W1cHCpW8253kW16SV/l3eLnDwaXxhbgd4LW8bj6h90r/FctdiXFyB/W+wJv0wPnlNGhz86XyH3I6/zCmKfbRwPFqCoXFF+fdT1Klx7Y2NKO2luOiR6zMBh/AOqWifzATkejKjYC93Q31/rs/EsP2Fb5zgf5xLM6A3ObN8wfw+YmcIls9AGzn7DJ/5XKWQ7Ol5TsYRWn9pPEr8V41H0cxx/DWO/ollEkhI8Qbrhz9wZVBWtiiJSCxzUXJrOdSMw3X/m1o9IP9mAO/vF10HB38lV3I7Rui78eX1DLb8mxH9snP+DRtp6HEFG11I3q6G/W9O8t7sZC3w6Ji5GY3ruliufLPp0S3fbJZ/+8nbsidXvkE269I3G3Dwd3PH+2h5W17GHZ9vua7z+VDiBD2uyOd4lHjDf/8byY9e0Dj05HY06+C+3Ktf0F/gf5A352rgPnLhFMU+Otb1y0zowU2C5oWwlv1vvCqnozZUknT7Wukp7B/QoFeVu1Z/BP/W7MNRq4ODv5vTGVDcRzdmPm8p5o9HbfX0Gn/tUDy0xxVXBmU1q7g2ln8wZLk7Uom+OLr3v+nRA/JvBnOv/gIHfz1fmNuxA19ez9C3/80IXbHxQtWInwcPSVyhWCrF1e1/c7iujc3EdV0sp99scvtm/UT+jR+Xvqnk9bfrj57NAgev5QtzO8BrueN4ZCx3LWj947DoElfU7X9TrFxbJYYCuR0v4+gXcPAqjufbWk5R7KOF49ESNMQP9riikF/cXFhbcOO15ncKv45hv7V75dx0rn3uoO/Pa3MCJB0c/O9w6Xn11+6jVc9VCsmeriSsGo9GjL86XIIYrcQrg7KyRYm0NpaLklvLoWYc2P+mxB+XfzNzTRoc/DV8YW7HDnx5PY35NyP6xdL2xMYLxRGfjTT0uIKNLiRvF/a/kSLf/LNV+on8Gz9Ov9nkdW7TpRk+cPB3c8f7aHlbXsYX5kjNR3HmRoorzppcnEJ8o6yN5SWxiq5PwOfziR1Z5HHN8q7wv3//YgD079+/2IpEbysLvKFfqB77SOqXGIvrfsDB382V3A7L8y2OAsl9FG12aKPCl9eTothH+XnWn283l55vlrbTL/nToAQlUlzB6vpkihbf5B+OAVRVzk3+jdmCtlJy3b4Gmdcz2iTxY6LnfqrKXas/gkvfSJKZRdovUTz6vtmAgz+dKzOg8TtAFPP7KJlpzr9J79BGhbP1nPm8pWgbj26ij0fszHT8t7aeXuOvHUNKvDIoq1k9enE1zhdH9/43cbXPqFM/Afk3g3lbv+xTf3DwabzqvsjvIwtf3kaFL69n6Nv/Jo4pzeORXs/ExgtVI35/vMFa1u1/Mz+m88J1XSyXvtmEENg1P6qzMzf2bzbLv/1QrKqDhSvfbNh+OX731yH07/J2gYNP43oOTfE+Sp5v+7TrlbxtPKL2Sf8Wy12LcXFF3f43TwxuPk77qTTvTwDuy439UuwvcPA/wnueb7iP+jlFsY8WjkdLMDSu6N3/xje4OYUcnR5dnwk4hP1vcp2ufUozCpY1zp31/fmZ7cNB+8Wig4P/NS49r+z3UW7/RL7quUoh2dPzvGo8GjH+6vCKK8QSrwwj1sYUY/1QMw7X/W9q1zgD8m8GcHu/9K9Jg4O/hi/M7diBL69nsOXfVI0v1L7Yv3o9ExsvFEd8l7hC91a9/02zvhbXdbFcinx7cjsu7H/jyqXzrPRLMUdKmuEDB383b7iPJD/L2/IyvjBHaj4cZ26UeKOwPjV8+mg8kNvxAm5cY0aOFDh4znfI7fjLnKLYR0d9v3iNRzMxJ8dXi2/mRFhK6S66fQ3yzNYspTXO4tpnVblr9Udwae2/KufmfEUOATh4LaczoLiPkjZO0CnGjUe5fU89vcZfO4bEFVeGEWtjioF+qBkH9r8p8arzsxt/a64AOLg778ntuOR8jqfcU8vrGbD/TelQf7zBWmL/m3Bg/5t1dbBw6ZvNeZ7FNWmlf5e3Cxx8Gl+Y2wFey9vGI2qf9G+x3LUYF1fw8Y2SQ2OZnop9sENw82l6t1HUY7viuz8SvegH3Jef2doz2y+JHu2X1x8cfDJXnm8hhPP3u/bs91H8krBDGxW+vJ4UxT6SznPt8y32r/3nU0KIAAAgAElEQVT8LAGNE/Logo037HFF+fdTtBJ5/Hhk7y6h9kbnSSkueuT0ImO/tbMzMcfvd3wkJVI9XkySH6ncDfX9OT3zyYVnvEL2aQs4+BwuzYAeGaruo3P1DLSRJ7O5uc1onUKypzPN+TiSjzs3ivaWehZH7XHzK4olG1cofvgDVwZlZYuSiMQyFyW3lkPNOFz3v6nVA/JvBvD+ftF1cPBXciW3Y4S+G19ez2DLvxnRLzvn37CRhh5XsNGF5O1q2P/mJK8zZedyNlmWSnBdF8st32wadMs3m+XffvK27MnpN5u8zm269M0GHPzd3PE+Wt6Wl3HH51uu63w+ijM3UlyRTNXo8Yb//jeSH72gcfgM2GelqIP7cq9+QX+B/0HevJ8N7iMXTlHso2Ndv8yEZVkqonkhrGX/G6/K6agNlSTdvlZ6CvsHNOhV5a7VH8G/Nftw1Org4O/mdAYU99GNmc9bivnjUVs9vcZfOxQP7XHFlUFZzSqujeUfDFnujlSiL47u/W969ID8m8Hcq7/AwV/PF+Z27MCX1zP07X8zQldsvFA14ufBQxJXKJZKcXX73xyua2MzcV0Xy+k3m9y+WT+Rf+PHpW8qef3t+qNns8DBa/nC3A7wWu44HhnLXQta/zgsusQV1fvf6JVrq8RQfPr2v+nXwfv5+XsvB3YfiAZ9ebvAwSdwr/vloffR8npSKH10E9/xyNJ2aYlqDhriB3tcUb3/jbGwtuCmtqmKHjm9yNhv7d+a/QNqdaXcDfVtOY3uHa+Q5e0CB5/AQwjJXeByHy2fgTbyWM9Vz1UKyZ6uJEwej6KZ49PVOPq7BDGHkrtzZVBWtiiR1sZyUXJrOdSMA/vflHjz+VnFZ65Jg4O/hi/M7diBL69nsOXfjOgXS9sTGy8UR3w20tDjCja6kLxd2P8mj7jz+jfolm82y7/95G3Zk9NvNnmd23Tpmw04+Lu54320vC0v4wtzpOajOHMjxRVnTS5OIb7Rp/fzSSFpmkicPhqPhjyP46fCxjXptrLAG/plkA4O/mK+MLdjB768nhTFPsrPszTuUF3qL0vb6Zf8aVCCEimuYPXCZMqVIV+Nkgyq9Nr1qc7Sj58FIHutqJJPiNHTwurUDzuNltQzn4KztMtRV3pkK4w4A09pOwD0w/IkbNCfchONGF+qdMuTR3o+04FGGY8uoZeLnXV/PI8Eho4vI3qENWNizDiB75tqpIRaI5a07rA0ujXOEFxcVGvUqZ9YtB41F22GcnraN/mmZed5f9XqtB/BwV/M7+d55/2S65LNbnx5Pe8nbZVNfp57xqOq8+OFqhG/P97gLdmwqD92y/XaaK4Tx+/8Yr1oKfYMv2PkeGb0T7GHpKIXYnkFjFDOs5ceDF8FoEN/kG559nbqz32AbFgBpb+ScScquZ77NBbNRgKdUIoe8bxlRW19yle3t9YFMb6hPZfz+woo6jePl1S0oT5ze6Vco81Qbjk/O3DlPHvplr6DDh061eNze59nBcuX15MOcEV79jxbxiPWj6XtiQcvBNuIL5m56EyrWLv+wiytdWzqwc3fSEpRDwTsp3L7Yj2jN/bQBF3pka0w4WYYcQVCh75Q1+9xF/1xD5B9eifXaX/lT6dEDwSs/6hbOi78/sbeVn+2dPboNaZH2EOm+Gb0zTDiPjlc97+JF5PjNxuLzVDefH5Wcfv5r9XjDbnJN2Po0Dv1queVr74bX17P0LGSwNY/GY8S/9Te0vbExgvFEV8yaNPZo0yrQhbcOVai9lAzjpr8m1wJv0EtJV1322YzFMsrYMSImyEXR1/n0KG/TH/WA2TzChTPszTuJB2R+DEWPT++cb8+WYNCfDPnZhhx/R3m/JuLi2TvCueRcrTJddaPVK7RZii3nJ8deMN5hg4d+mg9Prf3eVawfHk96QBX9Vl6nvXxKOf2tief8kKoH/F7dNaGaVVQA6Jmvba1naUf2P+mpCs9shUmnJkRVyB06At1+/3erD/6ATKzdySu+4n9SAn9N5pRJfFT7Kz743l8038elMtjRI+wZmJ8M/NmGHGfHJX5N4GLfPO+V3TqJxb9ym8VO/CQfZuROLVX/DT7j/dLZz29/BjbCz/NfnL7xE+xDhP8WPx3njfJ5258eT2TvrDY5Oc574vLPB7p9UxsvBBqRnzJ2K6zlv93cHDf3G85ruti+d21dz0T/a75rZ8/oPr9Weoz97Mzp9ihPnofUf0+z1RP+iv5rNQvdt3Lf48fr/bO9FM8z0fW1y/ww57PhX4mtBfckbeNR5b+tYwF8zEuruDjG8np/TdHotdWYig+n4/Oz+ydHVSPLUre4RKbWfQD7suT8yy9W0d5506VXvSf8OV+vNoFP4/2M62e4EVOIdkY+0sajyT75npOA40T9Lgiwh5X8PGNUonv95t4/xKwlbbjrHw9p0XXZwIOYSYm6rFp13V9ycxNbK/0jbZY7ob6/vzkvtncxKg3zNzo/r3qObm9c/x4nedn+Ulmtpb4mdPeZ/FVz1UKyZ6e58RPPu7k41Hiv208GjH+6lDiBDauUPywuim+qQ1W2oKbQ36naL9+R6nfn/c9Rf2OcBM9Rr6dulLuDnp+fvbkzTMfkt7wjcfFf6cfr/bu5me38zzt+lnlx+u8PY6vet4a6+M17jSMRzfGjb8smuOECj9XhiCnJcdUJqoHgvzjklvjoWYcffvfWCwVva3oyVheASOk68pyHRr7N35K0aXrXLlffP14tXeaH+lUJP8+zk/uJNFZ+4V+FL3nvElF7Ibl9bRUoLMfJd1YNBsJdEIp2nJRSde51EDWYWH+RoqMFF3yoxc0DlWRvuM3IXBHbjz/PWvSFt3Lf7Mfr/bCz1A/y3NiVp03cJZTSDajZ+Zq6zkaVXM/tXFIhBbfKB92qZyO2lBJ0oN5DfIU1iwb9Kpy1+qP4NLa/7cvd4T2l0X38t/mx6u98NPjR3oOWMqd6cfi3/28PYjPfN5SzB+P2urpNf7aoXhojivE+KYtKHH047sWKK1B5t9UvtPXPlfpFDt8y3H5ZnOMmSlx/6Y1yM/yGabadkn28OPrZ0I9n8X3eQ6zfPK4k8NLN6I2TjDa/6/2w7dOQ63v9xvtkxDMK0jqhx7F5/WkEXGDHs+D8k3CYjOU5/Xfk0vfVM7zjOcwhMBeh8b+TfqC6ufPbFyn/34/Xu2d6ad4vxy/74V3+Dmy5+RaPxPaC+7IG/pR799iuWtB6x8vOZe4onr/G71ybZUYCnukPEgH9+XJeR6do1D0f9i+6U7z49Uu+Hm0n2n1BC9yCsnGfaa5ob+WoCF+sMcV1fvfGAtrC26UEKpZL65Bfp1yblhdKXdDfX9+Yv8b7H+zvR/ap6v8zGnvs/iq5yqFZE/P86rxaMT4q8MliFFKxP43/3I9Rr6dulLuDnp+fvbkxpmP8wfsZw+uv4y6l/9OP17t3c3Pbue56Mdy/eTlrvUz4rw9jq963hrr4zXuSLpSzxvjxl8WJ/a/acaB/W+2r4ARbddVbX8N9Q8d+vv0Zz1ANq/AoP4yFs1GAp3QR/ziczgQUG9SA1mHhfgm92WBvT1KzToR4xvaczlPbGJP3xW+nRR57l/Sa22Gcsv52YE3nGfo0KGP1uNze59nBcuX15MOcFWfrR2D8v6ytD35lBdC/YgfbGD9sD6ZVgU1IGrWa1vbWXrsWnutqJKfUHpaWJ36SbqBrWdi4Hu2LbrSI1thwpkZcQVCh75Qt9/vzfqjHyAze0fiup/Yj5TQf6MZVRI/xc66P57HN/3nQbk8RvQIaybGNzNvhhH3yfF7fcoYKScfz/te0amfWPQrv1XswPXzX6vnfeHrHzr0yXoQZqYdy5VsduPL65n0hcUmP88945Fez8TGC6FmxJeM7TprybTqPlmdheV6VWv7cdTk30gnK5DgLKL4KfaQVPRCLK+AESNuhkRPDEZc/9Chz9Qtz95O/bkPkA0roPRXMu5EJddzn8ai18Y3LtcnK/LxTX9huW5vrQsOc/5N4CLcRA9cBJ34z+2Vco02Q7nl/OzAlfPspVv6Djp06FSPz+19nhUsX15POsAV7dnzbBmPWD+WticevBBsI75k5qIzrWLt+guztNaxqQc3fyMpRT0QsJ/K7Yv1jN7YQxN0pUe2woSbYcQVCB36Ql2/x130xz1A9umdXKf9lT+dEj0QsP6jbum48Psbe1v92dLZo9eYHmEPfa7rOn4j/zW59PvyKl35kbrX7+ApPp9PCCG6/Xz+a2mR3/sHUP2+Ao7jSHTFPu4xIJVlsRnK6WlfVQcjp+cfHBx8H77D86H2eT6Z30/aoo10PovjUeKf2lvanth4oTjiu8QVujf+/VP9hRXdTgbtPMrjhRL1eLLOjnf0nL/f28Jyi81QntT5ERwAgD2xw/Ph0TwfR46f4eYa/I6w+fANbqRSCvsXO1ZCL2gcqna6PIUdWo36Pjt1goODg4PvwCkkm6odwweNRzMxIbg59PhmToSllO6i5zM0kn6q73yx6DTitpe7VgcHBwf/a3zm85Zi3HiU2/fU02v8tWNIXHFlCGMS0yQD/VAzDux/U+JV5wccHBz8iVx6Vk/jwfZLXqnOcUxpHo/0eiY2Xqga8fvjDdaSz7/Rl5mKEVz87D65ONd1sVzKoUmi4yTnJue3T2lNlOXIvwEHBwcHT3jDeKTn7hTLXYt83EyO5qIxruDjGyW4YetBAxpqv0Nw87Fl1yf2dwKXMZtd8QMODg4OvpDHIGBVHSgkGyWH5rapHXdu3dJ2aYlqDpQ4gY0rDnNwcxTzi6sqYbTXS3HX6UXGrkFKOTQuulLuhjo4ODj4W/mq5yqFZK/n0MwZj0aMvzpq4wrFD3/gyqCsbFESkVjmouTWcqgZR2X+DeW1a5nsmmixLOTfgIODg4/mT8m/6R93cn3n/Bs20tDjCja6kLxdUv4NRRJhxVUqds3sK2/asxbXdbFcyaHp0ZF/Aw4ODg5u5/3jjqLrfD6KMzdSXJFM1ejxhv/+N5IfvaBx+NTsAZCvZbbp4ODg4ODgCSQbl3GnczyaCZd0l+JkSsv+N16V0+G15mdfg3Rc+6wqd60ODg4O/tf4zOctxfzxqK2e43JuJCge2uOKK4OymlVcG8s/GLLcHalEXxzd+9/06Mi/AQcHB9+BPyX/xlJnL12x8ULViJ8HD0oujuIhQd3+N4fr2thMXNfF8iC/Q6pHR/4NODg4OHgDdxyPjOWuBa1/HBZd4gp+fao2t8ZxWcodxXVHrzVO5OKAg4ODgyecQrIpvkNqwni0BA3xgz2uwP43h1fOTefa5w46ODg4+Fv5qucqhWRPVxJWjUcjxl8dLkGMVuKVQVnZokTPxbG4tRxqxoH9b0oc+Tfg4OCv50/JvxmRc7Nz/g0baehxBRtdSN6u5v1vEoNE2WFZKsF1XSyXIt/zPGO7wu/3fVB+cBHohf1vwMHBwcFruJJDo4xB58+OdNGe9aPz+Siu8BgngXQ/hfgm+TBNAnLZF2cCPjXvCknWLOn7O+K7P07yXo98jdNeFjg4ODj4aB6f4avqQCHZ6O+Q+v68D1Eaj24xH48sbadf8qfBJd2lGCS17H/jpevwWvOzr0Hma5aRG/Xop6rctTo4ODj4X+Mzn7cU48aj/hxQinE5NxKGxBVXBmU1q0ffPP+GzaFh10QlnfoJyL8BBwcH34BbclCG8tC3/00cU5rHI72eiY0Xqkb8/niDteTnb9bO3IzAdV0sp5Fvot81v/XzB1SXIm6prN04xQ71AQcHBwdvG49YP8Zy12JcXFG3/80Tg5tP6Xf/+ZolqzfvTwAODg4O/mc5hWRTO76MGI+WYGhc0bv/zZ45N1RPouBcl9Ysa3NuOtc+d9DBwcHB38pXPVcpJPtiDs2E8WjE+KvDcaWIL+DKMGJtTDHWDzXjcN3/pnaNE/k34ODg4Dvwp+TfVI0v1L6Yu6PXc1X+jUtcoXur3v+mWV+L67pYLkW+9+pmtPly78KgEXdS1on9b8DBwcHBzTwfRw6SQ1Mcj6I960fn8+E4c6PEG4X1qeHTR+NRtVZqXOMsrn2Cg4ODg4MnkGx6cm68xqOZmJPji/1v/tPzNUtpjbO49llV7lodHBwc/K/xmc9binHjUX8OKMW4nBsJQ+KKK8OItTHFQD/UjAP735Q48m/AwcFfz5+SfyPVOY4pzeORXs9V+TcWY7tekX+jLzMVI7j42X1yca7rYrmUQ5NEx0nOTc5vn9KaKMuRfwMODg4OnvCG8UjP3SmWuxb5uJkczUVjXMHHN0pww9aDBjTUfofg5lN6P0i+Znld1/fnfR+SvdEPODg4OPhCHoOAVXWgkGyUHJrbpnbcOX+/r8pyfpZAiRPYuOKoeYF37/43UmFrc26oTi8ydg2yav+AWl0pd0MdHBwc/K181XOVQrLXc2jmjEcjxl8dtXGF4oc/cGVQVrYoiUgsc1FyaznUjMN1/5taHfk34ODg4Dvwp+Tf9I87ub5z/g0baehxBRtdSN6uhv1v4ioVu2ZG9a1wXRfLlRyaHh35N+Dg4ODgdt4/7ii6zuejOHMjxRXJVI0eb/jvfyP50Qsah0/NHgD5WmabDg4ODg4OnkCycRl3OsejmXBJdylOprTsf+NVOR1ea372NUjHtc+qctfq4ODg4H+Nz3zeUswfj9rqOS7nRoLioT2uuDIoq1nFtbH8gyHL3ZFK9MXRvf9Nj478G3BwcPAd+FPybyx19tIVGy9Ujfh58KDk4igeEtTtf3O4ro3NxHVdLA/yO6R6dOTfgIODg4M3cMfxyFjuWtD6x2HRJa7g16dqc2scl6XcUVx39FrjRC4OODg4OHjCKSSb4jukJoxHS9AQP9jjCux/c3jl3HSufe6gg4ODg7+Vr3quUkj2dCVh1Xg0YvzV4RLEaCVeGZSVLUr0XByLW8uhZhzY/6bEkX8DDg7+ev6U/JsROTc759+wkYYeV7DRheTtat7/JjFIlB2WpRJc18VyKfI9zzO2K/x+3wflBxeBXtj/BhwcHBy8his5NMoYdP7sSBftWT86n4/iCo9xEkj3U4hvkg/TJCCXfXEm4FPzrpBkzZK+vyO+++Mk7/XI1zjtZYGDg4ODj+bxGb6qDhSSjf4Oqe/P+xCl8egW8/HI0nb6JX8aXNJdikFSy/43XroOrzU/+xpkvmYZuVGPfqrKXauDg4OD/zU+83lLMW486s8BpRiXcyNhSFxxZVBWs3r0zfNv2Bwadk1U0qmfgPwbcHBw8A24JQdlKA99+9/EMaV5PNLrmdh4oWrE7483WEt+/mbtzM0IXNfFchr5Jvpd81s/f0B1KeKWytqNU+xQH3BwcHDwtvGI9WMsdy3GxRV1+988Mbj5lH73n69Zsnrz/gTg4ODg4H+WU0g2tePLiPFoCYbGFb373+yZc0P1JArOdWnNsjbnpnPtcwcdHBwc/K181XOVQrIv5tBMGI9GjL86HFeK+AKuDCPWxhRj/VAzDtf9b2rXOJF/Aw4ODr4Df0r+TdX4Qu2LuTt6PVfl37jEFbq36v1vmvW1uK6L5VLke69uRpsv9y4MGnEnZZ3Y/wYcHBwc3MzzceQgOTTF8Sjas350Ph+OMzdKvFFYnxo+fTQeVWulxjXO4tonODg4ODh4AsmmJ+fGazyaiTk5vtj/5j89X7OU1jiLa59V5a7VwcHBwf8an/m8pRg3HvXngFKMy7mRMCSuuDKMWBtTDPRDzTiw/02JI/8GHBz89fwp+TdSneOY0jwe6fVclX9jMbbrFfk3+jJTMYKLn90nF+e6LpZLOTRJdJzk3OT89imtibIc+Tfg4ODg4AlvGI/03J1iuWuRj5vJ0Vw0xhV8fKMEN2w9aEBD7XcIbj6l94Pka5bXdX1/3vch2Rv9gIODg4Mv5DEIWFUHCslGyaG5bWrHnfP3+6os52cJlDiBjSuOmhd49+5/IxW2NueG6vQiY9cgq/YPqNWVcjfUwcHBwd/KVz1XKSR7PYdmzng0YvzVURtXKH5YnYkx8yLp9FE+f0ON8yUqxa3lUDPusDS6rYq422ZuqB6L1qPmos1Q3p8RBgAAsDm+3+/amaR7gCvaHOSt4IfTeCTZKH68UBzx2UgjcjauyA8p3g5pfUqpZVylkmKdTZalEtgj+rz+Dfr5kPybDXsKAADAFzvMHhV5/7ij6Dqfj+LMjRRXJLGOHm/4738j+dELGodPzR4AZ+W7PCQdHBwcHBw8gWTjMu50jkcz4ZLuUpxMadn/xqtyOrzW/Hr2G2jWq8qFDh06dOhv1Snmj0dt9fQaf+1QPLTHFVeGIO9/E37AiuwHw2P3v+nRA/a/AQcHBwfv3v9mhK7YeKFqxM+DhySuUCyV4ur2vzlc18Zm4roulgdh/5vbpll/Sv7NknLBwcHBwSXuOB4Zy10LWv+T/ESpP67g16dqc2scl6XcUVx39FrjRC4OODg4OHjCKSSb4jukJoxHS9AQP9jjCux/c3jl3HSufUKHDh069PfpFJI9XUlYNR6NGH91uAQxSonV+98Yy8srp7RkxEzPp3v/m3gRKJzaUz/hIfvftJ0fcHBwcHAjPz32v9HHI+r/fMX+NwrY+IQtrm7/G/r5zZelEtDOo1yKfOmJvgORPMhTcndO5N+Ag4ODg5u5nkNDxx12PIr2rB+dzwcbJ0hhimSv6Df897+pyt2ZgE/NWmmyZimtiRbXSsHBwcHBwRNINpYcmtHj0Ux4xRX6ZErL/jfulZBKd9Hta5D5mmXkRp1G3LutAUOHDh069Pk6xbjxKLfvqafX+GvHkLjiyhDk/W96dMlAP9SM4zhC3/434QdGnfoJ2P8GHBwcHLx7/5s4pjSPR3o9ExsvVI34/fEGa8nP36yduRmB67pYTiPfRL9rfuvnD6guRdxSWbtxih3qAw4ODg7eNh6xfozlrsW4uKJu/5snBjfFdUdpzbJ2jRO5OODg4ODgCaeQbGrHlxHj0RIMjSt697/ZM+eG6kkUnOvSmmVtzk3n2id06NChQ3+fTiHZ05WEVePRiPFXh+NKEV/AlWHE2phirB9qxlGZf0N5/xpnQP4NODg4OLg5/6ZqfKH2oZS7o9czsfFCccR3iSt0b3X73/Toa3FdF8ulyPde3Yw2X+x/Aw4ODg4+jOfjyPHH9r9x1G9g/5tf3LjGif1vwMHBwcEtnEKywf43B/a/adDta5D5mqW0xllc+6wqFzp06NChv1WnGDce9eeAUozLuZEwIq740KbSj7EfNraBfpBOo0m1GbGk9al8/9TJvUPq5sX3T+V+At4/BQ4ODg5ufv/UV32HVM94pNfzXPT+qVyxBxiSh8SSz79Rapas+SWFJfUbEbi0gXYe5UoODavfKNqfyL8BBwcHB6/nyfgSecN4ZCx3Ldh2ucQVdfvf2CtXVYmh+JTWHaU1Sy8dHBwcHPzPcgrJpnk/G8fxaAka4gd7XNG7/41UWFtw47XmR3UapbJrkFIOjYuulAsd+v+3d25bkoJIFCXXmv/CT6/+MuchpxwKIoIAQUlz76foIx7wUhItJKKjoz9eT9HK23NorumPZvS/NkOSGKvGvSDq69+kwUFWshQ1W8+mbkIIcdz6N616ZP0bYmJiYuIJ69/4da2M4TOKao8vZhp2XiFmF5rb3rH+zTtR0sbGtInJt7PvuxhrmW+5b5PO/BtiYmJiYn98vt8xdDu+nmvm+I5f/0bzsSuaR9NYKXNuiImJiYkHxilamRXmgF7JkOku1ZcpPevfjGqczagxP/8Y5MCxz6Z60dHR0dGfqqdc3x/1tXPenBsNw6E/r9gLjNGs6thYuWMs5u5oNY4lNM6/iUPHPiPzb4iJiYmJ3fNvUn1sf2S3MysziqYev0wesrzCKGlUx/o3MYwb4yzPg1bvzvwbYmJiYuIiHtgfOeu9l7T9R7c4JK9g/ZthY5zMxSEmJiYmzuIUrQzr3zj1wPo3qZ5mqeIY5Kg5NyfHPtHR0dHRn6enaOXTkYS7+qMZ/a/NkCTGqPFVXoaySu01kUHZOONIZrzpeTV+fyqNt8bvfWzSt6t++P4UMTEx8dfHm+/7U6H2TcO3LsY/5rer7HZuN31/Ssw0PM5ifiJW17b+Tbr/4sNSGenFS2Mt801P9DsRKZM8Y+7OxvwbYmJiYmJ3bM+hSfsdsT86yos+dnw9Yp6gpSlaeUN/M379m6a5OxfwahkrzcYstTHR6lgpMTExMTFxhlbGM4dmdn90JaPyCvtlSs/6N8MbodU+RPePQZZjlkfs1NOMe7UxYHR0dHT06/WUef1RWf5MO0f1v36m5BV7QdTXvzmjawXsTd2EEOK59W/iL0499Ymsf0NMTExMfHr9m6NP6e6P7HZmZUbR1OOfzzfEkvL7m3vf3Mxg33cxTjPfTH+3/K1vv6S6lnFrda0Wp6zQHmJiYmLivv5I9HHWey/z8oq29W8+MbmpjjtqY5atY5zMxSEmJiYmzuIUrUxr/zKjP7qFqXnF2fVv1pxzk+pZFlzq2phl65ybk2Of6Ojo6OjP01O08ulIwl390Yz+12bgSJFcwV4wY2zMKGxv6iY0zr9J4/NjnJH5N8TExMTE7vk3Tf1LWj7W5u7Y7czKjKLa4w/JK2y3tvVvzuj3su+7GGuZ73t08yjzw/o3xMTExMTT4rIfCV+2/s1A/Q3r3/yJnWOcrH9DTExMTOyJU7QyrH8TJrxMeZVJXJoYDmyE0RRx08naX78fQPC3KlWyhEzMlwEAAC6m7I/Snivt7zy9efj7XYhsx7K8U7+4xxeLqfmN1gKxuRlN59fe1M2r8ftTm/QNqXdc/f5U6RP5/hQxMTExsfv7Uz/6N6RCQkd/ZLdzu+n7U6XiTzCc6ZQ8/8ZoWfkOw3i3MSNx6SO9eGlszKER9TfV8hvzb4iJiYmJ2+Osf9HezRwY/ZGz3nsRj2tIXtG2/o2/cU2NmMqrNu64Na4fkJ2HanliYmJi4q+NU7Qy3evZtOrOdsz9KB4AABQnSURBVF5GR/7gzyvOrn+jVdaX3BgpVLeeZqmedQXSDFrT07rs8ka96Ojo6OiP11O08ulIwqh+qrWdM/pfmyFJjFXjXlD+jvxQ0uAgK1mKmq1nUzdh6Po3mR719Qayqo26PGWmxt3nh5iYmJjYGcfT69+Iz+pqP2WUMXxGUe3xxUzDzivE7EJz2zvWv9n+ztYOf1MnY4zwXvZ9F2Mt8y33bdKZf0NMTExM7I+N/qUckWjtp+z4eq6Z4zt+/RvNx65oHk1jpc6xzAPm3BATExMTG3GKVuauOTdaO2czZLpL9WWKld90jI0tOBfHPwbpH8s8atTKN9WLjo6Ojv5UPWVGf2Trfe2cN+dGw3Dozite6aGmu4k7Hy0oR6wOvRzPOl4raa2ZMaT1cq9/c1xgY12BjviH9W+IiYmJvz7efOvfBL1PSenoj+x2biutf3PoWV5hlDSqY/2b+hrHHfrG/BtiYmJiYnecdu3V7r/cKurONtyLmNYMyStY/6Z5LDM7D9XyxMTExMRfG6doZVj/xqmHlp+Ov8okThuZ0vKpcqzK//oo2zTwPUo6SGSUt192detaLggAAJCR9oAD+6MgZQNZ+e13fGrsOEZHj2/nFeKmtIBQ3V6g/b58L36GbuCx9WzqJty6/o1Hj8X6N30+3Xp6Wa+sFx0dHf179Hi6v4jft/6NgdNt33fhqGKxtE5T61t1e1M34W9+46/a034tzsqLm2KSVbTWO1Y3bgt0dHR09CG6FqeK7aPtVW2PViwrc31+M/w8iwUq+c3ARthHq23q5shv7Ow1KxN9mXV6To3yR7FqZu2sd6z+vihr/o8HHR0d/Rl6NPsLz3M49r4BikUfVMbZXqOI7T3+GV0sIxxVNBOibr31aE/Wflxaf6u08nZJo3y2KSufBZ560dHR0dE/S0+VPh/Nrepz/LMsf+hRym+M8k5dK6ltOlmjWEzNb84fXqa3Hu1JQuP8m9iSoZf3hFhei/e/6ddd/8MQz8+N7UFHR0d/nv5+2J7xiUk3OqSdRplRxJYeXyvs18WSwlG9L8bJykq96WjPE1rm38w43v3vTSkWnlSvU59xk6Gjo6Oj+3XPc1grWfXXNmXF7s1vhpxPUZTzm/OVlbr/aIcQ3PNvYntGnDbYKH/clOv8TyLVs/Nze3vQ0dHRn6dHs7/wPIffJh3tOaoWy+y//VSqjCL6enyt2BBdOCqx3PnKPEc78FCD9P5GUybpx50tls/u+wvak+nlTXZve9DR0dG/TU+3DvcvN5Xl499Mq1reqWtb000DaxQ3udb3G7Lsj2e1n4G83N+fKuNjecC3Xv2ux/b3+x0v5bsek/y7fdJFlqo+P8n3U8T2bOb3Uy728ZyTWHz/6xk+nvtwHZ/We/gjfJz38DU+/nvv/HNmlM9HPD+v7C9CQtPzUPM06h1Ftce/YDnBen4zthGlbm/qJn34ro+49nF1Tedjxz6f47bw+Bz7Vq/vCj5pGcOnep8v5ZP9GYs+2l63+ATf2qnleVjcx75v011W8LH/jlLW8akeV1bpp/gsy/X5TWj8KrjnPhcKiK96xFgr49Q9b6sGchxa0Mcdj6qDNCYafwe5jvgokyL6H/sauuEffHN3Tvqkx1j1KWPxvOEzz0e7vqkelfv5Fp+o3P+pj3YeVvbJzsPiPlr5j/ZJr+mn+IjXdy/+jkr/1FPzL+P99/7JPMU4VUYR23v8M7pYRv6+5pvuTMqp22hpb6sek7c4e5Kilvq7nal+xJl+kOmaT6v/O57to5W/qz0DfcLf66v5VK/XUj7aecBnNR/7vl3QJ5x7Hg73We38XPwcHu4fpOtS6imj+l8/U/IKLScSs6HoQ8ywRMPqpm6yo6vGUcp83zj10seOR/l3+6SX5nx74u//+Ffwicn/WgyfXfkf1bI+HefzRh8t/mif2P5m614f43479Nj1ZmueT3Yevsqn1ONfhvgb8ShiS48fkwnRVQyHDDm/0VoWkx5RrCzbV4s9LTuJ84LZJ8s+3uopTnfP9Kq/eE7G+pRXrXp9jfYY98P1Plr5WPBBPmXJvvNzpU92Hkqf0mp9n+w8iD5ZvTf6ZAeu+Yj13uJT7qUpH+SjnQqPv3iexfNf+mibMu7Nb6rHFQuc1cnjU9rrILHw2GGp4bxeLzvetu3fv39V/Yiz89Dq4/H/RB+t/LI+WfwYn9XOMz73+gTlHmt9Pqzms8hzb7bPcH8jvoWtPX/w5xXW/JszlRnl7VqG63ttDLJjDD6ta2+cc+Px/0QfrfyyPkG6Hx7gs9R59v9d4DPJJyj3WNPzYTUf7Tx8us8F7QzSc+bNjP7XZkgSY9Xoec8Tk9dE4nuktGQpGq+Pqpu6yY6uKY61Mc53g43yrXrmn5WZ5JNezfPHm9V7r095Hkr9OPyH+WTnc3Gf49if5BN/788VfGJyXxk+e+05c6VPdh6q+vo+Wuz0j0kX2fQ81DyNeBSx1uOXBWKCpot7adW1rX9zZEk/59Z18G/qJl3IyKCsehu3LkJQ1ts4drT9f4yf9Y/wSY+06pPeA/b1XcEnLWP4aPf5mj7H9TJ8tL1u8QnK/Z8dZnkeFvex79t0lxV87L+jlHV8qseVVfoRPsc/7b+j0r8US//0nsnuZ9E2w9ldNmFUbfwxhuREHXp2vOIBitVVxqc8f4Rl+/z6BXjGHVvHOA+2OWOoHzfGv5pPWGyuwCifk+cTn2t8br//W32y+Haf1c7PxT4znoerzb/RUp/WfMPO3nrWvxnVOJuN9W8m+2jl72rPQJ/w9/pqPtXrtZSPdh7wWc3Hvm8X9AnnnofDfVY7Pxc/h4f7B+m6lHrKqP7Xj+Hw05tXqPlNX1Iy0Efby6+/M9O3Xmasb73MfDP9Hb9P/bZt5f/IM//Mp6qP8u/wSc9b1ad6XGK9+Iz10a7voWv38y0+4nloum/xucanLL+4z6jn82o+mp7S9Nw4YlsvGaU72RrzBG95ce6POFUnncITE0q9LK9N/6lu6kY8NK3q6vH26elpmeF/Ui+3rtlOdHR09KfqnuewVrLqr23KcHaXTRhVZ5uOf8YETdcOShTl/EZrk1afVsZja2/q5rhg6ZUr43eDxTKGnjbYKH9cpFb/a/Q4+ldg6Ojo6OhNuuc5HGPs84/FrzLFOFVGEX09fizyh4OqXq1OOCqxXPztqj2IJp6jbWq6rYsXTGvVJL16Nu7Vsxvo9vago6Ojf5uebh3uX24Sy6eZlqe8R9e2ppuyMtGHaCjqDUmAp6She452ICEEO2M14vgdbz7Sm2yF9qCjo6Ojl3pMusgmH62MEY8i1np8rUCfLm4VjioWKdXARrRu6sZ5wcqqPe3X4qy8uGn2+fTrM24ydHR0dPSxz2Ftr6q/Vizj+vxm+PkUC1Tym4GNsI9W29TNccHsjDV2vYlJz6lR/ii2wv8AxGNfqj3o6Ojo36Z7nsOxd8QgFn2QGKfKKGJ7j39GF8sIRxXNhKhbbz3ak7Wnl9zZKq2ddkmjfLbJ74+Ojo6Ojl5ubfI5/lmWT/Uyv7HLe3StpLbpZI1iMfX7DNrvy7t14wfrrb999/D+cf9xdOn601kcY3zH//79+6o4ZYX2EBMTExOXcUqHj6cfLDOBkzT1+OfzDbHkf5paNkq/hvSCeWI/9x7XKJ5xFAAAz2bUs/p83zeDeXmFvH7xA5Kbg9ZvcLR+p2OGPzExMTEx8ZXxLUzNKyrf17ymEelew/U0S01f953RU2b4o6Ojo6OjX6nP6H9tBo4UyRWUU3Kie6JQk64Vtjd1kx3d2DgWc7I+MU5P+wrtISYmJiYu4yuf1aOo9vhD8grbrf7+5kOHpUII+74TG3HKCu0hJiYmJi7jlNn+13DNHN9KfjP99dF8Zo9TrjBuSkxMTExMfCa+kmvm+Mq/n9J2TtMUY+xN/OFWa4oz6lBnjFnO9kdHR0dHR79ST7l+3OadIXjm9FRXnPk/e4ExmhV/EUVxx+OfzL9ZLWb+DTExMfH68SPn35RKqmd5hVHSqK5t/ZuQpE6pcpTPkq/PWv/m2+KUFdpDTExMTFzGKbP9ryfNE44UYkhe0bb+TbVxfY2YyuxxyhXGTYmJiYmJic/Et9CRP1y3/o1WGevfoKOjo6Ojf4q+zvo3oSWJMWpUvz8lKuL7orRw+nKpauvZ1M07LT2O7uX47oY/vvHnYAAA8G0cXeTYvqyMR1Ht8e0fMIl5RbnJcAv276fEVr5r0sbGtGru4pEv9EYRY/z379/drQAAgAoP68uumeNbyW86fiSm+dgVDWedyVPLsm0bZwkAAC5myHSX6ssUa/5Nx9jY4nNx0NHR0dHR0a/R/RgO3XmFOv9G3PlogTY2Vu64FXN3+hoKw+G0AwDADJp6/DLryPIKo6RR3ZPXvwEAAICVEdOaIXnF89e/AQAAgAXpyB/8eUXz+jfbtpWJzvaLp3F2Lejo6Ojo6OgP08WSRp6w/eLxkTfsBc4vO7TqF39/Cqpw2gEAYAbVHn9IXmG71d/faBlWqw4AAAAwKq+w841KfjOwEXZFAAAA8A1ckNyEvvVvrnmjs9rYITo6Ojo6Orpf97PNyCuuGRszCtibYB6cdgAAmEFTj38+32iYfzMqk3JlWAAAAPCVzMsr5PyG5AYAAACmMjWvqP9+6oJGpHuho6Ojo6OjP0wXS879AdM1Y2NGYXsTzIPTDgAAM2D9GwAAAPguBr65Yf0bAAAAWIIV17/ZfknjlCClMn1vdFYbO0RHR0dHR0f36362Wl6R/jP48orXvu9lNT/Jp8nFY0g3pQdW7nj802iNp6EwHE47AADMoKnHL7OOLK8wShrV/ae1ZUeykippEuP0AQAAgC9HTGuG5BXy+FTTHBqtMpIbAAAA0OjIH65b/0arrC+5WW3sEB0dHR0dHf28LpY8n8QYNarzb0Rlk94XiXNxxLk7zL9ZCk47AADMoNrji5nGEWtzfEORXWhuQZt/Y7TyXZM2NqZVAwAAABCumuNbGZ/SdjZ0zceuCAAAAL6BIdNdqi9TrPymY2yMuTjo6Ojo6OjoTRgO3XkF6998L5x2AACYQVOPX2YdWV5hlDSqW2X9m/PZH3TAaQcAgBsR05oheYWc37TOrTk5LMVbBAAAgG+jI3/wJwz130+llW3bJmY5pcjYBwAAAGjYeYJ/eEEr6cpvjkZ4RrwMHQAAAKDME+ypurYupjiV34d3V1a1BQAAgC9kVF5h5xvj179pmrsDAAAAX8UFyU3oW/+GNzoAAAAwihl5hZrfkNwAAADAbCblFXJ+Q3IDAAAAs5mXV7Stf9OnH5NvmIUDAADw5aTpwcSXJntBnMbbvKwRHR0dHR0d/Rv0OIeyXjm/GX4wQ3zQ0dHR0dHRP12PMY71F7fW85vzjTCqR0dHR0dHR0c/o4sFKvnNkEbEGG8/eHR0dHR0dPQVdHHTGX+xjJXfLHhS0NHR0dHR0T9aL7ee9BeLqfnNwIMRN6150tHR0dHR0dGn6lmB8/5iSfX3UycrS3VnU9DR0dHR0dEfr2txt78ovvZ99//u3Pmb8+x37Zlh+k+np3N9nRV8/EfU8TXUu3w8DsHx9dcrfdJ77DE+2t9Rd2Om+vT9dS/u0/3IutGnuo7IkOfwKJ+lnuejfJZ6njt9pj7P09M7/D48kNf303YWL7n4x2af3GqjNf+P8Mnunu7zs47PqOu+lE+6y0f4pOKZ+3Ypn+yJ9gyfzOReH5EH+FSfe6v5rPM8H+Uz5Dk86v4R9cr3w6uNaCrf6jOqPQv6jDo/S/mMuu74dPv4TS7waQUffL7ch+d5B4ZP/f1NtvP2+x9NLXfrztREn/JRK/pU23Olz1FS8wkSi/uMuu7X+JTlRf3Y5TE+27Zp5/N6nyD9H/HTfYL5vMJniE/1+ZCZfITPUVLzCRI3+hjPh/SfwXF+xCbNvg9D9f2N8yBTvcknNGaa6MvqpXijTxh0X63mg367XooP8Anc5+h/9VIc6yPqYdx9+MbKb1pv4lZ91EF21IvPs31EHuCz2nke4vPpnfEDfESTu3y08vg822fg/XOg5jeenT20ZoKt7TFOyi0+reCDz5f7dD+8Vvbp/h8nPn6TD/Jp5dt8Rt0/GfL8m2qmtrWMjZW3SOp/bK36aO3ctq2pPVN9jh2f5BNWGpv/Wh/776ha7y0+R0nNJ0gs7pP+WdnXfQWfsryoH7vc7rNt28m/owV9wojn8Go+YdBzb9T9UyK/vzFOit049EfqpfgAn/D5wwroa+qleKNPWOz+HOWDfrteihfUG1qmAVTmF3dXNrDRj/T59IfLA3xEk0/30crj87U+Ig/wWe08f8pz76N9NLTnpyu/MRrRVL7VZ1R7FvQZdX6W8hl13fHp9vGbXODTCj74fLkPz/MODB/Wvxnvc5TUfILE4j6jrvs1PmV5UT92eYzPtm3a+bzeJxQ32AN8wkfN2fpQn+rzITP5CJ+jpOYTJG70MZ4P6T+D4/yITZp9H4YQKt+fEg+mSnkeS9FvmDWg9Olo1Tyf7lO0sk+fyb0+1T/O7sas7OM0ucbHf0T2w3QpH49DSJ7RK/hoz/M1fZZ6no/yWep57vSZ+jw3dL/hpucq/8P4DucKXxlFR0dHR0dHf5Jebj3pLxZT85uBByNuWvOko6Ojo6Ojo0/VswLn/cWScn4z9mCcTUFHR0dHR0d/vK7F3f6iaI1PjdKzAiucXHR0dHR0dPRb9OOfU+v15jdnKtPiUf7o6Ojo6Ojon6K/lYH+4iZXfnOyEcc/1zm56Ojo6Ojo6LfoMcax/uLWen5zvhFG9ejo6Ojo6OjoZ3SxgLz+jec36AAAAAArUK5/I+Q3AAAAAB+N9/uaAAAAAJ8C+Q0AAAA8DfIbAAAAeBrkNwAAAPA0yG8AAADgaZDfAAAAwNMgvwEAAICn8V/RdR8ZWoA2TAAAAABJRU5ErkJggg=="/>
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YOtlwNIV8j/QC+Dr00PM6DeO4O4jPloXGdTL5afAL58nrT5ncUz+M6Dr5Gv8eWg2LLEbHRX1lZ0eIiNDfFSN84hzXmojWbzUuXLt29e/eTTz6B3RaDwQBOvwX8zMzM5uZmo9G4e/cu4KempuAdqDd8H/EwAm1sbAC8srKyubmJeI0+8jW2H9pOfHP7oF/I221Yv+B+j1F+d7/g7dxI35aLZtNLa7e8X9jqbcu0vmLMEXTUJ7RbSTt02wehnaH9whjTkvQXW+6d3O7BbxWJab3xxht8rW5ycvKtt95yjDsjjWkJ86Wix7RSnlbK0wqIaWXW54YlT8tGk8uD31oeB0XZUp6WREcb/ZSnZesXyhLTksQpJfF7GtNCnydPTMv1qrGcOXOm3W7jOAkw4tXw7JB2uw211mw2lVIwigAeaoHim80m4vEdOOOE4wFWStneQZqU72Aw2BrGLRDfarWi8G02m0b6Rr5IE06mQZqcl02eTL00vEYT+Bp1t+EpfZDHxteoC6eJumuwVs82+hzvoC/XMbM+6/U64IU0Hd9a0j4pXqtb3zYD/QLld/MN7o8aPqxfGGly+o6+b6TP261cR8BzGYR2BvtszjbjaP82vmCTUS9bX3P0Qf5NM+05fgukQ/eZa2MHnALoVQrM02qI86WC80Js79D5qQM2zjvC+GbyQpjPs3znsPC+UEebn+GVp8Xn+0IdbTSFeVqcvk13o46Zc1jfNkN1D/Pt6DvyNkN1D/Z7hN/OWJ/CfsHxkm9nrM9MfX37Ptfdt97C2gz/dqNsM1s58rTc61gOe67FKWmeFq7J5cnTCvG0tHGSjp9KKTr2an4PnxMJ51nuuQ/AT58+9YXl84u4fAHGeZbvHDY/X5vumT5KmO6tVsumeyVrvhmmO+jo9d0lsEN3rqNDHl++vt/dJqe7bUf/7kbYV1+b7r7ySHS3vVOQ7sL1gJx8wW5vOfuafM1JYs+3iP3fGnpa7d1rcnQc8R2DCs/TouO/PO6SOZekc5A8sHzOuMXmXPlloDQ5L5s8OflOT0/jmdm+PkoY33q9Pj4+btQ9c74ZpjvqaJMnLP/fV0ebPL58ue552qEvX8l3l8sj50v7RXH9XdL389d5wDkU2C9y6h49puUbv48e0yo8T2tdlseA8JYsL0T+ji/spunOjwmDA3Ju8sBu+aPXZybN6PV5GHQccZs5DP1i9DqOps18/fXXtr3BANvytCTnSbrzxipDPxXPHlTDfeZ58rRUn5TZ2VnHn/1+v9frra6uzs7Orq6u9vv91dVVwCB+eXkZ8MvLyzs7Ozs7O/T9nZ0dBx5pAh5ocjzSh3d6vd7s7GxvWJaXlxEOxrv55qfP8ZpeWj3E0gvxtvqETxy9PgE/yvpEHY184+pF8bbvGFEvxKd+EUsvirf1i9F/x1j08U9Hv7DheT3s7OwI7fnOzg6nAzXM+6N73NEwz/X7fRzA5ubmbHlaUJ4+faqUQv+OxrQAj6M0PBvDWwE1DMfzJ0QC3O+kZ3qmZ3qmp+PZ6XROnz4d8FuJBbbZc4pRStXrdW2k0EaQ8fFxx7ijDUz7NU8rwQlOcIITnAlfv379X/7lXxzvqP2Wp1VsTKsSej7eVjFr1glOcIITfKhgGtMyvuMb0/I9Z1XFjmkVm6el3TejnQGcJ08rwQlOcIITnAk/fPhweXnZ/U5YnpbbnheXp1XgfVrr6+v0HPdMWDLOJzjBCU5wguXw119//T//8z/ud4xrWsa1Lrk9Rz9MkbMH1XBNrqT3abnH9kw4xbQSnOAEJzgnHDemFQDvp7MHt4bjc578f4rPk4ue4AQnOMGHEFbDswdt75w5cybgbCA5rGKfPahveVdKGXe9w6bDp0+f0nGy3W7DfkqUo9VqLS0tIR7e2RqOvV54oMnxIA/gAU74hE/4hE94I14pBf9yvF+v18fHx6PYbTkex5GnT5++/fbbjnFH2/Kue1q2PC3Ea+MkjFiKnT0ImQF87JXjoTYpHuYFtVpta2vrypUrCC8tLSV8wid8wic8xyul3O9XyNmD3N7mt+eKrM+tra0Zzx7MHHd2FXcqsvFEDJ7bjPDy8jLNqY4L94Y5+ShPghOc4AQn2AHjQUW2d8C0OuxtTrtNqdEnstZOxOBFG5i8By3Ou0fK8vJy3CfVHDBY1+mZnumZnunpfoJVd7yjjS7Lu+2t7b/yJ5CiIwUfQfrOknfQsvlYOFz3C/CxNBhrPMEJTnCCE+yA0ao73jGePVgEbBw79sbT0nzJgp7J00rP9EzP9PR6Jk8rxbQSnOAEJ3jfwCmmlTyt9EzP9EzPffM8XJ6W/D6t/vB+FKgIbbx134sTgMca53ImfMInfMInPOLxT8f78vu0cuKj3KeVPK30TM/0TM8D+zxcnhYvKaaV4AQnOMH7CD54Ma04NxfjE/Oii3jCTZpLS0sff/yx7bm5uemQP5VUUknlsJUrV644bKbb3uZ/KqXq9TqVJ+fNxQctT8u2bpvgBCc4wYcQTnla5hVJLMt7fSIG+sLpmZ7pmZ7pGRzTivVcJjEt27PvLHmXB/F8d3rWO8Iff/yxUgrP9N0i5/vmh3EFcmlpCeQBD5fCoMLHH3/88OFDLw86lVRSSeUglU8//VQpNTc3V61WHTYTDDjcTlKE3abW2zh2KKW8lgf3031aSikYsWBoxDVZIwzfbGJiIj3TMz3TM/qz5BYGLCEY7UybabxPKxasTHdo5blPS18etK0QAp7HtGCvPeLB5VyNscef54Qtk5hWZo7CwsICxSc4wQlOcER4YWFhz2VwwCDesiWmpdlPjGkVkZtlw9OYlnvcKTCmFXclNGdMC79ZeqZneqZn9GfJLQzO2g9eTOug5WnhF9LmQbSFJXzCJ3zC58Qb13LKIycawOA8rVgwtd5909ixl7sHk6eVnumZnofkWXILkzyt/y22PC0e01peXt4ZFiFs86v4GI41zuEU00pwghM8Anhfx7Q0WJ6nJbfnOzs7nE7p8rRsIy3qIMQnTys90zM9S/4suYXJ72nFyrUFgJbyxrS4/2Tzq4xjMofzxLQSnOAEJzgiXPK1nPwxLeNaF7XVDntO8ZSaca2uXJ6Wr3eVPK30TM/03BfPkluYWJ6W20q7V9F4TKtwT4uPYT3LfVqIh4qg4y19n657cjzSpLlfHA+SACMuZ4ppJTjBCR4BXPK1HB7TinKf1s7OjtCeo09W0vu0kqeVnumZnofqWXILc0g9LV4CYlqSdc+9imlhJSY4wQlOsBcMo8JeyeCwgVCKi2lJ4lh9sn5GqfVixLTi3KcF/7Xdp9VoNJrNJjwleHqbS8B9WnA65OLiolJqYmKCv/Pw4UPEU/qA55KMEk/voQE8v58mDG/jG4s+xdj0LUIv3k4OXn2Onq+73Y5Sr9J+xwsXLqysrETpF754St9m3/C/eIZ42H1a+e25Uqper2sjRZ77tL73i1/8Av+4fv367Oys48eDwQA51Wq1q1evAjw5OQn4bre7sLBw79490OH48eMzMzOgiVLq/v37eAYwxZ88eXJ9fR3w8NtKpTI5OfngwQN8/969exsbG5VKpVqtvvrqq3gqrgZfv34dzrK8ceMGfDP+zpdffgnw9PQ00AT63377rSbDiPHT09PQSk6cOIF4gEHOAPz09PSdO3dsfOv1+vj4eB76RrxNX/imUfRCPG8nlG9cvSje9h1Bnrh8ab3Z+MbSC9rMiL9jvV4HeB/1i16v96Mf/UjOF3XMbzcmJydPnTqFdsxo327cuPGrX/0KxrDZ2VmHzex0Osb6p23AaLdt9hzwYP/v3bv36NGjBw8ewHgBIwUdO2q12mAwGBtzHd2uDUzegxaOT8gVxk/AP3r0CDVcX1+/d+/e+vo6jL04Mm1tbWl4HJnxt1tbWzMzM1BriK/X6xsbG1jjH3/8MYcfPnz49ddfv/rqq/jNHO8b+e4hrOk7ApobGxtxdYFvZHuHf9P8sJumW56kY1g7jK6jW/5y9ou///3vjx8/lreTiN8IRgibDQS41+vB6AVW3WEzbbIZ25XEngMe7P/W1pZSan5+HsYLGCno2AEjmdegdajztHr+93XGWps20pfIE2tNHPftlER3CRxL9/PDIodj6e7gNcrvnslrxN/dLVsRugvlcdD0imn59rVM2GEDoRzgPK1iY1q+cSz65Cuqdc+Y1qeffup4072eK5dqlM/yc3e/k0d+22/DOG5vb7/wwgvyJ9DhsPtN3+foazWs5kfZDkvb5m/fvj01NbUnkkssYXExLfp0x7cAVkXHtGwrhHNzc7Ozszym1el0nj17xmNanU7n0qVLiq17njt3zoj/5JNPpqam+Lp5p9NBPI1pzc3NQezKEdOyrfkirK3dozwO2Pd9I2zjmykPj98E8KLr18a17Dy6Z8qPK0u+9WbT3V0nRt0/++wzGCEajca9e/cGg4ED/tvf/vbyyy8DHQ7TdwAGeYw0p6enNzc3HbzCvruwPuXfWmsznH6UdiiULU+bcdAXyuN4p9frXbhwQdIXgJdXX8vsC6dOnbLFqAB2x7So/aQxLW5vAUb8zMwM7j9w2HPA85hWs9l89uwZj2mdO3fOMe5kxLRsnhb8hse0nj17ZoxpTU1Nra+v83XPS5cuGddDYc7C180pnsa0wIsafUwrSvzAtp5eRCyBvx+8zi7RPTPeg3M333qz6e4V7wEYRggHr88++wzfefnll5EOh+GdJ0+e4PsOeRBP6cM729vbg8Eg7LsL26T8WxtjydHboVC2PG3GQV8oj6Nu5TEt4FWqmBa1n1Q2bm81vNCeAx5+q0hM64033jDGtN566y3HuKMNWq7wl7HA2Ej9LbgvGWCl1NZwvEXP8ezZs41GY2trC/aWGPG1Wq0y9C4BhpZK8UqpSqWC8wX0cI0wSIv4xcVF/k69Xr99+7bGF2Ab/sKFC17vG/E2vjZ8o9G4fft2o9FotVpavQEe4LNnz3K+9Xpdk6deryN9hPF9B334dhreq35g76+Gp/Lb9ELdef1AOxF+L9B3e3vbzfeFF16geI0OtEOqF/htDnmADnxfTr/RaPzrv/6rsS9gvTnaFZfHqBfobqtnRzvk9I3yuL9jvV6n9anVD2+HtD4z+0Vm++H0eTs0ykO/u0YfbJ2jPrHeQH7a78LsBq1/ze5x+4ZPpVSmzTTKRr87rXOJPUdbAXRwvKAwjiO+Y9Ao8rTCnimmha0EPULgLllHzs+RU6PcbRzzRF/ceqWYlvy/tCbzxJXdPdHW9mLxdesup5+nX1DuGn2MaXG+7hab/1memJbkqfZRnlYl97ptzjytgxHTevHFF3G9eHJyElY1G5Y8CQlNd0zLkYdx8eJFDU9lC45pNWT5fN99992rr74qyedzyMNjWjMzM3fv3m00Gj/+8Y/v37+PcSbEf/7558aYli0uZYxpAf1XXnkFY1pGvlrMIExH+C6QSULrE3R35NPY2owkpkXjHMbvOD09zdtPnpiW1vbc7SdKTAt2dSN9iGkZ+YJsZY5pBedpBcD7KU9rK3ZuShnytEYf06LrxThy2PIkMDfCQdMd03LkYdTr9YsXL1K89k5m/RjjE8J8PtBd0k4c8vCYlpHvZ599BiNKs9m0xbQoLxqjMsoD8V2Un9IHvhjT0uozQEf4Ljj3R73gHUc+ja3NSGJa2PZs33FjY8OIt7VDd5vhbc/dfi5evCjsg5o8VHeNPsS0jHwBLnNMKzhPKwBWsfO0QjwtbZyk4+etW7cePXoUZXy2ze86nY5jfgGeFnyz1157zTG/gJiW79wnYN+UYx4nwUOvgLkzWD2YF1M89Bbu9xhp0jkmn282Go2xsTEjfdCd4rlvl+kTGH07oG/TC/Bg9TSfIHM+qMkD+m5vb9frdY0+5Xv37l3Ao2yUDteR7v0zyoPz/Wq1Sukj388///yTTz4BOKeOOPJper3yyitAx1bPtjZjW/Pgvp3jO9br9e9973v3iE9ma5OSNuNoJ8Z+gbpLfDsqD9Ud+hfS/9Of/gRnVXC+0C/wt8ArYF3H0Y/ca0g4awer/vXXXzve39zcnJN3FZIAACAASURBVJ+fj7JH1AiDp6WtydFxRClVuKeljZN0/IQRK+c8wj2/c88vwNMC7/i1115zzC+WlpZwf4vXHMd335RjHifB4zwOrB59B+bvMKfmezVtNKn8Rp/ARh911/Dy+oFVcg3PfUQjffDzfOeDmjwADwaDK1eu3L17F/wb8JO2t7fv3r2r4REGOhzG3yIM8mh4oLO5uWnj++TJE/S9cuq4RfweWp/goxvr2d1mbGse9B1je6DfEb+dcD3A3Wa0fuFuP9THzeyDmjxUd+qbnjx58k9/+tN//ud/SvoL9bdi2cZms+lecwJPCyMmDpt59OjRgH25clgpNT8/r63J0bW6mJ4W7JHXBq1r165BblaNxbQ6nc7ExASPadG9/3I8H+ebzebU1BSPadGcgwMZ08Ke8N1339E60dbThXPYzJiWLT6BdGzxg8z6scW0VNY5ZpVhPC9iTMsRx0J8o9H4yU9+gnQgRhUW0/rJT34CeVoOvkp8Dqe7zo3xnnq9/txzzxnrOUpMy/0d0dcRrge420zFErez9YtYMS1Kv9fr/fCHP3TwLVtMy5bb+vHHH6+srHDZwN762m2Ov3XrFo4XNKaF44gW0+Ljjsegxb0u8LQgN4vHtN54441ut4tfaGNjA+CVlRWE5Xg+zgOezxfoPOJAxrQwPqHVibaeHiumZaOPutviB5n1Y4tpSeITcWNa7vjZlStXYEShfp4xzlERx7TukbgO0ke+4G/Jz+F017ktrmPT191mhDEt93l0+O0ixrR43M7WL2LFtGjc7k9/+tMPf/hDSX8pSUzL5m9NTU0ZZQN7y/E8p9aNn5iYMMa0cBzRPC0+7hQY0zpx4sStW7e63W7FdOZxGMznd4cwplXZHdexreMr2b6szJiWjT7dv4d4r/qxxbTA+rjjE7C6FSumBf6TLS4CoxqP59l0lMS0aFyH04d9iRFjWlwv3L+n4fl+xbCYFo338O+I8TzhHld3m7lnidvZ+kWsmBalf+PGjb/+9a82vpUU0xrC0WNacfK08IljbBFP3zwtVcB9WjR3YTT3bDVYnhbHF83XhgdYXj9Ufl++PGtEfp8Wx9PsKMDzrCmKp9lX7vd5npaEPs3TCqs3iqHfRfIdfdsJl4dSi8vX9n2L0EvSfpA+5mlJ+kXcfkrr32bfUp7W/xZbnhbCEfO0bGv3e3uflu/7RryNrxHP87RgfqfYOv5f//pXzpffG4RzTOM9RkDHRr9hykeR1w/EJzR5GsM8LTdfnqclv08L8cY8LaDP40yA5zEtoM9jWlQeDd8w5WlxvrbvKLlPi8d7tPrEPC0Nj75dZvt0yEPjPcbvCO3QuB7gvk+Lx7R4v8hst8b1Bvd9Wsb74RqmPK3MfqHFtPb1fVoBcEnztBCOmKfF4ZSnlfK0jDQDYlpufWkeFaeT8rRSnlYl5WmJYVXOPC2EI+ZpcfjQxrQaKU8r5Wl5xrS4XilPS9IHNXlSnlZ+u13SPC2EI+ZpGecXGylPK+Vp+cwHU55WJeVppTytg5Wnpd9cbLu8GPD83snZ2Vl6ByVehUnx9F7LKHjtLkt6Fyfi4V5Rx32d/dh3icphG18jHu8A3dnZ6fV6CFO88f5QG016Zyu/v9VNn8NeuhvvkBXyQt0l96u67+T10tH3+9ruewUVhHzz6Ki1GYShAiU6ZvYLh442vajutu8ibzM2HW0wp+/W0SYPpbmwsODgy3m570r2bWM2m4Yw3Fy8vLyMJtFoJ/u773DX7C3evzw7O2u8lzkAj/RxHAF831QAX8jNxeXcPXgwTnnfX9zd7+SR3/bb4jja6IyG4+h1lNMfZTssbZs/8DcXx3oqsnvQ9vTaPRjnPi2EFblPC+WOBavDep9WRXavkhFf97xPy0Ffme5t8qof431awnqz3ZsVcJ+W7/eqZN2nJZQnoL0F36fF36+L73OqB92n5dsOhd/FcZ+W/Dty+kJ5HO3ZaOuM9Vbfn/dpRbTbtvEi7D6tmGcPDgaDbrdLz7bID8eKacFOQh7T+uUvf2nkmx8PMh8/fhzlp+vpXnikw+vE/X6Frd0fP37cGNPKpLO1e43b9j7Ug0N+LT4h4UvjKHK8UR4vfW103PXgkCfz+4Z9d8l30b67m68mJ6cfpR3S99312Wq1wurNQV8oj6M9//3vf4dfZX4XqE95/UvagxbT4vYtf0wrFqxITMu4H2IUuwdt92lNTk52u91Tp07hV89zFsZo7tOCOWOs8ztsZ3kI90pl7i8K2M/je/agA5bsfcqU33iOnAS26R5w9qAXX04n+BsF7x/zPXvQCMt1Dzh7MKAdCmXL02Yc9APOHtTegTwtSZspydmDvnlasWCap2Xcc+6bp+W9PIjjZLvdpmcP4m3K7XYbx9g8sBp634gHH1YNvV1YA9RgfCqyTmh7H1YevGSD958+fZoHxpVujb4Nr9WJLy8N32q1kCaFR6A71Hme9mCkKZfBS98w3R3yRNfdC5brrsmZs84lujtko/00ou5CeRw0lVJeuge3PWOdOGygBoMxdLwTVzYOw+hAxwsN9h2DDvt9Wkoprzmj3EcM8MMy5zsBPl+9Xh8fH9fwSNNr7l+o7sL2EOavG3X3gn11HKXucnmEfLV2uIdrD4427At79TWUx0Hzxo0bcKaG5Lvk8bONdTKCPK1YMM3TMvpbyjNPK8TT4mMm4tUw9ph/fOY+kFJqa2sr1vxiaWmp1Wop5s/lh4NptlqtnD4ch91zqPxz2C3THNz9TaPrmPktko5xfbLoOmb6PSXsF2q4f0Hocwf72cb6z7SBynPNKa4N1NqnzcfC9Tm/wjfF2/7sD/O0+F57xGOeVv7cLJ4Lgu87cg5KkqdlzFFIcIITfGDghYWFzHeKsC3BeVqO3NaeKYesiFzbninHF7gb7bkR4xq0eIGPoY1V+JFQ1ihP/OoaBmvc+MSBE7+Z+8m5xJJcwj090zM99+kz08IUYVvkFgZn7WDVHW8WISF9gsB81KDPvrPkHbSMYybCIOKq/9kKfZ+zBlAeDuMXgiZlfAdhbaxFXkKZEeZyYqvKlCHBCU7wfoQz13KMtiUWnCknGkCcx9veXx0eZiThG2AbqfXum8aOwgetAE8LNRHiY3la2Kq0J8VTLoDnkgCey+l+38034RM+4fc1Hj0t9/u4ZojPuHgb3/yeFucY9lwmS6a2EaTvLBE8LT5m4hMqAsek/m5/i47bEn/FNuZjjXM4SkyLypMpf980H8HPkClDghOc4P0IC9dy+sXEyzPldJ89GCynxJ5T+6/RMfpbydOKH9Nyy2+TXMI9PdMzPffp88DHtGzy+9rzZRLT2jNPq+8T01q1rIdq+L5gnN+TmJYbn2JaCU7w4YQlMS15rEgOC21L/piWzTb2Pe0kpWZcqyuXp+XrXZXH0wrzDpOnlZ7peUieh9bTktvJEXlaYfdp8ZjW7Oyscd3TgTeO83tyn1bOddvlFNNKcIIPOryvY1rC+7Q0O99n8X63nXfQWd0d0/K6Tyt5WsnTSs/0TE/vZ/K0lkviabl/HBDTkqx7jiCmRVsY4nu93sLCAue1s7ODeE3+TPzq7piWkW/CJ3zC73e8cS2Hvk9jWtQ+ULu3sLDA7STFazZwYWHBGNPichYX0/KN91NqUWJaz/Vj3FwM/7XdXNxoNJrNJjwleHjWLfelxr25mHPxld8meea9ot4nbqWSSiplKm4LY7MtcnuY08LkvLk4v/x49mB9eHMx1FvOm4tTnpY1psXlNMrft6w7u+XEeZDjnQQnOMGlhfPEtCTxcvDJjLYlf0xLKKfNNgbH+43rc+XaPShZ97TFh/Y2puW7busrpy2bPT3TMz33xTM4piW3h1EsTMrTSnla5nVbTU7jujOFbWvlCU5wgvcFHJynRX0RoZ2hNirTtqB4AKQ8rbR7MM7uweRppWd67utnTk8r/yqUm/sh3T2Y8z4tHG9xLz9d9+R4pLnn92lpcrrhvskvTDGtBCf4YMP587SoPZHg0baExbSi3Kclt+doG9N9Whnzi/1yn1bytNIzPff1M3lawudybE/Le8v7tWvXarUa3pSswXB5c6VSATzseowFA5etra2lpSWQB3ZtUhj3dz58+PDTTz81voNwvV5XZKd+RDmVUrAn1SYn3ZGP+M3NTdcG21RSSWWPChpG7LOLi4uwp1zDIwwJQrBrnNqHs2fPKqVgXzjiG40G/FbDc/jp06du2wIwWBil1NzcHGQB2d4HA87lRHub0x5SavSJY4dSymvL+5jvxztz5gyOUggjXikFUlKJw+B6va7hlVIwYsHQiHkGRhg+m/EdxLdaLaAJ9BcXF43y+OIvXLiAWRRGvg6Zr1y5Uq1W0zM907M8T+ihWp9VSrn7NdgBbh8+/PBDyGei+GazyfEAa3am1WrV63UHX8CjzCinw2Ya5aS2MY89h9EB87S0sePatWu+Y1CBeVp8PdQLNu5dMca0KBwlppUfDotpZe7zSXCCEzx6mK6wIf5w5mnlhI17zsu1ezDFtGxPY0wrc/U5PdMzPUf/RKtCn4c2T2vPY1oF5mlFH6txXER5OBwlTyu/nL2gPC3JnCjBCU7wiGHjvrvDmacVAFNqxrW6vfS0QPO4z9F4WkU83XyTp5We6blfnkV4Wr5eV/K0sMS5T6tPhmuOXyZjbxR835lzAMA+jWll6pXwCZ/wI8YXFNOS5IMabUtv7+7TiojvkZiWe9wpxNPSfMmCnkV4WsVJ6+abPK30TM/98ozraY3GEh4iT8v94/0b0/K6T2t19/03AXhsVV739NhiWtrqa4ITnOCCYKNtkce0JPdp5bQzRjlHdp9WAEyp9coT01pNnlbytNIzPff502ZhkqeV57lcBk+rZ/e3oCKijM8OGGucw/s9puWQ061LghOc4JxwzxIrih7TymlbbHJSOOVp/W9Jnpb86eYb5mnhakZ6pmd6RnzS/uWwKvSZPC3hE0itxvO0vI9xgjOj6PlRFMaTP2q1Gp46FQuGM6LwxCO8MdoI0/NLbO/U6/Ui5KzVanDOikROicxwRiKeOwXndCU4wQmOAtP+Zeyb9Gk868/Wr+Esuui2xSanUeZgORFfr9fPnDkTDIMMcIaTUoqPHcqzPNf3PDCXcuVPekJi9Cd+LTw1iz83Nzer1ap2Iq3jWZy0br4PHz6E0zYpHk/7tf0KasD3G6eSSiruQvuXw6pQfKaFAWrFPYUWJtOqFGcD8ezBer3uGDXOnDkT7cDcubk5jrx27Vqn0zH6W51ORynF5widTsc4d/DFv/322zD+a/OFubm5iPOLKDDO3TLnQY65G+pF/TalFBwGj38inPAJn/ABeG1dhNqTPGs5cArt+Ph4pVKJC2fKZpTTplen0zGuOcWy25ubm7bxAtfnaDGOO7TE8bTwheiziaI9rT2fByVPK5VU9rzQ/uWwKgGe1l6tOR1ST8tYjGMm4HGNOOKcouiYFtCMPg8qNKbF54wJTnCCg+HiYlpx128QHk1MK+JeBNseiL2MacF/48a08ntaSinuzWheDuUCeC5JGN7NN3laqaRSnkL7l8OqGD0td3+PZU+4JXTzTZ7W/xXjmIl4ZYppBY/PfH5RyVrPVWR+gfeKau8gHkcsoA8tg8sTgDfGtKg8ymfupsW0sJslOMEJzg/nXBdx2JlY9oTbRjdfo5w2XWAULGgfNXpa7j3nXuUge1rymFbcmUWKaaWSyv4qtH85rEqKae1XT8sW04qbpzXKmFbc+YVKMa0EJ3j/wCmmlWJa/zfGNhqNZrMpeSZPayl5WqmkskeF9i+HVUmeVoBVV0V7WrY98og37rVXLKbV6XQajYZSqlKpgPRjY2ONRuPcuXNGPN/jD+9QPI1p2XIOlOf8gvtztVqt0WjAtzl79mwmbJwHBedpGfWq1+uIp91MlSDHJeETfr/jaf/S+qkjZwt/buvjRtsSy3dx8JXISfXaIjEtzQ7j2RaQywVws9ms1+uDwaBer587dw5hjof3QQAYHYw5vkow7tAyCk/LNkpLZhN75WnZ5JTInzytVFLZX4X2L4dVCfC09jwTNNjTkniKbjvJPS2o7fLGtFAf9EvArwIfS+KvGH2vsPnF4uIif6der1+4cIHPZRqNxocffsjlrFQqNvzt27epnBjTMvL1nbulmFaCE1wcHDGmpfV3tPtgZ3hOZwAeRywHX/o0yqnBxpiWMsXkJPYc1894TEuV5+xB+K9t92CY11KemJZkNpE8rVRS2b+F9i+HVQnwtNy2Jey5t56Wrz1XsT0t70GLjpPtdlvjDVXZbrdBh7GxscFgAJoopa5evYrjNsUrpUBPoAnv0BN4KR78OeN8h6qwuLiI+Qq2958+fYr+HKUPsnE5jfKPjY3R3wJcr9fhM9jkhBav4efm5qBvGOVcWloCgHYzB9xutwEDUiU4wYcKVoI+AjDtX+Pj47zPUruP+IcPH0IXtvVxGLfGx8e5fcgDg19olJPCOKZubm6CSYwip8SeA95oG/nYUavVoNqVveRdHsTxiY5YiFdKoZTNZrPdbuPYq4Yrh1tbWxoeR2b8LYzP9H34WoDHOQKH8alI07S9D6vDGl+QzSinUX7ttzhDEcpJ8TaZcVZFPwT90whDvx3xEyK6e8U9Pffjs4g2A6NXZh8BmPYvR5/VYPy57R2wA9w+5IQzbYuvnEDTaMeMtjHTnlP7DxYbxwsK4ziiPEuIp1Wzj5lQEdxfQd8L6HC80V+x+V6O+QXOiYTzIEVWNSVyaniuI8iphiONTU66toB425yI+m1KPH88ceIESPXVV1+h75UThjmp450vv/wSOlVcvsHylIRm2eQplY5FtBk1HMAk/SVzXYQaRsRnruVAMMW4lpMHRr/QxhdgXMuxrd8gDAacy2lc66K2WmgnKTX6xLFDDe82s5UInpY2TtLxUw1jdzj20rEa/SqOl4zzSqmt4T1VKvf8Ymm4r4HPZRxyanibjxh37oZzKxhlsde5YZzDnjhxApD5YZDE8c4PfvCDWLyiyFMSmmWTZ8Q6utthEW1GkZLZX2j/MvZN+sxcF6EwxoQi+luwPpRpT6iCYXIqi22U20mkw9fk6DiifIvjVmPtz36/D7cjz87Orq6u9vt97dZkvJQablne2dnZ2dmh7+/s7DjwSBPwQJPjQRJgxOVEGG+b5u8jjPdJo8xGOR34nZ0d7bd4U7WDb394V7eGxwrUdMHbtQGgl39D6bNLwZeXl48dO4bvHzt2jOLx/fLje73egZcHPlN56j+6PHvSDpct/YLjaf/q77Yny+zGesRjF1622xkgyO3DzrBkwkbbAmQdfPtDCwNqAp7rhXijnNTOLxMbKLTnaBv5eKHh0VpyOY0Yl6dlXCo8c+bM6dOnjTGt06dPq90xLRirT58+bVz3pHg6ngOej/Nra2vGmBasB4bNL2Kt2xYR00K9tJhWtVpVpjmjhsc5bLVaNc5Ji8DTOXUU+q1Wa5Ty74k8mt+z5/pGl8fdDtfW1qLr1SYxrcz+oq2LUHtSREwLbMjVq1d5XJ/jI8a0bHqdPn3aKCfYW24bJfacxvur1aoxpoXjiNpd3CEqNYKYlmTds4QxLd9121qKaaWYVtIxxbQIbItpnT17ltsNhz2plSymZZTTEe/fZzEtYXyooJjW4uKi8R3EazGtxcVF47rthx9+aJQf8Hwt+MKFC8aYlk0eY0ui+OgxLcjmlsOK+BmUDod5fCKYlwR2yFOcjhF5HRId88S0wupTkZLZX3LGtGz9GuwAtw9ue0LxAKNd0mJabvtGFYwb01Ke8X41ypgWLzSC1WcxLVwapvEeSXxIi2kBzGNaCDvWcyPGtITxrX5hMS1NTgTourwDxlgCXfdHGOQ/duwYAEY8wn0WP5DDDvpGvEZHi6/E5au9I4GN8tC6EuobRUfhd4ylY/B3dLTD4vRaFvSRZVNMa5n1wYJiWplx9LgxrQA5o8f7+djRZzEtXjxiWsaS8rSM67blzNNyzGFB/lqt9tJLL9nwoLXXfJzPqR30jfhYPoGEr/aOBDbKA3Ul4Rvd7xHyjaJj8Hd0+1JGPyynXu0S52kJ4+U2XyflaYV4Wo4xEyYvNl/KAUvGefS9HPMLnBMJ50FGf04os8NHxLmbTQacB1G8bU5E/Tb5/PHYsWPGeahxLiz0qzJ9Atuc2kZfw/v6dpk+gZCvl44S2MHXl2amb1fEd7S1GQlfXx0lfpivvtD4oWT2l8x1EeO+u8y1HLQDmn2gvojRhjhsS5/4hW6Z0QDa1m8QxkUyyVpXgG2k1IxrdaPwtHxjWrAfxg0XEdPKfMeRpyWRGWEuZ5nztIxzYeorhMVXlDOmZaOv4X19u0yfQMjXS0d33CWTr5Bmpo5CvaLoiN9FwpfrmD9Py82Xv69IKTqmxd8Xxork8SFjTMvBt9CYlq9tVEXHtGzOFuD5OElzqmhMy7jH3wvPc8Lw/b4z5wAnGpnzEVtMKz8cHNMy6gW5QX1TTMuRg2KcwwJemwvv7Oy48X02/5XjYc7lxXc5Us5QHr5e8uSsz+DcLwlfgKPkogXXp60dOuTR/O+A9rksyGVcHrpE2L+0fgr46DEt3/hQ9JiWZmdQzvx2W46nMS33uJPhadm2vCNeGydhr71iMS3cs6+N1XK82r33X4tp2XIOfOcXxnXbnHCemJZRr1arhXgs8KcjB8U4hwU8jxNcvnzZiPfNleE5NzAXttE34lW+nCHqtwXz9ZJHXp+A536Pbz3L9QI4Si6asD6pP+Ruh9wPQzz1n3zrUw0vezT2C46n/Uvrp46cLfx5QEzLNz4UPaZF9aIxLW5v89tzRdbn1tbWjDGtzHGHlgLztGx5BsFwnjwtY14U3Kc1NTXFed2+fTsYT/O0jHz3Nk8L8ifa7fadO3eUUgDTd2z4WHlaAXxtsFGenPSDc5gkfO/cuQPGKL+OSKeI72hrM0J9vXS0tRmhXkbZFFkkHGWeFu3XNE+L2geap4V4Lc/JYWdWVlZ4nha3JwXlaQXAlFrZ87Ty+ysRY1r05hvEt1qtlZUVowzYYgLwisS0jHx9527RY1rtdht9IIBxz5UDD3NwildkbqucMS3ue3nxtcEB8R4JTYkMXEd5vMdXR2NdCfWleF8dEdbqLZOvVj+0HXL60Gbk7UESB1WkZPaXiDEtrb9jrEizDxivQrwWx8KRjNsZY0yL2xmqYMSYVgCsSpunhVtlNCAPbFsLdqzn7veYlkPO/oHI0zo23NNo46vRMe5zw71hcr5GfYvYy+fge8yyn9NrL5+mu4RvLB29+Grt0Ka7DTbSxz8lei2nPC17TEsoZ3SYjx39vcrTwnuU4QnjdqvVygkbfS/HfCFgfgE0nz59ivSjwAc+T8vmc2TmadVqtfx5Wqis2+/J1DdsL5/b53DwRd0lOtpgAPYqT4v6Xl55WrXhTVeSNmOjr4a+SKZe7ZSnJZbTK08rAFb76D6t4DVQG1zE2YPR7xWtyM4H28OYlhHvG+9RQyPSLj4+ETHeg7rniffYdC8i3hMxbke/e3BMSykFKjj4xopp5dFXkQF+lDEtCmeePaidv2qEA2wLwAc4pvW9X/ziF/jH9evXZ2dnHT8eDAaTk5NXr15F3hr86NEjkPLevXsocSx4ZmZmY2MDmtqrr76K8wUKP3z48Ouvv15aWrpx48Zrr71mfAfhZrNZhJz37t3LlLPX63355ZcaHurfKCfA9Xq92+3eunULv4gDrlar9Xr9yZMn7733Hmyaqlar7733Hsz3Hz9+DPjXX3/9yJEj77///uPHjwGmeA1+8uQJ0Nnc3KQ0Ef7ggw80PPAC+pQvvKPxlchQrVZhvk/l0Whq9JEvGDLOV9PRxtemu00vI177raTOue7u+qR4rrtbRyP8+PFj1D2TL9fR2A6RPrQZtwxAH7+7xpe3AfxG7j4CQLfbxf6FfY32QbAqGv7GjRu/+tWvHH18ZmYGY0XUPty/f399fb1Sqayvr2fCRttik5PCYGFeffXV69evw/zY9v7Ro0c3NjZs9ja/PVRKzc/PY0xrcnJSGzsmJyfHxlxrftrA5Bq05ubmtDFsMBhcu3at0+k8e/asVqshV4A7nc7ExMTCwgJKXKvV7t271+l0pqamAM6DbzabU1NT1WoVa1wp9eqrr87NzcGcAr+QUurGjRswKgCevo/w9PQ0fBXOKydcr9fHxsZsfLHFa/jr16/DiKvpNT093Ww2l5aWBoNBt9vd3NyEKR72OoA1fLvdfuedd7rdrlLq5s2bV65cgZGs3W6/++67f/7znwH/5ptvfv/73z9y5Ei73Qb4m2++ceApHYA5fYp/9913T548CRbn3XffBYsG7z///PNyvm+++eY333wD9NVw77JbnpmZGeSL+lK8kC/ir1y5Mj093e12HfXp4AsjB9B5/vnn5XxBd6ADusv5AszrJ+C7Z9anhsf6eeedd2BkCvvub775JtDXvjvyNbZDW7/geNq/Tp06Re0JzibpugiOCq+99pqjjzebzXq9fuLEiei2RSl16tQpG1+AcUx9+PDh7OysZie191dWVricYG/z2+1bt27heAEjFo4XgB8MBnTQ4uOOx6DFvS7wtJ49e8Z9rDNnzjx79uzRo0d8vIWdMPnxKysrGxsbfL5A5xE4J8qcB0GrKsgvNMppnAdRvDYnQhh6FMzdut3uxMSEMs0ZNTz6PRMTE0Zf5NKlS48fP/7oo4+OHDkC81mAf/aznyHM8Zqvo9Gnc2rAa3PwWq0GfN977z0vvh999JE2j+Z6AYz0tbk/xwv5Ih58lJs3b/L5voQv9XG9+ILuoC/o7taL4rnfA3QCvjv6OkJ9qf9dq9Xwe/l+d6QPunO+vB222+1qtWrsF7y/dLtd7F/NZpP7Jbh+Q/GZazkQ0yrCtoCcwrUcXL+x+VtTU1MbGxs2e5vfbk9MTMzPz8MYoZTCtTocRzRPi4872sDkvREDxkm6LklhNYwc1mo1Yq/d3AAAIABJREFUXM2MBSulKpUKzhGg3m0wSOt+ByLA0eWs1WqwJ1Uip0RmmFstDfe+45K0Gwb70m63AY8w4qGhAKyUev311zNhqLH2MHbK6dvwlFcAX4Q1XVAeCS+4Iw1hL75UL18di9Ddl5fWHqLoLuRraydeMvjyoiYrs7/Q/mXsm/RpjCHZ+jXsZYhuW2xyGmUOllMN85fy221tv542dijPcpBjWrhCqL1z/fp1wGsxrevXr3/77becbwD+zp07Dr57HtNSLK7A57lGOCCm5YaFfKmvU82KaTlgqrsXX+7nefEtQndfvnuoO2+HRes+ypgW7df0nd///vd37tyJYk8oHmNaNr6AP6QxLV4gpkXjWBrc7XZ5TCsWDDVYZTEtCtOYFu7t0d7BWJcW04KWwfkG4I0xLRpjk8S0aOyNxrTgWyyxNXoNxphWlcQzOMxjCW7YRkcIa3EdOV8e0wqWIY/u09PTT548OZy6B/OCmNaIdZf0EYC1mBa3Le6Yli12/uWXXxpjWjntDMa0HHyXTDEtm83sdDpGOWF0nJychNErGO52uzMzM5OTk1DhfOzQYlqZg1acPK02yW1uRz3Hj8JF5GkVIWdFkEtBn3xtkMtJ34FC/zTCNdn52efOndvY2IB1GAnsm6elwTWSr+PF99y5c0gHlXXzKkL3zDNBDrDuju/uhrU8rRHo3i5Nntboc0B95axY8rQqMXJtQVpFsnjz52mFeFpGH0spNTk52e12Hz16FGV85vv6JicnHzx40Ol0jPMFbU6UubcHWlX0vT0A49zNJifOgyjeNidCvw3SX4TzRzqvt833fefdP/3pT8HPUJY5r8S3izjf9/V7Dq2vc9h0V8N9hpL+QvuXe/2G4jP3Jw8GgwcPHoAdAzsTEXbwVbvXcmzrNwhvbm7Oz88XtI+6Uqk8evTowYMHjvU5pVThnhb3seBfMJbGGp9Hc59W9HkQwGW+T6u2+2wCrzkvnpWAjPic2ogvaL7vey/UofV19lZ33g6L1l2RktlfirtPq7g1p0x7QhXcwzWnrd1nD9rW5/yKdsRTuk8rClye+7TwHDmAOf6LL7744osvAA+wG0/p99mZb5l88Qy6Xq/nxRcAwNPz92x6SfBCvojvk3P5AvgeO3YM8V58v/jiC6QDPw/TN893z1PPvd1nD/p+d6RzbHicpoSvrV8Yzx4s6D6tgs7x43L6nj24r+/T0pcHbcc4gXcGuwe13Cy6JwTztPLnZsEKIcXX63XMf7Lth/HN0wKacfc6wrpzWJ4WnEHF5QR9IaoJXyQzB6VarX7wwQe4vw5gjg/IVapWqzxXiebKOPjWhnvYPvjgAy++PFfJrZcEH5CrBKuRtVotgG9tmKsEunvlKtF9m8H65vnu8Fv47gF8a7v3Lnp9d6QDukv43rx5szrM08rsL91uF/uXlv8E+OA8rei2BW1jQJ4W1wvgSqWCcsbKqaV4pRTmaRlzfCcnJ9966y3HuBNh9yBfl8Q851u3bsGu9/zroXFjWouLizyGBPdpHT9+nMtw+/btYDzE5KBVGfnu35jWvottHOa4zmHWXe1RTIv2d4hp5bcnHM9jWtzOpJjW/5V0n1YmXpXmPi2VFdtQnjEtpIOMUlwn6V5C3RUpo4xpaf09ij3h+NHcp1XamFacPC1cM4yYpwV+Ffe9quI8LcnZg3i2cdx8sihnD1I5w/K0yjDnPczz/aT7Huou6SMqRp6WrY/jGe3RfZfJycmAswdt79vytGLB4GkZfay9zNNCvNqdpzUYDLaG92+6YeP4bPS9VNQ9M7HujNHkLEmeVhnmvId5vp903yvd2+XI0yrOd4koZ8Wep2WEJfac3rmsLOtzZbxPC+7gARi1BTocD+fC4fhshIu4T0spxe+Mkdxz47jzBkbx/XWfli+shkYkJ50Rw0n3Q6K7IoNcZn8p7j6tKPdRGWEHX4Cj3KelhjN7eD8Mphi1++zBdtB9WgXGtMCy07Ea9hEY8UZ/xeh7xZpfYKyIzymonM1m8+rVqzAy2fBczpLkaSlBTCsMRkY56YTBUeb7SfcDrLsiJbO/FJqnVdDd6Jn2hCoYFtNCvCOndmxsrNVqNRoNI74yPBtIDbN4lWmtTvkWvine9md/mKfF99ojHvO0lpeXd3Z2dnZ26Ps7OzsOvDH3y7jH35FzECVPS5PTgd/Z2eG5CHnytIx69YYJcAAIc1CEOVUjxmOuUh46kPRTKr0keJqrFEyH5qiVRK9yfvdlQS7jMulW/WGeFs+VDM7Twvyn5ag5oGF5Wo7cVqOcxlyrnZ0doT1H22jMzaJ4tJZcTiPG5WkZlwrPnDlz+vRpY0zr9OnTisS0wC/Z2to6ffo09b2MeDrOA14xH2htbc24ngvrgWHzC+O6syanA2/zEaPEtFAvLaYFQWY+Z9TwOPesVqvGOenm5qZxDuuLt9E34mu1Wn6+WA9yvho+j74U78UX1kNy8sWPHlb/h+S7t0lMK7O/aOsi1J7kjGl5xYqEcPDZgza9Tp8+bZQT7C23jRJ7Dnj4bbVa5WtydBxRu4s7RKWU09PihY6TRhgmMnwc1nwpDW/zV4xnZLjnFzgnEs6DuD+nySORn8uJczebDDgPonhj7vrybr/NOGc0wsfI2RPaeQH5YeSlwaPk1WfnUyQd96OORfBCf1TSX3pZ6yJGHyVzLQfliXsuRi/LtqB4KLz7/dXhYUY2eyuxexyPMKXWY2cqQS31nSXjRIzMLe/G+7TU8D5Kep/W+vp6pVJZX18/efIkjL3r6+u4G5LitXut6PkX/IyMJWceuO99WvTOGLy3RpPzd7/73V//+lcuP+CpzADDPToOvh+P9j4tfl5Afth2j9EoedH7tJKOZdbReK9bofWZ7tPqFXOflsSeAx7s/1YB92mF7B7k+wbxCY52m+wJhD2EsNfu6tWruAeG4pVlD55t740S7PPJ3NsD6vA9M7Xd+x4z5Tfue8zcj4R7eyjets8HT+AFAP6buSeq3W5/+eWX8H5J9nQFwKDywZbnwOu4J+1Q0kcApv1rfHyc91nck0zxwv3J4+Pj3D7kgWE3llFOCuP+ZNue5DA5JfYc8EbbaNxzDtWu7CXC7kFhnhasaUriQ7Y9eDxWZIxp5dkzY4tpyeNbfC24PHlavmeu54cz79PyhX3PcS8aLkKeA6+jux1GbzNqd0wLigMu9D6t8sS0bO/Y8rRixfsViWMp0/5z5VlSnlZGnpYbz3Usf55WoXPwEc+pk99THprBcBFtRpGN75n9pbg8LTXcNU7tw9mzZ1VoDij4JW7bAnCUPC2jbURbLbSTlBp91lKelu/8YkmWp+XGlzxPa/R+z4h9u+T3lIemA3a3wyLajCIls78Ul6dly39y533a7A/AsD6UaU+ogsFyGm2j3E4iHb4mV9L7tIx5Tg68ce+KMVegX/B9WnuYp2XUq5fjPi1tv1apcnckeG3v2YGUpze8F6ok9R9dnj1ph8sluE+r58zTktuZKHlaXC8up9He8hwsiT032kZjzlbP8z4t3dOyLQ8iXhsnYa+9YjGt06dPG9c9L1++bMTjHn9tnKd4GtOy5Rz4zi/Klqdl1KvVaiEeC/zpyEExzmFpLkuj0UD48uXLRrxvDtDa2poRb6OfyVfzCSTySOhTvBd9hzzBfFutlm89B9enhL5DnjC+7nZI/bBY33Fzc9PWLzie9i+tnzpytvDnvjEtuk4jtDPRY1pULxrT4vZWw2vxfps9B3ybxbTW1taMMa3McWdX4cOao/T2bZ6WMS+q1+stLCwYcxEQr8mfidfytIx8bfiC8rQQDzDIfOzYMZRfe8eG7zM/g8N8Ti2n7+Brg43y5KSfqWMevQCIomMefX119KLvq6OtzQj1Mr5zbI/ytGi/pnla1D742pM+sYELCwvGPC1uTw5wnlbhMS1t3RPPANbWc4uOaXndp9VsNvE+G01+jq+U+D4tYywBJK/Vai+99BLopb1jw4fFtOT0Ae+mL5FHrleYjhwGOhK+L730kpBmpo4B+gbr6EWf6xgW0xLqZWwzipRRxrS0/o6xIs0+OOwJxfOY1tTUlDGmVcR9WkoQ7zfac8CPLqblHvGM46QxpsXHbV/YOM5jTCtzThQrppUJG+UPjmk55OybYloO2O332Ob+mX6YL+ygb8RrdPL4PZl8I/o9kvr0oimE8/D11TH4O0r87+h6LYvXJGj/MvbZ6DEtaDCZcaydwmJaQjmjw8b1uVF4WvL7tPLAfJwfcZ6Wtp/HBseNaY0sT8s296d4X79HmebUDvpGfES/J5NvRL9HUp8qtm8n/I6xdAz+jgF5Wjn1apc4T0sex1KFxbSC87QCYLWP8rRobkEUeGR5WvnlVCXO0wLPXcPfuXNHKcXxsfK0bPQ1vFE2X3nu3LkDnV/O10tHCezgi7Ll1NFXrzw64neR8PXVUZKn5auvIouEJczTwjMj4P2mLJ+1DHlaATClVvY8rZzj8x7maeX3Ecucp+Ub/6BwcEwrT3yi5PEe5Rm3E9LM1HGUcTuvOGismFaeOKgiJbO/jD5Pyxgfwnds+K0S5GmF2cPRxbR4iIvnTtGY1uzu+7SMe/PleB7Tmh3VfVr54SgxLdRFi2kJc1AwlsBzWWABHfFanIDjkb4xfuDG83hPJl9KJ0/OUB6+XvLkrM/g3C8JXx77Cc5FC65PWzt0yLOzs5Ozfdr6BcdrMS2+V/Bg5Gk5cluNcobZbTee5/j2WUyLjzseMa2c92nheMtzsCR4Ps6P7D6t/D5iSe7Tgjksz7mBuTDitTkyxSsyh5Xk+vCcGz4Hz+RL6efJYcrD10seeX3GzUWT8OV+T3AumrA+ee6UrR0CbMztazabwfWpdse0MvvLiO/T2qs8rSj3aQXY82pp79PCpAScC8CfeWDbfkLH/MKWp2WEgVH0fTIov0POlKflxdcGZ+7lC6CfZ79iJt8i9vIV8R1tbUaor5eOtjYj1Mv4zrES36eF8vP9hBzP4UzbguKh8O73V33ytAJgSs24/9x392Cc+7TgTpRr167BfVobGxsPHjyAu1jywFum+11gjhD3Pi24uwvurQF4eno6GF+2+7S0e4weP34M8Pvvv//48eNGo/H48WP6jg1P73Zy3I2k4eX0Ae+mL5FHrleYjhwGOhK+77//vpBmpo4B+gbr6EWf65h5n5YRL9TL2GbKfJ+W+34+ige4VPdpBcAq9n1a3oMW3fuBXBHudrsLCwsoca1WiwhDDVarVaxxpZQGwxdSSt24cQP39mjvwJdWSk1PT0ME8sSJE/fu3YOWATDwCsbX6/WxsTEbX2zxmmzXr1+HEVfDT09PN5vNpaWlwWDQ7XbhWywtLWGvM8Ltdvudd97pdrvVarXdbl+5cgVGMoBnZmYeP37cbrfffffdP//5z0b8yZMnAdZ+6wU76BvxGp3p6eknT54UxFd7R0LfKA+tK6G+UXQUfsdYOgZ/R0c7LE4vSR8BmPavU6dOcduCdp/ie73ea6+9pvVrrb/X63WwCdSOffvtt7A/8OTJk+vr641G48UXXzx58iSMWBSvlLp//z7YGbSHsBvr1KlTDr4wa4cx9eHDh7Ozsw6b2el0jHKCTctvtx89evTgwQMYI2DE0saOwWDgNWjFydOi+0Dixof4fkJV8J6ZKPC+yNNqt9sYJwBYwyOMcQIjrJz7xHiejZuvRh9W2zP5UliS32OUQQJr8ii2t03CV66jDc6Tp+Wro+17+eZpeenoaCf7PU+rIs4BxVsWo8S0bO9U9lueVoinZfSxAL516xasEMb1sQCenJx88OBBp9Mxzhe0ORHOg2zzC2hVfH4RBca5m01OnAdRvG1OhH4bxGaF88f33nuvVqvxeSjiv/rqK8TfuXMHfQWK12CcgyulqtUqn+fa5tSXL1820tf44jzaIYOXT0D5/vznP0fdHfoiTRtfm+4///nPjfpS/J07d1A2iY42eahvJ+GrffdMHTUYv4tS6vLly26+Nh/IRv/LL7/ENmN7h34vG1/KSw33WUj6C+1f7vUbisfog62PDwYDXGGLa1swT8th33Atx7Z+g/Dm5ub8/DyXE+xtfpnB06JRJG3sUEoV7mm1TT5W9DwtDqsC8rSKkLPdbpc5T6tWq/E8Ht/8HmRknFMrk99jpB+Wp0V9Av4OPXtCo4+658nT4rrL6zN/nhb6H5L6pLKB5EIduV8OdNQwf8jBN26eFqXPfc39mKeV37Yc8jwtfdCam5szvod4Ok5eu3at0+kgDDLVarVKpdLpdGC8rQwzovPjoWbhG8zNzYGVh3pHGJ+KjATaOwiD/2vkmxOG0cXGV3vSEcuoV71eRzwW+BOuYKD/Qjz63TC/BjzMQ2FeA3iA3Xj4LacjwWv0we44+Gp0wN5peJteDr6ZeKFeRnmE9dlut4306/W6vD5B90K/o1GePPWphmNtzvZDv3umXrZ+wfG0f2n91IbXxgPjOzC6jN62SOSkegFNm73Nb7eVUjhGvP3223S8AFgJxh1a4tyn1WYxrbDcLDe+iPu0CvIL98V9WhRP586vv/56Jn5zc9NIx3afFvKl830J31arRfFAB5XN1EuCl+hL5aHzfS++tVrNyLfVaknqXxEfIo++mfXvkMf23d18f/CDH/h+dw3v+93LfJ9W0bZFImfwfVoBdlvFvk/rsMS0FhcXeQypXq//13/91/Hjxzmv27dv58FjTMvId6kcMS2Kf/PNN7///e8fOXLEDf/0pz8Ni2nZYCFfhHPuu6O6P//883K+b7755jfffOOOafnCOXX3hQ+V7jg+SfpLxJgW7e80ppXTnlD8L3/5Sx7T4nYmSkwLM4LywN1ud2ZmZnJyEqo9f0wrWp4WwDBibeXb12+DffO0XnvtNcTjF/14d/4TtgyNV048ymnk+/Ge5mnBjLU6zGt5/fXXjxw58tFHHx05ciQTxvwezIOpynJubLCQL8LwW/B1AvKNqO5efD/66KMqywGS8y1Cd1++e6g7b4dF6z7KPC2Kp/19ZmYGVgg3NjZ++ctfYh4nzekMwANNTU5uZ/LnaUXJtd3Y2FBKzczMaLsw9j5PC7PGut3u/Px8lPGZ713xzdNy7+1RSkFrKMIvNOZpGedBe5Wnleb7Ybrnyana77oH83rnnXc++OCDEesu6SMqRp6WrY/DzvUTLI8zPzw5OWmUU5nWcoLztGLBNE/LuD63N3la8C+IaV27dg1iRa1WKw+sRnif1tOnT5F+FLj8eVoInzt3bmNjA+IHEpjn1lCa7n1iWkzLi++5c+eQDirr5lWE7sY8LSG833V3fHc3rMW0RqB7uxx5WkXEyzNtoK+cFUueVixYCface5U4MS3Mc44Y07LlDcTN01JKoScbcR40MzNTnjyttbW1mZkZ8A/W1tZwzkvxEWNalFcmHCumJeGl6X706NHg+f7a2poX3yi65+GVU3f63YN1z+Pn+fJS5cjTipLnZLSN7jWkKDGtWDDN0zL6W2pPYlpKKcBHjGnBGm6smJbxfTx7MHrsDeduNjlHE9NSwzgTxn7AclF89JgW5ZUJx4ppCflS3fPEdXz5RtEdfgu6B/DNozv97sH65olp+eq+VzEtChdhW9A2GuWMG9OKBSty9qDt3Npog9bc3Jw2hoGn1el0nj17RsdM8LQ6nc7ExAQ/e7DT6UxNTfFx2I3nMa1mszk1NcVjWnNzczgP8o1pYS5C3HlQlJgW6qXFtDY3N+FYRW3OqOFxbquUunnzJl/3Bzyf237zzTcOvI2OEA+WC/BabMPNl8c2vPga8UK+mp8XzFeLacn5gu5ARzEfN0yeA//dbf2C47WYFrUn2vpNQEyrCN8lLKbF9UJ4ZWWFx7TC7DbH37p1SxsvAMZxRItp8XHHY9DiXhd4Ws+ePdPGTKUU4B89esTH26mpKeM47MbzecrKysrGxgafL9B5BM6JMudB0Kq4PxdlHtRqtYTzIIrX5kQIQ4+CuVu3252YmFCmOaOGx7ntxMRE1bTPCvB8bvuzn/3MOOcFPN/H5abP97Ah3osv38PmxdeIF/LV/LybN2/WTHvYMvnWdu/fk/MF3YEO93HD6uFgf/d2u12tVo39gveXbreL/avZbHK/BNdvKD5zLacI24JrOWgTMtdycP3G5m9NTU0Z5Qyz2xw/MTExPz/PfSwcRzRPi487EXYPHryYVvR5UKliWhHztPb1HrbDvH/vsOmuUkzr4Ma04pw9iHi1++xBuKNzMBhkwm3BGcPK8+zBxcVF4zuI1/YoLi4uIkxlAzyXmb5P5bxw4YJxP5JNHpW1zyf47EGVtYdNDc8dOAx72A7z/r3DprsiJbO/5Dx70NavL1y4YLQPNrshx4OcbvtGFcy0mV5nA0nsOcBotzPvBvEqcfK0MGuM3qfVaDTGxsbA58C7YdbX1yuVyvHjxyke7o8x+lXc96oWcJ8W0Md7a0A2lBPvudHkB/zx48e1+UV57tMqw5z3MM/3k+57qLukj6iC79My+h/a/VgBeIhpFX2fFoyOPI/24sWL9Xr9u+++y4ThfXoiRonu00K8IvdpwanMMDLBuhYdtykeRgijX8V9L1VAnpY2p6DyZMpv9BFLkqdVhjnvYZ7vJ933Svd2afK0oueAZtpAXzkr9vu0jHm0jUaj1WqNjY0J8SAAelT587Se6/f7+Mfc3NwVy8GFUJ4+fQpjI3LVYKgIGKsHgwHun8HVQqDD8XAGNo7zRhi4wAoh/RIUBhVgfgEuF38HYVhtA5pCOTU81xHkVMORxibn4uIinbsBfnNzE+qfyzk+Pq6Gnc04yHEYLEW73f7qq68AD7ARf/nyZaXUxsaGG4ZDWaCdgRHh9L1gIV+E8/DSdP/qq6/kfJPu+0t3RQa5zP5C+5exz1LDiPjFxUVcyzH+9unTp2q48mazaQHw06dP3bYFYLAwIHy1WnW8Dwacy4n21marhXaSUqNPHDuUUlD/tqINTAXGtMAXoX4M+lUcbxznjb5XrPkFj2lJ5NTwNh+xJPdpqRTTSr7OodRdkZLZX9J9WvL7tKitzrSTPKalYtynpfqkzM7Ozs7O9k0F8L1eb3V1FZ79fn91dXV2dhYxvV5veXkZ8Ts7Ozs7O6urq8vLy/D+zs6OA480AQ80OZ7KAwWYaviFhQWKN8IgMKe/s7OzvLxslFPD7+zsaL8FuNfrOfiCeByv1T+VE+t/eVjghdnZWYQ1/LFjx3q9HvwE4fx4Sh/5angHnWPHjuXnC0Ti6kXxNr3wE4TRP3bsWBhf+j78Weh3jF6f9Lvb+ErowJ/C9239guN7pH8Z7Qk8tb6MXdhhZ4Agtw95YFDQzRctDKjM39HsDMpptLcUDzZQYs+NtpHS7w3HEax/Xmj9Y9E3YtiWByEOBnlafK+9GkbYME9rampqfX0dd1hsbW3du3dvfX390qVLzWaT4/kef4j+UTzkPfDcrCVT7nqePK319XWIV3E5Nfz6+nrcPC1Y2+Rygr4Q1YQvkpmDUjWdF5Af785VWllZefLkiYNObfd5HL58ea5SLL0o3pEDpJ3L4EW/NsxV8uWrnfUQ8Tsa+TrowHcP4FsjOWoaXzgDXkKHn8fhkLM6zNPK7C/dbhf7l5b/BPjgPK1WqxU9T2tjYyMsT4vrBTDQ5LlW1DYiXmjPAQ+/VUphntYbb7zBz1SanJx86623HOOOthGj8JiWZN1zBDEtYwypXq9fuHABvocm24cffgh4Tf7bt2+78VpMy8i3hDEtIQzr6Y7YxpdffgmLLfljMF7yBMR1gmnadC+JjhLdg2kWoXsRbUaRRcJRxrRov6YxLWofqE0LwK+srPCYFrcnxcW04LfyeP8+i2kJ40MjiGnhF6XvtFqtlZUV47otthhNfo6H3yJei2kZ+QplpnKqoJiW8cx1aCvGOEEmjGecIyONvuRc+QC+DnkkvLx0185x57BNdzkcVuf5Y1pyHePqTtshpwltxlceN19FSmZ/iRjT0vo7xoqofaD5TJcuXdoy5TlRPLWBU1NTxpgWtzNUwbgxLeUZ71exY1ohnhb3sfAJxhrH3rGxMepvXb16Fcdttx9mG+cBViYrr6mQubcH1DHu7aF7AjPlN/qImXM3nAdRvG1OhPuFAID/Zs4fR+/3lNnPKLM8B17HPWmHkj4CMO1f4+PjvM/i+g3FC/cnj4+Pc/vgtoeIP3v2LH0HbYtSyignhdH3sq3fSOS02UaJ/EbbaFyfg2pX9hLB00p5Wu19kqcl93tiwZn3afnCvr5U0XAR8hx4Hd3tMHqbUcMVwsw+AnBxeVrG/KdMe+j2dTJti6+cFXueltE2CuVH26jI+pxKeVqOOVHK08oTuwqeg5c8prVXNMsmT6l0PEgxLQrb8rTQf5LbGWoPU55WytM6yHlatjlso9HwgpV4Ds7n1MG8JLBDnuJ0jMjrkOjo9qXcflhYfSpSMvvLiPO0FPFFlMzOUBuV8rT0PC3Hn/1hnhbfa4/45WGeFs1n0vb42/DG3C/jHn9HzsF+z9My6tUbJsABIMxBwaQWnhMDiiAe/nTg+/acnkw8VJcXX2POkC9fiV4Ovl7y5KxPSe5U8HcE2Iu+TZ7g+rS1Q4c8kOuTp33a+gXH0/7VN+WAFpSnJbczUfK0HLmtRjmNOVs0p9Ztz9E2GnOzKB6tJZfTiHF5WsalwjNnzpw+fdoY0zp9+rTaHdOCsfry5ctbW1sYqTPi6Xh++vRp4zi/trZmjGnBemDY/CLWum0RMS3US4tpQUoNnzNqeJzDVqtVbR760ksvUTzoZcQrMofldDiezqkB/9JLLznoG/GUfqvVkvCl+MuXL2fqlcnXSx55fVL/APGa3yORR64XwF70bfII6xPrP7MdAry2tsbxzWYzuD7V7phWZn/R1kWoPSkopuVrZ6LEtGx6nT592ign2FtuGyX2nMb7q9WqMaaF44jaXdwhKqWcnhYvdJw0wjCRiZX7bTwjwz2/wDmGFAYpAAAgAElEQVSRcB7E/TmcO9B5hBvmcuLczSYDzoMo3pi7vrzbbzPOGY2wdgYBncPivFWbq7rxfTYH53BveGaH450AvjbYKE9O+pk65tGL+z3BOubR11dHL/q+OtrajFAv4zvHhmemLAv6S+a6iNFHyVzLQTug2Qej3XDYEw3OtC0oHgrvfn91eJiRzd7mtNuUWo+dqYSOo6NknIgxm3U1Cc9nxhMxrl69CjdAbkW6/1c7qwLOyFhy5oFj7vqNGzfwljbtnevXrwO+2WzS+5GvX78OtwCsr6/jLSTr6+u/+93v/vrXvzrwmvy///3v79y54+D7MclXp+8Yc9dBTsyx73a7PM/fCONZA9p5B48fPwb4/ffff/z4caPRePz4MX3HhoezEhDWzm5Qw/MINLycPuDd9CXyyPUK05HDQEfC9/333xfSzNQxQN9gHb3ocx2N7dDRZrz0MrYZPDPF3UcA6Ha72L+wr9E+iOfsUDyeuUP7NX0H7AC3D2A3Go0GPU8H7QnFA4x2CejALSHNZtPGF/B45o52Hzp//+jRo9od8dTe5rfnSqn5+Xl6xz0dO+BmK6+rSQq8T6uS+/7fvbpPK//9NyW5T+udd97pdrtV051DMzMzjx8/brfb77777p///Gcj/uTJkwDnuUvJQd+I1+hMT0/DyUlF8NXekdA3ykPrSqhvFB2F3zGWjsHf0dEOi9NL0kdUwfdpGe+p+vbbbxvD+/kQr93bB/gXX3zx/v37mp2B3VgjuE8r1l3GcHNxbfcd9yW9T4uvh3rBau/ytHLC+yJPS4sTGPFaTEsC831iDvpGfKx9bhK+PN6TCRvl4XE7G9/oe/mEfKPoGPwdA/K0curVTnlaxeRpBcBqH+VpofSx4JHlaeWXU5U4TwsipRr+zp07SimOj5WnZaOv4Y2y+cpz584d6Pxyvl46SmAHX5Qtp46+euXREb+LhK+vjpI8LV99VcrTKiZPKwCm1Mqep5XfXzH6XrHmF0v2PK38PmKZ87SMc2HqK4TlDClnnpaNvob39e0yfQIhXy8d3blEmXyFNDN1FOoVRUf8LhK+XMc8eVoSvvx9RUpmf0l5WvI8rTB7WNL7tHCrDN5nw5G+eFuuQD/qfVpGefLDDr79Ed6npe3LMubuYE6MDd9n+768coky6fP9ZvlzmCR6Ofh6yZOzPnuhuWgSvjuRctHy1KetHTrk0fYHBrTP5dLfp0X3IY8gT4vrxeU02tuC8L29vU8L92JAzA3uwdrY2AC4Uqkg7IXfMt3vEvc+LSpDXLgk92lp+7IAr+3vevz48aVLl/jetsePH2feL6Xh4T4tvtfLRt+Ir+6+v0rCl+LpvrJgvl7yyOsT8Lb7q+T1LNcLYC/6NnmE9Un3+7nbId9biHi6J9C3PqvVapnv08L9gfJ7+7ZKc5+WposEr2Lfp3VY8rSMeVG9Xm9hYcHIKye+N8ylMPK14VOeVsrTkuuYR19fHVOeFscb13Jov8Z1F80+oPw7OzsLCwvUr+J4bmd6pjwtbk8OcJ5WnJgW3QcSNz4UK6Zlu0+L3nNDeeXEl/k+La/4RKyYVp74RMnjPconblfEXr4RxO286MeKaeWJgypSRhnTktyndfXq1ebwrsGpqSmEjXhuZ/b2Pq0yxLTi3KeFML1Pq6A9hLXi79PKD5f/Pi26H4zu9crcJxawj85G34iPtZdPwreIvXxCfaPoKPyOsXQM/o4B57jn10vSR9Qe3aeV07aovbtPKydcovu06JiZZ0x2w0XkaRXkF+67PC1j3k/EPC1bXhHHR/R7MvkWl6eVqW8UHYXfMZaOwd8xf56WV32qcudpFW1bfOWs7Lc8Le9BC8ZG6m9RWA09ylqtVhnu0I8FK6UqlQp+Cah3GwzSut+B3hJdzlqtBv67RE6JzDC3wnVCbIhuuN1uw4wG8ByGLHQ3rP0WasxBE7iH8XLw9ZInJ69MHfPUZ9JxNG2GmqzM/kL7l7Fv0qfRX7H1a7D70W2LTU6jzMFyqmGsJ7/dxjGCwjh2KM9yWGJaRriIedDW7phWpgwSmaPfpwXjWQAMNWakqQRz6igyaPJIeHnx1XS0wb58g3V3yBPMV6hjLL60HXKa0GbiyqBIyewvI87Tym9bRpmnBePZ06dPg2GlFPpYKkZMy3X24NzcnHYUIZw92Ol0nj17Vtt9ftTVq1c7nc7ExAQ/e7DT6UxNTdXYmVS+eIhPVtnZg3Nzc7C4rJ09aDubC+Hp6elY52tpsPHsQQpLzh5EvbSzBzc3NyFcp52lpuHbwzPflFI3b96k57N99dVX8M7NmzcBDsMDTU7fgccdyUK+09PT3W5Xw6vhvRJyvlH0pfL48gXda8MzSih9POtPIg/oHlb/Qn0z5fHl+84778Cu95z17/Xdbf2C47WzB6k9gb7pPnvQ1sebzWa9Xp+cnISTZyPCSinjGYkU5mcPcr0QXllZOcHOHgR7C3iwkwD74m/duvXs2bMTJ05oZw/iOKKdPcjHHY+zB+X3abWH96MoU0wL7sfKjy/iPq0yx7SKu08L4Dx4OuetOu/T0ujUajUvvsb7q7AeouslkWdzczOMDkjO8V73aeFHL05fhzy27+6m/4Mf/MDx3Y33aRnpyL97uzT3aV27dg3sTEQ4UzajnL73acWy21Vyn5Y2XoTdpxXt7EF4ASoU5gJqeCJtMFwZydmD+eW0wQ459/DsQRteAuO+MjU0Iu3c+8TywL777iS6Z9K06V4SHSW6B9MsQvci2owig1xmfynu7MHo55oi7OALcP6zB2PB1Hrbxo69OXtQKQWrk7HmFPnPHlxcXDS+g3joKsj3woULRnnC8A6+vnO3uDEtbb7/+uuvy2GcgyMjPqc24t2wlwzKHtPa3t52w7VajeJtOtr4wm9B+ExeQlhS50bdfXlR3R062mD3d3fDttgq0Ic24/XdM/kqUjL7S86Ylq1fX7hwwbges7i4mBMPcrrtG1VwD9ectnbnafGxI3JMi5d0n5YQX577tGZmZiA+sba2ZoTffPPN73//+0eOHBHCkvuQbLzW1tY++OADmGGtra0dPXpUzvfNN9/85ptvaGyD8/rDH/7gBfvq/vnnn2O8x5fXH/7wB9T9D3/4g6/uP/3pT4GOUmptbS1YhmDdHd80E4aYFuh+5cqV559/Pr/umXwlfUQVfJ9WLHvCbeMI7tOKBdP7tPjYUfO/Tyvk5mLt3kl6H+WjR4/y31kMML83k549CHOE/GcP8vuRo9y53Gq1ws4eNJ6piOeM8bMHHTCc+YZn5dngjz766MiRI6+//vqRI0ckMOykgDmv4y5aG1+YBQPsxfejjz5C+ngvLdLf3t6emZmR6JtTd7CMtVrNl1dO3ZHO5uamL98ousNv8+v+3nvvjUD3drttPHvQCHe7XexfxjP9gs8ejG5b0DbmPHuQwhVy9mBcOfnZg3zsgN0Zhd9czMdM3BNy69atR48eRRmf+b4+8L06nY5jzwza/cy9PbjapvlzUXxEbFU2OXFMpXjbnAj9Nsj2Fc4fca8a37/H8Xl8nTz3Gsfy8/793//9+eefz+RLdfed75dWdyF8qHRXw30Wkv5C+5d7/YbiM/cnDwaD6LYFbaODr9q9lmNbv0F4c3Nzfn6+oH3UlUoFPC2jjwWwUqrwm4vb6T6trDXckuRpKdO6f80U0zp37tzGxkYmjHSQkVdsg8NCvgjbYht/+ctflGdcx4sv6B43ppVf9+CYVoDu5fzuZYhp8fcRjm5b2iSm5eD78aGKadmcLdg7z2NasNeex7Ty52ahX4V4GtOy5Rz45mnRmFbEeVBwnpZxTjc9PX3u3LlPP/2Ux7QcOSjCHBqYz37zzTc3b97k81yOD8jNMuYqwXxfzhfm+8qZq/T5558jX4DdeCFfxPvS1/CYo/b5559rvk5mPWi+Tpi+FH+QvruRrySXUQ1jWti/tJgW2JngPK2CfBeIaTnWkDJjWtR+0phWrJxaiqcxLWOO72AwOHfunGPcyfC0bFveEW/ca494NczTgj37g8Fga2sL7t8E+PLly0Y83+OvlNLw9OxBW86B8pxf2M7XorK5YeM8KDhPy6hXq9VCPBb4s2rPQTHOQzke5rNwhhuf53I8/DZKrpIXX5jvVy25Sv/2b/8WII+QL+Lz5Cqd2J2j5sWX+zpefA/wd7fx3dzctPULjqf9S+unjpwt/Lmtj8c6u8/ou+Rcv6F6VcjZg5IcLIk9B3ybnT1ozPFVgnFnV3FcW8KL131a/J4Yes+Kdn+M5F6Wkd2nBffZcDnpvTg2PN4Q4+Brw4/mPi0j/osvvvjiiy8yYX5fUcC9UwF8EbbROX/+vIQv1d2Lb5l1F8KHSvdS3acFdsZ4v3kwPtOeRLlPy+uudhtMMSW6T0uZYlp4N4xSCs5mpmM4xcNdA9xfMfpeYfML231aKysrfC4D55FwObfIvTiIh9/S+3IUiWnt7X1aKsW0UkwrxbRGGNMy3qfVarXgHqwKy+kMw4/sPi2jDGNjY61Wq9FoCPEgA8auSp2n1Wg0jh8/DvvoGo2GUur+/fu47knxeKt0LWqeVnBMa2ZmBuXJlP/48eMRY1px87TKsI9rlHvYeCzHDQfkaQXzgpgW6M5jWmG655HnIH13IyzpIypGnpatj0NGTfT8p+CzB23v2/K0jPsJJfYc8GgbaUyLnj0YnKcV5z4txWJa4IuAvwW+lNq9l4bijXd0Krb3poj7tIzrzlSeTPnjxrRsctJ3oGTOH0sy53X4eRHn+9S3OGy6h8EHW/d2uk9LLCeNabnXuoT2nNr/rQLu0yo8pmWLY2n4fsExLSOMa6xyOTU8f0eLadlkGGVMC+UB2IgXxhjwfVtsQ+OVCeeMbXjx0nTPE9fx5RtF9zy8cupOv3uwDPTbFa37XsW0KIzyOGxaAJxpW1A8FN79viOmZbSNfU87San1YsS0Qk7E4LnNSinAQ2bx1tbWvXv31tfXG43G+vo6epfr6+snT56EMVnDG8+V0PK04YyMJWceOOauZ+arLy0tNZtNfu6GW04ND6uIWyxfHedumfnqFG/LXW82m5hl3O12hXn+1Wq1Xq8/efLEcS7DkydPgs8mqHqehVHEeRwaTXouhhGGuA7AXnzhPA74LZzLkMkrE85/JoUX3zy65zyPA9ohbSdFn8eB7dPdRwDodrvYv7Cv0T6I5+xQfOaZO2AHuH3ICUP0wSgnhXvDM3ds5+wgfPToUW4Dt0xnEmm2OtNO4prZ/Py8dnYSPRfD90QMl6fFHS8YIWdnZzUfC/E4dON4S9+n+wk5HmkCno/z+H7fPg9COHMe1B/OWfhcRpPTgbf5iJlzN5wHUbw2J0JdcG4FAL6mzRk1PE6KZ2dnjfusAM/ntm68jY4Qf+zYMcR78dV8HV++RryQL/Xzer1eMN9ju/fvedU/0uE+bpg8o/zu4OeN+Lvb+gXH0/7VN/lVuH5D8cK1HKN9yAOja+Lg2ydrOaiO0V8EvFFOaueXiQ0U2nO0jXy80PCap8XHHQ9Pi3td4Gk9e/bMePbgs2fP6NmDMN6ur6/Dzjr0vZrNJsfT8RzwfJxfWVkxnj1I5xFRzh7U5HTgbT5ilLMHEdbOHpyYmDDOGTU8zD2r1erExITmDwEMeD63/dnPfmac8wKenz1I6dM5tZFvrVZDvBdffvYgpQ8+hIOvES/kS/28J0+e3Lx5s2Y6dzGTb233+XtyvqA70OE+rlzf4r67my/4eUV8dxvfNjl7MLO/aGcPcr8k+OzBVqvF7QP4JbDbSwJrvs7GxkbY2YM2f2tqasp49iDYW24bJfYc8PDbiYkJPHtQDdfkzpw5g+OI5mnxcUcbmKLdpwUwBPdgP8lgMMD9JGq426I2vGeF4huNxtjYGEb8apZ7WQq6T4vfeUPlkcjP5VTpPq3R3jX1yiuvvPDCC5nvS3Q/VPdpCeutUN0P8H1aynQv4NmzZ7ndcNgTDYZv5+ALcP77tNDeSuTkeLD/MNohNfqs7fl9WiXM0xLep4X08d4aKk+z2fzwww+N8gOe7/PZX/dpecEF3aflC7fZfVoBeVq2d1qtlvsdECbWfVq+8rQj3acFMNSbvP5t390N2+7T8m0z8r2LipTM/lLcfVrG/Ce3PaF4gLX7tDBPq+j7tJTp7ESJPd/avQdbkT3nKkaeVsjuwR7bN4jP5d0xLb7uuWyKD9n24NnWdh3ruRFjWsL4Vr+wmJYmJwJ0Xd4BY0yLrvsDjHUuhPssfiCHNZoY1xHyMu4943GdYB199UJ56BkcQl7HLGeUGGnaZKC6F61jrDZD9y4KZTDSRHUk7XNZvM9Wi2kt2/ckU3yemJbbHiJeeydnTCtAzujxfj529FlMi5cIJ2KkPK32PsnTss1hX3rpJZBcCPN5rm3Oy+fUQAdhWBOQ84JVLA2Pyhp9Czi/TuML34vzdejllof6KJy+EY+6u2m6ZQCmlFcmX62u5DpSPP9ebr6aL2XT3QYb24YazuU1vvsrT0uY52TzdVKeVsrTOvh5WojX5rAUL/SrjHNwCkt8OwdeIoNRHs3v8eXrpaPEH3Lw9aJjkydAr8x6c7yf6d/k8e1sbSaPvsdKnKdFfRGhnaE2KuVpFRvT0s5E19Y9Kb6ImFbmO7b7tBxyanibj1iS+7SMsQTjXNg2R7bFtOTxCe4TOPg65s5ueWhMC3wLhJvNJo/x2PCSmJYkfubg60XHJk+AXkaawphWpi/l9u3yx7TcfPn7ipSiY1r8fWGsSB4fMsa0HHwLjWlJ7Lki62eq6JiWzdkCPB8naU4VjWkZ9/h74XlOGL7fd+Yc4EQjcz5SRL56zpiWUS/IDeqbYlqOHBTjHBbw2lx4Z2fHje+z+a8cD3MuL76UjuZneMmTh2+mPOCjyOmfP38e8dS/OX/+fHDul4QvwF70bfIE16etHTrk0fzvgPa5LMhlXB66RNi/tH4K+ILytHbE8aHoMS3NzqCc+e22HE9jWu5xJ8PTinufFvef5Hi1p/dp5YHLc58Wn8MCXpsLN5vNy5cvG/FVz3ub1tbWjHNhG30jntLXfDsbX3qfFvXbgvlmygM+irw+//KXvyCe+jd/+ctfWq2Wbz3L9QJYUm+It8kjrE/qD7nbIffDEE/9p0y+XK+S3Kdli2n5xoeix7Qk92lR25jHniuyPre2tpb/Pq0C87RQk1hwnjwtY15UvV6/cOEC3ipCed2+fTsYT/O0jHz3Nk8LVjXb7fadO3eUUgDTd2x4Sc6QJOcmgK8NNuYb5aQfnBcl4Xvnzh0wRgE6ajSRTp7vKMzTwjYj1NdLR1ubEepllE3tUZ4W7dc0T4vaB5qnhXgtz8lhZ1ZWVnieFrcnBeVpBcCUWtnztPL7KxFjWl73aW3tvh/LF69Kc5+WLaalxPGJWDGtPPGJgJhWlHiP4x0jLOFLY1pC+raYVh59A2JaXt9RoxMW08oTB1WkZPaXou/T4vYB40Due/t4TGvE92lFWX9SsWNaIZ4W97HwCcY6rl/F31EmK6+pkJmvDurw+UUUOHPuhvMgirfNiTAHHgCtIdpgt99D/S06L870wwL8Dxt9Iz6i35PJN6Lfoyy+lE3fKDoKv2N03873OwaceZFfL0kfAZj2r/Hxcd5ncf2G4oVn7oyPj3P7AH7V1atXEU/PD0L82bNn6TtoW5RSRjkpjL6Xbf1GImd02Lg+B9Wu7CWCpyXM08o/Pht9L2WfLwTML8oW07LJSd/BpuaGHXNYOnfmcQJJHowNNuZpefH19e24j5Kpl002CWyUx7F3TsPn0ZHC1M+Q6+uut0wdg7+je3+ge49rmF7tlKcllrPik6cVAKvS5mlhUgLub4E/88CjydPKL6cNdsiZ8rSM+H2RpyWBJXlavjoG1KdXvTneT3laHH8487QCYEqtV548LfCx4Anj9rVr12DlLQ8cMaZlhGPJaYQjzt1SnlamPKPM08oZ3/KlmfK0Mvny9xUpmf1lT/K0/n973xMa55Es3tEaH3c3F9/eZQ5rkMcm7ElaKeSaQxC7lmIGPb0cFkysjQMmmGEwLCJ5rHcshMnxXd4DGxMGEe/CaGB9ePji6GEwJMbo8tuDbrbBF9mHQYyRld+h3tQrdXXX1/++mW+k7sNHqfRNV1V/3dVdXV1dLnFOFYzTqoJPK00+rcHwDD5O3WtlnvEf2NdBkx6nZZQL11b9RPm0tNgdbY1sjJUx1uOC52vwQrq0nn5E/qoYul78RLZnPzQWzYVuTCxaqva09UOBHxqDFdY/beOC4+n4GpjsqpLitIJ1S398+bRSxWbdGXs+LcyPQvNp7R7NjxWPLyOfFq0/IWzkk8L9sebTunr1KsW/fv261Wq9fv2a45Vn3iaeT+vq1atC/UY8rf/NmzcudGk+rdu3b79+/VqWq5CuFz/u7Ql4rX7Mt+vezu5yAezSboX8OLYntj/NpyXItbGxoeU1hjqD27Pi+bTidcsY82kF6O1JyqeV/PxJGfm0SjozU5jzJsdp5TitHKcl95lJjNOisC2fVtm6BeBjHKclWVq8gKXFbSyE9/b2SrJddoe5jOX1Ba6JHjx48ODBA1hraO/cv38f8O1hbk2o//79+2/fvuV0A/BPnz4V6NJ1EH0H10Qavt1u49pte3ubrxmNsGb3KLKGxXWrtla14RWxMxRZI3MY1tQU71I/xcv12/j5xz/+gXYD1ENtCBmvwW/evCl8xwi70AVbwat+Iz+0ngB5sU5ot8J2duwn1B6i9Rj7odBn1NB+daFr7DOY31keIwBsb2/j+MKxRscg7t9QPO7l0HFN3/n73//+9OnTJPqE4nu9HvBpowt43MvR9m/4+++//76WI57q23i9rZS6fPkyzXGvzR2apcWLNjF5H8Sg8ySHlVKNRgNn17QwrAXUcIkE6wUNxqdSCtdB2juIhzOdWP+ZM2eMdAPwcGLCRld7GtdKFA9+V3wHCv3TCONZUljRAB5g6CLuMP2tLxxJC3z4jrT+4z/+o2wY+al4nV6wS5vHfEdbP0zVf4y/dRkjANPxJegWDcafC3oGWjJen1A86pZC/cbNSuP7UKdN38brbaUUzhEUxrlDeZY0cVodcg6kE3HORIbLiNMqg8+aQywFfRq3LDQ+6TtQ6J9GuDGqPMIUls+JBcABcVqlyhgQUzWWOh1h9zitGDggTisS7lQ4Tqts3eLLZ02M0zo4OIiElVJLS0sHBwep4rSyT+vE+bRi4CQ+rTL4cfTNJJFxxHAZ/JTRbsFwGX1GVcmnBbZRWligC3C8TysVTLW3ce5QY7l7kM6ZJdkuu+XEaZVkF1Y5TisGDojTKhU2xmnFxFelitNKCJfBj2+cViQcH6flCytSCsdL2XFayWNARxOnlVBvF+7P+RXtOLyc14THMy8O82lpV0LA2X9+T4QX3nb2X445AMA9TsvlbosAWKA7GHc+rYFbrEwV8MExTBPET0wsWhn45PyMpR+uVSCfVhkxoKBvZbqDnE9LOeTTUsMbMWAtsLCwYFwjuOPVqPJplbEOCvZplZFPi65zab6rTqeD8M7OTjBekXUurT8JXbCGk9Cl+GB5NX6S0F1fX/flx5euV/s78uNOF/phqv7m2M62ccHx66Xl0yrPdoncv3HJp0XppsqnBfMF35/zyqcVcnqwwc4NIl4Nb/5oJDorSPFKqVqthl/C8WzPzaEPib8D+bSMPDx+/DgYr8h5PyNdR54pnwDDXIgdUYZhzHc6HdgvRhjxz549Q7wvDFQa7OyWRssIx9ClMKV79epVFx6Sy+4ibxmy+9K1yf673/3uWMpOVVbheKHjyzg26ZPPBMquZ5LoE47nfHI9QwUs1D/aOeq0sHI4c+5Vcj6t45xPS5n2/W14LxgJRdYTBtM1uPLxaTUajXifEBAdl6+Lyu71W6Psvj6tqn33qvm0tPGeRJ9w/GjyaSW0C9P6tHI+reOcT6si598ofCHFmUY1VEzVkSvLXjXZXcaIKjmfVhm6BXRjzqflUXI+LRcbsSJxWu5r2E8++cQLdl/zynaeL11lWe/HxGlNuuwx8HGVvVONOK3ybJeEfNYscVqpYOVw5tyreF/jBHMj3sABMNzM0Wg0Hj16BDc5NRqNubm5ra2tVqt17ty5+fl5GT5//jze/NFoNOC2EoQBPz09/fLly263C18CbyKhMN5Z0u/3P/74Y+M7CMNu28uXLyndeHh6ehpvtLTxiXfAUPyrV68WFxeNfE5NTcHNuUqpGzdu4A00AvzFF1/Aiua7776DW50ANuIvXrz4m9/85vTp0zL8z3/+E95XStXrdayT1u8FO9JF2FbPv/zLv7x582Zubq7T6fzyl7+0wf/4xz9A9l/+8pf/+q//6k734sWL//3f/w31KKV++ctfFtIqhH1lj6EVKXtlv7sNVsMzFy7jhY4v45gFraLh8ZY42xg/PDxMrltQNwp0AQYNA1odbrazvb+zs3P58mWub42woz5HuFar7e3tvXz5ks4XGqyUKvcaJ3efFubi3NzchPvUaZ4YDW+0V4y2V6r1BfqKjGsEzG1TCBvXQRWJ01LOa96VlZVer1cIYz1IKHK970gXYcGnBUGyMoyy/8///I8X3ZWVFaxHKeVCqxD2lR1+C7IH0I2RvbLfvWo+LQ0uyXYZTZyW8Z6LdrsNNxQ7wmhpKXIvRiXyaSF+jeTTgkRK9H3If2PD89ivceXT0vgU8Pv7+zwWYa0y+bQGDjEuT548efLkCeABlvG+9Wv4s2fPIt6LLiDXSF7aeH4c6SI+QF6KP0tySXvRBQDwZ4c5eSP5Ofbf3TYuOL5fZj6tMmJAw+K0hNjWvnM+Lchz5qLPUTcaY7PGn09LKQV4mk9ra2sLLETMswKWY7vd5niY22leFn7HcBn5tJrNJs8Zo/Ep4Le2tvjdxuDTqkI+LZf8TN98883p06c/+eST06dPA/zHP/4RYY7HfEWNRsM9/xPiG40G4r3ofvPNN9od3lvZ0rUAACAASURBVF50jXhHuoiH3z58+BBl96ILFgDK7k4XZId68P7yAHlPznfvVCaf1suXL0GP9Xq9VPAY82k56nPAT14+LbAQW60W/BZ2AhvD8yQU32q1pqam0DJt2M/MJL97UCnFzyhSflz453yqovvBxnj3oBF/7949pVSv15PhXq+nkp5hc6SLcMIzbM+ePXOnm2WfLNkV2SQsHC85n5Z7Pi13fQj6vzaM1qpcPi01nD9pPi20Rebn52FmonYJxWt5rdBe0eb5MvJpUXsO89ZofP7tb3/76aefOP+ApzwDDHl0BLo3R5VPS5lyI9H1fr1ep2vbQpjnKzKued1hR7qarUPX+150NVsny35cZc/5tPrl5NNy0eeAxz0qlTqfluTT4qXP7h6kGNwapv4eF/+Q5tNaG96vZbuDS9jPTejTcvRvDUrzaWl8Dkx3Dwow3PmGd+XZYO5LkOEB8yVwWKCLfp1+v+9Fl/s23GVMKHswrUjZsZ6zw6v8Rix7DC0q+4D5tEqS3WWMrJl8WmtsDMb4tIz6IQYGAWW6g6K7B4P5jPT399ncMWA+LV48fFq8gKXFcxbj/Kn5tBz9Q2hFyvM82F6yryiVT8vdv1WeT4vySX1ajuvHer3+5ZdfYm5fG5x2zQs5agW6uN7/8ssvk6z3XWRMKPubN29A9gC6MbJjPTs7O8HyxsgOv42XPcDOC5Cd+rQKx4vm0xL2b276+7SS53AP9mnZ3oc6Xfa6wvz9SimjTwvnEV9Lq/Q4rVqtBjFY/Pw+xVcqTkvgU8OjjI2TEaf1+9//HjSCssTrfP7559vb2xxfUrzO7Ows8OMYx0Nl/9WvfuVOdxJjlU6y7KoacVq48m6ki9OanZ1Fn1apcVqgb7lunJqaKtTntjgttHkqHae1S87+0zgtDd+pUpyWwKeGRxtR47MicVrGPEaNiDgtzF+FhLT6fXMjRcbr+ObYpbIf+1il6sjO++EJidMyxj+5x4Bq+md3mKtvNHFayqIb3fUk1sPvTqpEPi3Np7W4uGjc9xTwRp+WMVZgkDSfVqXitIxy9cvMp+UYK6P5tE5srBL6TgLojj5WqSLfnfu0RvDdbeOC4/ul5dOSfUXueia5T2sxNJ+W5u+X9bxQz52IfFr69qDtyDtYZ9ynBWftFfNpzczMYJwW3fe8ffu2cT8Uz/hrPi2Kpz4t23mYSY/TgvP6nE+Ql/u0hBgU2N/XfE5lxyptbGy8efPmGMcqoV+n+rFKo/zuMl3u0yr7uz98+NDo0zKOl+3tbRxfmq8I8Gl9WvR8naOeSe7TovqT+rS4vtXwjvoc8Nyn9Yc//MHo0/r000+FeSfB6cGB/RwILF5czgdSvM1esZ0nFNYXuCbS1kG47tDWF6urq5zW/v4+4jX+C/F3hnmcBbo2vO2cD7XbjOtHI0zXtnQdinjkP+wcl7a2XRue3TLiKa0Autp6H2HN7pFp7e/vU9m96HJbx4suhfH9GNkdaSE8YDauFw9YD4rgKKP2vYJld5SRfyM+LjhcuC9i3P8w7uXQcY16QNMPvvqE6sDV1VXULbI+QQVoO5OMMG6S2fStTW/LeIRpbXyvDg1HoSQ4PTgpcVp0HYSnHuj77Xb766+/NsYinD9/nvNpxMNvEQ98ok/LSPfmqOK04CyfLV7n6tWrr1+/Dj7HVTfFx3DbrtVqvX79GmhRuoCPPLuI/FAeaP0a3UajgXjfM2x109lFLqMs79WrVzVbJ0x2oX4jPjJOC+vZ2dlxoVs3nSmNidOC+qnsnO644rQono530ANcP8j6hOI1nQn1YJyWja62l5PjtHKc1oTFaRnXucg/XxcXrmF9Ya1+ausY6Wr1GG0pm60j0DXK62ITuPAj2BlGO8+lThusye5CN5WMXnS1fmiT3QYb69fsPLmetQrHacn6kNpkJfm0HPlM7u9PEqdVYj4tvOsXbCmlFD0bQ/G2M3jG84Sq/HxaeB7GhX/juceK5NMSzvIB/41G44MPPrDhQWrjGS3bOS5+TkyrH2wdga5Wp/F8IApr5KFQLhtvLjBkHuIyurQnyu4io3wuDutxoRsgI8dDPSh7IV3tTGnDknPA2Gds9avhWbVCuTrVyKdlzFNF9YmmczS8Mp3fK9QtvnzWLPm0BN0o63OUscPyaSnT+XPlWUq8e7BjuTsrGB7Z3YPxfKpJu3vw6dOnSinoZ8LdbnDvWcd+B92PP/4Ig8qxfg0PvV/mwciPVicMHl4/yi7Ia6zTN3+uIC/yFimjS3vavnuhjBqM30UpBSIIdH1ltPWZGHkVmeALx8uI7x68dOnS5ubmbtC9po1x3z0YANPaktw9WGKcFl8jeMHjzacVA6vKx2l1iK0AMNgKHM/jogBGQnxNreGp3UbX4Ea6Ljxo/HAeNFuK0kXZBXk1W4rDXHZuW3B5lclecZTR9r1c6HLZXWTUYGwrRWwdR1tTHbWleP3QZ2Qe+PeidHkfUKQUjpcRx2mpoc5xjwelema8cVph+jBtnJZ0EGN5eVk7lwE3YnS73Xfv3jXIvRjgW+t2u2fOnFldXdViubvd7szMTIPFeMt4Ho/dbrdnZmbq9boW1728vIzx6hi7XhivrpSC2PKaGH8eAIOnFGLsjXRpvDrFa7HrKNfs7CyccD08PNze3t7Z2YElnhbbr+E7w/splFIPHz6k9wU8ffr0hx9+APyzZ8/m5ubAy23DP3v2DOoEvHYHAa+f4q9cuTI/Pw/1XLlyxYUu1vPs2bPZ2dnt7W2OL6T73XffYf0BdI3yUn4oXVq/jS7Fa/XjvR4CXSPehS7AhXK58FMol4bX7knxaue5ubkffvhB+F6UrrEf2sYFx9Px9dFHH1F9cnN4Qorui+BJB/nOHYiouXDhgqYf8A4dOLkOdtWLFy/wHRseT6gppT766CMb3ZvDE/lwOgPv2eFyIbyxscH5BH3rq7c5/tGjRzhf4N1Jm5ubOI8cHh7Sgxh83vG4EcO4Vbi0tLSwsGD0aS0sLCji08L5dmFhwTgPy3jF5vm7d+/umnxasB+o0vm04m3EJD4tlEvzacGA5GtGDY9r2Hq9blzvI15bI1O8ImtYXg/H0zU14PkavJAurX99fd2FLsXfu3evUK5Cul78uLcntVEQr9mLLvy4y8XtnsL6bfw4tie2f2E/BPju3bsc3263g9tTHfVpFY4XbV+E6pOSfFq7dj+WgN+N82nZ5FpYWDDyCfo2Xp/X63WjTwvnEXW0yC4qlX1a6uT5tNA/EeAXKfSFlOGfGIG/x0vGGLkS+rRsfrsk39HWZ8rw25XhB1XV9mkpTz8WhbNPK6VPCz4S2C4HBwe7Q79UDEwlV54+rWvXrhnfQbzm07p27ZrRfvLFX79+3ejTsvFj7EkUn9anhfaTu19EETtDMf+Bi0/L0d8jnFc0wjaflq+/x0tGDtv8dpxu2rN85X1H3md8/Xa0HmM/FPqMl1xj92nZxjXoAa4fvvrqK6Mfi+MB1vQM+rRk/UYFPGY+rTRxWgMSVu143j8GFmIOAuK0+sOSFpb5PLFxWl7xPQPPGCZfuiOO0/Kq0xGelDit0cu1luO0SojTioQrFKdF58yYOVmGy4jTgj3i77//PjnsyKdx7cb5pO9AKVw/CmtY7icw4n3tHuUQp+UV3xNp9xTSTWj3OMZLpZXR8TumkjH4O8p3/7vHabnL1ZmQOC05HlRVL04rAFY5TiutT+vUqVPJ+Ww47DtXwadVhr+n4nFaLvIG+7QqHqcVI6OXHzTHad0UfVpl6xaAs0/r/4rNxkoep2XbY021vgBfURl8djqdKsdp+fo/KBzs04rxT1Tc36P847SSyDhKv52XHzSVTyvGD6pIKRwvI47TitctJzxOK00+rQHzaRXmZYnBD0rOpxUPB/u0RpNPS/PB7O/vy/gB8xm4413q5/6z+PxVjnR95TLyE9me8H0D2tmRrle72fiJ+Y62fijwE98/beOC4/tjyqcVrFvifVrB+bQS4vvjzaeFUcY0n9bu0TuD4/Fl5NOitBLCyKeR7s1x59Pid4HLePf8STyflkv9/K5urF+7x92dH0e6jnLJ/ES255s3b8LyYznS9Wo3Gz8x31HO60bvgEd8ZP+scj6teN0yxnxaAXpbpc6ndVJ8WkYfUrPZvH79OrSvRuvx48cxeNx3NtIdr08rBk4SpzVKfipSZ9X4qZSMZfQZNSafFh3X1KcVqU8ofmNjg/u0uD7JPq3/KxPq08IvSt9ZX1/HnqHRisSjT8tI15FnyqdK59OKgQN8WqXCAf6nsdRZNX5GLGO8T8sXVqQUjpeEPi1tvKOvKKGeMfq0uJ6hAsb4tOJjbZVS6M1SKXxaIZaW0cbC6Rqm7rQ2lgYrk5bXRCg82wPiJD/b0xmeFpXXbrgOonjbmgjtNgC0jmiDR2/3TIqdUTV+jr2MY+mHLmMEYDq+Tp06xccs7t9QvPudO2p4Y1xC2MgnhdH2su3f8L2csvU2ny8AhmZX9pLA0jpmcVpl2IXVj9MqCR69bZftnurzExCnFQl3KhOnNfoYUF8+a5Y4rVSwctif8yrJfFrwAjRoqjVFQp+W8f3y1kGqwncPlroGzz6tLGMV7DA1Jp8WhUFblmS7yHtIKoVPKxVMtbdt7hjP3YNKKbC0Uq0pRpZPq4x1UAXjtJLAjj6t5HSNtICf0cuYVq4sYxl9RpFSOF7Ki9Mqb8+pUJ9QAce457R7NE7LaG8pzyJNWsvLyxwJebNgnkT/FuKVUo1GA2dXgLvdLsLueDU804H4zz77DPDQ1qDlwbpCGJ+KzATa+wiD/W7kIQZGe8tGV3sa10pULuij+M7Ozg4VE2EN3+l0YP1Sr9cRhtVNDB7qBzzAHD9Kuqnqp3ibXOOim79jAN42Ljieji9Nnwg6BKuyvVOGbgG4kDcjnza5ut0uzPRJ9DbH7+zsaPMFwDiPqKPFOO/QkvNpHed8WrD2rHvmo8r4jJ90fKca+bTKs10C9m9882mF6W2Or5N8WtTGyvm0wn1aJy2fVoYzfOxhlX1a2aeFRcin1UkapxXv08r5tJT9bFUS2Fa/CzwuHrLsJ0F2RUrheIn0aQn5tJLoE45vjiSfVipYpfZp6dc40dsyeDk8PKT7kngbB97ttL29vbq6Crd3tFqtc+fOzc/Pb21tucAwP+ONINPT0y9fvsR5+/nz571er1ar1et1vK1EKaXB9+/fh/XFgwcPcB2kvQO3myilZmdncX3x/Pnzt2/fajwE45vN5tTUlI0u3jKl8Xb//n24LUbDz87Owq0th4eHeI3TjRs38DYaI9zpdL777rtHjx7BXj+Fnz17lgS21S/AX3zxBdp/wXSVUvV6PYyHLPsJkd1ljABMx9dHH33EdQtoFQ3f7/c//vhjbVxr4z2VPuG68aOPPhLo3rhxA++xe/Xq1eLioqAzwad14cIFja4Rnpubc9TnrVbr/Pnzz58/39vbe/nyJZ0vNPjw8HBqSjKftIkpTZwW4hXxabXb7c3NTZonBu76s+GNdhW3vVTSMzO2fWfMc1MIG23EisRpxa+LbXDwuluw/9xhFLZUGbPskyt7pxpxWuXZLgn5rIn5tLR7LtrtdrPZbLfbkK1GhuG3apjXfgLyaQH3dH+z1WpBPRw/NTWFrdYYt09L4FPDcxmr79NK4utSQyUSWc+I4Sz7CZFdkUlujD4tNY4YUIBLunuQ6mpHPUlrq9Ddg8rk0wJbiq4R0K7ieNs8z22vVOsL7tNy4VPD22zEisRpKYc17yeffOIFqxLW+748pFrvZ9mPq+yKlMLxUl6cVvIYUIxhLdQnVMAwn5ay6EZ3Pcl9Wqo6+bQQv0byaUHCG5pPBfLf2PBa/hWocyz5tCBnj5FPDb+/v89zxqxVJp/WwJ6vCPFPnjx58uQJ4AGW8b71a/izZ88i3osuAICHSuL5caSL+AB5Kf7s2bOI96ILSMCD7PH8HPvvbhsXHJ/zabnn0wId6KLPjbqxQvm0lFKAp/m0tra28ITF7u7u8+fPt7a2bt++3W63OZ7nZZmbm+v1emXn02qSnDGUH/C3cT41/NbWFs8lAz6tKuTT4vmKaL4rwH/zzTenT5/+4x//ePr0aYA/+eQThDke8xU1Gg05n5aRbqPRQLwX3W+++aY+zLe0s7PjS9eId6SLePgtrPcD6DYaDcR70QXZoR6QPUzetN/diy5YP/C9Ar471AOyu9DN+bRKyqflqM8BX1I+Le/tQWNsM+LV0KJsNBqg31ut1qVLl8B+rNVqU1NTYD9SPGTRxt3PxvBeCYQBr5Sq1Wq4k3bDJ1792rVr/J1ms3n9+nWNLvDz1VdfcT5rtZoN//jxY8onxtgb6TryTPlUwxh7ZYrtN8KgWzvs7gAjXg33YWQYIufRd9og9xpwPL+zIJguwpTWjRs3kB8XWprsXnSpXL4yppI9hlYVZNf6SamyU5VVOF7o+DKOTfo0+pBsegZ8HJp+oDotAA9zoUyXPo18ajDyyfUt142F+hzwCCultLuT6NyBtwC6l3J9Wo7+oRH4tGz5tDY2Noz7tpjPRuOf4+G3NP+NIj6tCubTMvo2VlZWer1eIYx31iEhrX7fe+Ud6SKs+TYc79Azyu5Fd2VlBeuxye4LR8ruS3eMsvN+WLbsipRR+rSOXz6teH+/Su3TSpNPC5/rJJ8WnDOB83VwnmRzcxPnbYpX7PyJ7exKbST5tOiZwEL+jeceC88jVSef1r1795RSvV7PEU54hu3Zs2fudO/du9fr9VTSM2wBssfcjz7psgfT+vHHH3/729+OWHaXMaLKz6eVPE9Vc6z5tFz0OeCNurFC+bSUJU6rMzxDCPMwnberHKdF+Snk32gjViROy8XuSbvmLbyzfNJtHZixJs7WKfu7yzDMWKOUvVONOC1j/JN7DCjAmm4s1C2+fNbEOC2uGwv1OdX/u0fzaakcpyWsiXKc1gWfOC3HNe/09DT0b2VZ8/rmRopc7/vaPSfW1jlpsisyyRWOl7LjtDT9cOnSJbRF4H1HPQkw2oU2ugDnOK3/KzlOa4LitLJPK9s6VZD95Pi0NFj2FbnrGaqjcpyWHqcl/DkYxmnxs/aIXxvGaa2ReCbtjL8Nb4z9Mp7xF2IOJj1OyygXBsAB4BiDcvbsWXxfi2UBEUYTqwS0kC7GKu3v75caq6TRRXkpPiBWCWJKhPYU6CaPVXKka2wf3+/u0p4Ur/XDmBg1rB9IcLrGfmgbFxxPx9fAFANaUpyWu55JEqclxLYa+TTGbNGYWlmfo240xmZRPGpLzqcRI12Yu8guz4U4LYjNomftlVKAxzitWq2GcVr0jD+NczKe/d8dnpyBOC2K39jYwDitG5aYg0mP06KyIIwxGRCnJcRmUXy9Xv/yyy8xtonGVF29evX169eAj49VssWEAR5otVqt169fX716tdFoID4gVgn4h3gdLhfAt2/fBlqULspL8QGxSm/evOExarb6NXyj0QB8fIyaLJeG19on7LtDnfDdZbrQ/rR9vvzyS/zuATFqWP/Ozo6RLu+HnU4H47QKx8v29jaOL4yJpGMzbZxWq9UCveGuZ3ZTxGnZYltnZma4DkR9y3Wjiz4HPPz2zJkzGKcFMwWN8YU4LXphLp939Jvc5SlOK3SeNMKwkOHzcCEsrEe0OzLk9QWuiRzXQdye0/ihfGrvGPHAJ67dbDzgOojijbHra0ftNuOa0QjTdT1dayOe2xyFMMhlvJsA19RGPIUD6D45ei8DwsiPrX4Nr9k6XjxgPTbZBbrUFkF8jOy0Hhe6A3YnhRcP1NZxoVvYByJlp3SNPCCfaw7jpXBfxGijFO7loB7Q9IOvPtHgQt2C7CHz8vt3hpcZ2fStjU8XWKuN36mEhqNQPCwtXsDS0uKZ6fy5t7dH52SwRV68eFEIG+0VbZ4H20teX+Ca6MGDBw8ePIC1hvbO/fv3Ad9ut6k9d//+fcgCsLW1hTfwt9vtv/3tbz/99BOsjzheWwft7u7+/e9/f/r0qUCXroPoO8bYdeAT127b29t8zWiENbsH19qN4d0EsFala9tC+M2bN9TWoet3attRPF0LU7rU1nHnQbPzkB9b/Rpes3W8ZNfsPC6jQJfaIoiPkZ3W40KX30nhJTu1dVzoau3D+2Gk7JTu69eveR9APuUxAsD29jaOLxxrdAzi/g3F414OHdf0HdADXD9QfUL3pTgeYNRLUE+v1wM+bXQBj3s52v4Nf//999/X9rSovtXwjvoc4d3hjRh0T47OHZDZyis1SYn5tGpiXpZCeLz5tKDFIR8M4AHmeM5/dfJpff7559vb23VTzqG5uTnY7bl48eJvfvOb06dPO8K+uZSuXLnyww8/1FlepStXrvz61792p3vx4sV//vOfdee8ShpdlJfiA2SfnZ198+YNpzU/P8/r1+jCrAn4X/3qV0lkN8ol4JFnX9kd60c8pfX555/DDmG87Pfu3ZPlqlQ+LWOeqrdv38L5uhcvXiB+bm4OZiyKP3fu3IsXLzQ9A6exRpBPC/RtjA4HmObTgpmiEZdPK8TS0uZJ492DfN72hfk8T+8etNlbSXxakXAqnxblk/q04FsUrh+Ndg/CqWydwjW1tu5GW4f7tGJsHWWye4zyRto6MGMZfVqFdBPaedTOcJc3xtaBelD2Qrrcp6VC7Twqe6Fc3KdVOF40n5awf5PKp+Xox0rr07K9XyN3D8p7XWGwIncPKuLToncPek1aJcZpdYrirnzhkcVpxfOpJi1O6+nTp0opOM8qxMFgXJTyjNOy1a/hIe5N5sHIj1YnHLrl9aPsgryFsV822R3lRd4iZXRpT9t3941vw++ilAIRBLq+MrrE9vnKq8jB98LxkuO03OO0AmBaW9XjtJDjMHiMcVqRsKp8nBbcUEzxH3zwAcRbyHEwAXFaUKetfg0Pyq4wFqcjxml98MEHtvobw1glQd7C2C8uu3t7Ut4c45w0fkB2x/akvDVInJZvfBt+FzWMyxHochnle1JcYvug/g6L0wK88I1UjtNKGqcVpg8nJp+WnJelED/GfFrxcEXyafGzfMbYnX1LTM++KeaG1uOCh3NExlglG11aj3Y+0CuvUqFcAl0vfhzrP0tilSjeGPtl4+csiVFzoQuw13e08RPcnhCn5dXO2vlA43eX++da5fNp0bN2I4jT4nJxPuP1tjs+OJ+WbmnZtgcRr82TCwsLOH/CCwcHB7u7u3fv3t3d3QUYbCZfPMzzCwsLmu0FawTYA4xfXxjv14q3EYPvHjTKtb6+jngs8Cds5fP1Y71eN65hAQ9rYVy3ttvtnZ0dAc/vI6B4Wv/du3eNa+F79+4BDHsCMl1av3bXH+BRWE0uzbagdOn7LnQd+aHtSes30m00Gsb619fXXdoZ8FChTS6OB5i2T6G8Nn60drPRpXYY9kP63V3amdpVSFf77kiX98OdnR3buOB4Or60cWrDu+zlyHcPdnzu8aN6Jsndg1SuGrl7kOtbjqf8uOAV2Z+7e/eu8e7BwnnnSOHTmlC84rTS2i6RcVrGuKh+v7+6ugpr5/6wJMTb6Nrwo4nTojFDLvE99LfGuCgK+8ZpOdK1wb5xWi71F8oYI5dLDJOjjDHy+sroVb+vjLY+4yiX8Z2zY4rTouOaxmmtrq4a47QQr8U20fcHRAeininUJyXFaQXAtLYkcVppfFp0zkzrH0rl07Ll04L8NLDW+P777xGOxwt0x+vTQh+Au19EOftCbD4tR3+Po09L5ifA3+MlI4fd/XbxPi1F7KfyviPvMzF+uzCfVowfVJEySp+WSz4tRfxVt2/f3h2eJzTiNR049nxaVfBppcmnhTDNp1XSGcJG+fm04uHq59PC82DaWS+KVw7nCQthoX4jPvIedy+6ZZzlc5Q3iYyO3zGVjMHf0ffu/yRyuYwRlfNplcanEa5QPi06Z6ayqzhcRj6tkuzC6ufTsq39Kd7X7lGmNbVQvxGf0O4ppJvQ7nFpT5XatnP8jqlkDP6O8vlA235AjFydCufTKlu3+PJZ88mnFQCr1Pm0TopPywjLZ3ti4CrfPWj0adlg7bfBPi0XWmX4tMqQ0QY70vWqsyIyetEqw6flK+O4fFoUtt09GAmP9+7BKvi00tw9iDC9exDn27R3ZNxwvntQjle/ceNGe3gPcXKeC/kc492DeFcb3OMgw9pvjXf9yXcPutMS6Npg4e7B8mS0wY50veqsiIxetFzuHiy7z4zy7kHbGJ+bm8O9nLS6xcYnhUu6ezAAVqO8e3B5eVmbw+DuwW63++7du8bR+6M2Nze73e6ZM2f43YPdbndmZqbB7qTyxbfb7ZmZmTq7e3B5eRk2l7W7B213cyE8Ozub6n4tDTbePUhhl7sHUS7t7sGdnR1w12l3qWn4zvDuQaXUw4cP+f1sE4GfnZ3d3t4+3vxo9xmOvf2T8zOWfmgbFxyv3T1I9QmuJoW7B21jvN1uG+/0i9ctSinjHYkU5ncPcrkQ3tjY4HyCvo3X248ePcL5gt49iPOIdvcgn3e0iUma34yHMjA2i/u0FhYWlMmnFXPGn+IhlkuJMQeKbFhPuk8L5dJ8WnV7bBbFoy+hTmJ0lCW2KRWe+ieS1L++vj5K/sfCj+ZDGru8yfmR+yGP7YunS31aheNF82kJsVkT7dOyybWwsGDkMz7WFuB6vb60tHRwcKD5tHAeUUeLfBhQ5bsHSzozU3g/2BjvHoyBC8+5BZwTK5WfitRZNX4qJWMZfUaRg++F46XsuwfBNkoLC3QBjr97MBVMtbdx7lBjvHsQPhKdY+NhKrnyjNO6du2a8R3Ea+uLa9euGdc4AXjjeSQbP8aeRPFp47Ri4IA4rVLhgHN3Y6mzavyMWMb4uwd9YUVK4XiJjNOyjevr168bYzrj8cCnrN+ogGPcc9o9GqfF546xxWnhM2GclnDHsLKvLwLitMpYB1U/TmtS4ErZBCfB7imDn7H0Q5cxokqO0ypvzynHaXkU1MPuJgAAIABJREFU45yJeJUuTkuxeOwy4rRg35mua+LhmLsHbXzSd7CryTCuYek6NxWsHNbUSWBHm2BkMsL3zTJ6we5xWqngTjXitMqzXRLyWbPEaaWClcM9Sl7Fe9KCuZHaWzBXAayGM02j0cDdzDAY91gRr5Sq1Wr4JaDdbTBwK78DtlEknxxWSoH97sKnC8/AJ+4TYkeU4U6nAysaWMWkhYEWh0dJa1x0s4zVp0VVVuF4oePLODbp02iv2MZ1ct2CurFQn1ABC/mE+TU5n6gPtflCg5Vnyfm0jnM+LTVuf0yGMzwWWJFSOF4S3j2owSXZLqPJp5VQH6b1aelxWrb4Yjg7D3FaWmzWu3fvMF5se3sb4rTiY7Omp6dfvnxJ8RBTBXFatpgD3zgttOcSxlJA9F9YnBbyr/G5srLy7bffQpwWdkQ5BqU6sU0Zn/Gjx7vEMgKeji8t/gn0THCcVnLdgroxIE6LywVwt9vFeLJUMbUUv7e39/Lly8bR2Cwa43t4eLiysiLMOwVxWraDGN855NOiPq342CyV82kRPr8LyqfF16EZn/EnAV+RfFrl2S6R+zffOeTTCtPbHK9MsVkx+bRKjNOC+5hbrRb8VoanpqZQ8kYJcVrGuKhms3n9+nXMGoC0Wq3WV199dfv2bc6nEV+r1R4/foz1wCwOO4RGujZ89eO0MpzhiYAV2SQsHC8J47TouAZtCTqB6geq04LxhfqkpDgtR32OMHq2Khqn1Tnq0wKOaZ6Ydru9ublpxBvtFaPtFba+sOXT2tjY4GsZuL/EyCfHw2+1fDnr1cinpSrjY8hwhkcJK1IKx0tCn5Y23lEnUP1AdVoYfjT5tIyxs+12G6wRRxgtLTWM5a10nBbYT9Te2tzcxHmb22E2u4rP+cqk5TURYvJpAW+cTyP/RhuxInFaVVjzZjjDY4FdxogqP58WwMnjQccVp+WizwFv1I1Vj9MC+wltFHX0LA3Fo73C7Spueyn7eiFgfWHcd6b8FPJvtBErEqclr0k7nU4S2IVWFehWgYcs+2jodqoRp5U8BrQ27nxaLvqc6v/dEvJple7Tsu2HaviyfVrG92HNwu05gU8Nz2XUfFo2Psfo07LhvWA13ISpwpraHc6ynxDZFdkkHKVPi8J496CLr8gdLrzXFOB4n5Zxr4vqakc9SWujz0Y1fVqtVkvzFamhf0jDu8zzalRxWgKfGt5mI1YkTst4X4AN7wiroz4D4zq37Lsb6Lrbqx5H2W1yUdnHdc9IKtllGW31xMse02fcZVekFI6X8uK0yoh/wrsHBbr0GcynsuhGdz2J9fA9uRifljRpLS8vcyTk09JimxGvlGoMY6Fhvq3Vat1uF+ZhsB+NeJzPEa9YPPlnn30G+BtH47qXl5cRxqciM4H2PsJgv2P9SEvjU8BD5m+NT9x3ttHVnsa1EpWL3q+hhsd58U+ENTza3RC/wu8OCMPfYPcacLxQT6fT8aLbbDZ5/WXIxe9uMMqL/ATU3zl6RwniQc86tifIXup3RH5StSf0RpmuYz3u79vGBcdr99dQfSLoEKzK9g7ehqXph0i4ULfY+LTJBXFanBboW64bXfQ54OG3Ozs7/O4kOo+oo8U479CSJp8W4tVRn5Y6Gmul7XtSPJ3PAa/YPF9GPq1U+7Zl+LRGmU/rk08+QRh6m4yna15aD13zGuk2Gg0vuuvr6xSviK2TKqbHRV7Kz87OThjdxtHznFj/+vq6S/tDPfjRg+UtbH+BH9t3l+n+9re/9f3uGt73u3dyPi3GZ1g+La4bXfQ59fdDPq0O82lVMZ+WfD5wxHFaxvcFn5bvvq3Gp5o0n9a9e/eUUr1eT4anp6ehfyuLb8P3Pm9Hughr9fjeR05lf/bsmTvde/fu9Xo9ldSvEym7L3yiZFdkkiscLyP2aV26dEn5xDlp+nDsPi0jb4K/P7lPS7/GyXiXBpbDw8Pp6Wm8gWNpaQlgpRTg9/b2gMvnz59vbW3VarWtra35+Xn4EltbW3jbB8W3223Ew2/BXun1ehQ/NzfX6/Wgq+GtJBr86tUryFj/4MEDvMlJe+f+/fuAb7fbUCfUf//+/bdv3wJvlM+//e1vP/30E+cf8JRngP/+978/ffpUoHvz5s1+v895g/bncrXbbYCbzeb29jbeQKOUEuB6vd5sNt+8efPFF1/AorJer3/xxRcwmAGu1+uffPLJ6dOnv/nmm9OnTxfCb968gd/u7OzQOhH+8ssvjXgb7EgXYfgtrPe/+OIL5MeFlia7F91vvvkG67HJ7gtHyu5Ld4yy835YtuzIpzxGANje3sbxhWONjkHQKhoe70mi45q+A3qA6wfUJ+12+8WLF6gnOR50DuolqAduiWu32za6gAcNgzfbCTrz/fffRx3I9a2Gd9HngAe5YG/s8uXLuCeHd/7hPDI9PT01Je35aROT96Sl3T2IVLW7B2HuPX/+/NzcHK4dXrx4gfM2xc/Pz4OEDXb3IL6v3T2I6wXh7kFcB2nv4J2E2t2D0DOAN+Rnbm4OehLnH/Dnz5/X7t16+/at8e5Behei7e5BmHEVu3uw3W7fuHGD3z0owJ1O5/PPP9/e3q6TO9k4fPHixd/85jenT592hG31OMKgPQH+1a9+5U734sWL//znP9GvU6/Xg3mIkX12dvbNmzcnU/ZgWp9//vmXX345Ytldxoga3j2I48t4p59896DtjtMff/wR7/TT9IOgTyj+3LlzL168QL2Eq3ml1EcffSTQvVF09yCF6d2DXN82jt4r6KLPAY+6kd49CDNFg9096DVp5Tit4xyn5ZITdmVlpdfrgS/BBea+DVpn4Tkx6tfxoruysoL1oLAyrTJkh93IMLqTLrvw3WUYfFqjlL1TmTgtrh8c/eVGHRjj07K9U5u0OC01IGVxcXEgln6/f+fOncFgcOfOHSO8tra2trYG8P7+PsJ37txZW1vbHxaOR5jiNRiorK2tIT8cBhHW1tZWV1dt7yDc7/exTkc+NTx/B/js9/syn8Cehsf253wiDP9aGxYBPnv27Nra2tmzZxEPMOJRlrNnzz558uTJkyeFMMh19uxZqITXDy9wPKUVQBdhTRbkx4XW/v4+ld2LLgCy7AJdCuP7MbI70kJY6w++smM9KIKjjNr3CpbdUUb+jfi44DAdX8YxSxUj4ldXV23vA4x6QNMP+/v7vnqG6qhC3YLsIfPy+6CyOC2bbizkU8PT2ugTSWP724o2MZXr0yrc90R8GT6tjz/+2PgO9RWl2rfV+MS1m43P8fq0Wq3W69evr169+vr167J9WpQWhVVpPi1av0YX/TpXr15N6NfhctnkvXr1ahK/jlC/hgc40qeF9e/s7LjQTe7Tgvqp7Pxbj8unZRvjoAe4fkBviLueoboRfVo2urh7WZJPy11PluTT0i0tm7EFeD5PLi4u0vkTp+7FxUU63yIs4I3zPMfzude4JipcBw2GaxZeP+VNxu9bbMTCtRuugyhea3/KJ7a/tk7EZRTHG+0ewPP1PuD5OpfjaT0Dto7mePy+mq0zGAy86AIAeG7rGPmhdI14R7qIHzDbTq5fw589exbr8aLL7Tx3ugDz9gn47oXtyW0s7Icx3x3r17474o390DYuOJ6OL6M+wf0bOjYd93KM+sFXz2i6hfPJYdzLMe7faHoG+TTqW4p31+dG3Ujrx3kE258X2v5YdEvLduQdJjqwtOg8+e7dOzp/7u3twXw7MzOztbVFz8YALOCN8zzFg+0FawTb2gHXRIXrIMjSxu05tBHb7TasiWAdgZ5Girede1xfX3dcB1E8tL+RT5B3bm4OD2Jgpjvj+vHMmTNGuwfwfL3/xz/+0bjO5Xio5+HDh8ZzXBsbG9qaGtbCt2/f1mwdWO+70wVbB/jntg7gqd3zxRdfULr0fcQ70kU82Hb0DBtvT4Fuo9EAPLd1CttBsyFkuSgeYNo+wd/99evX8N1lutj+SBdOYQR/d6xf++6I5/3w4cOH9XrdOC74eNne3sbxBScycAwCHvdv6Ngs3MsBPcD1A92nofrEpn80W6fX63E+hb0c4/4N1Z9QJ+pt414X4t31OdpeYGnBfPGHP/yB79VNT09/+umnwryT4PSgdvaDngl59OgR7BA2UuT/NZ4n7Ha7xjMwuMMG30PLK3rt2jWYw+j7kE/r/PnznIf//M//PH/+PHwJOAMDMMfD+48fP8Z6pqensVcZ6dKzPRRvO+eDZxHBz+l4JoqeVTOeYbt37978/Dzsujie4/r9738PWltZznHZziv+6U9/QjiAru0Mm/Es35UrV7B+jS7MmoBPfoaNymWT98qVKz/88EM9+vwerceFbuTZxYsXL0I9VHYbXcpbqrOLNrn+9Kc/zc3NoYz4jhrGDruMFzq+5DPJFG/MjU7H++HhIe6wUf1w7tw5nI1Qn7RaLSNe00uPHz/++uuvMU5L0G94Ptl2JhnhnZ2dy5cv2/RtjA4HGE4PaufM6TyilCr3yLu7T0tbX/jCaX1a+EU1X9HXX39t3M/FHhaApz4tI92x+7QUsYFG49Pithfgy/NpGemiPy9trJLRh2TkJ6FPy0XehD4tqIfKLtDV2idtnJZGt1I+LTreqU+L6gfqB0K85h8CPPdpnT9/3ujT4nqmJJ9WAKwmKE4rcn6Oj9OyxTEgrMVpxfOMfBrjtIzroHHFaeH6tOx4HW3djev9K1eu/PrXv05r6wh0Ud5IW6fQthPoop2XMFbJKJeAD7Z1HOs32j0J47Tu3bsnyzX6OC3bGAfvA49/ArtKFcU51YZxWpqewTgtG11tLydtnFYAnDxOK8TS0uZJo08rfn7m8zz1adnsrSQ+rXgbMdinZVwT4f4192kJsNHuQTiVrVO4puZ+HbQ5Eto6ymT3GOWNtHU0n5YSbSmNbkI7j9oZ7vJGnt+j372QrmZ/x9h5VPZCubB/1k0+LSO8vb2N48voK0ru03L0Y5Xn06Iw9WnJe11hsCI+LTXck9N8WqVbWpPo0zK+D2uWJPu2Gp/Yq2x8VsGnRf0EZfu0bP6PknxaNn8P9eclt/MEv4uRt0ifVqEfi+IT+rTQ1nHx26XyaTn67cbu06Iw9WlR/QD2E/djoe8c8XiPH9UzsD8k7yEdb59WynxacEEkxFEfHBzsDmOqY+DOSPJppeVZVTKfliL3MvB7tR3vJgBOhLsJ+B0cQOuDDz7AbAUJ72VAfmidH3zwAYUp3cbwXoYPPvgg4b0MXC6bvJS3GNmF+jU8lz3gTgpYLUENhXSpjLZ7Unxlh/o77D4OwPM+oEgpHC8jzqelyJ0Ryi1vH/62M+58WgGwSp1PS7oRg5+d57FTWszW2jBOy3Y2PwleiDlIEqcVDwfHaRnlwgA4ABxjUDBOyxg7RfH7R+8y4PiBPRaqEI8xHBinVUiX1gMxHMb7Dgr5KZRLoOvFj2P9Z4/eUSLHftn4obFKLnRtsVOCvDZ+gtsT4rS82pnGYGH92neX+6dtXHA8HV8DUwzo8YjTEmJbjXwm19vGGF9sdsrP4GjRMGnyaXWG+VEUuXsQ51vMsxKJLyOfVvw6wghXPJ8WrIURr62RKV7Z8xUZ8TyflrYGb5C8Sja6yCfYUhyP7cDfV0rdu3evUK5CugI/PJ+WY/2ajYt4zV6U+QGku1zc7imU18YP2joyXWx/2g8bR/Np0frv3r3L8e12m9evfXfN5qtPSD4tsJ8wcxPe12fD++oWG59J8mkF6O36BOXTQu5TwWXk04J8smn5bDjkvKlCPq2nT58qpUAT0XdseJq/SkXk0wqga4ON+bSE+mHWDKjTmKspQK6nT5+CMoqXEetxbE/aH3zzkIEm1WQX6HrJaOszjnIhb5OST6ts3QJwSfm0AmBaW5J8Wml8WvS+3pJsl11/n9a1a9eM7yBeW19cu3bNSDcAb/Rp2fgx9iSKT+7T6hC/SIfYTDKe3nGOhPiaWsPb/B9edG2wzadl87ug7HKd8jtcdtlvx/09vjIa28pFXs2f5y6jBuN3obK7+O24/c3rhz7j3h80umP3adnG9fXr1417OZF6Bn1asn6jAh4zn1aaOC2EE8ZpcbiMfFr0zIyWtyYGX/F8Wk+fPsUzVy7ws2fP8LcUdozTwnroWS9HWng+0JcHR7p4zs1Wv40fIU7LSJfifWW0wbb6bWf5fGWkeNpuLnRtZ0odecB4L1s/oXQnLp9WjJ4Zbz6t4xOnhXDCOC1b3EDaOK0y+KzVaoV8jjdOy3ZPtsv92b45aiNp+eYm9qXrVaf7vfJZRvmeFLnP0Hsuwvpnp8JxWvG65YTHaWWf1onzacXAhb4QF5/WKPmpSJ1V46dSMpbRZ1T2aWWfFpYJ8mkVvmM8M5MErnKcVgxs9CHJPq1S4UJ+KlJn1fgZsYxyPyyjzyhSCsdLqXFaaWNAYcYaZZxWkrhV9GapMnxath3C5eXlxcVF7tPqdrvv3r1rMJ9Wt9udmZnh+5sxeOrTWl5e5jHqAXcPptq31eDguweNsfezs7MrKyvffvst92nt7OzAck/br9/Z2Xn48CH3aSmlHj58yH0AlcVrPqRjyc/s7Oz29nZ12j85P2Pph7ZxwfF0fGk+LdAzwXcP1mo18BWBnkkFT09PR949SPUn9WlxfQv4drs9MzPD+XHBg0/rwoULm5ub7Xabzhfo01pZWRHmnYIbMWzbg4jnsVlwFwbMokopmGPhjD+fe33x9Ow/zts37TEHynN9kXwdtDu8e1CgK6zdjHKtr68jHgv8WbfHoBjXsHWfmKQAvDHmJqZ+rximEeDL4McYizZGeZPzI/dDHtsXT3dnZ0dZxgXH0/GljVMhZgt/bhvj/E6fhHtOkfs3VK5arYZ7TqliailemWKztP25wnmHlpPi0zL6kCCfFuQ302g9fvw4GA/zN+wQGulmn9bI+KlInVXjp1IyHiefFh3XoC3j9YkRX6hP4n1aqWCqvY1zhxqLTwvxKp1PK+3dg/hF6Tvr6+sbGxtGHrDHBOAVucPCSNd37ZbEp5UEdvRpJadrpAX8jF7GtHJlGcvoM4qUwvGS0Keljfck+oTjOZ9cz1ABw3xaCe1C2xmIMJ9WiKXF50x8grJOa1fxd5RJy2siFJ7tAXFKWl8Urt1wHUTxtjURnhcCQOuINrgzvB8FuMpwhk8UrJz3JOj4OnXqFB+zuH9D8S7nk8vbczLySWG0vWz7N3wvJzmfHDbaW9Dsyl60icl70lJKaScX0ZuFc0ySJ3iGOAY6nO0J2YY0e1l4ciqpOJfpvnr1CuZUiqdjQ+BW+EC55JJLQKHjS9AqFF+oYcrQLQEaplCrlMEhfSqlms0mnzXos9ztQZgbqb0F9h3AamgRNxoN5DsMRhsI8UqpWq2GawRsdyNM+6LtHdhti+STw/CRHPl04Rn4xH1CXCJlOMMZjofp+DKOTfo02iu2cZ1ct6BuLNQnVMBCPsEXk5xP1IfafKHByrNkSytbWrnkctILHV+CVsmWVtUtreXlZY78/vvvu92uNmciXimFc2yr1bp06VKr1ep2uwgLeJyfu90u2lUU/9lnnwFeWy8sLy8Hry+4PddoNDQ+Zdi4DsK1W+E6SFi7oVzUblPD47x8zZjxGZ/xAXhtX4Tqk5i9HKNuSWW7yLwZ+bTJBXFanBboYa4bHfU56sadnR2jjYXziDpajPMOLeVaWpAVhmM4vmqWlo1PF/6zpZVLLpNV6PgStEqApVXe01HDBFtaqfhUww1YLNX1aaF+p7bU1NRUrVbT8DZ7ha8vaiPxabVaLSOfNv45n9mnleEMTwpcnk8L18SnTp1CnRYJ44wl0KVPRz6NeozzALqx1WoV4hFWSuEcoUz+LeVZRuHTCrNa4i0tNbzKRbByKBXAc04Az/mU35fpZksrl1yqU+j4ErSK0dKSx7tNP8TggU+ZbipLK16fK+LTgtYeg6XFz4EgXh31aVF7Sx21aSjeZq8YbS/lvL7AOC3tHcRrPi3oGejTQhhmLM4/4LmNeObMGaNPi/KjfNZumk8Lh1mGM5zheDhyX0TQM0ZfEeqZMDzqlkL9pvFpkwXqdNnrctTnVP+jpaXtydF5RHmW42xppTo9KPNv41ymmy2tXHKpTqHjS9AqAT4tWbeEPUfp0zomlpa7T0v2A1F81XxaLn4s2MPNPq0MZ3ii4VJ9Wlw/RMIj9mlx3ejr71dkllLV92nl04O2Z7a0csmlOoWOL0GrZEsrYBdKlW1p2c7II9541l4xnxac2Vds33NlZcWI5zEB8A7FU5+WLeZAea4vUu3bajZicJyWUa5ms4l4OsxUBWJcMj7jJx1Px5c2ToWYLfy5bYzjTcfyXo4M898W6hYXPqlcu8SnxfWthtf8/TZ9Dnju0/rss8+MPq3CeYeWbGllSyuXXE56oeNL0CpJLC2qPWL8/Y4a5vhbWoVlQuO0rl27xt9pNpvXr183roO++uorzmetVrPhHz9+TPlEn5aRru/aLfu0Mpzh8uCEPi1tvKOvSNMPhfoE8ZoOfPz4sdGnxfUMFdBlz8ndp+Xr71epfVol5tOCFm+320opkGqX5Fmh+Ha7Xal8WpArmvO5S/LcIB5+O8p8WmDvZjjDGU4Cr5eWTwstFU0/CPqE4jWdCXjYdZTp0qeRTw1GPrm+5bpRFelzqv93j+bTUqbcWsq3DEhZXFwciKXf79+5cweeg8EAYXyura0Bfm1tbX9/fzAY7O/vA7y/vw94+C3FA4x1Agx1cjxwAoQ4jCKsrq7a3kEYGOb1U34K+dd+C3C/35f5XF1d5fjFxUWBT1mWDGc4w5EwDFuOB62i4XEIC3VChVw/yPoQ8do7qFtsfFIY2FtbW0OVGMCnTTe68G/UjXzuwGYXijYxeU9a2iwFT8QDf9oT5XHE47cxYrDFjU/U+/jN5Cen4su/jXOZLs6p9EnHRn7mZ36O+GkbuahV6LNQw9h0i7s+TKJhCrWKTe/F8w9PqEqbKbTnQCyxk5Y8ZwKLNltKgAcO8zzOi8gPh/ELOa6DjPacI8+CjVhoG9Eej3jbmgg/doYznOFSYeOYpYoR8YV7OVinph+oLWLUIYJuGTjvu6ACtO3fIIybZC57XQG6kdbWN+3V9StoaYU9sR01zEBcNZRhaYVxLtPNllZ+5uekPMuwtOJ3oWTq5Vlavs+1UVpafA4DGouLi5qNhXhoCG1+pu+74/k8j+9ji3M+k/i04uF+Cp+WcX2X8Rmf8SPGJ/dp3fH0D2m6pR/k0xLkNfIZprdlPLWxEK9NWnzeyZaW02ooW1r5mZ/5Cc9saU2MpcVL38enldZ2uTNCn1Y8n4X7zl4+rQxnOMNjhJP7tHz9WBQer08rAKa1ZZ+WtCZaXV01WjNrR60cSgXwnJMwvEw3W1r5mZ+T8pQtLXm82/QDt6I4HmBeD2gtmW62tP63GOdJ+oSGSGtX8XewxTl8nHxaGc5whqsA5zitVLBxf26cllZ/eH404TPG0pLfxK9V0lOmmy2t/MzPSXnmOK1KWVreF+bCnVF4A4cGw6UgcFcV3vCRCgYqcJMT8MNvP8LbIV+9evXtt98a30G42WyeOnUqOZ+NRuPg4ADvBzPyQG/bRDxcQZ1LLrlUraBixDF77do1zBGsTGMcronCO1RRP1y6dEkNbzyC9wU4QLcADBpGKbW8vAy3/dreBwXO+UR9G6kPaW30iXOHUqrcC3ONdw8irMjdg/zeqkhYRdw9aITX19fL4LPT6eDdg4U8ULher3/33Xf5mZ/5WbWn492DyuFOv83NTbyXtRA26hbbHYkjuHswTG+Xe/egbYcQ8NynpZ3BB5PzTjln/BE/cIixmESfVoYznOFJgePjtIJ1S7xPS9OfyGepepvPF+jTkuedUnxad46emyjpWYZPqzxuZbq2kz/5mZ/5ORHPYJ/WaDThMfZpnZQ4LWNcVL/fX11dNdKKxGOvMtIV8BnOcIYnAjbu5dBxjWfT4vUJxaNusdFF9gDIcVrZ0sqWVn7mZ35mS2uiLC3B3oKGSDI/CzC2OIezTyvDGc7wCOCJ9mk58onTTCrYOHf4TlreR94VyZfMn/SMY/In5pnGcy/8ubOzU6/XtTPlwrM8bmW6r1698j4zk0suuVSpyBoG9FV5z0INAyfyMQpo9DoQTw82m01h1lhaWvI68n5SfFpe64t42LjvnOEMZ/jkwKl8Qka4kId4n1YqmGrvgWnuGI9PS7MEEz6p5MfJp5Wf+Zmfx/s56T6tVM814tOyPQdi8Zi0+BzWz/m0Evm0MpzhDB97uCTbJcynlfNpTcAt7/Kbg5JXGS7U8zM/8/O4PrOldWf0lhYv2aflCGefVoYzfMLh7NNaI7NXQp9WmtOD8N+0pwfhhEzM6UGlFJyfsZ2r0U7OAJ5zEoaX6WZ8xmf8ScCn0idcE8p08+nB/y3UpqNzJj5x6o6fn4V1inG9oImQfVoZznCGxwuXt+dUyEPOp/W/Jfu03J8u1PMzP/PzuD6zT+vOxPm0aC7OQniQfVoZznCGjxE86T4tGsUUA1OMca+uWpaWS3bObGnlZ37m5/F7Trql5cK/nIWZW1q2GWQgloJJKyyfFvdpLS4ugiFF1wj7+/sC3mhXTW4+rVTrlAxnOMMTCpehW+6k8GkF59PC2ahQnxv3z5Lk09IzF9tODyJeyzu5sLBA81EqpSBn5cLCQrvdVkdzX7bb7Xv37hnxCwsLxryZFN9sNgF/8+ZNYy7RmynydSaB19fXv//+e6h/fX0daMGZn1Qwrb9sWthWRrpl0DoJMtpojb7PZBlLkrEM3YI6sFC/AQzKUMNT/Qk8o97W9K2Gp/mUBX0OePitIvnu7969a8x3Xzjv0PKLP//5z/jH/fv3FxcXjT+Gcnh4+P333zcajc3NTaAK8PT0NMCPHj3a29ur1WqNRmNubq7dbrdarXPnzs3Pz29tbdVqtfPnzz9//nxra4viW60W4EHyRqPx/PnzXq+HMOCnp6dfvnzZ7XaNvwuQAAAgAElEQVThS3z44Yf4VRC+f/8+3GLZ7/c//vhjxF+7du0vf/mL9n6z2fyv//qv8+fPU7oAP378OBX+66+/hh584cIFlAvoAuyLh3aw0Y2v34a3yQv8lEHX1s5p5aJ423dM3p7NZhPwxu84OzsLfSYh3a+//lr4js1m89SpU2nbUx5fycfFhQsXZmdnhe/YbDavX78+snFRHr7X62l6j+u3Bw8e/OUvfwGt/v/+3/8TdObOzs7ly5dt+lbjwUWfA35ubg7gvb29ly9fwnwBMwWdO8DmmZrSzSdatInJe9Kanp7GGWtpaQmpAh5mrN3dXZCkVqttbW3Nz8/D7LW1tYUtQvHtdhvx8FvoYb1ej+Ln5ubga928eRNbXINfvXoFX+jBgwcff/wx4vGL0vfb7Tb2DKQLcEI89IaE9UM72N6HdksrF/8W7vyE4VHDBvAThpfbTeYnAC/zn7w9C/th8vaEOkc5LgrbbcTjojx8s9lst9tU73H91u/3f/zxxw8//BDX8Tad+f777xu/BR3XRr1t0+eAB/2/u7urlLp8+TJG9OK8hfPI9PS016RVYpwW7GnSs4Lavufa0TOERp+WcW9X2M8t1aeVar97vH6ysD30Yy+7wFsZssv89Mm51lSy98WzsjZ+yqMr81PGd5fbfJSyj92npcHufLroc6r/tXr61cmnBf+13YgBthQ8XfDwjL8RY7z5tGxPLlfaGmL+W3adqd4cvRRlf7X8nMTnuL7paPJp2aTz1eeK3IiBM0XMjRjl+rQK9z0RX7ZPy/i+5legtIyw7/u1oX+CysLl8q3HuNfsWL/8W6FOQXb3Ot1l1+pM0obB7dZsNpVSAe0m1C/3JSqvJnsAD0BLrsfGT1ifd6HrIpev7Px9yn/y8Z6cf/e+JOhAVbJPa2pqqlCfU/yE+bQK9z0RT/dSscck9GkZ3zf60gRY48cR1vaFuVy+9Rj3mh3rl38r1Lm+vh5fp7vsWp1J2jC43Xq9Xli7CfXL/AuyB8BAS65HkL0kui5y+crO33dv8wDZC/th/Lez0dV8Whzul+bTctHngK8NLa3R+bQi82nh/qZ2xt+Gxzorm0/L933j3n2/3/e6KwT3iB33nXm7edGy+Rd9ZTfWb5M9oA3LkNHru3vRAtnd+1L/qE8rQEajb8a3bwPbYe1ZSNeGp3VCh3GR0Van7NOS5eKyu/cZrzHrC4f5tJLk09onMbXat+B4Xk+fxfgO/PNpSZYWt7rA0nr37h2dJ3H+fPfu3d7enjbfbm1tzczM7BLbq91uczydzwHP5/mNjY1er8fXC3QdAZYWWsfC+uLDDz/EtUDwOi5gvTY3N3fr1i1sB+Bha2vrxYsXtH0Qj1Y21hNgS2H9zWbz1q1bhXR5nbi77bjexLOjtH6QneN97RL5XJNNLpAd8F52GOyOajzQs68u31G2HV3sA6jTVr+GpzICrQCbYH5+3vi9jHT5folM14jX6u/1eoXjQq5TbnNZrl6vR/FcxkL7O8ZOFWCIJpL3nMDSAo/J4uKipifp+zMzM0Y+Qd/yce2iz+m4PnPmzOXLl7U9uaWlJZxHNEuLzzux24MTGqdlfH9cPi2vfWEYRZE+LfQvwm8D/Iu+Pi1j/SC7LZ4j0qdV2N9+/vnnDz/80L2/yT4td38t4EH7x/i0HONjkLd4nxascur1eiHdc+fOvXjxwlinl08L6sH6f/e738E7wriQ65R9WrLfvdls/uIXv0C8UkqT8WT6tMYep3WcTw+qsebTsuG5XIDn7SDjw+qn/3Wvv0ny9/jKS+un9ch0OZ++/Pi2p63dbPykrT+sPW14gOP7La1Hpkv/G0OX15NqXKTqJ6nGRQye0i0vn9axOj2ozZN0/tze3l5dXdXmZJBEKYV2lRFfK5rnYS1Qr9eF9QVYWkqpBw8ewDfj74DVrJTS1kFv376tmdY1iPd9X1vfAX56ehrW+7XhWu+nn37i6ziO1+qx0eXt9vbtW6wH+Zfp8m8xNzf39OlTF3mF+kF2DY92D61Ha2dtjQwyanShHpf21Pqb0G743WH0UrxmWxTS/fnnnzXbUWhPo31Av6NMF3jT+q3cf4z8gK3z9OnTQrq8PQvpGvHauGg2m++9955LOxv7iSYXH7+yXGjnCeOC90OZH3e9IeCnp6c/+ugj1GNG/Yb+kVevXi0uLgo6s9vtGvmU9zMK9TmOa7C0tD05uld3eHhY+ulB7ewHPROi+bSwN7vAu0U+BvAryGdmJsWnhe/Y/BAcH+nTwh0P+K1A11hngE+L16/587APFNbp6NOS5dL8eS7tht/d6NOSv5eGT+XTcqGb1qflQjehT4t+R/heLu1sq7PQpyXUz8fpRPu0bO/b+HTxVcsw/FYpZfRp4Tzie3qwRJ+WNm/7wsfbpxXgn4j0acE6CP06NroJfVrcbwdawCavUKejT0tuT+rPS+LT8trfT+LTov4eFz8opRXs06J+HRtdxeyeQro2nxatf3Z2FmbNQr+drc5Cn5bgB9X8edxvdwJ9WgHwJMVpRa4pjnGcFq73Ww5xbAhjPQHxRrj2QVvHRtd2ls83TstYv8bb1tF4DqFOo83NZZTbE+t0se20785lFM6V8e9IbVyXvmSUndqm7v2nFhGnBbZOYf3cXnGha7PtaP34vYRxIdcpt7ncnr1ej+K5jCcwTisAVqnjtPRJyzZvLS8vLy4ucp9Wt9t99+4d92l1u92ZmRk+97rj0a5CPPVpLS8vg+9K8GnZ9nwRjo+3d4G5PwZ2Jo376RyP6zusR+bBZvfgel+ma7N7sAe723bUP4F2HuUN8YV2j9GnxWWU25P6JwptO+27U58Wfhe6jy9/R6NPy9HuQZi3p0v/aTDfknvfpuf3Cuna6vS6a0Oz2+AdeVzIdcp3i+C4sLUbHS9efUaQMR4Gn5awh1To06L6k/q0uL711dscT31a7Xb73bt3DebTWllZEeadgknLdnoQfsN9WnDWXjGfFp7Z1+ZedzxoSYqnPi3b2mFSfFoB/olIn9bzo34dG920cVpa/RpviC+s09GnJbcn9ed5rSttPi0apyV/x61EcVpbRX47Iz7Sp1VYf1qfFvfjyuNCrrPQpyW3m+y3m1yfFtWflE+ub+P1uSI+rT/84Q9Gn9ann34qzDuxR95hbsQsXgjDC5AYDXwAapgtLRiGeRuznwHF3d3dG0czm1EYz3e+evUKlhI3h/lm8P5cfL/ZbF6/fh3aV6P1+PFjjvd9H/AbGxuaLK1W66uvvoL3YR2nlILZAuvheKwH20GmS/GHh4eF9SN+amqK19NsNk+dOmWs38iPu1y3b9/GdbqN/4ODA5BdkBfqEejCISV4B9s/1Xd3l7ewPTV58btfunTJvX7OP++HLvw0m03YuklOV+YH6j88PNS+u0yX9xMqF/+O8rig7wN+c3PTa9y59NswvKb3uH4DDGh1iAKy6UxQ4IK+1fC+MK2NPuncUe6Rd6NPCz1s4NPq9XqYFTAG5uuLYJ9WknxavaB8PEafFr6v7acLeKNPyzEvFK4TMS+UQJfLxX1ahfm0jPVzf9758+eNdo+Wv0qrn9s9WI8gF7VxvfJp9Xo9nk+r8HtpeK1+zj+lS+WlPi2XfrLL/D1A1zimZH7w/F4h3X//93832j0CXSMe64H60f9a2M7GflJjNqttXBjr5+MUZXTMpyWM0xg892mNLJ9WAKzK9mmFxWkhTOO0aiWcman5xGlV2acV4J+I9Gkp5tex0U3l0+L1G/15CX1agn+C+vMc4wLpdzf6tFz8STZ/XphPy9cPSmkF+7QK/aBGf0+wT4vWb4zTMrazrc5Cn5YgF/fnufcZQcZ4ON6nFRynFQBXNE4LYRqnFTk/czjHadF2sNHNcVo2uXKclm/fznFaGv7Y+LSC47QCYFXNOC2EE8ZpcfhYxmnh2l+LF6F4rZ4kcVoC3VRxWrx+auvw+BihTvc4LUEukN3xvKL23VVRnFbhd0x196DQT1rlxGm99957hXRV6jgttHW0OC0+LuQ6feO0aP00TssoY6EtkuO0apW9exCfOMeW8WzmzMUONcT8t+w6U705einK/mr5OYnPcX1TF01Y3t2Dvk81yrsH4Yw8/TFYWhCbxe2tbrd75swZ7tOKj9kCuN1uz8zMcJ8WjTmYCJ9W2PolxqdVI2s0X7q1IJ9WAG9CnUnaMLjdjD6tsH0Cx74k2wdhtn6ATyvSVgjwaQW8I78fkwO68P3J8mnZYltv3ry5sbHB+QR9G6+3Hz16hPMF9WnhPKL5tP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diff --git a/docs/rules/periphery/periphery-split-csv.py b/docs/rules/periphery/periphery-split-csv.py
new file mode 100755
index 0000000..a56577a
--- /dev/null
+++ b/docs/rules/periphery/periphery-split-csv.py
@@ -0,0 +1,332 @@
+#!/usr/bin/env python3
+
+from __future__ import print_function
+
+
+import csv
+import os
+import re
+import textwrap
+
+from tabulate import tabulate
+import enum
+from typing import List, Tuple
+from dataclasses import dataclass, field, asdict
+
+
+def filesafe_template(s):
+    s = s.replace('(', '')
+    s = s.replace(')', '')
+    s = s.replace(' ', '_')
+    s = s.replace('/', '')
+    s = s.replace('.-', '_dotdash')
+    return s
+
+
+class RuleFlags(enum.Enum):
+    """
+
+    Note: some rules contain correction factors to compensate possible mask
+    defect and unpredicted process biases)
+    """
+
+    P   = u'Rule applies to periphery only (outside :drc_tag:`areaid.ce`). A corresponding core rule may or may not exist.'
+    NE  = u'Rule not checked for esd_nwell_tap. There are no corresponding rule for esd_nwell_tap.'
+    NC  = u'Rule not checked by DRC. It should be used as a guideline only.'
+    TC  = u'Rule not checked for cell name "*_tech_CD_top*"'
+    A   = u'Rule documents a functionality implemented in CL algorithms and may not be checked by DRC.'
+    AD  = u'Rule documents a functionality implemented in CL algorithms and checked by DRC.'
+    DE  = u'Rule not checked for source of Drain Extended device'
+    LVS = u'Rule handled by LVS'
+    F   = u'Rule intended for Frame only, not checked inside Die'
+    DNF = u'Drawn Not equal Final. The drawn rule does not reflect the final dimension on silicon. See table J for details.'
+    RC  = u'Recommended rule at the chip level, required rule at the IP level.'
+    RR  = u'Recommended rule at any IP level'
+    AL  = u'Rules applicable only to Al BE flows'
+    CU  = u'Rules applicable only to Cu BE flows'
+    IR  = u'IR drop check compering Al database and slotted Cu database for the same product (2 gds files) must be clean'
+
+    EXEMPT = u'Rule is an exception?'
+
+
+@dataclass
+class Rule:
+    name: str = ''
+    description: str = ''
+    flags: Tuple[RuleFlags] = field(default_factory=tuple)
+    value: str = ''
+
+
+@dataclass
+class RuleTable:
+    fname: str = ''
+    order: int = -1
+    template: str = ''
+    name: str = ''
+    description: str = ''
+    image: str = ''
+    rules: List[Rule] = field(default_factory=list, repr=False)
+    enabled: bool = True
+    notes: str = ''
+
+    @property
+    def csv_fname(self):
+        return 'p{:03d}-{}.csv'.format(self.order, self.fname)
+
+
+data = [[]]
+for l in open('periphery.csv'):
+    if '.-)' in l:
+        data.append([])
+
+    only_comma = True
+    for i in l:
+        if i not in ' ,\n':
+            only_comma = False
+            break
+    if only_comma:
+        continue
+    data[-1].append(l)
+
+no_pics = [
+    'p024-hvtr_dotdash.svg',
+    'p033-licon_dotdash.svg',
+    'p042-via3_dotdash.svg',
+    'p043-nsm_dotdash.svg',
+    'p044-m5_dotdash.svg',
+    'p044-via4_dotdash.svg',
+    'p045-pad_dotdash.svg',
+    'p045-rdl_dotdash.svg',
+    'p053-hv_dotdash_dotdash.svg',
+    'p055-uhvi_dotdash_dotdash.svg',
+    'p055-ulvt-_dotdash.svg',
+    'p055-vhvi_dotdash_dotdash.svg',
+]
+
+image_files = {}
+image_location = {}
+image_re = re.compile('p([0-9][0-9][0-9])-([^.]*)\.svg')
+for i in sorted(os.listdir('.')+no_pics):
+    if not i.endswith('.svg'):
+        continue
+    page, name = image_re.match(i).groups()
+    page = int(page, 10)
+    if name in image_files:
+        assert page-1 == image_location[name], (name, i, image_files[name], page, image_location[name])
+    if i not in no_pics:
+        image_files[name] = i
+    image_location[name] = page
+
+
+rule_tables = []
+for d in data[1:]:
+    rows = list(csv.reader(d))
+
+    rule_template, rule_name, a, process = rows.pop(0)
+    rule_template = rule_template.strip()
+    rule_name = rule_name.strip()
+    a = a.strip()
+    process = process.strip()
+    assert a == '', (d[0], a)
+    assert process in ('sky130', ''), process
+
+    image_name = filesafe_template(rule_template)
+
+    if 'High Voltage' in rule_name and not 'hv' in rule_template:
+        rule_template = rule_template.replace('(', '(hv')
+
+    # Extract the function line (if it exists)
+    func = 'Function: Defines '+rule_name+' (FIXME)'
+    if rows[0][1].startswith('Function:'):
+        a, func, b, c = rows.pop(0)
+        assert a == '', a
+        assert b == '', b
+        assert c == '', c
+
+    # Strip off the notes
+    notes = []
+    for i, r in enumerate(rows):
+        if r[0] not in ('Note', ''):
+            break
+        if r[1] == '':
+            assert r[2] == '', (r[2], rule_name, i, r)
+            assert r[3] == 'NA', (r[3], rule_name, i, r)
+            continue
+        assert r[1] != '', (r[1], rule_name, i, r)
+        assert r[2] == '', (r[2], rule_name, i, r)
+        assert r[3] == '', (r[3], rule_name, i, r)
+        notes.append(r[1])
+    rows = rows[i:]
+
+    # Strip off the flags table
+    for i, r in enumerate(rows):
+        if r[0] == 'Use' and r[1] == 'Explanation':
+            break
+    rows = rows[:i]
+
+    # Join together description which span multiple rows.
+    continued_index = []
+    for i, row in enumerate(rows):
+        if row[0] == '':
+            continued_index.append(i)
+    for i in reversed(continued_index):
+        previous_row = rows[i-1]
+        l = rows[i]
+        a, extra, b, c = rows.pop(i)
+        assert a.strip() == '', (a, l)
+        assert b.strip() in ('', previous_row[2]), (b, l, previous_row)
+        assert c.strip() in ('', 'NA', 'N/A', previous_row[3]), (c, l, previous_row)
+        if extra.strip() == '':
+            continue
+        previous_row[1] += '\n'+extra
+
+    # Calculate the actual rule name.
+    pr = None
+    values = []
+    for r in rows:
+        values.append(r[-1])
+
+        if r[0].startswith('.'):
+            r[0] = rule_template.replace('.-.-', r[0])
+        elif r[0].strip() == '':
+            r[0] = pr[0]
+        else:
+            r[0] = rule_template.replace('.-', '.'+r[0], 1)
+        pr = r
+
+    rt = RuleTable()
+    rt.template = rule_template
+    rt.fname = filesafe_template(rule_template)
+    rt.name = rule_name
+    rt.description = func
+
+    if notes:
+        rt.notes = "\n\n".join(notes)
+
+    if rt.fname in image_files:
+        rt.image = image_files[rt.fname]
+    if rt.fname in image_location:
+        rt.order = image_location[rt.fname]
+
+    # Check for all the rules having Not Applicable values
+    if len(values) == len([v for v in values if v in ('NA', 'N/A')]):
+        rt.enabled = False
+
+    for r in rows:
+        assert len(r) == 4, r
+
+        if r[0] == 'Use' and r[1] == 'Explanation':
+            break
+
+        rc = Rule()
+        rc.name = r[0]
+        rc.description = r[1].strip()
+        flags = [getattr(RuleFlags, f.upper().replace(',', '')) for f in r[2].strip().split()]
+        if r[3] == 'NC':
+            flags.append(RuleFlags.NC)
+            r[3] = ''
+        rc.flags = tuple(flags)
+        rc.value = r[3]
+        rt.rules.append(rc)
+
+    if rule_tables:
+        assert rt.order >= rule_tables[-1].order, "{} >= {}\n{}\n{}\n".format(rt.order, rule_tables[-1].order, rt, rule_tables[-1])
+    rule_tables.append(rt)
+    continue
+
+
+PERIPHERY_RULES_FILE = os.path.join('..', 'periphery-rules.rst')
+
+rst = open(PERIPHERY_RULES_FILE, 'w')
+
+rst.write("""\
+.. Do **not** modify this file it is generated from the periphery.csv file
+   found in the periphery directory using the
+   ./periphery/periphery-split-csv.py script. Instead run `make
+   rules/periphery-rules.rst` in the ./docs directory.
+
+.. list-table::
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75
+
+   * - Use
+     - Explanation
+""")
+for e in RuleFlags:
+    rst.write("""\
+   * -
+       .. _{e.name}:
+
+       :drc_flag:`{e.name}`
+
+     - {e.value}
+""".format(e=e))
+
+
+for rt in rule_tables:
+
+    rst.write("""\
+
+:drc_rule:`{rt.template}`
+{hd}
+
+""".format(rt=rt, hd='-'*(len(rt.template)+len(':drc_rule:``'))))
+
+    if rt.notes:
+        rst.write("""\
+.. note::
+
+{}
+
+
+""".format(textwrap.indent(rt.notes, prefix='    ')))
+
+    headers = ('Name', 'Description', 'Flags', 'Value')
+    headers_fmt = (':drc_rule:`Name`', 'Description', ':drc_flag:`Flags`', 'Value')
+
+    rst.write("""\
+.. list-table:: {rt.description}
+   :header-rows: 1
+   :stub-columns: 1
+   :width: 100%
+   :widths: 10 75 5 10
+
+   * - {h}
+""".format(rt=rt,h='\n     - '.join(headers_fmt)))
+
+
+    for r in rt.rules:
+        f = ' '.join(':drc_flag:`{}`'.format(f.name) for f in r.flags)
+        d = textwrap.indent(r.description, prefix='        ').strip()
+        rst.write("""\
+   * - :drc_rule:`{r.name}`
+     - {d}
+     - {f}
+     - {r.value}
+""".format(r=r, d=d, f=f))
+
+    rst.write('\n\n')
+
+    with open(rt.csv_fname, 'w', newline='') as f:
+        w = csv.DictWriter(f, headers)
+        w.writeheader()
+        for r in rt.rules:
+            d = {f: getattr(r, f.lower()) for f in headers}
+            d['Flags'] = ' '.join(f.name for f in d['Flags'])
+            w.writerow(d)
+
+    if rt.image:
+        rst.write("""\
+.. figure:: {image_file}
+    :width: 100%
+    :align: center
+
+
+""".format(image_file=os.path.join('periphery', rt.image)))
+
+rst.close()
+
+with open(PERIPHERY_RULES_FILE) as f:
+    print(f.read())
diff --git a/docs/rules/periphery/periphery.csv b/docs/rules/periphery/periphery.csv
new file mode 100644
index 0000000..d210225
--- /dev/null
+++ b/docs/rules/periphery/periphery.csv
@@ -0,0 +1,1720 @@
+0 Errors, ,,10
+Rule,Section G2: Design Rules for SKY130*,Use,
+,,,sky130
+,Section G2a. Periphery Rules,,
+, ,,
+(x.-),General,,
+,,,
+1a,"p1m.md (OPC), DECA and AMKOR layers (pi1.dg, pmm.dg, rdl.dg, pi2.dg, ubm.dg, bump.dg) and mask data for p1m, met1, via, met2 must be on a grid of [mm]",,0.001
+1b,Data for SKY130 layout and mask on all layers except those mentioned in 1a must be on a grid of [mm] (except inside Seal ring),,0.005
+2,Angles permitted on: diff,,N/A
+ ,"Angles permitted on: diff except for:\n- diff inside ""advSeal_6um* OR cuPillarAdvSeal_6um*"" pcell, \n- diff rings around the die at min total L>1000 um and W=0.3 um",,n x 90
+ ,"Angles permitted on: tap (except inside :drc_tag:`areaid.en`), poly (except for ESD flare gates or gated_npn), li1(periphery), licon1, capm, mcon, via, via2. Anchors are exempted.",,n x 90
+ ,Angles permitted on: via3 and via4. Anchors are exempted.,,n x 90
+2a,Analog circuits identified by :drc_tag:`areaid.analog` to use rectangular diff and tap geometries only; that are not to be merged into more complex shapes (T's or L's) ,,
+2c,"45 degree angles allowed on diff, tap inside UHVI",,
+,,,
+3,Angles permitted on all other layers and in the seal ring for all the layers,,
+3a,"Angles permitted on all other layers except WLCSP layers (pmm, rdl, pmm2, ubm and bump)",,n x 45
+4,Electrical DR cover layout guidelines for electromigration,NC,
+5,"All ""pin""polygons must be within the ""drawing"" polygons of the layer",Al,
+6,All intra-layer separation checks will include a notch check,,
+7,Mask layer line and space checks must be done on all layers (checked with s.x rules),NC,
+8,"Use of areaid ""core"" layer (""coreid"") must be approved by technology",NC,
+9,"Shapes on maskAdd or maskDrop layers (""serifs"") are allowed in core only. Exempted are: \n- cfom md/mp inside ""advSeal_6um* OR cuPillarAdvSeal_6um*"" pcell \n- diff rings around the die at min total L>1000 um and W=0.3 um, and PMM/PDMM inside areaid:sl",,
+ ,"Shapes on maskAdd or maskDrop layers (""serifs"") are allowed in core only. PMM/PDMM inside areaid:sl are excluded.",,N/A
+10,"Res purpose layer for (diff, poly) cannot overlap licon1",,
+11,Metal fuses are drawn in met2,LVS,N/A
+ ,Metal fuses are drawn in met3,LVS,N/A
+ ,Metal fuses are drawn in met4,LVS,
+\n12a\n12b\n12c,"To comply with the minimum spacing requirement for layer X in the frame:\n- Spacing of :drc_tag:`areaid.mt` to any non-ID layer\n- Enclosure of any non-ID layer by :drc_tag:`areaid.mt`\n- Rules exempted for cells with name ""*_buildspace""",F,
+12d,- Spacing of :drc_tag:`areaid.mt` to huge_metX (Exempt met3.dg),F,N/A
+12d,- Spacing of :drc_tag:`areaid.mt` to huge_metX (Exempt met5.dg),F,
+12e,- Enclosure of huge_metX by :drc_tag:`areaid.mt` (Exempt met3.dg),F,N/A
+12e,- Enclosure of huge_metX by :drc_tag:`areaid.mt` (Exempt met5.dg),F,
+13,Spacing between features located across areaid:ce is checked by …,,
+14,Width of features straddling areaid:ce is checked by …,,
+15a,"Drawn compatible, mask, and waffle-drop layers are allowed only inside areaid:mt (i.e., etest modules), or inside areaid:sl (i.e., between the outer and inner areaid:sl edges, but not in the die) or inside areaid:ft (i.e., frame, blankings). Exception: FOM/P1M/Metal waffle drop are allowed inside the die",P,
+15b,"Rule X.15a exempted for cpmm.dg inside cellnames ""PadPLfp"", ""padPLhp"", ""padPLstg"" and ""padPLwlbi"" (for the SKY130di-5r-gsmc flow)",Exempt,
+16,"Die must not overlap :drc_tag:`areaid.mt` (rule waived for test chips and exempted for cellnames ""*tech_CD_*"", ""*_techCD_*"", ""lazX_*"" or ""lazY_*"" )",,
+17,"All labels must be within the ""drawing"" polygons of the layer; This check is enabled by using switch ""floating_labels""; Identifies floating labels which appear as warnings in LVS. Using this check would enable cleaner LVS run; Not a gate for tapeout",,
+18,"Use redundant mcon, via, via2, via3 and via4 (Locations where additional vias/contacts can be added to existing single vias/contacts will be identified by this rule).\nSingle via under :drc_tag:`areaid.core` and :drc_tag:`areaid.standarc` are excluded from the single via check",RR,
+19,"Lower left corner of the seal ring should be at origin i.e (0,0)",,
+20,"Min spacing between pins on the same layer (center to center); Check enabled by switch ""IP_block""",,
+21,prunde.dg is allowed only inside :drc_tag:`areaid.mt` or :drc_tag:`areaid.sc`,,
+22,"No floating interconnects (poly, li1, met1-met5) or capm allowed; Rule flags interconnects with no path to poly, difftap or metal pins. Exempt floating layers can be excluded using poly_float, li1_float, m1_float, m2_float, m3_float, m4_float and m5_float text labels. Also flags an error if these text labels are placed on connected layers (not floating) and if the labels are not over the appropriate metal layer.  \nIf floating interconnects need to be connected at a higher level (Parent IP or Full chip), such floating interconnects can be exempted using poly_tie, li1_tie, m1_tie, m2_tie, m3_tie, m4_tie and m5_tie text labels.\nIt is the responsibility of the IP owner and chip/product owner to communicate and agree to the node each of these texted lines is connected to, if there is any risk to how a line is tied, and to what node.\nOnly metals outside :drc_tag:`areaid.stdcell` are checked.\n",RC,
+,"The following are exempt from x.22 violations: _techCD_ , inductor.dg, modulecut, capacitors and s8blerf",,
+,The 'notPublicCell' switch will deactivate this rule,,
+23a,:drc_tag:`areaid.sl` must not overlap diff,,N/A
+23b,diff cannot straddle :drc_tag:`areaid.sl`,,
+23c,":drc_tag:`areaid.sl` must not overlap tap, poly, li1 and metX",,
+23d,":drc_tag:`areaid.sl` must not overlap tap, poly",,N/A
+23e,"areaid:sl must not overlap li1 and metX for pcell ""advSeal_6um""",,N/A
+23f,"areaid:SubstrateCut (:drc_tag:`areaid.st`, local_sub) must not straddle p+ tap",RR,
+24,condiode label must be in iso_pwell,,
+25,"pnp.dg must be only within cell name ""s8rf_pnp"", ""s8rf_pnp5x"" or ""s8tesd_iref_pnp"", ""stk14ecx_*""",,
+26,"""advSeal_6um"" pcell must overlap diff",,
+27,"If the sealring is present, then partnum is required.  To exempt the requirement, place text.dg saying ""partnum_not_necessary"".\n""partnum*block"" pcell should be used instead of ""partnum*"" pcells",RR,N/A
+28,Min width of :drc_tag:`areaid.sl`,,N/A
+29,nfet must be enclosed by dnwell. Rule is checked when switch nfet_in_dnwell is turned on.,,
+ ,,,
+Use,Explanation,,
+P,Rule applies to periphery only (outside :drc_tag:`areaid.ce`). A corresponding core rule may or may not exist.,,
+NE,Rule not checked for esd_nwell_tap. There are no corresponding rule for esd_nwell_tap.,,
+NC,Rule not checked by DRC. It should be used as a guideline only.,,
+TC,"Rule not checked for cell name ""*_tech_CD_top*""",,
+A,Rule documents a functionality implemented in CL algorithms and may not be checked by DRC.,,
+AD,Rule documents a functionality implemented in CL algorithms and checked by DRC.,,
+DE,Rule not checked for source of Drain Extended device,,
+LVS,Rule handled by LVS,,
+F,"Rule intended for Frame only,  not checked inside Die",,
+DNF,Drawn Not equal Final. The drawn rule does not reflect the final dimension on silicon. See table J for details.,,
+RC,"Recommended rule at the chip level, required rule at the IP level.",,
+RR,Recommended rule at any IP level,,
+Al  Cu,Rules applicable only to Al or Cu BE flows,,
+IR,IR drop check compering Al database and slotted Cu database for the same product (2 gds files) must be clean,Cu,
+,,,
+,,,
+Note: some rules contain correction factors to compensate possible mask defect and unpredicted process biases,,,
+,,,
+(dnwell.-),Deep Nwell,,sky130
+,Function: Define deep nwell for isolating pwell and noise immunity,,
+,,,
+2,Min width of deep nwell,,3.000
+3,Min spacing between deep nwells. Rule exempt inside UHVI.,,6.300
+3a,Min spacing between deep nwells on same net inside UHVI.,,N/A
+3b,Min spacing between deep-nwells inside UHVI and deep-nwell outside UHVI,,N/A
+3c,Min spacing between deep-nwells inside UHVI and nwell outsideUHVI,,N/A
+3d,Min spacing between deep-nwells inside UHVI on different nets,,N/A
+4,Dnwell can not overlap pnp:dg,,
+5,P+_diff can not straddle Dnwell ,,
+6,RF NMOS must be enclosed by deep nwell (RF FETs are listed in $DESIGN/config/tech/model_set/calibre/fixed_layout_model_map of corresponding techs),,
+7,Dnwell can not straddle areaid:substratecut,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(nwell.-),Nwell,,sky130
+,Function: Define nwell implant regions,,
+,,,
+1,Width of nwell,,0.840
+2a,Spacing between two n-wells,,1.270
+2b,Manual merge wells if less than minimum,,
+4,All n-wells will contain metal-contacted tap  (rule checks only for licon on tap) . Rule exempted from high voltage cells inside UHVI,,
+5,Deep nwell must be enclosed by nwell by atleast... Exempted inside UHVI or :drc_tag:`areaid.lw`,TC,0.400
+,Nwells can merge over deep nwell if spacing too small (as in rule nwell.2),,
+5a,min enclosure of nwell by dnwell inside UHVI,,N/A
+5b,nwell inside UHVI must not be on the same net as nwell outside UHVI,,N/A
+6,Min enclosure of nwell hole by deep nwell outside UHVI,TC,1.030
+7,Min spacing between nwell and deep nwell on separate nets,TC,4.500
+,"Spacing between nwell and deep nwell on the same net is set by the sum of the rules nwell.2 and nwell.5. By default, DRC run on a cell checks for the separate-net spacing, when nwell and deep nwell nets are separate within the cell hierarchy and are joined in the upper hierarchy. To allow net names to be joined and make the same-net rule applicable in this case, the ""joinNets"" switch should be turned on.",,
+,,,
+,,,
+,waffle_chip,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(pwbm.-),Pwbm,,sky130
+,Function: Define p-well block,,
+,,,
+1,Min width of pwbm.dg,,N/A
+2,Min spacing between two pwbm.dg inside UHVI,,N/A
+3,Min enclosure of dnwell:dg by pwbm.dg inside UHVI (exempt pwbm hole inside dnwell),,N/A
+4,dnwell inside UHVI must be enclosed by pwbm (exempt pwbm hole inside dnwell),,N/A
+5,Min Space between two pwbm holes inside UHVI,,N/A
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(pwdem.-),Pwdem,,sky130
+,,,
+,,,
+1,Min width of pwdem.dg,,N/A
+2,Min spacing between two pwdem.dg inside UHVI on same net,,N/A
+3,Min enclosure of pwdem:dg by pwbm.dg inside UHVI,,N/A
+4,pwdem.dg must be enclosed by UHVI,,N/A
+5,pwdem.dg inside UHVI must be enclosed by deep nwell,,N/A
+6,Min enclosure of pwdem:dg by deep nwell inside UHVI,,N/A
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(hvtp.-),Hvtp,,sky130
+,Function: Define Vt adjust implant region for high Vt LV PMOS; ,,
+,,,
+1,Min width of hvtp,,0.380
+2,Min spacing between hvtp to hvtp,,0.380
+3,Min enclosure of pfet by hvtp,P,0.180
+4,Min spacing between pfet and hvtp,P,0.180
+5,Min area of hvtp (um^2),,0.265
+6,Min area of hvtp Holes (um^2),,0.265
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(hvtr.-),Hvtr,,sky130
+,Function: Define low VT adjust implant region for pmedlvtrf; ,,
+,,,
+1,Min width of hvtr,,0.380
+2,Min spacing between hvtp to hvtr,,0.380
+3,Min enclosure of pfet by hvtr,P,0.180
+,,,
+,,,
+(lvtn.-),Lvtnm,,sky130
+,"Function: Define regions to block Vt adjust implant for low Vt LV PMOS/NMOS, SONOS FETs and Native NMOS",,
+,,,
+1a,Min width of lvtn,,0.380
+2,Min space lvtn to lvtn,,0.380
+3a,Min spacing of lvtn to gate. Rule exempted inside UHVI.,P,0.180
+3b,Min spacing of lvtn to pfet along the S/D direction,P,0.235
+4b,Min enclosure of gate by lvtn. Rule exempted inside UHVI.,P,0.180
+9,"Min spacing, no overlap, between lvtn and hvtp",,0.380
+10,Min enclosure of lvtn by (nwell not overlapping Var_channel) (exclude coincident edges),,0.380
+12,Min spacing between lvtn and (nwell inside :drc_tag:`areaid.ce`),,0.380
+13,Min area of lvtn (um^2),,0.265
+14,Min area of lvtn Holes (um^2),,0.265
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(ncm.-),Ncm,,sky130
+,Function: Define Vt adjust implant region for LV NMOS in the core of NVSRAM,,
+,,,
+X.2,Ncm overlapping areaid:ce is checked for core rules only,,
+X.3,Ncm overlapping core cannot overlap N+diff in periphery,TC,
+1,Width of ncm,,0.380
+2a,Spacing of ncm to ncm,,0.380
+2b,Manual merge ncm if space is below minimum,,
+3,Min enclosure of P+diff by Ncm,P,0.180
+4,Min enclosure of P+diff within (areaid:ed AndNot areaid:de) by Ncm,P,0.180
+5,"Min space, no overlap, between ncm and (LVTN_gate) OR (diff containing lvtn)",P,0.230
+6,"Min space, no overlap, between ncm and nfet",P,0.200
+7,Min area of ncm (um^2),,0.265
+8,Min area of ncm Holes (um^2),,0.265
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(difftap.-),Diff/tap,,sky130
+,Function: Defines active regions and contacts to substrate,,
+,,,
+1,Width of diff or tap,P,0.150
+2,"Minimum channel width (Diff And Poly) except for FETs inside :drc_tag:`areaid.sc`: Rule exempted in the SP8* flows only, for the cells listed in rule difftap.2a ",P,0.420
+2a,"Minimum channel width (Diff And Poly) for cell names ""s8cell_ee_plus_sseln_a"", ""s8cell_ee_plus_sseln_b"", ""s8cell_ee_plus_sselp_a"", ""s8cell_ee_plus_sselp_b"" , ""s8fpls_pl8"", ""s8fpls_rdrv4"" , ""s8fpls_rdrv4f"" and ""s8fpls_rdrv8""",P,NA
+2b,Minimum channel width (Diff And Poly) for FETs inside :drc_tag:`areaid.sc`,P,0.360
+3,"Spacing of diff to diff, tap to tap, or non-abutting diff to tap",,0.270
+4,Min tap bound by one diffusion,,0.290
+5,Min tap bound by two diffusions,P,0.400
+6,Diff and tap are not allowed to extend beyond their abutting edge,,
+7,Spacing of diff/tap abutting edge to a non-conciding diff or tap edge,NE,0.130
+8,Enclosure of (p+) diffusion by N-well. Rule exempted inside UHVI.,"DE, NE, P",0.180
+9,Spacing of (n+) diffusion to N-well outside UHVI,"DE, NE, P",0.340
+10,Enclosure of (n+)  tap by N-well. Rule exempted inside UHVI.,"NE, P",0.180
+11,Spacing of (p+) tap to  N-well. Rule exempted inside UHVI.,,0.130
+12,ESD_nwell_tap is considered shorted to the abutting diff,NC,
+13,Diffusion or the RF FETS in Table H5 is defined by Ldiff and Wdiff.,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(tunm.-),Tunnel,,sky130
+,Function: Defines SONOS FETs ,,
+,,,
+1,Min width of tunm,,0.410
+2,Min spacing of tunm to tunm,,0.500
+3,Extension of tunm beyond (poly and diff),,0.095
+4,Min spacing of tunm to (poly and diff) outside tunm,,0.095
+5,(poly and diff) may not straddle tunm,,
+6a,Tunm outside deep n-well is not allowed,TC,
+7,Min tunm area,,0.672
+8,tunm must be enclosed by :drc_tag:`areaid.ce`,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(poly.-),Poly  ,,sky130
+,"Function: Defines FET gates, interconnects and resistors",,
+,,,
+X.1,All FETs would be checked for W/Ls as documented in spec 001-02735  (Exempt FETs that are pruned; exempt for W/L's inside :drc_tag:`areaid.sc` and inside cell name scs8*decap* and listed in the MRGA as a decap only W/L),,
+X.1a,Min & max dummy_poly L is equal to min L allowed for corresponding device type (exempt rule for dummy_poly in cells listed on Table H3),,
+1a,Width of poly,,0.150
+1b,Min channel length (poly width) for pfet overlapping lvtn (exempt rule for dummy_poly in cells listed on Table H3),,0.350
+2,Spacing of poly to poly except for poly.c2 and poly.c3; Exempt cell: sr_bltd_eq where it is same as poly.c2,,0.210
+3,Min poly resistor width,,0.330
+4,Spacing of poly on field to diff (parallel edges only),P,0.075
+5,Spacing of poly on field to tap,P,0.055
+6,Spacing of poly on diff to abutting tap (min source),P,0.300
+7,Extension of diff beyond poly (min drain),P,0.250
+8,Extension of poly beyond diffusion (endcap),P,0.130
+9,Poly resistor spacing to poly or spacing (no overlap) to diff/tap,,0.480
+10,Poly can't overlap inner corners of diff,,
+11,No 90 deg turns of poly on diff,,
+12,"(Poly NOT (nwell NOT hvi)) may not overlap tap; Rule exempted for cell name ""s8fgvr_n_fg2"" and gated_npn and inside UHVI.",P,
+15,Poly must not overlap diff:rs,,
+16,"Inside RF FETs defined in Table H5, poly cannot overlap poly across multiple adjacent instances",,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+, ,,
+, ,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(rpm.-),P+ Poly resistor,,sky130
+,Function: Defines p+ poly resistors,,
+,,,
+1a,Min width of rpm,,1.270
+1b,Min/Max prec_resistor width xhrpoly_0p35,,0.350
+1c,Min/Max prec_resistor width xhrpoly_0p69,,0.690
+1d,Min/Max prec_resistor width xhrpoly_1p41,,1.410
+1e,Min/Max prec_resistor width xhrpoly_2p85,,2.850
+1f,Min/Max prec_resistor width xhrpoly_5p73,,5.730
+1g,Only 1 licon is allowed in xhrpoly_0p35 prec_resistor_terminal,,
+1h,Only 1 licon is allowed in xhrpoly_0p69 prec_resistor_terminal,,
+1i,Only 2 licons are allowed in xhrpoly_1p41 prec_resistor_terminal,,
+1j,Only 4 licons are allowed in xhrpoly_2p85 prec_resistor_terminal,,
+1k,Only 8 licons are allowed in xhrpoly_5p73 prec_resistor_terminal,,
+2,Min spacing of rpm to rpm,,0.840
+3,rpm must enclose prec_resistor by atleast,,0.200
+4,prec_resistor must be enclosed by psdm by atleast,,0.110
+5,prec_resistor must be enclosed by npc by atleast,,0.095
+6,"Min spacing, no overlap, of rpm and nsdm",,0.200
+7,Min spacing between rpm and poly,,0.200
+8,poly must not straddle rpm,,
+9,"Min space, no overlap, between prec_resistor and hvntm",,0.185
+10,Min spacing of rpm to pwbm,,N/A
+11,rpm should not overlap or straddle pwbm except cells\ns8usbpdv2_csa_top\ns8usbpdv2_20vconn_sw_300ma_ovp_ngate_unit\ns8usbpdv2_20vconn_sw_300ma_ovp\ns8usbpdv2_20sbu_sw_300ma_ovp,,N/A
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(varac.-),Varactor,,sky130
+,Function: Defines varactors,,
+,,,
+1,Min channel length (poly width) of Var_channel,,0.180
+2,Min channel width (tap width) of Var_channel,,1.000
+3,Min spacing between hvtp to Var_channel,,0.180
+4,Min spacing of licon on tap to Var_channel,,0.250
+5,Min enclosure of poly overlapping Var_channel by nwell,,0.150
+6,Min spacing between VaracTap and difftap,,0.270
+7,Nwell overlapping Var_channel must not overlap P+ diff,,
+8,Min enclosure of Var_channel by hvtp,,0.255
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(photo.-),Photo diode,,sky130
+,Function: Photo diode for sensing light,,
+,,,
+1,Rules dnwell.3 and nwell.5 are exempted for photoDiode,,
+2,Min/Max width of photoDiode,,3.000
+3,Min spacing between photoDiode,,5.000
+4,Min spacing between photoDiode and deep nwell,,5.300
+5,photoDiode edges must be coincident with :drc_tag:`areaid.po`,,
+6,photoDiode must be enclosed by dnwell ring,,
+7,photoDiode must be enclosed by p+ tap ring,,
+8,Min/Max width of nwell inside photoDiode,,0.840
+9,Min/Max enclosure of nwell by photoDiode,,1.080
+10,Min/Max width of tap inside photoDiode,,0.410
+11,Min/Max enclosure of tap by nwell inside photoDiode,,0.215
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(npc.-),Nitride Poly Cut (NPC),,sky130
+,Function: Defines nitride openings to contact poly and Li1,,
+,,,
+1,Min width of NPC,,0.270
+2,Min spacing of NPC to NPC,,0.270
+3,Manual merge if less than minimum,,
+4,Spacing (no overlap) of NPC to Gate,,0.090
+5,Max enclosure of poly overlapping slotted_licon by npcm (merge between adjacent short edges of the slotted_licons if space < min),,0.095
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(n/ psd.-),N+/P+ Source/Drain Implants (Nsdm and Psdm),,sky130
+,Function: Defines opening for N+/P+ implants,,
+,,,
+1,Width of nsdm(psdm),P,0.380
+2,Spacing of nsdm(psdm) to nsdm(psdm),P,0.380
+3,Manual merge if less than minimum,,
+5a,"Enclosure of diff by nsdm(psdm), except for butting edge",,0.125
+5b,"Enclosure of tap by nsdm(psdm), except for butting edge",P,0.125
+6,Enclosure of diff/tap butting edge by nsdm (psdm) ,,0.000
+7,Spacing of NSDM/PSDM to opposite implant diff or tap (for non-abutting diff/tap edges),,0.130
+8,Nsdm and psdm cannot overlap diff/tap regions of opposite doping,DE,
+9,"Diff and tap must be enclosed by their corresponding implant layers. Rule exempted for\n- diff inside ""advSeal_6um* OR cuPillarAdvSeal_6um*"" pcell for SKY130P*/SP8P*/SKY130DI-5R-CSMC flows\n- diff rings around the die at min total L>1000 um and W=0.3 um\n- gated_npn \n- :drc_tag:`areaid.zer`.",DE,
+10a,Min area of Nsdm (um^2),,0.265
+10b,Min area of Psdm (um^2),,0.255
+11,Min area of n/psdmHoles (um^2),,0.265
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(licon.-),Local Interconnect Contact (Licon),,sky130
+,Function: Defines contacts between poly/diff/tap and Li1,,
+, ,,
+1,Min and max L and W of licon (exempt licons inside prec_resistor),,0.170
+1b,Min and max width of licon inside prec_resistor,,0.190
+1c,Min and max length of licon inside prec_resistor,,2.000
+2,Spacing of licon to licon,P,0.170
+2b,Min spacing between two slotted_licon (when the both the edges are 0.19um in length),,0.350
+2c,Min spacing between two slotted_licon (except for rule licon.2b),,0.510
+2d,Min spacing between a slotted_licon and 0.17um square licon,,0.510
+3,Only min. square licons are allowed except die seal ring where licons are (licon CD)*L ,,0.170 *L
+4,Licon1 must overlap li1 and (poly or diff or tap),,
+5a,Enclosure of licon by diff,P,0.040
+5b,Min space between tap_licon and diff-abutting tap edge,P,0.060
+5c,Enclosure of licon by diff on one of two adjacent sides,P,0.060
+6,Licon cannot straddle tap,P,
+7,Enclosure of licon by one of two adjacent edges of isolated tap,P,0.120
+8,Enclosure of poly_licon by poly,P,0.050
+8a,Enclosure of poly_licon by poly on one of two adjacent sides,P,0.080
+9,"Spacing, no overlap, between poly_licon and psdm; In SKY130DIA/SKY130TMA/SKY130PIR-10 flows, the rule is checked only between (poly_licon outside rpm) and psdm",P,0.110
+10,Spacing of licon on (tap AND (nwell NOT hvi)) to Var_channel,P,0.250
+11,"Spacing of licon on diff or tap to poly on diff (except for all FETs inside :drc_tag:`areaid.sc` and except s8spf-10r flow for 0.5um phv inside cell names ""s8fs_gwdlvx4"", ""s8fs_gwdlvx8"", ""s8fs_hvrsw_x4"", ""s8fs_hvrsw8"", ""s8fs_hvrsw264"", and ""s8fs_hvrsw520"" and for 0.15um nshort inside cell names ""s8fs_rdecdrv"", ""s8fs_rdec8"", ""s8fs_rdec32"", ""s8fs_rdec264"", ""s8fs_rdec520"")",P,0.055
+11a,Spacing of licon on diff or tap to poly on diff (for all FETs inside :drc_tag:`areaid.sc` except 0.15um phighvt),P,0.050
+11b,Spacing of licon on diff or tap to poly on diff (for 0.15um phighvt inside :drc_tag:`areaid.sc`),P,0.050
+11c,"Spacing of licon on diff or tap to poly on diff (for 0.5um phv inside cell names ""s8fs_gwdlvx4"", ""s8fs_gwdlvx8"", ""s8fs_hvrsw_x4"", ""s8fs_hvrsw8"", ""s8fs_hvrsw264"", and ""s8fs_hvrsw520"")",P,0.040
+11d,"Spacing of licon on diff or tap to poly on diff (for 0.15um nshort inside cell names ""s8fs_rdecdrv"", ""s8fs_rdec8"", ""s8fs_rdec32"", ""s8fs_rdec264"", ""s8fs_rdec520"")",P,0.045
+12,Max SD width without licon,NC,5.700
+13,Spacing (no overlap) of NPC to licon on diff or tap,P,0.090
+14,Spacing of poly_licon to diff or tap,P,0.190
+15,poly_licon must be enclosed by npc by…,P,0.100
+16,"Every source_diff and every tap must enclose at least one licon1, including the diff/tap straddling areaid:ce. \nRule exempted inside UHVI.",P,
+17,Licons may not overlap both poly and (diff or tap),,
+18,Npc must enclose poly_licon,,
+19,poly of the HV varactor must not interact with licon,P,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(li.-.-),Local Interconnect (LI),,sky130
+,Function: Defines local interconnect to diff/tap and poly,,
+,,,
+1,Width of LI (except for li.1a),P,0.170
+1a,Width of LI inside of cells with name s8rf2_xcmvpp_hd5_*,P,0.140
+2,Max ratio of length to width of LI without licon or mcon,NC,10.000
+3,Spacing of LI to LI (except for li.3a),P,0.170
+3a,Spacing of LI to LI inside cells with names s8rf2_xcmvpp_hd5_*,P,0.140
+5,Enclosure of licon by one of two adjacent LI sides,P,0.080
+6,Min area of LI,P,0.0561
+7,"Min LI resistor width (rule exempted within :drc_tag:`areaid.ed`; Inside :drc_tag:`areaid.ed`, min width of the li resistor is determined by rule li.1)",,0.290
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(ct.-),Metal contact (Mcon),,sky130
+,Function: Defines contact between Li1 and met1,,
+,,,
+1,Min and max L and W of mcon,DNF,0.170
+2,Spacing of mcon to mcon,DNF,0.190
+3,Only min. square mcons are allowed except die seal ring where mcons are…,,0.170*L
+4,Mcon must be enclosed by LI by at least …,P,0.000
+irdrop.1,"For 1 <= n <= 10 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.2
+irdrop.2,"For 11 <= n <= 100 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.3
+irdrop.3,"For n > 100 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.7
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(capm.-),MIM Capacitor (Capm),,sky130
+,Function: Defines MIM capacitor,,
+,,,
+1,Min width of capm,,N/A
+2a,Min spacing of capm to capm,,N/A
+2b,Minimum spacing of capacitor bottom_plate to bottom plate,,N/A
+3,Minimum enclosure of capm (top_plate) by met2,,N/A
+4,Min enclosure of via2 by capm,,N/A
+5,Min spacing between capm and via2,,N/A
+6,Maximum Aspect Ratio (Length/Width) ,,N/A
+7,Only rectangular capacitors are allowed,,N/A
+8,"Min space, no overlap, between via and capm",,N/A
+10,"capm must not straddle nwell, diff, tap, poly, li1 and met1 (Rule exempted for capm overlapping capm_2t.dg)",TC,N/A
+11,Min spacing between capm to (met2 not overlapping capm),,N/A
+12,Max area of capm (um^2),,N/A
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(vpp.-),VPP Capacitor ,,sky130
+,Function: Defines VPP capacitor,,
+,,,
+1,Min width of capacitor:dg,,1.430
+1b,Max width of capacitor:dg; Rule not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5 and vpp_with_noLi,,11.350
+1c,"Min/Max width of cell name ""s8rf_xcmvpp1p8x1p8_m3shield """,,3.880
+3,"capacitor:dg must not overlap (tap or diff or poly); (one exception: Poly is allowed to overlap  vpp_with_Met3Shield and vpp_with_Met5PolyShield); (not applicable for vpp_over_Moscap or ""s8rf2_xcmvppx4_2xnhvnative10x4"" or vpp_with_LiShield)",,
+4,capacitor:dg must not straddle (nwell or dnwell),,
+5,Min spacing between (capacitor:dg edge and (poly or li1 or met1 or met2)) to (poly or li1 or met1 or met2) on separate nets (Exempt area of the error shape less than 2.25 (um^2) and run length less than 2.0um); Rule not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5 and vpp_with_noLi,,1.500
+5a,Max pattern density of met3.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5),,0.25
+5b,Max pattern density of met4.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_Met5 and vpp_over_MOSCAP),,0.3
+5c,"Max pattern density of met5.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_Met5 and vpp_over_MOSCAP and vpp_with_noLi); (one exception: rules does apply to cell ""s8rf2_xcmvpp11p5x11p7_m1m4"" and ""s8rf2_xcmvpp_hd5_atlas*"")",,0.4
+8,Min enclosure of capacitor:dg by nwell,,1.500
+9,Min spacing of capacitor:dg to nwell (not applicable for vpp_over_MOSCAP),,1.500
+10,vpp capacitors must not overlap; Rule checks for capacitor.dg overlapping more than one pwell pin,,
+11,Min pattern density of (poly and diff) over capacitor.dg; (vpp_over_Moscap only),,0.87
+12a,"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp8p6x7p9_m3_lim5shield""  must overlap with size 2.01 x 2.01 (no other met4 shapes allowed)",,9.00
+12b,"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp11p5x11p7_m3_lim5shield""  must overlap with size 2.01 x 2.01 (no other met4 shapes allowed)",,16.00
+12c,"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp4p4x4p6_m3_lim5shield""  must overlap with size 1.5 x 1.5 (no other met4 shapes allowed)",,4.00
+13,Min space of met1 to met1inside VPP capacitor,Cu,0.160
+14,Min space of met2 to met2 inside VPP capacitor,Cu,0.160
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(m1.-),Met1,,sky130
+,"Function: Defines first level of metal interconnects, buses etc;",,
+,,,
+.X.1,"Algorithm should flag errors, for met1, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm1 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. NOTE: Required for IP, Recommended for Chip-level.",RC,
+1,Width of metal1,,0.140
+2,Spacing of metal1 to metal1,,0.140
+3a,Min. spacing of features attached to or extending from huge_met1 for a distance of up to  0.280 um to metal1 (rule not checked over non-huge met1 features),,0.280
+3b,Min. spacing of huge_met1 to metal1 excluding features checked by m1.3a,,0.280
+4,Mcon must be enclosed by Met1 by at least …(Rule exempted for cell names documented in rule m1.4a),P,0.030
+4a,"Mcon must be enclosed by Met1 by at least (for cell names ""s8cell_ee_plus_sseln_a"", ""s8cell_ee_plus_sseln_b"", ""s8cell_ee_plus_sselp_a"", ""s8cell_ee_plus_sselp_b"", ""s8fpls_pl8"", and ""s8fs_cmux4_fm"")",P,0.005
+5,Mcon must be enclosed by Met1 on one of two adjacent sides by at least …,"P, Al",0.060
+6,Min metal 1 area [um2],,0.083
+7,Min area of metal1 holes [um2],,0.140
+pd.1,Min MM1_oxide_Pattern_density,"RR, Al",0.7
+pd.2a,Rule m1.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,"A, Al",700
+pd.2b,Rule m1.pd.1 has to be checked by dividing the chip into steps of …,"A, Al",70
+11,Max width of metal1after slotting,"Cu, NC",4.000
+12,Add slots and remove vias and contacts if met1 wider than…..,Cu,3.200
+13,Max pattern density (PD) of met1,Cu,0.77
+14,Met1 PD window size ,Cu,50.000
+14a,Met1 PD window step,Cu,25.000
+15,Mcon must be enclosed by met1 on one of two adjacent sides by at least …,Cu,0.030
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(via.-),Via,,sky130
+,Function: Defines contact between met1  and met2,,
+,,,
+1a,Min and max L and W of via outside :drc_tag:`areaid.mt`,Al,0.150
+1b,"Three sizes of square Vias allowed inside areaid:mt: 0.150um, 0.230um and 0.280um",Al,
+2,Spacing of via to via,Al,0.170
+3,Only min. square vias are allowed except die seal ring where vias are (Via CD)*L,,0.2*L
+4a,0.150 um Via must be enclosed by Met1 by at least …,,0.055
+4b,"Inside :drc_tag:`areaid.mt`, 0.230 um Via must be enclosed by met1 by atleast",Al,0.030
+4c,"Inside :drc_tag:`areaid.mt`, 0.280 um Via must be enclosed by met1 by atleast",Al,0.000
+5a,0.150 um Via must be enclosed by Met1 on one of two adjacent sides by at least …,,0.085
+5b,"Inside :drc_tag:`areaid.mt`, 0.230 um Via must be enclosed by met1 on one of two adjacent sides by at least …",Al,0.060
+5c,"Inside :drc_tag:`areaid.mt`, 0.280 um Via must be enclosed by met1 on one of two adjacent sides by at least …",Al,0.000
+11,Min and max L and W of via outside :drc_tag:`areaid.mt`,Cu,0.180
+12,Min spacing between vias,Cu,0.130
+13,Max of 5 vias within …,Cu,0.350
+14,0.180 um Via must be enclosed by parallel edges of Met1 by at least …,Cu,0.040
+irdrop.1,"For 1 <= n <= 2 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.0
+irdrop.2,"For 3 <= n <= 15 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.6
+irdrop.3,"For 16 <= n <= 30 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.8
+irdrop.4,"For n > 30 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.9
+14a,0.180 um Via must be enclosed by 45 deg edges of Met1 by at least …,Cu,0.037
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(m2.-),Metal 2,,sky130
+,"Function: Defines second level of metal interconnects, buses etc",,
+,,,
+.X.1,"Algorithm should flag errors, for met2, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm2 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. Required for IP, Recommended for Chip-level.",RC,
+1,Width of metal 2,,0.140
+2,Spacing of metal 2 to metal 2,,0.140
+3a,Min. spacing of features attached to or extending from huge_met2 for a distance of up to  0.280 um to metal2 (rule not checked over non-huge met2 features),,0.280
+3b,Min. spacing of huge_met2 to metal2 excluding features checked by m2.3a,,0.280
+3c,"Min spacing between floating_met2 with AR_met2_A >= 0.05 and AR_met2_B =< 0.032, outside areaid:sc must be greater than",RR,0.145
+4,Via must be enclosed by Met2 by at least … ,"P, Al",0.055
+5,Via must be enclosed by Met2 on one of two adjacent sides by at least …,Al,0.085
+6,Min metal2 area [um2],,0.0676
+7,Min area of metal2 holes [um2],,0.140
+pd.1,Min MM2_oxide_Pattern_density,RR,0.7
+pd.2a,Rule m2.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700
+pd.2b,Rule m2.pd.1 has to be checked by dividing the chip into steps of …,A,70
+11,Max width of metal2,Cu,4.000
+12,Add slots and remove vias and contacts if met2 wider than…..,Cu,3.200
+13,Max pattern density (PD) of metal2,Cu,0.77
+14,Met2 PD window size ,Cu,50.000
+14a,Met2 PD window step,Cu,25.000
+15,Via must be enclosed by met2 by at least…,Cu,0.040
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(via2.-),Via2,,sky130
+,Function: Via2 connects met2 to met3 in the SKY130T*/SKY130P*/SP8Q/SP8P* flows and met2/capm to met3 in the SKY130DI* flow.,,
+,,,
+X.1,Via2 connects met2 to met3 in the SKY130T*/SKY130P*/SP8Q/SP8P* flow and met2/capm to met3 in the SKY130DI* flow. ,,
+1a,Min and max L and W of via2 (except for rule via2.1b/1c/1d/1e/1f),Al,0.200
+1b,"Three sizes of square Vias allowed inside areaid:mt: 0.280um, 1.2 um and 1.5 um",Al,N/A
+1c,Two sizes of square Vias allowed inside areaid:mt: 1.2 um and 1.5 um,Al,N/A
+1d,"Four sizes of square Vias allowed inside areaid:mt: 0.2um, 0.280um, 1.2 um and 1.5 um",Al,
+1e,"Three sizes of square Vias allowed inside areaid:mt: 0.8um, 1.2 um and 1.5 um",Al,N/A
+1f,Two sizes of square Vias allowed outside areaid:mt: 0.8um and 1.2 um,Al,N/A
+2,Spacing of via2 to via2,Al,0.200
+3,Only min. square via2s are allowed except die seal ring where via2s are (Via2 CD)*L,Al,0.2*L
+4,Via2 must be enclosed by Met2 by at least …,Al,0.040
+4a,"Inside :drc_tag:`areaid.mt`, 1.5 um Via2 must be enclosed by met2 by atleast",,0.140
+5,Via2 must be enclosed by Met2 on one of two adjacent sides by at least …,Al,0.085
+11,Min and max L and W of via2,Cu,0.210
+12,Min spacing between via2's,Cu,0.180
+13,Min spacing between via2 rows,Cu,0.200
+14,Via2 must be enclosed by met2 by atleast,Cu,0.035
+irdrop.1,"For 1 <= n <= 2 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.0
+irdrop.2,"For 3 <= n <= 4 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.6
+irdrop.3,"For 5 <= n <= 30 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.79
+irdrop.4,"For n > 30 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.9
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(m3.-),Metal 3,,sky130
+,"Function: Defines third level of metal interconnects, buses etc",,
+,,,
+.X.1,"Algorithm should flag errors, for met3, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm3 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. NOTE: Required for IP, Recommended for Chip-level.",RC,
+1,Width of metal 3,,0.300
+2,Spacing of metal 3 to metal 3,,0.300
+3a,Min. spacing of features attached to or extending from huge_met3 for a distance of up to 0.480 um to metal3  (rule not checked over non-huge met3 features),,N/A
+3b,Min. spacing of huge_met3 to metal3 excluding features checked by m3.3a,,N/A
+3c,Min. spacing of features attached to or extending from huge_met3 for a distance of up to 0.400 um to metal3  (rule not checked over non-huge met3 features),,0.400
+3d,Min. spacing of huge_met3 to metal3 excluding features checked by m3.3a,,0.400
+4,Via2 must be enclosed by Met3 by at least …,Al,0.065
+5,Via2 must be enclosed by Met3 on one of two adjacent sides by at least …,,N/A
+5a,Via2 must be enclosed by Met3 on all sides by at least …(Rule not checked on a layout when it satisfies both rules m3.4 and m3.5),,N/A
+6,Min area of metal3 ,,0.240
+7,Min area of metal3 holes [um2],Cu,0.200
+pd.1,Min MM3_oxide_Pattern_density,RR,0.7
+pd.2a,Rule m3.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700
+pd.2b,Rule m3.pd.1 has to be checked by dividing the chip into steps of …,A,70
+11,Max width of metal3,Cu,4.000
+12,Add slots and remove vias and contacts if wider than…..,Cu,3.200
+13,Max pattern density (PD) of metal3,Cu,0.77
+14,Met3 PD window size ,Cu,50.000
+14a,Met3 PD window step,Cu,25.000
+15,Via2 must be enclosed by met3 by at least…,Cu,0.060
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(via3.-),Via3,,sky130
+,Function: Via3 connects met3 to met4 in the SKY130Q*/SKY130P*/SP8Q/SP8P* flow ,,
+,,,
+1,Min and max L and W of via3 (except for rule via3.1a),Al,0.200
+1a,Two sizes of square via3 allowed inside :drc_tag:`areaid.mt`: 0.200um and 0.800um,Al,
+2,Spacing of via3 to via3,Al,0.200
+3,Only min. square via3s are allowed except die seal ring where via3s are (Via3 CD)*L,,0.2*L
+4,Via3 must be enclosed by Met3 by at least …,Al,0.060
+5,Via3 must be enclosed by Met3 on one of two adjacent sides by at least …,Al,0.090
+11,Min and max L and W of via3,Cu,0.210
+12,Min spacing between via2's,Cu,0.180
+13,Via3 must be enclosed by Met3 by at least …,Cu,0.055
+14,Min spacing between via3 rows,Cu,0.350
+irdrop.1,"For 1 <= n <= 2 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.0
+irdrop.2,"For 3 <= n <= 15 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.6
+irdrop.3,"For 16 <= n <= 30 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.8
+irdrop.4,"For n > 30 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.9
+,,,
+(nsm.-),Nitride Seal Mask,,sky130
+,,,
+1,Min. width of nsm, ,3.000
+2,Min. spacing of nsm to nsm,,4.000
+3,"Min spacing, no overlap, between NSM_keepout to diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5). Exempt the following from the check: (a) cell name ""nikon*"" and (b) diff ring inside :drc_tag:`areaid.sl` ",Al,1.000
+3a,"Min enclosure of diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5) by :drc_tag:`areaid.ft`. Exempt the following from the check: (a) cell name ""s8Fab_crntic*""  (b)  blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)",,3.000
+3b,"Min spacing between :drc_tag:`areaid.dt` to diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5). Exempt the following from the check: (a) blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)",,3.000
+,,,
+(indm.-),Inductor metal,,sky130
+,"Function: Defines third level of metal interconnects, buses and inductor; top_indmMetal is met3 for SKY130D* flows; Similarly top_padVia is Via2 for SKY130D*",,
+,,,
+1,Min width of top_indmMetal,,N/A
+2,Min spacing between two top_indmMetal,,N/A
+3,top_padVia must  be enclosed by top_indmMetal by atleast,,N/A
+4,Min area of top_indmMetal,,N/A
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(m4.-),Metal 4,,sky130
+,Function: Defines Fourth level of metal interconnects;,,
+,,,
+.X.1,"Algorithm should flag errors, for met4, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm4 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. Required for IP, Recommended for Chip-level.",RC,
+1,Min width of met4,,0.300
+2,Min spacing between two met4,,0.300
+3,via3 must  be enclosed by met4 by atleast,Al,0.065
+4,Min area of met4 (rule exempted for probe pads which are exactly 1.42um by 1.42um),,N/A
+4a,Min area of met4 ,,0.240
+5a,Min. spacing of features attached to or extending from huge_met4 for a distance of up to  0.400 um to metal4 (rule not checked over non-huge met4 features),,0.400
+5b,Min. spacing of huge_met4 to metal4 excluding features checked by m4.5a,,0.400
+7,Min area of meta4 holes [um2],Cu,0.200
+pd.1,Min MM4_oxide_Pattern_density,RR,0.7
+pd.2a,Rule m4.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700
+pd.2b,Rule m4.pd.1 has to be checked by dividing the chip into steps of …,A,70
+11,Max width of metal4,Cu,10.000
+12,Add slots and remove vias and contacts if wider than…..,Cu,10.000
+13,Max pattern density (PD) of metal4; met4 overlapping pdm areas are excluded from the check,Cu,0.77
+14,Met4 PD window size ,Cu,50.000
+14a,Met4 PD window step,Cu,25.000
+15,Via3 must be enclosed by met4 by at least…,Cu,0.060
+16,Min enclosure of pad by met4,Cu,0.850
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(via4.-),Via4,,sky130
+,Function: Via4 connects met4 to met5 in the SKY130P*/SP8P* flow ,,
+,,,
+1,Min and max L and W of via4,,0.800
+2,Spacing of via4 to via4,,0.800
+3,Only min. square via4s are allowed except die seal ring where via4s are (Via4 CD)*L,,0.8*L
+4,Via4 must be enclosed by Met4 by at least …,,0.190
+irdrop.1,"For 1 <= n <= 4 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.0
+irdrop.2,"For 5 <= n <= 10 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.2
+irdrop.3,"For 11 <= n <= 100 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.5
+irdrop.4,"For n > 100 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than… ","Cu, IR",0.8
+,,,
+(m5.-),Metal 5,,sky130
+,Function: Defines Fifth level of metal interconnects;,,
+,,,
+1,Min width of met5,,1.600
+2,Min spacing between two met5,,1.600
+3,via4 must  be enclosed by met5 by atleast,,0.310
+4,"Min area of met5 (For all flows except SKY130PIR*/SKY130PF*, the rule is exempted for probe pads which are exactly 1.42um by 1.42um)",,4.000
+,,,
+(pad.-),Pad,,sky130
+,Function: Opens the passivation,,
+,,,
+2,Min spacing of pad:dg to pad:dg,,1.270
+3,Max area of hugePad NOT top_metal ,,30000
+,,,
+(rdl.-),Cu Inductor,,sky130
+,Function: Defines the Cu Inductor. Connects to met5 through the pad opening,,
+,,,
+1,Min width of rdl,,10
+2,Min spacing between two rdl,,10
+3,"Min enclosure of pad by rdl, except rdl interacting with bump",,10.750
+4,Min spacing between rdl and outer edge of the seal ring,,15.000
+5,(rdl OR ccu1m.mk) must not overlap :drc_tag:`areaid.ft`. Exempt the following from the check: (a)  blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption),,
+6,"Min spacing of rdl to pad, except rdl interacting with bump",,19.660
+,,,
+(mf.-),Metal Fuse,,sky130
+,Function: Defines metal fuses,,
+,For SKY130D* and SKY130TM* CADflow use MM2 for Metal Fuse,,
+,For SP8P*/SKY130P* (PLM) CADflow use MM4 for Metal Fuse,,
+1,Min. and max width of fuse,,0.800
+2,Length of fuse,,7.200
+3,Spacing between centers of adjacent fuses,,2.760
+4,Spacing between center of fuse and fuse_metal (fuse shields are exempted),,3.300
+5,Max. extension of fuse_metal beyond fuse boundary ,,0.830
+6,Spacing (no overlapping) between fuse center and Metal1,,3.300
+7,Spacing (no overlapping) between fuse center and LI,,3.300
+8,Spacing (no overlapping) between fuse center and poly,,2.660
+9,Spacing (no overlapping) between fuse center and tap,,2.640
+10,Spacing (no overlapping) between fuse center and diff,,3.250
+11,Spacing (no overlapping) between fuse center and nwell,,3.320
+12,Size of  fuse_shield, ,0.5x2.4
+13,Min. spacing of center of fuse to fuse_shield,,2.200
+14,Max. spacing of center of fuse to fuse_shield,,3.300
+15,"Fuse_shields are only placed between periphery metal (i.e., without fuse:dg) and non-isolated edges of fuse as defined by mf.16",,
+16,The edge of a fuse is considered non-isolated if wider than or equal to mf.2 and spaced to fuse_metal by less than …,,4.000
+17,Offset between fuse_shields center and fuse center,NC,0.000
+18,Min and max space between fuse_shield and fuse_metal (opposite edges). Rule checked within 1 gridpoint.,,0.600
+19,Spacing (no overlapping) between fuse center and Metal2,,3.300
+20,Only one fuse per metal line allowed,,
+21,"Min spacing , no overlap, between metal3 and fuse center",,3.300
+22,Min spacing between fuse_contact to fuse_contact,,1.960
+23,Spacing (no overlapping) between fuse center and Metal4,,N/A
+24,Spacing (no overlapping) between fuse center and Metal5,,3.300
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+Section G2b: Rules for HV devices,,,
+,,,
+(hvi.-),HVI,,sky130
+,Function: Defines thick oxide for high voltage devices,,
+,,,
+1,Min width of Hvi,P,0.600
+2a,Min spacing of Hvi to Hvi,P,0.700
+2b,Manual merge if space is below minimum,,
+4,Hvi must not overlap tunm,,
+5,Min space between hvi and nwell (exclude coincident edges),,0.700
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(nwell.-),High Voltage Nwell,,sky130
+,"Function: Defines rules for HV nwell; All nwell connected to voltages greater than 1.8V must be enclosed by hvi; Nets connected to LV nwell or nwell overlapping hvi but connected to LV voltages (i.e 1.8V) should be tagged ""lv_net"" using text.dg; This tag should be only on Li layer",,
+,,,
+8,Min space between HV_nwell  and any nwell on different nets,,2.000
+9,(Nwell overlapping hvi) must be enclosed by hvi,,
+10,"LVnwell and HnWell should not be on the same net (for the purposes of this check, short the connectivity through resistors); Exempt HnWell with li nets tagged ""lv_net"" using text.dg and Hnwell connected to nwell overlapping :drc_tag:`areaid.hl`",TC,
+11,"Nwell connected to the nets mentioned in the ""Power_Net_Hv"" field of the latcup GUI must be enclosed by hvi (exempt nwell inside :drc_tag:`areaid.hl`). Also for the purposes of this check, short the connectivity through resistors. The rule will be checked in the latchup run and exempted for cells ""s8tsg5_tx_ibias_gen"" and ""s8bbcnv_psoc3p_top_18"",  ""rainier_top, indus_top*"", ""rainier_top, manas_top, ccg3_top""",,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(difftap.-),High Voltage Diff/Tap,,sky130
+,Function: Defines rules for HV diff/tap,,
+,,,
+14,"Min width of diff inside Hvi, except HV Pdiff resistors (difftap.14a)",P,0.290
+14a,"Min width of diff inside Hvi, HV Pdiff resistors only",P,0.150
+15a,Min space of Hdiff to Hdiff ,P,0.300
+15b,Min space of n+diff to non-abutting p+tap inside Hvi,P,0.370
+16,Min width tap butting diff on one or two sides inside Hvi (rule exempted inside UHVI),,0.700
+17,P+ Hdiff or Pdiff inside areaid:hvnwell must be enclosed by Hv_nwell by at least ….[Rule exempted inside UHVI],"DE, NE",0.330
+18,Spacing of N+ diff to HV_nwell (rule exempted inside UHVI),"DE, NE",0.430
+19,N+ Htap must be enclosed by Hv_nwell by at least …Rule exempted inside UHVI.,NE,0.330
+20,Spacing of P+ tap to HV_nwell (Exempted for p+tap butting pwell.rs; rule exempted inside UHVI),,0.430
+21,Diff or tap cannot straddle Hvi ,P,
+22,Min enclosure of Hdiff or Htap by Hvi. Rule exempted inside UHVI.,P,0.180
+23,Space between diff or tap outside Hvi and Hvi,P,0.180
+24,Spacing of nwell to N+ Hdiff (rule exempted inside UHVI),"DE, NE",0.430
+25,Min space of N+ Hdiff inside HVI across non-abutting P+_tap,NC,1.070
+26,Min spacing between pwbm to difftap outside UHVI,,N/A
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(poly.-),High Voltage Poly,,sky130
+,Function: Defines rules for HV poly,,
+,,,
+13,Min width of poly over diff inside Hvi,P,0.500
+14,(poly and diff) cannot straddle Hvi,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(hvntm.-),Hvntm,,sky130
+,Function: Defines tip implants for the HV NMOS,,
+,,,
+X.1 ,Hvntm can be drawn inside HVI. Drawn layer will be OR-ed with the CL and rechecked for CLDRC,,
+1,Width of hvntm,P,0.700
+2,Spacing of hvntm to hvntm,P,0.700
+3,Min. enclosure of (n+_diff inside Hvi) but not overlapping :drc_tag:`areaid.ce` by hvntm,P,0.185
+4,"Space, no overlap, between n+_diff outside Hvi and hvntm",P,0.185
+5,"Space, no overlap, between p+_diff  and hvntm","P, DE",0.185
+6a,"Space, no overlap, between p+_tap and hvntm (except along the diff-butting edge)",P,0.185
+6b,"Space, no overlap, between p+_tap and hvntm along the diff-butting edge",P,0.000
+7,hvntm must enclose ESD_nwell_tap inside hvi by atleast,P,0.000
+9,Hvntm must not overlap :drc_tag:`areaid.ce`,,
+10,Hvntm must overlap hvi,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(denmos.-),Denmos,,sky130
+,Function: Defines rules for the 16V Drain extended NMOS devices,,
+,,,
+1,Min width of de_nFet_gate,,1.055
+2,Min width of de_nFet_source not overlapping poly,,0.280
+3,Min width of de_nFet_source overlapping poly,,0.925
+4,Min width of the de_nFet_drain,,0.170
+5,Min/Max extension of de_nFet_source over nwell,,0.225
+6,Min/Max spacing between de_nFet_drain and de_nFet_source,,1.585
+7,Min channel width for de_nFet_gate,,5.000
+8,90 degree angles are not permitted for nwell overlapping de_nFET_drain,,
+9a,"All bevels on nwell are 45 degree, 0.43 um from corners",,NC
+9b,"All bevels on de_nFet_drain are 45 degree, 0.05 um from corners",,NC
+10,Min enclosure of de_nFet_drain by nwell,,0.660
+11,Min spacing between p+ tap and (nwell overlapping de_nFet_drain),,0.860
+12,Min spacing between nwells overlapping de_nFET_drain,,2.400
+13,de_nFet_source must be enclosed by nsdm by,,0.130
+14,nvhv FETs must be enclosed by :drc_tag:`areaid.mt`,,N/A
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(depmos.-),Depmos,,sky130
+,Function: Defines rules for the 16V Drain extended NMOS devices,,
+,,,
+1,Min width of de_pFet_gate,,1.050
+2,Min width of de_pFet_source not overlapping poly,,0.280
+3,Min width of de_pFet_source overlapping poly,,0.920
+4,Min width of the de_pFet_drain,,0.170
+5,Min/Max extension of de_pFet_source beyond nwell,,0.260
+6,Min/Max spacing between de_pFet_drain and de_pFet_source,,1.190
+7,Min channel width for de_pFet_gate,,5.000
+8,90 degree angles are not permitted for nwell hole overlapping de_pFET_drain,,
+9a,"All bevels on nwell hole are 45 degree, 0.43 um from corners",,NC
+9b,"All bevels on de_pFet_drain are 45 degree, 0.05 um from corners",,NC
+10,Min enclosure of de_pFet_drain by nwell hole,,0.860
+11,Min spacing between n+ tap and (nwell hole enclosing de_pFET_drain),,0.660
+12,de_pFet_source must be enclosed by psdm by,,0.130
+13,pvhv fets( except those with W/L = 5.0/0.66) must be enclosed by :drc_tag:`areaid.mt`,,N/A
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(extd.-),Extended Drain,,sky130
+,Function: Defines rules :drc_tag:`areaid.en`,,
+,,,
+1,Difftap cannot straddle areaid:en,,
+2,DiffTap must have 2 or 3 coincident edges with areaid:en if enclosed by areaid:en,,
+3,Poly must not be entirely overlapping difftap in areaid:en,,
+4,"Only cell name ""s8rf_n20vhv1*"" is a valid cell name for n20vhv1 device  (Check in LVS as invalid device)",,N/A
+5,"Only cell name ""s8rf_n20vhviso1"" is a valid cell name for n20vhviso1 device  (Check in LVS as invalid device)",,N/A
+6,"Only cell name ""s8rf_p20vhv1"" is a valid cell name for p20vhv1 device  (Check in LVS as invalid device)",,N/A
+7,"Only cell name ""s8rf_n20nativevhv1*"" is a valid cell name for n20nativevhv1 device  (Check in LVS as invalid device)",,N/A
+8,"Only cell name ""s8rf_n20zvtvhv1*"" is a valid cell name for n20zvtvhv1 device  (Check in LVS as invalid device)",,N/A
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(hv.-.-),High Voltage Rules,,sky130
+,,,
+Note,High voltage rule apply for an operating voltage range of 5.5 - 12V; Nodes switching between 0 to 5.5V do not need to follow these rules,,
+.X.1,High voltage source/drain regions must be tagged by diff:hv,,
+.X.3,"High voltage poly can be drawn over multiple diff regions that are ALL reverse-biased by at least 300 mV (existence of reverse-bias is not checked by the CAD flow).  It can also be drawn over multiple diffs when all sources and all drain are shorted together. In these case, the high voltage poly can be tagged with the text:dg label with a value “hv_bb”.  Exceptions to this use of the hv_bb label must be approved by technology.  Under certain bias conditions, high voltage poly tagged with hv_bb can cross an nwell boundary. The poly of the drain extended device crosses nwell by construction and can be tagged with the ""hv_bb"" label. Use of the hv_bb label on high voltage poly crossing an nwell boundary must be approved by technology. All high voltage poly tagged with hv_bb will not be checked to hv.poly.1, hv.poly.2, hv.poly.3 and hv.poly.4.",,
+.X.4,Any piece of layout that is shorted to hv_source/drain becomes a high voltage feature.,,
+.X.5,"In cases where an hv poly gate abuts only low voltage source and drain, the poly gate can be tagged with the text:dg label with a value ""hv_lv"".  In this case, the ""hv_lv"" tagged poly gate and its extensions will not be checked to hv.poly.6, but is checked by rules in the poly.-.- section.  The use of the hv_lv label must be approved by technology.",,
+.X.6,"Nwell biased at voltages >= 7.2V must be tagged with text ""shv_nwell""",NC,
+.nwell.1,"Min spacing of nwell tagged with text ""shv_nwell"" to any nwell on different nets",,2.500
+.diff.1a,Minimum hv_source/drain spacing to diff for edges of hv_source/drain and diff not butting tap,,0.300
+.diff.1b,Minimum spacing of (n+/p+ diff resistors and diodes) connected to hv_source/drain to diff,,0.300
+.diff.2,Minimum spacing of nwell connected to hv_source/drain to n+ diff,DE,0.430
+.diff.3a,Minimum n+ hv_source/drain spacing to nwell,,0.550
+.diff.3b,Minimum spacing of (n+ diff resistors and diodes) connected to hv_source/drain to nwell,,0.550
+.poly.1,Hv poly feature hvPoly (including hv poly resistors) can be drawn over only one diff region and is not allowed to cross nwell boundary except (1) as allowed in rule .X.3 and (2) nwell hole boundary in depmos,,
+.poly.2,Min spacing of hvPoly (including hv poly resistor) on field to diff (diff butting hvPoly are excluded),,0.300
+.poly.3,Min spacing of hvPoly (including hv poly resistor) on field to n-well (exempt poly stradding nwell in a denmos/depmos),,0.550
+.poly.4,Enclosure of hvPoly (including hv poly resistor) on field by n-well (exempt poly stradding nwell in a denmos/depmos),,0.300
+.poly.6a,Min extension of poly beyond hvFET_gate (exempt poly extending beyond diff along the S/D direction in a denmos/depmos),,0.160
+.poly.6b,Extension of hv poly beyond FET_gate (including hvFET_gate; exempt poly extending beyond diff along the S/D direction in a denmos/depmos),,0.160
+.poly.7,Minimum overlap of hv poly ring_FET and diff,,
+.poly.8,Any poly gate abutting hv_source/drain becomes a hvFET_gate,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(vhvi.-.-),VHVI - Very HV ID and Rules,,sky130
+,Function: Identify nets working between 12-16V,,
+,,,
+.vhv.1,Terminals operating at nominal 12V (maximum 16V) bias must be tagged as Very-High-Voltage (VHV) using vhvi:dg layer,,NC
+.vhv.2,A source or drain of a drain-extended device can be tagged by vhvi:dg. A device with either source or drain (not both) tagged with vhvi:dg serves as a VHV propagation stopper,,NC
+.vhv.3,Any feature connected to VHVSourceDrain becomes a very-high-voltage feature,,NC
+.vhv.4,Any feature connected to VHVPoly becomes a very-high-voltage feature,,NC
+.vhv.5,"Diffusion that is not a part of a drain-extended device (i.e., diff not areaid:en) must not be on the same net as VHVSourceDrain. Only diffusion inside :drc_tag:`areaid.ed` and LV diffusion tagged with vhvi:dg are exempted.",,
+.vhv.6,"Poly resistor can act as a VHV propagation stopper. For this, it should be tagged with text ""vhv_block""",,NC
+1,Min width of vhvi:dg,,0.020
+2,Vhvi:dg cannot overlap areaid:ce,,
+3,VHVGate must overlap hvi:dg,,
+4,Poly connected to the same net as a VHVSourceDrain must be tagged with vhvi:dg layer,,
+5,Vhvi:dg cannot straddle VHVSourceDrain,,
+6,Vhvi:dg overlapping VHVSourceDrain must not overlap poly,,
+7,Vhvi:dg cannot straddle VHVPoly,,
+8,"Min space between nwell tagged with vhvi:dg and deep nwell, nwell, or n+diff on a separate net (except for n+diff overlapping nwell tagged with vhvi:dg).",,11.240
+,,,
+(uhvi.-.-),UHVI - Ultra HV ID and Rules,,sky130
+,Function: Identify nets working between 20V,,
+,,,
+1,diff/tap can not straddle UHVI,,N/A
+2,poly can not straddle UHVI,,N/A
+3,pwbm.dg must be enclosed by UHVI (exempt inside :drc_tag:`areaid.lw`),,N/A
+4,dnw.dg can not straddle UHVI,,N/A
+5,UHVI must enclose :drc_tag:`areaid.ext`,,N/A
+6,UHVI must enclose dnwell,,N/A
+7,natfet.dg must be enclosed by UHVI layer by at least,,N/A
+8,Minimum width of natfet.dg,,N/A
+9,Minimum Space spacing of natfet.dg ,,N/A
+10,natfet.dg layer is not allowed,,N/A
+, ,,
+(ulvt-.-),:drc_tag:`areaid.low_vt` for UHV Diodes ,,sky130
+,Function: Identify dnwdiodehv_Psub(BV~60V),,
+,,,NA
+1,":drc_tag:`areaid.low_vt` must enclose dnw for the UHV dnw-psub diode texted ""condiodeHvPsub""",,NA
+2,":drc_tag:`areaid.low_vt` must enclose pwbm.dg for the UHV dnw-psub diode texted ""condiodeHvPsub""",,NA
+3,:drc_tag:`areaid.low_vt` can not straddle UHVI,,NA
+,,,
+(pwres.-.-),Pwell resistor,,sky130
+,Function: Identify pwell resistors,,
+,,,
+1,Pwell resistor has to be enclosed by the res layer,NC,
+2,Min/Max width of pwell resistor ,,2.650
+3,Min length of pwell resistor,,26.500
+4,Max length of pwell resistor,,265.00
+5,Min/Max spacing of tap inside the pwell resistor to nwell ,,0.220
+6,Min/Max width of tap inside the pwell resistor ,,0.530
+7a,Every pwres_terminal must enclose 12 licon1,,
+7b,Every pwres_terminal must enclose 12 mcons if routed through metal1,,
+8,Diff or poly is not allowed in the pwell resistor.,,
+9,Nwell surrounding the pwell resistor must have a full ring of contacted tap strapped with metal.,,
+10,The res layer must abut pwres_terminal on opposite and parallel edges,,
+11,The res layer must abut nwell on opposite and parallel edges not checked in Rule pwres.10,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+(rfdiode.-.-),Areaid.re for RF Diodes ,,sky130
+,Function: Identify RF diodes; Used for RCX,,
+,,,
+1,Only 90 degrees allowed for :drc_tag:`areaid.re`,,
+2,:drc_tag:`areaid.re` must be coincident with nwell for the rf nwell diode,,
+3,:drc_tag:`areaid.re` must be coincident with innwer edge of the nwell ring for the rf pwell-deep nwell diode,,
+,,,
+,,,
+,Allowed PNP layout,,
+,Layout: pnppar,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,Allowed NPN layout,,
+,Layout: npnpar1x1,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
+,,,
diff --git a/libraries/sky130_fd_sc_ms/latest b/libraries/sky130_fd_sc_ms/latest
new file mode 120000
index 0000000..5eb312c
--- /dev/null
+++ b/libraries/sky130_fd_sc_ms/latest
@@ -0,0 +1 @@
+v0.0.0
\ No newline at end of file
diff --git a/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/README.rst b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/README.rst
new file mode 100644
index 0000000..bd52d32
--- /dev/null
+++ b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/README.rst
@@ -0,0 +1,33 @@
+
+:cell_name:`sky130_fd_sc_ms__xor3`
+==================================
+
+.. list-table::
+   :header-rows: 1
+   :widths: 50 50
+
+   * - Without Power Pins
+     - With Power Pins
+
+   * -
+       .. no-license:: sky130_fd_sc_ms__xor3.blackbox.v
+          :language: verilog
+          :linenos:
+
+     -
+       .. no-license:: sky130_fd_sc_ms__xor3.pp.blackbox.v
+          :language: verilog
+          :linenos:
+
+   * -
+       .. image:: sky130_fd_sc_ms__xor3.symbol.svg
+     -
+       .. image:: sky130_fd_sc_ms__xor3.pp.symbol.svg
+
+   * - .. image:: sky130_fd_sc_ms__xor3.schematic.svg
+     - .. image:: sky130_fd_sc_ms__xor3.pp.schematic.svg
+
+   * - .. image:: sky130_fd_sc_ms__xor3.schematic.svg
+     - .. image:: sky130_fd_sc_ms__xor3.pp.schematic.svg
+
+
diff --git a/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.behavioral.pp.v b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.behavioral.pp.v
new file mode 100644
index 0000000..6b47ebb
--- /dev/null
+++ b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.behavioral.pp.v
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_MS__XOR3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_MS__XOR3_BEHAVIORAL_PP_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
+
+`celldefine
+module sky130_fd_sc_ms__xor3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire xor0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    xor                                xor0        (xor0_out_X       , A, B, C               );
+    sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_MS__XOR3_BEHAVIORAL_PP_V
\ No newline at end of file
diff --git a/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.behavioral.v b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.behavioral.v
new file mode 100644
index 0000000..92d45e1
--- /dev/null
+++ b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.behavioral.v
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_MS__XOR3_BEHAVIORAL_V
+`define SKY130_FD_SC_MS__XOR3_BEHAVIORAL_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ms__xor3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire xor0_out_X;
+
+    //  Name  Output      Other arguments
+    xor xor0 (xor0_out_X, A, B, C        );
+    buf buf0 (X         , xor0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_MS__XOR3_BEHAVIORAL_V
\ No newline at end of file
diff --git a/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.blackbox.v b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.blackbox.v
new file mode 100644
index 0000000..b198396
--- /dev/null
+++ b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.blackbox.v
@@ -0,0 +1,57 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_MS__XOR3_BLACKBOX_V
+`define SKY130_FD_SC_MS__XOR3_BLACKBOX_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ms__xor3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_MS__XOR3_BLACKBOX_V
diff --git a/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.functional.pp.v b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.functional.pp.v
new file mode 100644
index 0000000..4a2b9ef
--- /dev/null
+++ b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.functional.pp.v
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_MS__XOR3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_MS__XOR3_FUNCTIONAL_PP_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
+
+`celldefine
+module sky130_fd_sc_ms__xor3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire xor0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    xor                                xor0        (xor0_out_X       , A, B, C               );
+    sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_MS__XOR3_FUNCTIONAL_PP_V
\ No newline at end of file
diff --git a/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.functional.v b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.functional.v
new file mode 100644
index 0000000..0f3372a
--- /dev/null
+++ b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.functional.v
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_MS__XOR3_FUNCTIONAL_V
+`define SKY130_FD_SC_MS__XOR3_FUNCTIONAL_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ms__xor3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Local signals
+    wire xor0_out_X;
+
+    //  Name  Output      Other arguments
+    xor xor0 (xor0_out_X, A, B, C        );
+    buf buf0 (X         , xor0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_MS__XOR3_FUNCTIONAL_V
\ No newline at end of file
diff --git a/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.pp.blackbox.v b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.pp.blackbox.v
new file mode 100644
index 0000000..c964bb8
--- /dev/null
+++ b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.pp.blackbox.v
@@ -0,0 +1,58 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_MS__XOR3_PP_BLACKBOX_V
+`define SKY130_FD_SC_MS__XOR3_PP_BLACKBOX_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ms__xor3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_MS__XOR3_PP_BLACKBOX_V
diff --git a/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.pp.symbol.svg b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.pp.symbol.svg
new file mode 100644
index 0000000..c69dc71
--- /dev/null
+++ b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.pp.symbol.svg
@@ -0,0 +1,67 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<!-- Created by Symbolator http://kevinpt.github.io/symbolator -->
+<svg xmlns="http://www.w3.org/2000/svg"
+xmlns:xlink="http://www.w3.org/1999/xlink"
+xml:space="preserve"
+width="191" height="295" viewBox="-25 -56 191.0 295.0" version="1.1">
+<style type="text/css">
+<![CDATA[
+.fnt1 { fill:#000000; font-family:Times; font-size:12pt; font-weight:normal; font-style:italic; }
+.fnt2 { fill:#000000; font-family:Helvetica; font-size:12pt; font-weight:normal; font-style:normal; }
+.fnt3 { fill:#000000; font-family:Helvetica; font-size:16pt; font-weight:bold; font-style:normal; }
+.fnt4 { fill:#000000; font-family:Helvetica; font-size:10pt; font-style:normal; }
+.label {fill:#000;
+  text-anchor:middle;
+  font-size:16pt; font-weight:bold; font-family:Sans;}
+.link {fill: #0D47A1;}
+.link:hover {fill: #0D47A1; text-decoration:underline;}
+.link:visited {fill: #4A148C;}
+]]>
+</style>
+<defs>
+
+</defs>
+<rect x="-25" y="-56" width="100%" height="100%" fill="white"/><g transform="translate(0,0)">
+<rect x="0" y="-21.0" width="140" height="105.0" stroke="#000000" fill="#CCFED2" stroke-width="1"/>
+<text class="fnt1" x="70.0" y="-5.0" text-anchor="middle" dy="5.5">Data Signals</text>
+<g transform="translate(0,19)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">A</text>
+</g>
+<g transform="translate(0,41)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">B</text>
+</g>
+<g transform="translate(0,63)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">C</text>
+</g>
+<g transform="translate(140,19)">
+<line x1="20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="-10" y="0" text-anchor="end" dy="5.5">X</text>
+</g>
+</g>
+<g transform="translate(0,105.0)">
+<rect x="0" y="-21.0" width="140" height="127.0" stroke="#000000" fill="#FFBBBB" stroke-width="1"/>
+<text class="fnt1" x="70.0" y="-5.0" text-anchor="middle" dy="5.5">Power</text>
+<g transform="translate(0,19)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">VPB</text>
+</g>
+<g transform="translate(0,41)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">VPWR</text>
+</g>
+<g transform="translate(0,63)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">VGND</text>
+</g>
+<g transform="translate(0,85)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">VNB</text>
+</g>
+</g>
+<rect x="1.0" y="-20.0" width="138.0" height="230.0" stroke="#000000" fill="none" stroke-width="3"/>
+<text class="fnt3" x="70.0" y="-30.0" text-anchor="middle" dy="-1.0">xor3</text>
+<text class="fnt4" x="70.0" y="230.0" text-anchor="middle" dy="1.0">sky130_fd_sc_ms</text>
+</svg>
\ No newline at end of file
diff --git a/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.pp.symbol.v b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.pp.symbol.v
new file mode 100644
index 0000000..1473fef
--- /dev/null
+++ b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.pp.symbol.v
@@ -0,0 +1,53 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_MS__XOR3_PP_SYMBOL_V
+`define SKY130_FD_SC_MS__XOR3_PP_SYMBOL_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ms__xor3 (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B   ,
+    input  C   ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_MS__XOR3_PP_SYMBOL_V
diff --git a/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.schematic.svg b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.schematic.svg
new file mode 100644
index 0000000..73ff300
--- /dev/null
+++ b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.schematic.svg
@@ -0,0 +1,75 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="255" height="129">
+  <style>svg {
+    stroke:#000;
+    fill:none;
+  }
+  text {
+    fill:#000;
+    stroke:none;
+    font-size:10px;
+    font-weight: bold;
+    font-family: "Courier New", monospace;
+  }
+  .nodelabel {
+    text-anchor: middle;
+  }
+  .inputPortLabel {
+    text-anchor: end;
+  }
+  .splitjoinBody {
+    fill:#000;
+  }</style>
+  <g s:type="reduce_xor" transform="translate(77,27)" s:width="33" s:height="25" id="cell_$xor$../skywater-pdk-scratch-new/skywater-pdk/libraries/sky130_fd_sc_ms/v0.0.1/cells/xor3/sky130_fd_sc_ms__xor3.functional.v:52$1">
+    <s:alias val="$xor"/>
+    <s:alias val="$reduce_xor"/>
+    <s:alias val="$_XOR_"/>
+    <path d="M3,0 A30 25 0 0 1 3,25 A30 25 0 0 0 33,12.5 A30 25 0 0 0 3,0" class="cell_$xor$../skywater-pdk-scratch-new/skywater-pdk/libraries/sky130_fd_sc_ms/v0.0.1/cells/xor3/sky130_fd_sc_ms__xor3.functional.v:52$1"/>
+    <path d="M0,0 A30 25 0 0 1 0,25" class="cell_$xor$../skywater-pdk-scratch-new/skywater-pdk/libraries/sky130_fd_sc_ms/v0.0.1/cells/xor3/sky130_fd_sc_ms__xor3.functional.v:52$1"/>
+    <g s:x="3" s:y="5" s:pid="A"/>
+    <g s:x="3" s:y="20" s:pid="B"/>
+    <g s:x="33" s:y="12.5" s:pid="Y"/>
+  </g>
+  <g s:type="reduce_xor" transform="translate(145,34.5)" s:width="33" s:height="25" id="cell_$xor$../skywater-pdk-scratch-new/skywater-pdk/libraries/sky130_fd_sc_ms/v0.0.1/cells/xor3/sky130_fd_sc_ms__xor3.functional.v:52$2">
+    <s:alias val="$xor"/>
+    <s:alias val="$reduce_xor"/>
+    <s:alias val="$_XOR_"/>
+    <path d="M3,0 A30 25 0 0 1 3,25 A30 25 0 0 0 33,12.5 A30 25 0 0 0 3,0" class="cell_$xor$../skywater-pdk-scratch-new/skywater-pdk/libraries/sky130_fd_sc_ms/v0.0.1/cells/xor3/sky130_fd_sc_ms__xor3.functional.v:52$2"/>
+    <path d="M0,0 A30 25 0 0 1 0,25" class="cell_$xor$../skywater-pdk-scratch-new/skywater-pdk/libraries/sky130_fd_sc_ms/v0.0.1/cells/xor3/sky130_fd_sc_ms__xor3.functional.v:52$2"/>
+    <g s:x="3" s:y="5" s:pid="A"/>
+    <g s:x="3" s:y="20" s:pid="B"/>
+    <g s:x="33" s:y="12.5" s:pid="Y"/>
+  </g>
+  <g s:type="outputExt" transform="translate(213,37)" s:width="30" s:height="20" id="cell_X">
+    <text x="15" y="-4" class="nodelabel cell_X" s:attribute="ref">X</text>
+    <s:alias val="$_outputExt_"/>
+    <path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_X"/>
+    <g s:x="0" s:y="10" s:pid="A"/>
+  </g>
+  <g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_A">
+    <text x="15" y="-4" class="nodelabel cell_A" s:attribute="ref">A</text>
+    <s:alias val="$_inputExt_"/>
+    <path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A"/>
+    <g s:x="28" s:y="10" s:pid="Y"/>
+  </g>
+  <g s:type="inputExt" transform="translate(12,87)" s:width="30" s:height="20" id="cell_B">
+    <text x="15" y="-4" class="nodelabel cell_B" s:attribute="ref">B</text>
+    <s:alias val="$_inputExt_"/>
+    <path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_B"/>
+    <g s:x="28" s:y="10" s:pid="Y"/>
+  </g>
+  <g s:type="inputExt" transform="translate(80,97)" s:width="30" s:height="20" id="cell_C">
+    <text x="15" y="-4" class="nodelabel cell_C" s:attribute="ref">C</text>
+    <s:alias val="$_inputExt_"/>
+    <path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_C"/>
+    <g s:x="28" s:y="10" s:pid="Y"/>
+  </g>
+  <line x1="40" x2="80" y1="32" y2="32" class="net_3"/>
+  <line x1="40" x2="52" y1="97" y2="97" class="net_4"/>
+  <line x1="52" x2="52" y1="97" y2="47" class="net_4"/>
+  <line x1="52" x2="80" y1="47" y2="47" class="net_4"/>
+  <line x1="110" x2="148" y1="39.5" y2="39.5" class="net_6"/>
+  <line x1="108" x2="120" y1="107" y2="107" class="net_5"/>
+  <line x1="120" x2="120" y1="107" y2="54.5" class="net_5"/>
+  <line x1="120" x2="148" y1="54.5" y2="54.5" class="net_5"/>
+  <line x1="178" x2="213" y1="47" y2="47" class="net_2"/>
+</svg>
diff --git a/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.specify.v b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.specify.v
new file mode 100644
index 0000000..4d2849c
--- /dev/null
+++ b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.specify.v
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((!B&!C)) (A +=> X) = (0:0:0,0:0:0);
+if ((!B&C)) (A -=> X) = (0:0:0,0:0:0);
+if ((B&!C)) (A -=> X) = (0:0:0,0:0:0);
+if ((B&C)) (A +=> X) = (0:0:0,0:0:0);
+if ((!A&!C)) (B +=> X) = (0:0:0,0:0:0);
+if ((!A&C)) (B -=> X) = (0:0:0,0:0:0);
+if ((A&!C)) (B -=> X) = (0:0:0,0:0:0);
+if ((A&C)) (B +=> X) = (0:0:0,0:0:0);
+if ((!A&!B)) (C +=> X) = (0:0:0,0:0:0);
+if ((!A&B)) (C -=> X) = (0:0:0,0:0:0);
+if ((A&!B)) (C -=> X) = (0:0:0,0:0:0);
+if ((A&B)) (C +=> X) = (0:0:0,0:0:0);
+endspecify
\ No newline at end of file
diff --git a/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.symbol.svg b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.symbol.svg
new file mode 100644
index 0000000..ec8a1bd
--- /dev/null
+++ b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.symbol.svg
@@ -0,0 +1,47 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<!-- Created by Symbolator http://kevinpt.github.io/symbolator -->
+<svg xmlns="http://www.w3.org/2000/svg"
+xmlns:xlink="http://www.w3.org/1999/xlink"
+xml:space="preserve"
+width="191" height="168" viewBox="-25 -56 191.0 168.0" version="1.1">
+<style type="text/css">
+<![CDATA[
+.fnt1 { fill:#000000; font-family:Times; font-size:12pt; font-weight:normal; font-style:italic; }
+.fnt2 { fill:#000000; font-family:Helvetica; font-size:12pt; font-weight:normal; font-style:normal; }
+.fnt3 { fill:#000000; font-family:Helvetica; font-size:16pt; font-weight:bold; font-style:normal; }
+.fnt4 { fill:#000000; font-family:Helvetica; font-size:10pt; font-style:normal; }
+.label {fill:#000;
+  text-anchor:middle;
+  font-size:16pt; font-weight:bold; font-family:Sans;}
+.link {fill: #0D47A1;}
+.link:hover {fill: #0D47A1; text-decoration:underline;}
+.link:visited {fill: #4A148C;}
+]]>
+</style>
+<defs>
+
+</defs>
+<rect x="-25" y="-56" width="100%" height="100%" fill="white"/><g transform="translate(0,0)">
+<rect x="0" y="-21.0" width="140" height="105.0" stroke="#000000" fill="#CCFED2" stroke-width="1"/>
+<text class="fnt1" x="70.0" y="-5.0" text-anchor="middle" dy="5.5">Data Signals</text>
+<g transform="translate(0,19)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">A</text>
+</g>
+<g transform="translate(0,41)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">B</text>
+</g>
+<g transform="translate(0,63)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">C</text>
+</g>
+<g transform="translate(140,19)">
+<line x1="20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="-10" y="0" text-anchor="end" dy="5.5">X</text>
+</g>
+</g>
+<rect x="1.0" y="-20.0" width="138.0" height="103.0" stroke="#000000" fill="none" stroke-width="3"/>
+<text class="fnt3" x="70.0" y="-30.0" text-anchor="middle" dy="-1.0">xor3</text>
+<text class="fnt4" x="70.0" y="103.0" text-anchor="middle" dy="1.0">sky130_fd_sc_ms</text>
+</svg>
\ No newline at end of file
diff --git a/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.symbol.v b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.symbol.v
new file mode 100644
index 0000000..7abe57e
--- /dev/null
+++ b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.symbol.v
@@ -0,0 +1,54 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_MS__XOR3_SYMBOL_V
+`define SKY130_FD_SC_MS__XOR3_SYMBOL_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ms__xor3 (
+    //# {{data|Data Signals}}
+    input  A,
+    input  B,
+    input  C,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_MS__XOR3_SYMBOL_V
diff --git a/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.tb.v b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.tb.v
new file mode 100644
index 0000000..645ffed
--- /dev/null
+++ b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.tb.v
@@ -0,0 +1,104 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_MS__XOR3_TB_V
+`define SKY130_FD_SC_MS__XOR3_TB_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include "sky130_fd_sc_ms__xor3.v"
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg C;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1'bX;
+        B    = 1'bX;
+        C    = 1'bX;
+        VGND = 1'bX;
+        VNB  = 1'bX;
+        VPB  = 1'bX;
+        VPWR = 1'bX;
+
+        #20   A    = 1'b0;
+        #40   B    = 1'b0;
+        #60   C    = 1'b0;
+        #80   VGND = 1'b0;
+        #100  VNB  = 1'b0;
+        #120  VPB  = 1'b0;
+        #140  VPWR = 1'b0;
+        #160  A    = 1'b1;
+        #180  B    = 1'b1;
+        #200  C    = 1'b1;
+        #220  VGND = 1'b1;
+        #240  VNB  = 1'b1;
+        #260  VPB  = 1'b1;
+        #280  VPWR = 1'b1;
+        #300  A    = 1'b0;
+        #320  B    = 1'b0;
+        #340  C    = 1'b0;
+        #360  VGND = 1'b0;
+        #380  VNB  = 1'b0;
+        #400  VPB  = 1'b0;
+        #420  VPWR = 1'b0;
+        #440  VPWR = 1'b1;
+        #460  VPB  = 1'b1;
+        #480  VNB  = 1'b1;
+        #500  VGND = 1'b1;
+        #520  C    = 1'b1;
+        #540  B    = 1'b1;
+        #560  A    = 1'b1;
+        #580  VPWR = 1'bx;
+        #600  VPB  = 1'bx;
+        #620  VNB  = 1'bx;
+        #640  VGND = 1'bx;
+        #660  C    = 1'bx;
+        #680  B    = 1'bx;
+        #700  A    = 1'bx;
+    end
+
+    sky130_fd_sc_ms__xor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_MS__XOR3_TB_V
diff --git a/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.v b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.v
new file mode 100644
index 0000000..7383dd3
--- /dev/null
+++ b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3.v
@@ -0,0 +1,54 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_MS__XOR3_V
+`define SKY130_FD_SC_MS__XOR3_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include "sky130_fd_sc_ms__xor3.pp.functional.v"
+`else  // FUNCTIONAL
+`include "sky130_fd_sc_ms__xor3.pp.behavioral.v"
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include "sky130_fd_sc_ms__xor3.functional.v"
+`else  // FUNCTIONAL
+`include "sky130_fd_sc_ms__xor3.behavioral.v"
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_MS__XOR3_V
diff --git a/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3_1.v b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3_1.v
new file mode 100644
index 0000000..92c4a80
--- /dev/null
+++ b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3_1.v
@@ -0,0 +1,119 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_MS__XOR3_1_V
+`define SKY130_FD_SC_MS__XOR3_1_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog wrapper for xor3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include "sky130_fd_sc_ms__xor3.v"
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ms__xor3_1 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ms__xor3 cell (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ms__xor3_1 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ms__xor3 cell (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_MS__XOR3_1_V
diff --git a/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3_2.v b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3_2.v
new file mode 100644
index 0000000..675d438
--- /dev/null
+++ b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3_2.v
@@ -0,0 +1,119 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_MS__XOR3_2_V
+`define SKY130_FD_SC_MS__XOR3_2_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog wrapper for xor3 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include "sky130_fd_sc_ms__xor3.v"
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ms__xor3_2 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ms__xor3 cell (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ms__xor3_2 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ms__xor3 cell (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_MS__XOR3_2_V
diff --git a/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3_4.v b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3_4.v
new file mode 100644
index 0000000..0e9db33
--- /dev/null
+++ b/libraries/sky130_fd_sc_ms/v0.0.0/cells/xor3/sky130_fd_sc_ms__xor3_4.v
@@ -0,0 +1,119 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_MS__XOR3_4_V
+`define SKY130_FD_SC_MS__XOR3_4_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog wrapper for xor3 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include "sky130_fd_sc_ms__xor3.v"
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ms__xor3_4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ms__xor3 cell (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ms__xor3_4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ms__xor3 cell (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_MS__XOR3_4_V