diff --git a/docs/rules/device-details.py b/docs/rules/device-details.py
index 2a84c79..bb809ee 100755
--- a/docs/rules/device-details.py
+++ b/docs/rules/device-details.py
@@ -29,9 +29,9 @@
 
     # 20V MOS
     "nfet_20v0",
-    "nfet_20v0_iso",
     "nfet_20v0_nvt",
     "nfet_20v0_zvt",
+    "nfet_20v0_iso",
     "pfet_20v0",
 
     # ESD MOS
diff --git a/docs/rules/device-details.rst b/docs/rules/device-details.rst
index 2997b36..805a67a 100644
--- a/docs/rules/device-details.rst
+++ b/docs/rules/device-details.rst
@@ -216,7 +216,7 @@
 .. |cross-section-pfet_01v8_hvt| image:: device-details/pfet_01v8_hvt/cross-section-pfet_01v8_hvt.svg
 
 
-1.8V Accumulation-Mode MOS Varactors
+1.8V accumulation-mode MOS varactors
 ------------------------------------
 
 Spice Model Information
@@ -545,45 +545,6 @@
 .. |cross-section-nfet_20v0| image:: device-details/nfet_20v0/cross-section-nfet_20v0.svg
 
 
-20V isolated NMOS FET
----------------------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
--  Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain`
--  Model Name: :model:`sky130_fd_pr__nfet_20v0_iso`
-
-Operating Voltages where SPICE models are valid, subject to SOA limitations:
-
--  :math:`V_{DS} = 0` to +22V
--  :math:`V_{GS} = 0` to 5.5V
--  :math:`V_{BS} = 0` to -2.0V
-
-Details
-~~~~~~~
-
-The 20V isolated NMOS FET has the same construction as the 20V NMOS FET, but is built over a Deep N-well. This permits the p-well to be isolated from the substrate and permit “high-side” usage (where the PW body is held above ground).
-
-Major model output parameters are shown below and compared against the EDR (e-test) specs
-
-
-.. include:: device-details/nfet_20v0_iso/nfet_20v0_iso-table0.rst
-
-
-
-The symbol of the :model:`sky130_fd_pr__nfet_20v0_iso` (20V isolated NMOS FET) is shown below.
-
-|symbol-nfet_20v0_iso|
-
-The cross-section of the 20V isolated NMOS FET is shown below.
-
-|cross-section-nfet_20v0_iso|
-
-.. |symbol-nfet_20v0_iso| image:: device-details/nfet_20v0_iso/symbol-nfet_20v0_iso.svg
-.. |cross-section-nfet_20v0_iso| image:: device-details/nfet_20v0_iso/cross-section-nfet_20v0_iso.svg
-
-
 20V native NMOS FET
 -------------------
 
@@ -623,7 +584,7 @@
 .. |cross-section-nfet_20v0_nvt| image:: device-details/nfet_20v0_nvt/cross-section-nfet_20v0_nvt.svg
 
 
-20V NMOS zero-VT FET
+20V zero-VT NMOS FET
 --------------------
 
 Spice Model Information
@@ -659,6 +620,45 @@
 .. |cross-section-nfet_20v0_zvt| image:: device-details/nfet_20v0_zvt/cross-section-nfet_20v0_zvt.svg
 
 
+20V isolated NMOS FET
+---------------------
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+-  Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain`
+-  Model Name: :model:`sky130_fd_pr__nfet_20v0_iso`
+
+Operating Voltages where SPICE models are valid, subject to SOA limitations:
+
+-  :math:`V_{DS} = 0` to +22V
+-  :math:`V_{GS} = 0` to 5.5V
+-  :math:`V_{BS} = 0` to -2.0V
+
+Details
+~~~~~~~
+
+The 20V isolated NMOS FET has the same construction as the 20V NMOS FET, but is built over a Deep N-well. This permits the p-well to be isolated from the substrate and permit “high-side” usage (where the PW body is held above ground).
+
+Major model output parameters are shown below and compared against the EDR (e-test) specs
+
+
+.. include:: device-details/nfet_20v0_iso/nfet_20v0_iso-table0.rst
+
+
+
+The symbol of the :model:`sky130_fd_pr__nfet_20v0_iso` (20V isolated NMOS FET) is shown below.
+
+|symbol-nfet_20v0_iso|
+
+The cross-section of the 20V isolated NMOS FET is shown below.
+
+|cross-section-nfet_20v0_iso|
+
+.. |symbol-nfet_20v0_iso| image:: device-details/nfet_20v0_iso/symbol-nfet_20v0_iso.svg
+.. |cross-section-nfet_20v0_iso| image:: device-details/nfet_20v0_iso/cross-section-nfet_20v0_iso.svg
+
+
 20V PMOS FET
 ------------
 
@@ -703,7 +703,7 @@
 .. |cross-section-pfet_20v0| image:: device-details/pfet_20v0/cross-section-pfet_20v0.svg
 
 
-NMOS ESD FET
+ESD NMOS FET
 ------------
 
 Spice Model Information
@@ -809,8 +809,8 @@
 .. |symbol-diode-17| image:: device-details/diodes/symbol-diode-17.svg
 
 
-Bipolar (NPN)
--------------
+Bipolar NPN transistor
+----------------------
 
 Spice Model Information
 ~~~~~~~~~~~~~~~~~~~~~~~
@@ -861,8 +861,8 @@
 .. |cross-section-npn_11v0| image:: device-details/npn_05v0/cross-section-npn_11v0.svg
 
 
-Bipolar (PNP)
--------------
+Bipolar PNP transistor
+----------------------
 
 Spice Model Information
 ~~~~~~~~~~~~~~~~~~~~~~~
@@ -1022,7 +1022,7 @@
 .. |cross-section-sonos-cell| image:: device-details/special_sonosfet/cross-section-sonos-cell.svg
 
 
-Generic Resistors
+Generic resistors
 -----------------
 
 Generic resistors are supported in the PDK but are not recommended for analog applications. Resistor values will be extracted from the layout as long as the resistor layer is utilized, for LVS against schematic elements.
@@ -1214,8 +1214,8 @@
 .. |symbol-res_xhigh_po| image:: device-details/res_xhigh/symbol-res_xhigh_po.svg
 
 
-MiM Capacitor
--------------
+MiM capacitors
+--------------
 
 Spice Model Information
 ~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/rules/device-details/cap_mim/index.rst b/docs/rules/device-details/cap_mim/index.rst
index 6a3958f..16ed45f 100644
--- a/docs/rules/device-details/cap_mim/index.rst
+++ b/docs/rules/device-details/cap_mim/index.rst
@@ -1,5 +1,5 @@
-MiM Capacitor
--------------
+MiM capacitors
+--------------
 
 Spice Model Information
 ~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/rules/device-details/cap_var/index.rst b/docs/rules/device-details/cap_var/index.rst
index 10691a9..9383211 100644
--- a/docs/rules/device-details/cap_var/index.rst
+++ b/docs/rules/device-details/cap_var/index.rst
@@ -1,4 +1,4 @@
-1.8V Accumulation-Mode MOS Varactors
+1.8V accumulation-mode MOS varactors
 ------------------------------------
 
 Spice Model Information
diff --git a/docs/rules/device-details/esd_nfet/index.rst b/docs/rules/device-details/esd_nfet/index.rst
index 1d57c06..8f3e89c 100644
--- a/docs/rules/device-details/esd_nfet/index.rst
+++ b/docs/rules/device-details/esd_nfet/index.rst
@@ -1,4 +1,4 @@
-NMOS ESD FET
+ESD NMOS FET
 ------------
 
 Spice Model Information
diff --git a/docs/rules/device-details/nfet_20v0_zvt/index.rst b/docs/rules/device-details/nfet_20v0_zvt/index.rst
index f02630c..a1e7648 100644
--- a/docs/rules/device-details/nfet_20v0_zvt/index.rst
+++ b/docs/rules/device-details/nfet_20v0_zvt/index.rst
@@ -1,4 +1,4 @@
-20V NMOS zero-VT FET
+20V zero-VT NMOS FET
 --------------------
 
 Spice Model Information
diff --git a/docs/rules/device-details/npn_05v0/index.rst b/docs/rules/device-details/npn_05v0/index.rst
index 7ec820d..771e840 100644
--- a/docs/rules/device-details/npn_05v0/index.rst
+++ b/docs/rules/device-details/npn_05v0/index.rst
@@ -1,5 +1,5 @@
-Bipolar (NPN)
--------------
+Bipolar NPN transistor
+----------------------
 
 Spice Model Information
 ~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/rules/device-details/pnp_05v0/index.rst b/docs/rules/device-details/pnp_05v0/index.rst
index 0ffc275..38ba1dc 100644
--- a/docs/rules/device-details/pnp_05v0/index.rst
+++ b/docs/rules/device-details/pnp_05v0/index.rst
@@ -1,5 +1,5 @@
-Bipolar (PNP)
--------------
+Bipolar PNP transistor
+----------------------
 
 Spice Model Information
 ~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/rules/device-details/res_generic/index.rst b/docs/rules/device-details/res_generic/index.rst
index f565c73..98d616d 100644
--- a/docs/rules/device-details/res_generic/index.rst
+++ b/docs/rules/device-details/res_generic/index.rst
@@ -1,4 +1,4 @@
-Generic Resistors
+Generic resistors
 -----------------
 
 Generic resistors are supported in the PDK but are not recommended for analog applications. Resistor values will be extracted from the layout as long as the resistor layer is utilized, for LVS against schematic elements.