Merge pull request #265 from antmicro/87-cell-waveform-generator
Cell VCD waveform generator script
diff --git a/.github/labels.yml b/.github/labels.yml
index 30c8c0f..968c362 100644
--- a/.github/labels.yml
+++ b/.github/labels.yml
@@ -51,6 +51,10 @@
description: "Item which references a specific open task which needs finishing."
color: "57dbba" # FIXME: blueish
+- name: "type-blocker"
+ description: "Issue which is blocking a launch."
+ color: "ff0000" # Very Red
+
##########################################################################
# Labels related to files found in the repository
#
@@ -241,6 +245,10 @@
description: "Issues with using OpenROAD with the PDK."
color: "054caa"
+- name: "tools-ngspice"
+ description: "Issues with using Ngspice with the PDK."
+ color: "054caa"
+
# Partially open or with closed source dependencies.
- name: "tools-BAG"
description: "Issues with using the Berkeley Analog Generator (BAG) with the PDK."
diff --git a/.github/workflows/manage-labels.yml b/.github/workflows/manage-labels.yml
index 35b6777..838c2c0 100644
--- a/.github/workflows/manage-labels.yml
+++ b/.github/workflows/manage-labels.yml
@@ -8,11 +8,11 @@
steps:
-
name: Checkout
- uses: actions/checkout@v2
+ uses: actions/checkout@v3
-
name: Run Labeler
if: success()
- uses: crazy-max/ghaction-github-labeler@v3.1.0
+ uses: crazy-max/ghaction-github-labeler@v4.0.0
with:
yaml_file: .github/labels.yml
env:
diff --git a/.gitmodules b/.gitmodules
index 12f5cd4..464b6c4 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -5,61 +5,61 @@
# sky130_fd_pr
[submodule "libraries/sky130_fd_pr/latest"]
path = libraries/sky130_fd_pr/latest
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_pr.git
- branch = master
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git
+ branch = main
shallow = true
fetchRecurseSubmodules = false
[submodule "libraries/sky130_fd_pr/v0.20.1"]
path = libraries/sky130_fd_pr/v0.20.1
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_pr.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git
branch = branch-0.20.1
shallow = true
fetchRecurseSubmodules = false
[submodule "libraries/sky130_fd_pr/v0.20.0"]
path = libraries/sky130_fd_pr/v0.20.0
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_pr.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git
branch = branch-0.20.0
shallow = true
fetchRecurseSubmodules = false
[submodule "libraries/sky130_fd_pr/v0.13.0"]
path = libraries/sky130_fd_pr/v0.13.0
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_pr.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git
branch = branch-0.13.0
shallow = true
fetchRecurseSubmodules = false
[submodule "libraries/sky130_fd_pr/v0.12.1"]
path = libraries/sky130_fd_pr/v0.12.1
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_pr.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git
branch = branch-0.12.1
shallow = true
fetchRecurseSubmodules = false
[submodule "libraries/sky130_fd_pr/v0.12.0"]
path = libraries/sky130_fd_pr/v0.12.0
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_pr.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git
branch = branch-0.12.0
shallow = true
fetchRecurseSubmodules = false
[submodule "libraries/sky130_fd_pr/v0.11.0"]
path = libraries/sky130_fd_pr/v0.11.0
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_pr.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git
branch = branch-0.11.0
shallow = true
fetchRecurseSubmodules = false
[submodule "libraries/sky130_fd_pr/v0.10.1"]
path = libraries/sky130_fd_pr/v0.10.1
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_pr.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git
branch = branch-0.10.1
shallow = true
fetchRecurseSubmodules = false
[submodule "libraries/sky130_fd_pr/v0.10.0"]
path = libraries/sky130_fd_pr/v0.10.0
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_pr.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git
branch = branch-0.10.0
shallow = true
fetchRecurseSubmodules = false
[submodule "libraries/sky130_fd_pr/v0.0.9"]
path = libraries/sky130_fd_pr/v0.0.9
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_pr.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git
branch = branch-0.0.9
shallow = true
fetchRecurseSubmodules = false
@@ -67,36 +67,36 @@
# sky130_fd_sc_hd
[submodule "libraries/sky130_fd_sc_hd/latest"]
path = libraries/sky130_fd_sc_hd/latest
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hd.git
- branch = master
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd.git
+ branch = main
shallow = true
[submodule "libraries/sky130_fd_sc_hd/v0.0.2"]
path = libraries/sky130_fd_sc_hd/v0.0.2
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hd.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd.git
branch = branch-0.0.2
shallow = true
[submodule "libraries/sky130_fd_sc_hd/v0.0.1"]
path = libraries/sky130_fd_sc_hd/v0.0.1
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hd.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd.git
branch = branch-0.0.1
shallow = true
# sky130_fd_sc_hdll
[submodule "libraries/sky130_fd_sc_hdll/latest"]
path = libraries/sky130_fd_sc_hdll/latest
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hdll.git
- branch = master
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hdll.git
+ branch = main
shallow = true
fetchRecurseSubmodules = true
[submodule "libraries/sky130_fd_sc_hdll/v0.1.1"]
path = libraries/sky130_fd_sc_hdll/v0.1.1
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hdll.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hdll.git
branch = branch-0.1.1
shallow = true
fetchRecurseSubmodules = false
[submodule "libraries/sky130_fd_sc_hdll/v0.1.0"]
path = libraries/sky130_fd_sc_hdll/v0.1.0
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hdll.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hdll.git
branch = branch-0.1.0
shallow = true
fetchRecurseSubmodules = false
@@ -104,19 +104,19 @@
# sky130_fd_sc_hs
[submodule "libraries/sky130_fd_sc_hs/latest"]
path = libraries/sky130_fd_sc_hs/latest
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hs.git
- branch = master
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hs.git
+ branch = main
shallow = true
fetchRecurseSubmodules = true
[submodule "libraries/sky130_fd_sc_hs/v0.0.2"]
path = libraries/sky130_fd_sc_hs/v0.0.2
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hs.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hs.git
branch = branch-0.0.2
shallow = true
fetchRecurseSubmodules = false
[submodule "libraries/sky130_fd_sc_hs/v0.0.1"]
path = libraries/sky130_fd_sc_hs/v0.0.1
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hs.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hs.git
branch = branch-0.0.1
shallow = true
fetchRecurseSubmodules = false
@@ -124,19 +124,19 @@
# sky130_fd_sc_ms
[submodule "libraries/sky130_fd_sc_ms/latest"]
path = libraries/sky130_fd_sc_ms/latest
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_ms.git
- branch = master
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_ms.git
+ branch = main
shallow = true
fetchRecurseSubmodules = true
[submodule "libraries/sky130_fd_sc_ms/v0.0.2"]
path = libraries/sky130_fd_sc_ms/v0.0.2
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_ms.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_ms.git
branch = branch-0.0.2
shallow = true
fetchRecurseSubmodules = false
[submodule "libraries/sky130_fd_sc_ms/v0.0.1"]
path = libraries/sky130_fd_sc_ms/v0.0.1
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_ms.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_ms.git
branch = branch-0.0.1
shallow = true
fetchRecurseSubmodules = false
@@ -144,39 +144,38 @@
# sky130_fd_sc_ls
[submodule "libraries/sky130_fd_sc_ls/latest"]
path = libraries/sky130_fd_sc_ls/latest
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_ls.git
- branch = master
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_ls.git
+ branch = main
shallow = true
fetchRecurseSubmodules = true
[submodule "libraries/sky130_fd_sc_ls/v0.1.1"]
path = libraries/sky130_fd_sc_ls/v0.1.1
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_ls.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_ls.git
branch = branch-0.1.1
shallow = true
fetchRecurseSubmodules = false
[submodule "libraries/sky130_fd_sc_ls/v0.1.0"]
path = libraries/sky130_fd_sc_ls/v0.1.0
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_ls.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_ls.git
branch = branch-0.1.0
shallow = true
fetchRecurseSubmodules = false
-
# sky130_fd_sc_lp
[submodule "libraries/sky130_fd_sc_lp/latest"]
path = libraries/sky130_fd_sc_lp/latest
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_lp.git
- branch = master
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_lp.git
+ branch = main
shallow = true
fetchRecurseSubmodules = true
[submodule "libraries/sky130_fd_sc_lp/v0.0.2"]
path = libraries/sky130_fd_sc_lp/v0.0.2
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_lp.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_lp.git
branch = branch-0.0.2
shallow = true
fetchRecurseSubmodules = false
[submodule "libraries/sky130_fd_sc_lp/v0.0.1"]
path = libraries/sky130_fd_sc_lp/v0.0.1
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_lp.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_lp.git
branch = branch-0.0.1
shallow = true
fetchRecurseSubmodules = false
@@ -184,25 +183,25 @@
# sky130_fd_sc_hvl
[submodule "libraries/sky130_fd_sc_hvl/latest"]
path = libraries/sky130_fd_sc_hvl/latest
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hvl.git
- branch = master
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hvl.git
+ branch = main
shallow = true
fetchRecurseSubmodules = true
[submodule "libraries/sky130_fd_sc_hvl/v0.0.3"]
path = libraries/sky130_fd_sc_hvl/v0.0.3
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hvl.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hvl.git
branch = branch-0.0.3
shallow = true
fetchRecurseSubmodules = false
[submodule "libraries/sky130_fd_sc_hvl/v0.0.2"]
path = libraries/sky130_fd_sc_hvl/v0.0.2
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hvl.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hvl.git
branch = branch-0.0.2
shallow = true
fetchRecurseSubmodules = false
[submodule "libraries/sky130_fd_sc_hvl/v0.0.1"]
path = libraries/sky130_fd_sc_hvl/v0.0.1
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hvl.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hvl.git
branch = branch-0.0.1
shallow = true
fetchRecurseSubmodules = false
@@ -210,37 +209,66 @@
# sky130_fd_io
[submodule "libraries/sky130_fd_io/latest"]
path = libraries/sky130_fd_io/latest
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_io.git
- branch = master
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_io.git
+ branch = main
shallow = true
fetchRecurseSubmodules = true
[submodule "libraries/sky130_fd_io/v0.2.1"]
path = libraries/sky130_fd_io/v0.2.1
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_io.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_io.git
branch = branch-0.2.1
shallow = true
fetchRecurseSubmodules = false
[submodule "libraries/sky130_fd_io/v0.2.0"]
path = libraries/sky130_fd_io/v0.2.0
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_io.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_io.git
branch = branch-0.2.0
shallow = true
fetchRecurseSubmodules = false
[submodule "libraries/sky130_fd_io/v0.1.0"]
path = libraries/sky130_fd_io/v0.1.0
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_io.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_io.git
branch = branch-0.1.0
shallow = true
fetchRecurseSubmodules = false
[submodule "libraries/sky130_fd_io/v0.0.2"]
path = libraries/sky130_fd_io/v0.0.2
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_io.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_io.git
branch = branch-0.1.0
shallow = true
fetchRecurseSubmodules = false
[submodule "libraries/sky130_fd_io/v0.0.1"]
path = libraries/sky130_fd_io/v0.0.1
- url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_io.git
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_io.git
branch = branch-0.0.1
shallow = true
fetchRecurseSubmodules = false
+#sky130_fd_pr_reram
+[submodule "libraries/sky130_fd_pr_reram/v0.0.9"]
+ path = libraries/sky130_fd_pr_reram/v0.0.9
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr_reram.git
+ branch = branch-0.0.9
+ shallow = true
+ fetchRecurseSubmodules = false
+[submodule "libraries/sky130_fd_pr_reram/v2.0.1"]
+ path = libraries/sky130_fd_pr_reram/v2.0.1
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr_reram.git
+ branch = branch-2.0.1
+ shallow = true
+ fetchRecurseSubmodules = false
+[submodule "libraries/sky130_fd_pr_reram/v2.0.2"]
+ path = libraries/sky130_fd_pr_reram/v2.0.2
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr_reram.git
+ branch = branch-2.0.2
+ shallow = true
+ fetchRecurseSubmodules = false
+[submodule "libraries/sky130_fd_pr_reram/v2.0.3"]
+ path = libraries/sky130_fd_pr_reram/v2.0.3
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr_reram.git
+ branch = branch-2.0.3
+ shallow = true
+ fetchRecurseSubmodules = false
+[submodule "libraries/sky130_fd_pr_reram/latest"]
+ path = libraries/sky130_fd_pr_reram/latest
+ url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr_reram.git
+ branch = main
diff --git a/.readthedocs.yml b/.readthedocs.yml
index 5321847..bea9451 100644
--- a/.readthedocs.yml
+++ b/.readthedocs.yml
@@ -32,3 +32,6 @@
include:
- libraries/sky130_fd_io/latest
recursive: false
+
+formats:
+ - pdf
diff --git a/Makefile b/Makefile
index 1896b7e..ae7d4f7 100644
--- a/Makefile
+++ b/Makefile
@@ -79,9 +79,9 @@
@true
-LIBRARIES = $(sort $(notdir $(wildcard libraries/sky130_*_sc_*)))
+SC_LIBS = $(sort $(notdir $(wildcard libraries/sky130_*_sc_*)))
-$(LIBRARIES): | $(CONDA_ENV_PYTHON)
+$(SC_LIBS): | $(CONDA_ENV_PYTHON)
@$(IN_CONDA_ENV) for V in libraries/$@/*; do \
if [ -d "$$V/cells" ]; then \
python -m skywater_pdk.liberty $$V; \
@@ -99,7 +99,7 @@
sky130_fd_sc_ms: sky130_fd_sc_ms-leakage
-timing: $(LIBRARIES) | $(CONDA_ENV_PYTHON)
+timing: $(SC_LIBS) | $(CONDA_ENV_PYTHON)
@true
diff --git a/docs/_static/skywater-pdk-logo-top.png b/docs/_static/skywater-pdk-logo-top.png
new file mode 100644
index 0000000..fe7e334
--- /dev/null
+++ b/docs/_static/skywater-pdk-logo-top.png
Binary files differ
diff --git a/docs/_templates/relbar.html b/docs/_templates/relbar.html
new file mode 100644
index 0000000..a61838b
--- /dev/null
+++ b/docs/_templates/relbar.html
@@ -0,0 +1,13 @@
+{% extends '!relbar.html' %}
+
+{%- block extralinks -%}
+{{ super() }}
+
+<li class="md-tabs__item"><a href="https://www.skywatertechnology.com/" class="md-tabs__link"><i class="md-icon">business</i> SkyWater</a></li>
+<li class="md-tabs__item"><a href="https://efabless.com/open_shuttle_program" class="md-tabs__link"><i class="md-icon">precision_manufacturing</i> Shuttle Program</a></li>
+<li class="md-tabs__item"><a href="https://join.skywater.tools/" class="md-tabs__link"><i class="md-icon">chat_bubble</i> Chat</a></li>
+<li class="md-tabs__item"><a href="https://groups.google.com/g/skywater-pdk-announce" class="md-tabs__link"><i class="md-icon">campaign</i>Announcements</a></li>
+<li class="md-tabs__item"><a href="https://groups.google.com/g/skywater-pdk-users" class="md-tabs__link"><i class="md-icon">mail</i> Mailing List</a></li>
+
+
+{%- endblock -%}
diff --git a/docs/conf.py b/docs/conf.py
index b817d54..f5c16d7 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -61,12 +61,17 @@
'sphinx.ext.autosectionlabel',
'sphinx.ext.githubpages',
'sphinx.ext.ifconfig',
+ 'sphinx.ext.imgconverter',
'sphinx.ext.mathjax',
'sphinx.ext.napoleon',
'sphinx.ext.todo',
'sphinxcontrib_hdl_diagrams',
+ 'sphinxcontrib.bibtex',
]
+bibtex_default_style = 'plain'
+bibtex_bibfiles = ['refs.bib']
+
# Add any paths that contain templates here, relative to this directory.
templates_path = ['_templates']
@@ -86,8 +91,8 @@
"display_github": True, # Integrate GitHub
"github_user": "google", # Username
"github_repo": "skywater-pdk", # Repo name
- "github_version": "master", # Version
- "conf_py_path": "/doc/",
+ "github_version": "main", # Version
+ "conf_py_path": "/docs/",
}
else:
docs_dir = os.path.abspath(os.path.dirname(__file__))
@@ -124,6 +129,9 @@
'code-of-conduct.rst',
'rules/periphery-rules.rst',
'rules/device-details/*/index.rst',
+ 'rules/summary/*-key.rst',
+ 'rules/layers/*-key.rst',
+ 'rules/hv/*-key.rst',
]
# The name of the Pygments (syntax highlighting) style to use.
@@ -146,56 +154,24 @@
#
html_theme = "sphinx_symbiflow_theme"
+html_logo = "_static/skywater-pdk-logo-top.png"
+
# Theme options are theme-specific and customize the look and feel of a theme
# further. For a list of options available for each theme, see the
# documentation.
-#
+# https://sphinx-symbiflow-theme.readthedocs.io/en/latest/customization.html
html_theme_options = {
- # Specify a list of menu in Header.
- # Tuples forms:
- # ('Name', 'external url or path of pages in the document', boolean, 'icon name')
- #
- # Third argument:
- # True indicates an external link.
- # False indicates path of pages in the document.
- #
- # Fourth argument:
- # Specify the icon name.
- # For details see link.
- # https://material.io/icons/
- 'header_links': [
- ('Home', 'index', False, 'home'),
- ("GitHub", "https://github.com/google/skywater-pdk", True, 'code'),
- ("SkyWater", "https://www.skywatertechnology.com/", True, 'link'),
- ],
+ 'nav_title': 'SkyWater SKY130 PDK',
- # Customize css colors.
- # For details see link.
- # https://getmdl.io/customize/index.html
- #
- # Values: amber, blue, brown, cyan deep_orange, deep_purple, green, grey, indigo, light_blue,
- # light_green, lime, orange, pink, purple, red, teal, yellow(Default: indigo)
- 'primary_color': 'light_green',
- # Values: Same as primary_color. (Default: pink)
- 'accent_color': 'teal',
+ 'color_primary': 'light-green',
+ 'color_accent': 'teal',
- # Customize layout.
- # For details see link.
- # https://getmdl.io/components/index.html#layout-section
- 'fixed_drawer': True,
- 'fixed_header': True,
- 'header_waterfall': True,
- 'header_scroll': False,
+ # Set the repo location to get a badge with stats
+ 'github_url': 'https://github.com/google/skywater-pdk',
+ 'repo_name': 'google/skywater-pdk',
- # Render title in header.
- # Values: True, False (Default: False)
- 'show_header_title': False,
- # Render title in drawer.
- # Values: True, False (Default: True)
- 'show_drawer_title': True,
- # Render footer.
- # Values: True, False (Default: True)
- 'show_footer': True,
+ 'globaltoc_depth': 4,
+ 'globaltoc_collapse': False,
# Hide the symbiflow links
'hide_symbiflow_links': True,
@@ -320,6 +296,23 @@
# If true, `todo` and `todoList` produce output, else they produce nothing.
todo_include_todos = True
+latex_elements = {
+ 'preamble': r'\DeclareUnicodeCharacter{03A9}{\ensuremath{\Omega}}' +
+ r'\DeclareUnicodeCharacter{03BC}{\ensuremath{\mu}}' +
+ r'\DeclareUnicodeCharacter{2184}{\ensuremath{\supset}}' +
+ r'\DeclareUnicodeCharacter{2295}{\ensuremath{\oplus}}' +
+ r'\DeclareUnicodeCharacter{2228}{\ensuremath{\vee}}' +
+ r'\DeclareUnicodeCharacter{22BB}{\ensuremath{\veebar}}' +
+ r'\DeclareUnicodeCharacter{01C1}{\ensuremath{\parallel}}' +
+ r'\DeclareUnicodeCharacter{2220}{\ensuremath{\angle}}' +
+ r'\DeclareUnicodeCharacter{2227}{\ensuremath{\wedge}}' +
+ r'\DeclareUnicodeCharacter{25A1}{\ensuremath{\Box}}' +
+ r'\DeclareUnicodeCharacter{F06D}{\ensuremath{\mu}}' +
+ r'\DeclareUnicodeCharacter{03B2}{\ensuremath{\beta}}' +
+ r'\DeclareUnicodeCharacter{2264}{\ensuremath{\leq}}' +
+ r'\usepackage{pmboxdraw}' +
+ r'\DeclareUnicodeCharacter{2534}{\textSFvii}'
+}
import re
from docutils.parsers.rst import directives, roles, nodes
diff --git a/docs/contents/libraries.rst b/docs/contents/libraries.rst
index ca3c24e..b7b29de 100644
--- a/docs/contents/libraries.rst
+++ b/docs/contents/libraries.rst
@@ -34,7 +34,7 @@
+--------------------------------+---------------------------------------+
| Digital Standard Cells | :lib_type:`sc` |
+--------------------------------+---------------------------------------+
- | Build Space (Flash, SRAM, etc) | :lib_type:`sp` |
+ | Build Space (Flash, SRAM, etc) | :lib_type:`bd` |
+--------------------------------+---------------------------------------+
| IO and Periphery | :lib_type:`io` |
+--------------------------------+---------------------------------------+
diff --git a/docs/environment.yml b/docs/environment.yml
index 23797fd..d8345d8 100644
--- a/docs/environment.yml
+++ b/docs/environment.yml
@@ -16,13 +16,12 @@
name: skywater-pdk-docs
channels:
- symbiflow
-- conda-forge
- defaults
dependencies:
- python=3.8
- pip
-- yosys
- netlistsvg
# Packages installed from PyPI
- pip:
- - -r file:requirements.txt
+ - -r requirements.txt
+ - ../scripts/python-skywater-pdk
diff --git a/docs/index.rst b/docs/index.rst
index 828ea9b..3261a63 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -24,7 +24,7 @@
contributing
partners
-
+ references
Welcome to SkyWater SKY130 PDK's documentation!
diff --git a/docs/previous.rst b/docs/previous.rst
index 2c87fcb..887518a 100644
--- a/docs/previous.rst
+++ b/docs/previous.rst
@@ -29,13 +29,9 @@
process. It stood for the "8th generation" of the SONOS technology
developed originally by Cypress.
- :lib_process:`s8phrc`
:lib_process:`s180`
The name for using 180nm technology on the 130nm process.
-
- :lib_process:`s8phirs`
-
:lib_process:`s8pfhd`
The base process. 5 metal layer backend stack, 16V devices, deep
nwell.
diff --git a/docs/references.rst b/docs/references.rst
new file mode 100644
index 0000000..4563312
--- /dev/null
+++ b/docs/references.rst
@@ -0,0 +1,8 @@
+.. _References:
+
+References
+##########
+
+.. bibliography::
+ :notcited:
+ :labelprefix: R
diff --git a/docs/refs.bib b/docs/refs.bib
new file mode 100644
index 0000000..5d605d1
--- /dev/null
+++ b/docs/refs.bib
@@ -0,0 +1,6 @@
+@Online{SkyWaterPDKIntro_Edwards21,
+ author = {Edwards, Tim},
+ title = {{Introduction to the SkyWater PDK: The New Age of Open Source Silicon}},
+ url = {https://isn.ucsd.edu/courses/beng207/lectures/Tim_Edwards_2021_slides.pdf},
+ year = {2021},
+}
diff --git a/docs/requirements.txt b/docs/requirements.txt
index f20b3a6..4605163 100644
--- a/docs/requirements.txt
+++ b/docs/requirements.txt
@@ -1,8 +1,9 @@
-git+https://github.com/SymbiFlow/sphinx_materialdesign_theme.git#egg=sphinx-symbiflow-theme
+git+https://github.com/SymbiFlow/sphinx_symbiflow_theme.git#egg=sphinx-symbiflow-theme
docutils
sphinx
sphinx-autobuild
+sphinxcontrib-bibtex
# Verilog domain
sphinx-verilog-domain
@@ -10,7 +11,7 @@
sphinxcontrib-hdl-diagrams
# Module diagrams
-git+https://github.com/SymbiFlow/symbolator.git#egg=symbolator
+#git+https://github.com/SymbiFlow/symbolator.git#egg=symbolator
# pycairo
# vext.gi
diff --git a/docs/rules/device-details.py b/docs/rules/device-details.py
index ce51e73..bb809ee 100755
--- a/docs/rules/device-details.py
+++ b/docs/rules/device-details.py
@@ -2,28 +2,66 @@
import re
import os
-import sys
-from pathlib import Path
-from pprint import pformat
-
RE_IMAGE = re.compile('.. (.*) image:: (.*)')
RE_INCLUDE = re.compile('.. include:: (.*)')
+device_list = [
+ # 1.8V MOS
+ "nfet_01v8",
+ "nfet_01v8_lvt",
+ "pfet_01v8",
+ "pfet_01v8_lvt",
+ "pfet_01v8_hvt",
+ "cap_var",
+
+ # 3.3V MOS
+ "nfet_03v3_nvt",
+
+ # 5V MOS
+ "nfet_05v0_nvt",
+ "nfet_g5v0d10v5",
+ "pfet_g5v0d10v5",
+ "pfet_g5v0d16v0",
+
+ # 11V MOS
+ "nfet_g11v0d16v0",
+
+ # 20V MOS
+ "nfet_20v0",
+ "nfet_20v0_nvt",
+ "nfet_20v0_zvt",
+ "nfet_20v0_iso",
+ "pfet_20v0",
+
+ # ESD MOS
+ "esd_nfet",
+
+ # Diodes/Bipolar
+ "diodes",
+ "npn_05v0",
+ "pnp_05v0",
+
+ # Special active devices
+ "special_sram",
+ "special_sonosfet",
+
+ # Well/Diffusion/Poly/Metal Resistors
+ "res_generic",
+ "res_high",
+ "res_xhigh",
+
+ # Metal Capacitors
+ "cap_mim",
+ "cap_vpp",
+]
+
print('Device Details')
print('==============')
print()
-def r(m):
- n = m.group(0)
- while len(n) < 10:
- n = '0'+n
- return n
-
-def k(s):
- return re.sub('([0-9.V/]*)', r, str(s))
-
-for fname in sorted(Path('.').rglob('index.rst'), key=k):
+for device_name in device_list:
+ fname = os.path.join("device-details", device_name, "index.rst")
with open(fname) as f:
data = f.read()
@@ -33,4 +71,3 @@
data = RE_IMAGE.sub(r'.. \1 image:: {}/\2'.format(dirname), data)
data = RE_INCLUDE.sub(r'.. include:: {}/\1'.format(dirname), data)
print(data)
-
diff --git a/docs/rules/device-details.rst b/docs/rules/device-details.rst
index 6ae9877..805a67a 100644
--- a/docs/rules/device-details.rst
+++ b/docs/rules/device-details.rst
@@ -1,371 +1,43 @@
Device Details
==============
-MiM Capacitor
+1.8V NMOS FET
-------------
Spice Model Information
~~~~~~~~~~~~~~~~~~~~~~~
-- Cell Name: :cell:`sky130_fd_pr__cap_mim_m3__base`, :cell:`sky130_fd_pr__cap_mim_m4__base`
-- Model Names: :model:`sky130_fd_pr__model__cap_mim`, :model:`sky130_fd_pr__cap_mim_m4`
-
-Operating Voltages where SPICE models are valid
-
-- :math:`|V_{c0} – V_{c1}| = 0` to 5.0V
-
-Details
-~~~~~~~
-
-The MiM capacitor is constructed using a thin dielectric over metal, followed by a thin conductor layer on top of the dielectric. There are two possible constructions:
-
-- CAPM over Metal-3
-- CAP2M over Metal-4
-
-The constructions are identical, and the capacitors may be stacked to maximize total capacitance.
-
-Electrical specs are listed below:
-
-
-.. include:: device-details/cap_mim/cap_mim-table0.rst
-
-
-
-The symbol for the MiM capacitor is shown below. Note that the cap model is a sub-circuit which accounts for the parasitic contact resistance and the parasitic capacitance from the bottom plate to substrate.
-
-|symbol-cap_mim|
-
-Cell name
-
-M \* W \* L
-
-Calc capacitance
-
-The cross-section of the “stacked” MiM capacitor is shown below:
-
-|cross-section-cap_mim|
-
-.. |symbol-cap_mim| image:: device-details/cap_mim/symbol-cap_mim.svg
-.. |cross-section-cap_mim| image:: device-details/cap_mim/cross-section-cap_mim.svg
-
-
-Varactors
----------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
-- Cell Name: :cell:`capbn_b`
-- Model Name: :model:`sky130_fd_pr__cap_var_lvt`, :model:`sky130_fd_pr__cap_var_hvt`
-- Model Type: subcircuit
-
-Operating Voltages where SPICE models are valid
-
-- :math:`|V_0 – V_1| = 0` to 2.0V
-
-Details
-~~~~~~~
-
-The following devices are available; they are subcircuits with the N-well to P-substrate diodes built into the model:
-
-- :model:`sky130_fd_pr__cap_var_lvt` - low VT PMOS device option
-- :model:`sky130_fd_pr__cap_var_hvt` - high VT PMOS device option
-
-The varactors are used as tunable capacitors, major e-test parameters are listed below. Further details on the device models and their usage are in the SKY130 process Family Spice Models (002-21997), which can be obtained from SkyWater upon request.
-
-
-.. include:: device-details/cap_var/cap_var-table0.rst
-
-
-
-There is no equivalent varactor for 5V operation. The NHV or PHV devices should be connected as capacitors for use at 5V.
-
-The symbols for the varactors are shown below:
-
-|symbol-cap_var-a| |symbol-cap_var-b|
-
-The cross-section of the varactor is shown below:
-
-|cross-section-cap_var|
-
-.. |symbol-cap_var-a| image:: device-details/cap_var/symbol-cap_var-a.svg
-.. |symbol-cap_var-b| image:: device-details/cap_var/symbol-cap_var-b.svg
-.. |cross-section-cap_var| image:: device-details/cap_var/cross-section-cap_var.svg
-
-
-Vertical Parallel Plate (VPP) capacitors
-----------------------------------------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
-- Cell Name: :cell:`sky130_fd_pr__cap_vpp_XXpXxYYpY_{MM}(_shield(SS)*)(_float(FF)*)(_(VVVV))`
-- Model Names: :model:`sky130_fd_pr__cap_vpp_*`
-
- - X and Y are size dimentions
- - MM refers to the layers which are used for the capacitance
- - SS refers to the layers which are used as shields (`noshield` when no shield is used)
- - FF refers to the layers which are floating.
- - VVVVV refers to the "variant" when there are multiple devices of the same configuration
-
-Operating Voltages where SPICE models are valid
-
-- :math:`|V_{c0} – V_{c1}| = 0` to 5.5V
-
-Details
-~~~~~~~
-
-The VPP caps utilize the tight spacings of the metal lines to create capacitors using the available metal layers. The fingers go in opposite directions to minimize alignment-related variability, and the capacitor sits on field oxide to minimize silicon capacitance effects. A schematic diagram of the layout is shown below:
-
-.. todo::
-
- M3
-
- **M2**
-
- LI
-
- M1
-
- LAYOUT of M2, M3, M4
-
- LAYOUT of LI and M1 (with POLY sheet)
-
- **POLY**
-
- **M4**
-
-These capacitors are fixed-size, and they can be connected together to multiply the effective capacitance of a given node. There are two different constructions.
-
-Parallel VPP Capacitors
-^^^^^^^^^^^^^^^^^^^^^^^
-
-These are older versions, where stacked metal lines run parallel:
-
-
-- :model:`sky130_fd_pr__cap_vpp_08p6x07p8_m1m2_noshield` (M1 \|\| M2 only, 7.84 x 8.58)
-- :model:`sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_noshield_o2` (M1 \|\| M2 only, 4.38 x 4.59)
-- :model:`sky130_fd_pr__cap_vpp_02p4x04p6_m1m2_noshield` (M1 \|\| M2 only, 2.19 x 4.59)
-- :model:`sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_noshield` (M1 :sub:`┴` M2, 4.4 x 4.6, 4 quadrants)
-- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_m1m2_noshield` (M1 :sub:`┴` M2, 11.5 x 11.7, 4 quadrants)
-- :model:`sky130_fd_pr__cap_vpp_44p7x23p1_pol1m1m2m3m4m5_noshield`
-- :model:`sky130_fd_pr__cap_vpp_02p7x06p1_m1m2m3m4_shieldl1_fingercap` (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 5.0)
-- :model:`sky130_fd_pr__cap_vpp_02p9x06p1_m1m2m3m4_shieldl1_fingercap2` (M1 \|\| M2 \|\| M3 \|\| M4, 2.85 x 5.0)
-- :model:`sky130_fd_pr__cap_vpp_02p7x11p1_m1m2m3m4_shieldl1_fingercap` (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 10.0)
-- :model:`sky130_fd_pr__cap_vpp_02p7x21p1_m1m2m3m4_shieldl1_fingercap` (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 20.0)
-- :model:`sky130_fd_pr__cap_vpp_02p7x41p1_m1m2m3m4_shieldl1_fingercap` (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 40.0)
-
-The symbol for these capacitors is shown below. The terminals c0 and c1 represent the two sides of the capacitor, with b as the body (sub or well).
-
-|symbol-cap_vpp-parallel|
-
-Perpendicular VPP Capacitors
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-These are newer versions, where stacked metal lines run perpendicular and there are shields on top and bottom:
-
-- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3m4_shieldm5` (11.5x11.7, with M5 shield)
-- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3m4_shieldpom5` (11.5x11.7, with poly and M5 shield)
-- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3m4_shieldl1m5` (11.5x11.7, with LI and M5 shield)
-- :model:`sky130_fd_pr__cap_vpp_04p4x04p6_m1m2m3_shieldl1m5_floatm4` (4.4x4.6, M3 float, LI / M5 shield)
-- :model:`sky130_fd_pr__cap_vpp_08p6x07p8_m1m2m3_shieldl1m5_floatm4` (8.6x7.9, M3 float, LI / M5 shield)
-- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3_shieldl1m5_floatm4` (11.5x11.7, M3 float, LI / M5 shield)
-- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3_shieldm4` (11.5x11.7, with M4 shield)
-- :model:`sky130_fd_pr__cap_vpp_06p8x06p1_l1m1m2m3_shieldpom4` (6.8x6.1, with poly and M4 shield)
-- :model:`sky130_fd_pr__cap_vpp_06p8x06p1_m1m2m3_shieldl1m4` (6.8x6.1, with LI and M4 shield)
-- :model:`sky130_fd_pr__cap_vpp_11p3x11p8_l1m1m2m3m4_shieldm5` (11.5x11.7, over 2 :model:`sky130_fd_pr__nfet_05v0_nvt` of 10/4 each)
-
-The symbol for these capacitors is shown below. The terminals c0 and c1 are the two capacitor terminals, “top” represents the top shield and “sub” the bottom shield.
-
-|symbol-cap_vpp-perpendicular|
-
-The capacitors are fixed-size elements and must be used as-is; they can be used in multiples.
-
-
-.. include:: device-details/cap_vpp/cap_vpp-table0.rst
-
-.. |symbol-cap_vpp-parallel| image:: device-details/cap_vpp/symbol-cap_vpp-parallel.svg
-.. |symbol-cap_vpp-perpendicular| image:: device-details/cap_vpp/symbol-cap_vpp-perpendicular.svg
-
-Diodes
-------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
-- Cell Name: :cell:`diode`
-- Model Names: :model:`sky130_fd_pr__diode_pw2nd_05v5`, :model:`sky130_fd_pr__diode_pw2nd_11v0`, :model:`sky130_fd_pr__diode_pw2nd_05v5_nvt`, :model:`sky130_fd_pr__diode_pw2nd_05v5_lvt`, :model:`sky130_fd_pr__diode_pd2nw_05v5`, :model:`sky130_fd_pr__diode_pd2nw_11v0`, :model:`sky130_fd_pr__diode_pd2nw_05v5_hvt`, :model:`sky130_fd_pr__diode_pd2nw_05v5_lvt`, :model:`sky130_fd_pr__model__parasitic__rf_diode_ps2nw`, :model:`sky130_fd_pr__model__parasitic__rf_diode_pw2dn`, :model:`sky130_fd_pr__model__parasitic__diode_pw2dn`, :model:`sky130_fd_pr__model__parasitic__diode_ps2dn`, :model:`dnwdiode_psub_victim`, :model:`dnwdiode_psub_aggressor`, :model:`sky130_fd_pr__model__parasitic__diode_ps2nw`, :model:`nwdiode_victim`, :model:`nwdiode_aggressor`, :model:`xesd_ndiode_h_X`, :model:`xesd_ndiode_h_dnwl_X`, :model:`xesd_pdiode_h_X (X = 100 or 200 or 300)`
-- Cell Name: :cell:`lvsdiode`
-- Model Names: :model:`sky130_fd_pr__diode_pw2nd_05v5`, :model:`sky130_fd_pr__diode_pw2nd_11v0`, :model:`sky130_fd_pr__diode_pd2nw_05v5`, :model:`sky130_fd_pr__diode_pd2nw_11v0`, :model:`sky130_fd_pr__model__parasitic__diode_ps2dn`, :model:`dnwdiode_psub_victim`, :model:`dnwdiode_psub_aggressor`, :model:`nwdiode_victim`, :model:`nwdiode_aggressor`, :model:`xesd_ndiode_h_X`, :model:`xesd_ndiode_h_dnwl_X`, :model:`xesd_pdiode_h_X (X = 100 or 200 or 300)`
-
-Operating regime where SPICE models are valid
-
-- :math:`|V_{d0} – V_{d1}| = 0` to 5.0V
-
-Details
-~~~~~~~
-
-
-.. include:: device-details/diodes/diodes-table0.rst
-
-
-
-Symbols for the diodes are shown below
-
-|symbol-diode-01|
-|symbol-diode-02|
-|symbol-diode-03|
-|symbol-diode-04|
-|symbol-diode-05|
-|symbol-diode-06|
-|symbol-diode-07|
-|symbol-diode-08|
-|symbol-diode-09|
-|symbol-diode-10|
-|symbol-diode-11|
-|symbol-diode-12|
-|symbol-diode-13|
-|symbol-diode-14|
-|symbol-diode-15|
-|symbol-diode-16|
-|symbol-diode-17|
-
-.. |symbol-diode-01| image:: device-details/diodes/symbol-diode-01.svg
-.. |symbol-diode-02| image:: device-details/diodes/symbol-diode-02.svg
-.. |symbol-diode-03| image:: device-details/diodes/symbol-diode-03.svg
-.. |symbol-diode-04| image:: device-details/diodes/symbol-diode-04.svg
-.. |symbol-diode-05| image:: device-details/diodes/symbol-diode-05.svg
-.. |symbol-diode-06| image:: device-details/diodes/symbol-diode-06.svg
-.. |symbol-diode-07| image:: device-details/diodes/symbol-diode-07.svg
-.. |symbol-diode-08| image:: device-details/diodes/symbol-diode-08.svg
-.. |symbol-diode-09| image:: device-details/diodes/symbol-diode-09.svg
-.. |symbol-diode-10| image:: device-details/diodes/symbol-diode-10.svg
-.. |symbol-diode-11| image:: device-details/diodes/symbol-diode-11.svg
-.. |symbol-diode-12| image:: device-details/diodes/symbol-diode-12.svg
-.. |symbol-diode-13| image:: device-details/diodes/symbol-diode-13.svg
-.. |symbol-diode-14| image:: device-details/diodes/symbol-diode-14.svg
-.. |symbol-diode-15| image:: device-details/diodes/symbol-diode-15.svg
-.. |symbol-diode-16| image:: device-details/diodes/symbol-diode-16.svg
-.. |symbol-diode-17| image:: device-details/diodes/symbol-diode-17.svg
-
-
-NMOS ESD FET
-------------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
- Cell Name: :cell:`sky130_fd_pr__nfet_01v8`
-- Model Name: :model:`sky130_fd_pr__esd_nfet_01v8`, :model:`sky130_fd_pr__esd_nfet_g5v0d10v5`, :model:`sky130_fd_pr__esd_nfet_g5v0d10v5_nvt`
+- Model Name: :model:`sky130_fd_pr__nfet_01v8`
Operating Voltages where SPICE models are valid
-- :math:`V_{DS} = 0` to 11.0V (:model:`sky130_fd_pr__nfet_g5v0d10v5*`), 0 to 1.95V (:model:`sky130_fd_pr__nfet_01v8*`)
-- :math:`V_{GS} = 0` to 5.0V (:model:`sky130_fd_pr__nfet_g5v0d10v5*`), 0 to 1.95V (:model:`sky130_fd_pr__nfet_01v8*`)
-- :math:`V_{BS} = 0` to -5.5V, (:model:`sky130_fd_pr__nfet_g5v0d10v5`), +0.3 to -5.5V (:model:`sky130_fd_pr__nfet_05v0_nvt`), 0 to -1.95V (:model:`sky130_fd_pr__nfet_01v8*`)
+- :math:`V_{DS} = 0` to 1.95V
+- :math:`V_{GS} = 0` to 1.95V
+- :math:`V_{BS} = +0.3` to -1.95V
Details
~~~~~~~
-The ESD FET’s differ from the regular NMOS devices in several aspects, most notably:
-
-- Increased isolation spacing from contacts to surrounding STI
-- Increased drain contact-to-gate spacing
-- Placement of n-well under the drain contacts
-
-Major model output parameters are shown below and compared against the EDR (e-test) specs
+Major model output parameters are shown below and compared against the EDR (e-test) specs.
-.. include:: device-details/esd_nfet/esd_nfet-table0.rst
+.. include:: device-details/nfet_01v8/nfet_01v8-table0.rst
-The symbols of the :model:`sky130_fd_pr__esd_nfet_g5v0d10v5` and :model:`sky130_fd_pr__esd_nfet_g5v0d10v5_nvt` (ESD NMOS FET) are shown below:
+The symbol of the :model:`sky130_fd_pr__nfet_01v8` (1.8V NMOS FET) is shown below:
-|symbol-esd_nfet_g5v0d10v5| |symbol-esd_nfet_g5v0d10v5_nvt|
+|symbol-nfet_01v8|
-The cross-section of the ESD NMOS FET is shown below.
+The cross-section of the NMOS FET is shown below:
-|cross-section-esd_nfet|
+|cross-section-nfet_01v8|
-.. |symbol-esd_nfet_g5v0d10v5| image:: device-details/esd_nfet/symbol-esd_nfet_g5v0d10v5.svg
-.. |symbol-esd_nfet_g5v0d10v5_nvt| image:: device-details/esd_nfet/symbol-esd_nfet_g5v0d10v5_nvt.svg
-.. |cross-section-esd_nfet| image:: device-details/esd_nfet/cross-section-esd_nfet.svg
+The device shows the p-well inside of a deep n-well, but it can be made either with or without the DNW under the p-well
-
-5.0V/10.5V NMOS FET
--------------------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
-- Cell Name: :cell:`sky130_fd_pr__nfet_01v8`
-- Model Name: :model:`sky130_fd_pr__nfet_g5v0d10v5`
-
-Operating Voltages where SPICE models are valid
-
-- :math:`V_{DS} = 0` to 11.0V
-- :math:`V_{GS} = 0` to 5.5V
-- :math:`V_{BS} = 0` to -5.5V
-
-Details
-~~~~~~~
-
-Major model output parameters are shown below and compared against the EDR (e-test) specs
-
-
-.. include:: device-details/nfet_g5v0d10v5/nfet_g5v0d10v5-table0.rst
-
-
-
-The symbols of the :model:`sky130_fd_pr__nfet_g5v0d10v5` (5.0/10.5 V NMOS FET) is shown below:
-
-|symbol-nfet_g5v0d10v5|
-
-The cross-section of the 5.0/10.5 V NMOS FET is shown below.
-
-|cross-section-nfet_g5v0d10v5|
-
-.. |symbol-nfet_g5v0d10v5| image:: device-details/nfet_g5v0d10v5/symbol-nfet_g5v0d10v5.svg
-.. |cross-section-nfet_g5v0d10v5| image:: device-details/nfet_g5v0d10v5/cross-section-nfet_g5v0d10v5.svg
-
-
-11V/16V NMOS FET
-----------------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
-- Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain`
-- Model Name: :model:`sky130_fd_pr__nfet_g5v0d16v0`
-
-Operating Voltages where SPICE models are valid, subject to SOA limitations:
-
-- :math:`V_{DS} = 0` to +16V (\ :math:`V_{GS} = 0`\ )
-- :math:`V_{DS} = 0` to +11V (\ :math:`V_{GS} > 0`\ )
-- :math:`V_{GS} = 0` to 5.5V
-- :math:`V_{BS} = 0` to -2.0V
-
-Details
-~~~~~~~
-
-Major model output parameters are shown below and compared against the EDR (e-test) specs
-
-
-.. include:: device-details/nfet_g11v0d16v0/nfet_g11v0d16v0-table0.rst
-
-
-
-The symbol of the :model:`sky130_fd_pr__nfet_g5v0d16v0` (11V/16V NMOS FET) is shown below:
-
-|symbol-nfet_g11v0d16v0|
-
-The cross-section of the 11V/16VV NMOS FET is shown below.
-
-|cross-section-nfet_g11v0d16v0|
-
-.. |symbol-nfet_g11v0d16v0| image:: device-details/nfet_g11v0d16v0/symbol-nfet_g11v0d16v0.svg
-.. |cross-section-nfet_g11v0d16v0| image:: device-details/nfet_g11v0d16v0/cross-section-nfet_g11v0d16v0.svg
+.. |symbol-nfet_01v8| image:: device-details/nfet_01v8/symbol-nfet_01v8.svg
+.. |cross-section-nfet_01v8| image:: device-details/nfet_01v8/cross-section-nfet_01v8.svg
1.8V low-VT NMOS FET
@@ -412,20 +84,20 @@
.. |cross-section-nfet_01v8_lvt| image:: device-details/nfet_01v8_lvt/cross-section-nfet_01v8_lvt.svg
-1.8V NMOS FET
+1.8V PMOS FET
-------------
Spice Model Information
~~~~~~~~~~~~~~~~~~~~~~~
-- Cell Name: :cell:`sky130_fd_pr__nfet_01v8`
-- Model Name: :model:`sky130_fd_pr__nfet_01v8`
+- Cell Name: :cell:`sky130_fd_pr__pfet_01v8`
+- Model Name: :model:`sky130_fd_pr__pfet_01v8`
Operating Voltages where SPICE models are valid
-- :math:`V_{DS} = 0` to 1.95V
-- :math:`V_{GS} = 0` to 1.95V
-- :math:`V_{BS} = +0.3` to -1.95V
+- :math:`V_{DS} = 0` to -1.95V
+- :math:`V_{GS} = 0` to -1.95V
+- :math:`V_{BS} = -0.1` to +1.95V
Details
~~~~~~~
@@ -433,22 +105,159 @@
Major model output parameters are shown below and compared against the EDR (e-test) specs.
-.. include:: device-details/nfet_01v8/nfet_01v8-table0.rst
+.. include:: device-details/pfet_01v8/pfet_01v8-table0.rst
-The symbol of the :model:`sky130_fd_pr__nfet_01v8` (1.8V NMOS FET) is shown below:
+Inverter Gate Delays using sky130_fd_pr__nfet_01v8/:model:`sky130_fd_pr__pfet_01v8` device combinations:
-|symbol-nfet_01v8|
-The cross-section of the NMOS FET is shown below:
+.. include:: device-details/pfet_01v8/pfet_01v8-table1.rst
-|cross-section-nfet_01v8|
-The device shows the p-well inside of a deep n-well, but it can be made either with or without the DNW under the p-well
-.. |symbol-nfet_01v8| image:: device-details/nfet_01v8/symbol-nfet_01v8.svg
-.. |cross-section-nfet_01v8| image:: device-details/nfet_01v8/cross-section-nfet_01v8.svg
+The symbol of the :model:`sky130_fd_pr__pfet_01v8` (1.8V PMOS FET) is shown below:
+
+|symbol-pfet_01v8|
+
+The cross-section of the PMOS FET is shown below:
+
+|cross-section-pfet_01v8|
+
+.. |symbol-pfet_01v8| image:: device-details/pfet_01v8/symbol-pfet_01v8.svg
+.. |cross-section-pfet_01v8| image:: device-details/pfet_01v8/cross-section-pfet_01v8.svg
+
+
+1.8V low-VT PMOS FET
+--------------------
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+- Cell Name: :cell:`sky130_fd_pr__pfet_01v8`
+- Model Name: :model:`sky130_fd_pr__pfet_01v8_lvt`
+
+Operating Voltages where SPICE models are valid
+
+- :math:`V_{DS} = 0` to -1.95V
+- :math:`V_{GS} = 0` to -1.95V
+- :math:`V_{BS} = -0.1` to +1.95V
+
+Details
+~~~~~~~
+
+Major model output parameters are shown below and compared against the EDR (e-test) specs
+
+
+.. include:: device-details/pfet_01v8_lvt/pfet_01v8_lvt-table0.rst
+
+
+
+Inverter Gate Delays using sky130_fd_pr__nfet_01v8_lvt/:model:`sky130_fd_pr__pfet_01v8_lvt` device combinations:
+
+
+.. include:: device-details/pfet_01v8_lvt/pfet_01v8_lvt-table1.rst
+
+
+
+The symbol of the :model:`sky130_fd_pr__pfet_01v8_lvt` (1.8V low-VT PMOS FET) is shown below:
+
+|symbol-pfet_01v8_lvt|
+
+The cross-section of the low-VT PMOS FET is shown below. The cross-section is identical to the std PMOS FET except for the :math:`V_T` adjust implants (to achieve the lower :math:`V_T`)
+
+|cross-section-pfet_01v8_lvt|
+
+.. |symbol-pfet_01v8_lvt| image:: device-details/pfet_01v8_lvt/symbol-pfet_01v8_lvt.svg
+.. |cross-section-pfet_01v8_lvt| image:: device-details/pfet_01v8_lvt/cross-section-pfet_01v8_lvt.svg
+
+
+1.8V high-VT PMOS FET
+---------------------
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+- Cell Name: :cell:`sky130_fd_pr__pfet_01v8`
+- Model Name: :model:`sky130_fd_pr__pfet_01v8_hvt`
+
+Operating Voltages where SPICE models are valid
+
+- :math:`V_{DS} = 0` to -1.95V
+- :math:`V_{GS} = 0` to -1.95V
+- :math:`V_{BS} = -0.1` to +1.95V
+
+Details
+~~~~~~~
+
+Major model output parameters are shown below and compared against the EDR (e-test) specs
+
+
+.. include:: device-details/pfet_01v8_hvt/pfet_01v8_hvt-table0.rst
+
+
+
+Inverter Gate Delays using sky130_fd_pr__nfet_01v8/:model:`sky130_fd_pr__pfet_01v8_hvt` device combinations:
+
+
+.. include:: device-details/pfet_01v8_hvt/pfet_01v8_hvt-table1.rst
+
+
+
+The symbol of the :model:`sky130_fd_pr__pfet_01v8_hvt` (1.8V high-VT PMOS FET) is shown below:
+
+|symbol-pfet_01v8_hvt|
+
+The cross-section of the high-VT PMOS FET is shown below. The cross-section is identical to the std PMOS FET except for the :math:`V_T` adjust implants (to achieve the higher :math:`V_T`)
+
+|cross-section-pfet_01v8_hvt|
+
+.. |symbol-pfet_01v8_hvt| image:: device-details/pfet_01v8_hvt/symbol-pfet_01v8_hvt.svg
+.. |cross-section-pfet_01v8_hvt| image:: device-details/pfet_01v8_hvt/cross-section-pfet_01v8_hvt.svg
+
+
+1.8V accumulation-mode MOS varactors
+------------------------------------
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+- Cell Name: :cell:`capbn_b`
+- Model Name: :model:`sky130_fd_pr__cap_var_lvt`, :model:`sky130_fd_pr__cap_var_hvt`
+- Model Type: subcircuit
+
+Operating Voltages where SPICE models are valid
+
+- :math:`|V_0 – V_1| = 0` to 2.0V
+
+Details
+~~~~~~~
+
+The following devices are available; they are subcircuits with the N-well to P-substrate diodes built into the model:
+
+- :model:`sky130_fd_pr__cap_var_lvt` - low VT PMOS device option
+- :model:`sky130_fd_pr__cap_var_hvt` - high VT PMOS device option
+
+The varactors are used as tunable capacitors, major e-test parameters are listed below. Further details on the device models and their usage are in the SKY130 process Family Spice Models (002-21997), which can be obtained from SkyWater upon request.
+
+
+.. include:: device-details/cap_var/cap_var-table0.rst
+
+
+
+There is no equivalent varactor for 5V operation. The NHV or PHV devices should be connected as capacitors for use at 5V.
+
+The symbols for the varactors are shown below:
+
+|symbol-cap_var-a| |symbol-cap_var-b|
+
+The cross-section of the varactor is shown below:
+
+|cross-section-cap_var|
+
+.. |symbol-cap_var-a| image:: device-details/cap_var/symbol-cap_var-a.svg
+.. |symbol-cap_var-b| image:: device-details/cap_var/symbol-cap_var-b.svg
+.. |cross-section-cap_var| image:: device-details/cap_var/cross-section-cap_var.svg
3.0V native NMOS FET
@@ -498,7 +307,7 @@
Spice Model Information
~~~~~~~~~~~~~~~~~~~~~~~
-- Cell Name: :cell:`sky130_fd_pr__nfet_01v8`
+- Cell Name: :cell:`sky130_fd_pr__nfet_05v0_nvt`
- Model Name: :model:`sky130_fd_pr__nfet_05v0_nvt`
Operating Voltages where SPICE models are valid for :model:`sky130_fd_pr__nfet_05v0_nvt`
@@ -534,214 +343,41 @@
.. |cross-section-nfet_05v0_nvt| image:: device-details/nfet_05v0_nvt/../nfet_03v3_nvt-and-nfet_05v0_nvt/cross-section-nfet_03v3_nvt-and-nfet_05v0_nvt.svg
-20V NMOS FET
-------------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
-- Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain`
-- Model Name: :model:`sky130_fd_pr__nfet_20v0`
-
-Operating Voltages where SPICE models are valid, subject to SOA limitations:
-
-- :math:`V_{DS} = 0` to +22V
-- :math:`V_{GS} = 0` to 5.5V
-- :math:`V_{BS} = 0` to -2.0V
-
-Details
-~~~~~~~
-
-The 20V NMOS FET has similar construction to the 11V/16V NMOS FET, with several differences:
-
-- Longer drift region
-- Longer poly gate
-- Larger W/L
-- Devices placed in pairs (drain in center, sources on outside)
-
-Major model output parameters are shown below and compared against the EDR (e-test) specs
-
-
-.. include:: device-details/nfet_20v0/nfet_20v0-table0.rst
-
-
-
-The symbol of the :model:`sky130_fd_pr__nfet_20v0` (20V NMOS FET) is shown below.
-
-|symbol-nfet_20v0|
-
-The cross-section of the 20V NMOS FET is shown below.
-
-|cross-section-nfet_20v0|
-
-.. |symbol-nfet_20v0| image:: device-details/nfet_20v0/symbol-nfet_20v0.svg
-.. |cross-section-nfet_20v0| image:: device-details/nfet_20v0/cross-section-nfet_20v0.svg
-
-
-20V isolated NMOS FET
----------------------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
-- Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain`
-- Model Name: :model:`sky130_fd_pr__nfet_20v0_iso`
-
-Operating Voltages where SPICE models are valid, subject to SOA limitations:
-
-- :math:`V_{DS} = 0` to +22V
-- :math:`V_{GS} = 0` to 5.5V
-- :math:`V_{BS} = 0` to -2.0V
-
-Details
-~~~~~~~
-
-The 20V isolated NMOS FET has the same construction as the 20V NMOS FET, but is built over a Deep N-well. This permits the p-well to be isolated from the substrate and permit “high-side” usage (where the PW body is held above ground).
-
-Major model output parameters are shown below and compared against the EDR (e-test) specs
-
-
-.. include:: device-details/nfet_20v0_iso/nfet_20v0_iso-table0.rst
-
-
-
-The symbol of the :model:`sky130_fd_pr__nfet_20v0_iso` (20V isolated NMOS FET) is shown below.
-
-|symbol-nfet_20v0_iso|
-
-The cross-section of the 20V isolated NMOS FET is shown below.
-
-|cross-section-nfet_20v0_iso|
-
-.. |symbol-nfet_20v0_iso| image:: device-details/nfet_20v0_iso/symbol-nfet_20v0_iso.svg
-.. |cross-section-nfet_20v0_iso| image:: device-details/nfet_20v0_iso/cross-section-nfet_20v0_iso.svg
-
-
-20V native NMOS FET
+5.0V/10.5V NMOS FET
-------------------
Spice Model Information
~~~~~~~~~~~~~~~~~~~~~~~
-- Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain`
-- Model Name: :model:`sky130_fd_pr__nfet_20v0_nvt`
+- Cell Name: :cell:`sky130_fd_pr__nfet_01v8`
+- Model Name: :model:`sky130_fd_pr__nfet_g5v0d10v5`
-Operating Voltages where SPICE models are valid, subject to SOA limitations:
+Operating Voltages where SPICE models are valid
-- :math:`V_{DS} = 0` to +22V
+- :math:`V_{DS} = 0` to 11.0V
- :math:`V_{GS} = 0` to 5.5V
-- :math:`V_{BS} = 0` to -2.0V
+- :math:`V_{BS} = 0` to -5.5V
Details
~~~~~~~
-The 20V native NMOS FET is similar to the 20V isolated NMOS FET, but has all Vt implants blocked to achieve a very low VT.
-
Major model output parameters are shown below and compared against the EDR (e-test) specs
-.. include:: device-details/nfet_20v0_nvt/nfet_20v0_nvt-table0.rst
+.. include:: device-details/nfet_g5v0d10v5/nfet_g5v0d10v5-table0.rst
-The symbol of the :model:`sky130_fd_pr__nfet_20v0_nvt` (20V native NMOS FET) shown below.
+The symbols of the :model:`sky130_fd_pr__nfet_g5v0d10v5` (5.0/10.5 V NMOS FET) is shown below:
-|symbol-nfet_20v0_nvt|
+|symbol-nfet_g5v0d10v5|
-The cross-section of the 20V native NMOS FET is shown below.
+The cross-section of the 5.0/10.5 V NMOS FET is shown below.
-|cross-section-nfet_20v0_nvt|
+|cross-section-nfet_g5v0d10v5|
-.. |symbol-nfet_20v0_nvt| image:: device-details/nfet_20v0_nvt/symbol-nfet_20v0_nvt.svg
-.. |cross-section-nfet_20v0_nvt| image:: device-details/nfet_20v0_nvt/cross-section-nfet_20v0_nvt.svg
-
-
-20V NMOS zero-VT FET
---------------------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
-- Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain`
-- Model Name: :model:`sky130_fd_pr__nfet_20v0_zvt`
-
-Operating Voltages where SPICE models are valid, subject to SOA limitations:
-
-- :math:`V_{DS} = 0` to +22V
-- :math:`V_{GS} = 0` to 5.5V
-- :math:`V_{BS} = 0` to -2.0V
-
-Details
-~~~~~~~
-
-The 20V NMOS zero-VT FET has p-well and all Vt implants blocked to achieve a zero VT.
-
-Major model output parameters are shown below and compared against the EDR (e-test) specs
-
-
-.. include:: device-details/nfet_20v0_zvt/nfet_20v0_zvt-table0.rst
-
-
-
-The symbol of the :model:`sky130_fd_pr__nfet_20v0_zvt` (20V NMOS zero-VT FET) is still under development.
-
-The cross-section of the 20V NMOS zero-VT FET is shown below.
-
-|cross-section-nfet_20v0_zvt|
-
-.. |cross-section-nfet_20v0_zvt| image:: device-details/nfet_20v0_zvt/cross-section-nfet_20v0_zvt.svg
-
-
-Bipolar (NPN)
--------------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
-- Cell Name: :cell:`sky130_fd_pr__npn_05v5`
-- Model Names: :model:`sky130_fd_pr__npn_05v5`, :model:`sky130_fd_pr__npn_11v0`
-
-Operating regime where SPICE models are valid
-
-- :math:`|V_{CE}| = 0` to 5.0V
-- :math:`|V_{BE}| = 0` to 5.0V
-- :math:`I_{CE} = 0.01` to 10 µA/µm\ :sup:`2`
-
-Details
-~~~~~~~
-
-The SKY130 process offers “free” NPN devices. The NPN uses the deep n-well as the collector. The device is not optimized, and must be used in the forward-active mode. The following sizes of NPN’s are available:
-
-- ungated device with emitter 1.0 x 1.0
-- ungated device with emitter 1.0 x 2.0
-- poly-gated version with octagonal emitter of A = 1.97 µm\ :sup:`2`
-
-The :model:`sky130_fd_pr__npn_11v0` device has a poly gate placed between the emitter and base diffusions, to prevent carrier recombination at the STI edge and increase β. The poly gate is connected to the emitter terminal.
-
-Using this device must be done in conjunction with the correct guard rings, to avoid potential latchup issues with nearby circuitry. Reverse-active mode operation of the BJT’s are neither modeled nor permitted. E-test specs for the NPN devices are shown in the table below:
-
-
-.. include:: device-details/npn_05v0/npn_05v0-table0.rst
-
-
-
-Symbols for the :model:`sky130_fd_pr__npn_05v5` are shown below
-
-|symbol-npn_05v0-1| |symbol-npn_05v0-2| |symbol-npn_05v0-3|
-
-The cross-section of the :model:`sky130_fd_pr__npn_05v5` is shown below.
-
-|cross-section-npn_05v0|
-
-The cross-section of the :model:`sky130_fd_pr__npn_11v0` is shown below. The poly gate is tied to the emitter to prevent the parasitic MOSFET from turning on.
-
-|cross-section-npn_11v0|
-
-.. |symbol-npn_05v0-1| image:: device-details/npn_05v0/symbol-npn_05v0-1.svg
-.. |symbol-npn_05v0-2| image:: device-details/npn_05v0/symbol-npn_05v0-2.svg
-.. |symbol-npn_05v0-3| image:: device-details/npn_05v0/symbol-npn_05v0-3.svg
-.. |cross-section-npn_05v0| image:: device-details/npn_05v0/cross-section-npn_05v0.svg
-.. |cross-section-npn_11v0| image:: device-details/npn_05v0/cross-section-npn_11v0.svg
+.. |symbol-nfet_g5v0d10v5| image:: device-details/nfet_g5v0d10v5/symbol-nfet_g5v0d10v5.svg
+.. |cross-section-nfet_g5v0d10v5| image:: device-details/nfet_g5v0d10v5/cross-section-nfet_g5v0d10v5.svg
5.0V/10.5V PMOS FET
@@ -827,20 +463,21 @@
.. |cross-section-pfet_g5v0d16v0| image:: device-details/pfet_g5v0d16v0/cross-section-pfet_g5v0d16v0.svg
-1.8V high-VT PMOS FET
----------------------
+11V/16V NMOS FET
+----------------
Spice Model Information
~~~~~~~~~~~~~~~~~~~~~~~
-- Cell Name: :cell:`sky130_fd_pr__pfet_01v8`
-- Model Name: :model:`sky130_fd_pr__pfet_01v8_hvt`
+- Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain`
+- Model Name: :model:`sky130_fd_pr__nfet_g5v0d16v0`
-Operating Voltages where SPICE models are valid
+Operating Voltages where SPICE models are valid, subject to SOA limitations:
-- :math:`V_{DS} = 0` to -1.95V
-- :math:`V_{GS} = 0` to -1.95V
-- :math:`V_{BS} = -0.1` to +1.95V
+- :math:`V_{DS} = 0` to +16V (\ :math:`V_{GS} = 0`\ )
+- :math:`V_{DS} = 0` to +11V (\ :math:`V_{GS} > 0`\ )
+- :math:`V_{GS} = 0` to 5.5V
+- :math:`V_{BS} = 0` to -2.0V
Details
~~~~~~~
@@ -848,115 +485,178 @@
Major model output parameters are shown below and compared against the EDR (e-test) specs
-.. include:: device-details/pfet_01v8_hvt/pfet_01v8_hvt-table0.rst
+.. include:: device-details/nfet_g11v0d16v0/nfet_g11v0d16v0-table0.rst
-Inverter Gate Delays using sky130_fd_pr__nfet_01v8/:model:`sky130_fd_pr__pfet_01v8_hvt` device combinations:
+The symbol of the :model:`sky130_fd_pr__nfet_g5v0d16v0` (11V/16V NMOS FET) is shown below:
+
+|symbol-nfet_g11v0d16v0|
+
+The cross-section of the 11V/16VV NMOS FET is shown below.
+
+|cross-section-nfet_g11v0d16v0|
+
+.. |symbol-nfet_g11v0d16v0| image:: device-details/nfet_g11v0d16v0/symbol-nfet_g11v0d16v0.svg
+.. |cross-section-nfet_g11v0d16v0| image:: device-details/nfet_g11v0d16v0/cross-section-nfet_g11v0d16v0.svg
-.. include:: device-details/pfet_01v8_hvt/pfet_01v8_hvt-table1.rst
+20V NMOS FET
+------------
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+- Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain`
+- Model Name: :model:`sky130_fd_pr__nfet_20v0`
+
+Operating Voltages where SPICE models are valid, subject to SOA limitations:
+
+- :math:`V_{DS} = 0` to +22V
+- :math:`V_{GS} = 0` to 5.5V
+- :math:`V_{BS} = 0` to -2.0V
+
+Details
+~~~~~~~
+
+The 20V NMOS FET has similar construction to the 11V/16V NMOS FET, with several differences:
+
+- Longer drift region
+- Longer poly gate
+- Larger W/L
+- Devices placed in pairs (drain in center, sources on outside)
+
+Major model output parameters are shown below and compared against the EDR (e-test) specs
+
+
+.. include:: device-details/nfet_20v0/nfet_20v0-table0.rst
-The symbol of the :model:`sky130_fd_pr__pfet_01v8_hvt` (1.8V high-VT PMOS FET) is shown below:
+The symbol of the :model:`sky130_fd_pr__nfet_20v0` (20V NMOS FET) is shown below.
-|symbol-pfet_01v8_hvt|
+|symbol-nfet_20v0|
-The cross-section of the high-VT PMOS FET is shown below. The cross-section is identical to the std PMOS FET except for the :math:`V_T` adjust implants (to achieve the higher :math:`V_T`)
+The cross-section of the 20V NMOS FET is shown below.
-|cross-section-pfet_01v8_hvt|
+|cross-section-nfet_20v0|
-.. |symbol-pfet_01v8_hvt| image:: device-details/pfet_01v8_hvt/symbol-pfet_01v8_hvt.svg
-.. |cross-section-pfet_01v8_hvt| image:: device-details/pfet_01v8_hvt/cross-section-pfet_01v8_hvt.svg
+.. |symbol-nfet_20v0| image:: device-details/nfet_20v0/symbol-nfet_20v0.svg
+.. |cross-section-nfet_20v0| image:: device-details/nfet_20v0/cross-section-nfet_20v0.svg
-1.8V low-VT PMOS FET
+20V native NMOS FET
+-------------------
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+- Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain`
+- Model Name: :model:`sky130_fd_pr__nfet_20v0_nvt`
+
+Operating Voltages where SPICE models are valid, subject to SOA limitations:
+
+- :math:`V_{DS} = 0` to +22V
+- :math:`V_{GS} = 0` to 5.5V
+- :math:`V_{BS} = 0` to -2.0V
+
+Details
+~~~~~~~
+
+The 20V native NMOS FET is similar to the 20V isolated NMOS FET, but has all Vt implants blocked to achieve a very low VT.
+
+Major model output parameters are shown below and compared against the EDR (e-test) specs
+
+
+.. include:: device-details/nfet_20v0_nvt/nfet_20v0_nvt-table0.rst
+
+
+
+The symbol of the :model:`sky130_fd_pr__nfet_20v0_nvt` (20V native NMOS FET) shown below.
+
+|symbol-nfet_20v0_nvt|
+
+The cross-section of the 20V native NMOS FET is shown below.
+
+|cross-section-nfet_20v0_nvt|
+
+.. |symbol-nfet_20v0_nvt| image:: device-details/nfet_20v0_nvt/symbol-nfet_20v0_nvt.svg
+.. |cross-section-nfet_20v0_nvt| image:: device-details/nfet_20v0_nvt/cross-section-nfet_20v0_nvt.svg
+
+
+20V zero-VT NMOS FET
--------------------
Spice Model Information
~~~~~~~~~~~~~~~~~~~~~~~
-- Cell Name: :cell:`sky130_fd_pr__pfet_01v8`
-- Model Name: :model:`sky130_fd_pr__pfet_01v8_lvt`
+- Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain`
+- Model Name: :model:`sky130_fd_pr__nfet_20v0_zvt`
-Operating Voltages where SPICE models are valid
+Operating Voltages where SPICE models are valid, subject to SOA limitations:
-- :math:`V_{DS} = 0` to -1.95V
-- :math:`V_{GS} = 0` to -1.95V
-- :math:`V_{BS} = -0.1` to +1.95V
+- :math:`V_{DS} = 0` to +22V
+- :math:`V_{GS} = 0` to 5.5V
+- :math:`V_{BS} = 0` to -2.0V
Details
~~~~~~~
+The 20V NMOS zero-VT FET has p-well and all Vt implants blocked to achieve a zero VT.
+
Major model output parameters are shown below and compared against the EDR (e-test) specs
-.. include:: device-details/pfet_01v8_lvt/pfet_01v8_lvt-table0.rst
+.. include:: device-details/nfet_20v0_zvt/nfet_20v0_zvt-table0.rst
-Inverter Gate Delays using sky130_fd_pr__nfet_01v8_lvt/:model:`sky130_fd_pr__pfet_01v8_lvt` device combinations:
+The symbol of the :model:`sky130_fd_pr__nfet_20v0_zvt` (20V NMOS zero-VT FET) is still under development.
+
+The cross-section of the 20V NMOS zero-VT FET is shown below.
+
+|cross-section-nfet_20v0_zvt|
+
+.. |cross-section-nfet_20v0_zvt| image:: device-details/nfet_20v0_zvt/cross-section-nfet_20v0_zvt.svg
-.. include:: device-details/pfet_01v8_lvt/pfet_01v8_lvt-table1.rst
-
-
-
-The symbol of the :model:`sky130_fd_pr__pfet_01v8_lvt` (1.8V low-VT PMOS FET) is shown below:
-
-|symbol-pfet_01v8_lvt|
-
-The cross-section of the low-VT PMOS FET is shown below. The cross-section is identical to the std PMOS FET except for the :math:`V_T` adjust implants (to achieve the lower :math:`V_T`)
-
-|cross-section-pfet_01v8_lvt|
-
-.. |symbol-pfet_01v8_lvt| image:: device-details/pfet_01v8_lvt/symbol-pfet_01v8_lvt.svg
-.. |cross-section-pfet_01v8_lvt| image:: device-details/pfet_01v8_lvt/cross-section-pfet_01v8_lvt.svg
-
-
-1.8V PMOS FET
--------------
+20V isolated NMOS FET
+---------------------
Spice Model Information
~~~~~~~~~~~~~~~~~~~~~~~
-- Cell Name: :cell:`sky130_fd_pr__pfet_01v8`
-- Model Name: :model:`sky130_fd_pr__pfet_01v8`
+- Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain`
+- Model Name: :model:`sky130_fd_pr__nfet_20v0_iso`
-Operating Voltages where SPICE models are valid
+Operating Voltages where SPICE models are valid, subject to SOA limitations:
-- :math:`V_{DS} = 0` to -1.95V
-- :math:`V_{GS} = 0` to -1.95V
-- :math:`V_{BS} = -0.1` to +1.95V
+- :math:`V_{DS} = 0` to +22V
+- :math:`V_{GS} = 0` to 5.5V
+- :math:`V_{BS} = 0` to -2.0V
Details
~~~~~~~
-Major model output parameters are shown below and compared against the EDR (e-test) specs.
+The 20V isolated NMOS FET has the same construction as the 20V NMOS FET, but is built over a Deep N-well. This permits the p-well to be isolated from the substrate and permit “high-side” usage (where the PW body is held above ground).
+
+Major model output parameters are shown below and compared against the EDR (e-test) specs
-.. include:: device-details/pfet_01v8/pfet_01v8-table0.rst
+.. include:: device-details/nfet_20v0_iso/nfet_20v0_iso-table0.rst
-Inverter Gate Delays using sky130_fd_pr__nfet_01v8/:model:`sky130_fd_pr__pfet_01v8` device combinations:
+The symbol of the :model:`sky130_fd_pr__nfet_20v0_iso` (20V isolated NMOS FET) is shown below.
+|symbol-nfet_20v0_iso|
-.. include:: device-details/pfet_01v8/pfet_01v8-table1.rst
+The cross-section of the 20V isolated NMOS FET is shown below.
+|cross-section-nfet_20v0_iso|
-
-The symbol of the :model:`sky130_fd_pr__pfet_01v8` (1.8V PMOS FET) is shown below:
-
-|symbol-pfet_01v8|
-
-The cross-section of the PMOS FET is shown below:
-
-|cross-section-pfet_01v8|
-
-.. |symbol-pfet_01v8| image:: device-details/pfet_01v8/symbol-pfet_01v8.svg
-.. |cross-section-pfet_01v8| image:: device-details/pfet_01v8/cross-section-pfet_01v8.svg
+.. |symbol-nfet_20v0_iso| image:: device-details/nfet_20v0_iso/symbol-nfet_20v0_iso.svg
+.. |cross-section-nfet_20v0_iso| image:: device-details/nfet_20v0_iso/cross-section-nfet_20v0_iso.svg
20V PMOS FET
@@ -1003,8 +703,166 @@
.. |cross-section-pfet_20v0| image:: device-details/pfet_20v0/cross-section-pfet_20v0.svg
-Bipolar (PNP)
--------------
+ESD NMOS FET
+------------
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+- Cell Name: :cell:`sky130_fd_pr__nfet_01v8`
+- Model Name: :model:`sky130_fd_pr__esd_nfet_01v8`, :model:`sky130_fd_pr__esd_nfet_g5v0d10v5`, :model:`sky130_fd_pr__esd_nfet_g5v0d10v5_nvt`
+
+Operating Voltages where SPICE models are valid
+
+- :math:`V_{DS} = 0` to 11.0V (:model:`sky130_fd_pr__nfet_g5v0d10v5*`), 0 to 1.95V (:model:`sky130_fd_pr__nfet_01v8*`)
+- :math:`V_{GS} = 0` to 5.0V (:model:`sky130_fd_pr__nfet_g5v0d10v5*`), 0 to 1.95V (:model:`sky130_fd_pr__nfet_01v8*`)
+- :math:`V_{BS} = 0` to -5.5V, (:model:`sky130_fd_pr__nfet_g5v0d10v5`), +0.3 to -5.5V (:model:`sky130_fd_pr__nfet_05v0_nvt`), 0 to -1.95V (:model:`sky130_fd_pr__nfet_01v8*`)
+
+Details
+~~~~~~~
+
+The ESD FET’s differ from the regular NMOS devices in several aspects, most notably:
+
+- Increased isolation spacing from contacts to surrounding STI
+- Increased drain contact-to-gate spacing
+- Placement of n-well under the drain contacts
+
+Major model output parameters are shown below and compared against the EDR (e-test) specs
+
+
+.. include:: device-details/esd_nfet/esd_nfet-table0.rst
+
+
+
+The symbols of the :model:`sky130_fd_pr__esd_nfet_g5v0d10v5` and :model:`sky130_fd_pr__esd_nfet_g5v0d10v5_nvt` (ESD NMOS FET) are shown below:
+
+|symbol-esd_nfet_g5v0d10v5| |symbol-esd_nfet_g5v0d10v5_nvt|
+
+The cross-section of the ESD NMOS FET is shown below.
+
+|cross-section-esd_nfet|
+
+.. |symbol-esd_nfet_g5v0d10v5| image:: device-details/esd_nfet/symbol-esd_nfet_g5v0d10v5.svg
+.. |symbol-esd_nfet_g5v0d10v5_nvt| image:: device-details/esd_nfet/symbol-esd_nfet_g5v0d10v5_nvt.svg
+.. |cross-section-esd_nfet| image:: device-details/esd_nfet/cross-section-esd_nfet.svg
+
+
+Diodes
+------
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+- Cell Name: :cell:`diode`
+- Model Names: :model:`sky130_fd_pr__diode_pw2nd_05v5`, :model:`sky130_fd_pr__diode_pw2nd_11v0`, :model:`sky130_fd_pr__diode_pw2nd_05v5_nvt`, :model:`sky130_fd_pr__diode_pw2nd_05v5_lvt`, :model:`sky130_fd_pr__diode_pd2nw_05v5`, :model:`sky130_fd_pr__diode_pd2nw_11v0`, :model:`sky130_fd_pr__diode_pd2nw_05v5_hvt`, :model:`sky130_fd_pr__diode_pd2nw_05v5_lvt`, :model:`sky130_fd_pr__model__parasitic__rf_diode_ps2nw`, :model:`sky130_fd_pr__model__parasitic__rf_diode_pw2dn`, :model:`sky130_fd_pr__model__parasitic__diode_pw2dn`, :model:`sky130_fd_pr__model__parasitic__diode_ps2dn`, :model:`dnwdiode_psub_victim`, :model:`dnwdiode_psub_aggressor`, :model:`sky130_fd_pr__model__parasitic__diode_ps2nw`, :model:`nwdiode_victim`, :model:`nwdiode_aggressor`, :model:`xesd_ndiode_h_X`, :model:`xesd_ndiode_h_dnwl_X`, :model:`xesd_pdiode_h_X (X = 100 or 200 or 300)`
+- Cell Name: :cell:`lvsdiode`
+- Model Names: :model:`sky130_fd_pr__diode_pw2nd_05v5`, :model:`sky130_fd_pr__diode_pw2nd_11v0`, :model:`sky130_fd_pr__diode_pd2nw_05v5`, :model:`sky130_fd_pr__diode_pd2nw_11v0`, :model:`sky130_fd_pr__model__parasitic__diode_ps2dn`, :model:`dnwdiode_psub_victim`, :model:`dnwdiode_psub_aggressor`, :model:`nwdiode_victim`, :model:`nwdiode_aggressor`, :model:`xesd_ndiode_h_X`, :model:`xesd_ndiode_h_dnwl_X`, :model:`xesd_pdiode_h_X (X = 100 or 200 or 300)`
+
+Operating regime where SPICE models are valid
+
+- :math:`|V_{d0} – V_{d1}| = 0` to 5.0V
+
+Details
+~~~~~~~
+
+
+.. include:: device-details/diodes/diodes-table0.rst
+
+
+
+Symbols for the diodes are shown below
+
+|symbol-diode-01|
+|symbol-diode-02|
+|symbol-diode-03|
+|symbol-diode-04|
+|symbol-diode-05|
+|symbol-diode-06|
+|symbol-diode-07|
+|symbol-diode-08|
+|symbol-diode-09|
+|symbol-diode-10|
+|symbol-diode-11|
+|symbol-diode-12|
+|symbol-diode-13|
+|symbol-diode-14|
+|symbol-diode-15|
+|symbol-diode-16|
+|symbol-diode-17|
+
+.. |symbol-diode-01| image:: device-details/diodes/symbol-diode-01.svg
+.. |symbol-diode-02| image:: device-details/diodes/symbol-diode-02.svg
+.. |symbol-diode-03| image:: device-details/diodes/symbol-diode-03.svg
+.. |symbol-diode-04| image:: device-details/diodes/symbol-diode-04.svg
+.. |symbol-diode-05| image:: device-details/diodes/symbol-diode-05.svg
+.. |symbol-diode-06| image:: device-details/diodes/symbol-diode-06.svg
+.. |symbol-diode-07| image:: device-details/diodes/symbol-diode-07.svg
+.. |symbol-diode-08| image:: device-details/diodes/symbol-diode-08.svg
+.. |symbol-diode-09| image:: device-details/diodes/symbol-diode-09.svg
+.. |symbol-diode-10| image:: device-details/diodes/symbol-diode-10.svg
+.. |symbol-diode-11| image:: device-details/diodes/symbol-diode-11.svg
+.. |symbol-diode-12| image:: device-details/diodes/symbol-diode-12.svg
+.. |symbol-diode-13| image:: device-details/diodes/symbol-diode-13.svg
+.. |symbol-diode-14| image:: device-details/diodes/symbol-diode-14.svg
+.. |symbol-diode-15| image:: device-details/diodes/symbol-diode-15.svg
+.. |symbol-diode-16| image:: device-details/diodes/symbol-diode-16.svg
+.. |symbol-diode-17| image:: device-details/diodes/symbol-diode-17.svg
+
+
+Bipolar NPN transistor
+----------------------
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+- Cell Name: :cell:`sky130_fd_pr__npn_05v5`
+- Model Names: :model:`sky130_fd_pr__npn_05v5`, :model:`sky130_fd_pr__npn_11v0`
+
+Operating regime where SPICE models are valid
+
+- :math:`|V_{CE}| = 0` to 5.0V
+- :math:`|V_{BE}| = 0` to 5.0V
+- :math:`I_{CE} = 0.01` to 10 µA/µm\ :sup:`2`
+
+Details
+~~~~~~~
+
+The SKY130 process offers “free” NPN devices. The NPN uses the deep n-well as the collector. The device is not optimized, and must be used in the forward-active mode. The following sizes of NPN’s are available:
+
+- ungated device with emitter 1.0 x 1.0
+- ungated device with emitter 1.0 x 2.0
+- poly-gated version with octagonal emitter of A = 1.97 µm\ :sup:`2`
+
+The :model:`sky130_fd_pr__npn_11v0` device has a poly gate placed between the emitter and base diffusions, to prevent carrier recombination at the STI edge and increase β. The poly gate is connected to the emitter terminal.
+
+Using this device must be done in conjunction with the correct guard rings, to avoid potential latchup issues with nearby circuitry. Reverse-active mode operation of the BJT’s are neither modeled nor permitted. E-test specs for the NPN devices are shown in the table below:
+
+
+.. include:: device-details/npn_05v0/npn_05v0-table0.rst
+
+
+
+Symbols for the :model:`sky130_fd_pr__npn_05v5` are shown below
+
+|symbol-npn_05v0-1| |symbol-npn_05v0-2| |symbol-npn_05v0-3|
+
+The cross-section of the :model:`sky130_fd_pr__npn_05v5` is shown below.
+
+|cross-section-npn_05v0|
+
+The cross-section of the :model:`sky130_fd_pr__npn_11v0` is shown below. The poly gate is tied to the emitter to prevent the parasitic MOSFET from turning on.
+
+|cross-section-npn_11v0|
+
+.. |symbol-npn_05v0-1| image:: device-details/npn_05v0/symbol-npn_05v0-1.svg
+.. |symbol-npn_05v0-2| image:: device-details/npn_05v0/symbol-npn_05v0-2.svg
+.. |symbol-npn_05v0-3| image:: device-details/npn_05v0/symbol-npn_05v0-3.svg
+.. |cross-section-npn_05v0| image:: device-details/npn_05v0/cross-section-npn_05v0.svg
+.. |cross-section-npn_11v0| image:: device-details/npn_05v0/cross-section-npn_11v0.svg
+
+
+Bipolar PNP transistor
+----------------------
Spice Model Information
~~~~~~~~~~~~~~~~~~~~~~~
@@ -1050,7 +908,121 @@
.. |cross-section-pnp_05v0| image:: device-details/pnp_05v0/cross-section-pnp_05v0.svg
-Generic Resistors
+SRAM cells
+----------
+
+The SKY130 process currently supports only single-port SRAM’s, which are contained in hard-IP libraries. These cells are constructed with smaller design rules (Table 9), along with OPC (optical proximity correction) techniques, to achieve small memory cells. Use of the memory cells or their devices outside the specific IP is prohibited. The schematic for the SRAM is shown below in Figure 10. This cell is available in the S8 IP offerings and is monitored at e-test through the use of “pinned out” devices within the specific arrays.
+
+|figure-10-schematics-of-the-single-port-sram|
+
+**Figure 10. Schematics of the Single Port SRAM.**
+
+A Dual-Port SRAM is currently being designed using a similar approach. Compilers for the SP and DP SRAM’s will be available end-2019.
+
+Operating Voltages where SPICE models are valid
+
+- :math:`V_{DS} = 0` to 1.8V
+- :math:`V_{GS} = 0` to 1.8V
+- :math:`V_{BS} = 0` to -1.8V
+
+Details
+~~~~~~~
+
+N-pass FET (SRAM)
+^^^^^^^^^^^^^^^^^
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+- Cell Name: :cell:`sky130_fd_pr__nfet_01v8`
+- Model Name (SRAM): :model:`sky130_fd_pr__special_nfet_pass`
+
+
+.. include:: device-details/special_sram/special_sram-table0.rst
+
+
+
+N-latch FET (SRAM)
+^^^^^^^^^^^^^^^^^^
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+- Cell Name: :cell:`sky130_fd_pr__nfet_01v8`
+- Model Name (SRAM): :model:`sky130_fd_pr__special_nfet_latch`
+
+
+.. include:: device-details/special_sram/special_sram-table1.rst
+
+
+
+P-latch FET (SRAM)
+^^^^^^^^^^^^^^^^^^
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+- Cell Name: :cell:`sky130_fd_pr__pfet_01v8`
+- Model Name (SRAM): :model:`sky130_fd_pr__special_pfet_pass`
+
+
+.. include:: device-details/special_sram/special_sram-table2.rst
+
+
+
+.. |figure-10-schematics-of-the-single-port-sram| image:: device-details/special_sram/figure-10-schematics-of-the-single-port-sram.svg
+
+
+SONOS cells
+-----------
+
+The SKY130 process currently supports two SONOS flash memory cells:
+
+- The original cell is supported in the S8PFHD, S8PHRC and S8PFN-20 technology options, with operating temperatures from -55°C to +155°C
+- The “star” cell is supported in the S8PHIRS technology option. Its cell size is approximately 25% smaller than the original cell, but its temperature range is restricted to -40°C to +125°C.
+
+Spice models for the memory cells exist for multiple conditions:
+
+
+.. include:: device-details/special_sonosfet/special_sonosfet-table0.rst
+
+
+
+Program and Erase characteristics are described in more detail in the ***S8 Nonvolatile Technology Spec*** (001-08712), and summarized below:
+
+
+.. include:: device-details/special_sonosfet/special_sonosfet-table1.rst
+
+
+
+Endurance behavior is illustrated below (100K cycles guaranteed):
+
+|sonos-erase-program|
+
+Data retention behavior is shown below at 85C\ |sonos-data-retention|
+
+E-test parameters are summarized below for both original and star cells:
+
+
+.. include:: device-details/special_sonosfet/special_sonosfet-table2.rst
+
+
+
+The schematic for the 2-T SONOS memory cell is shown below:
+
+|schematic-sonos-cell|
+
+The cross-section of the 2-T SONOS cell is shown below.
+
+|cross-section-sonos-cell|
+
+.. |sonos-erase-program| image:: device-details/special_sonosfet/sonos-erase-program.svg
+.. |sonos-data-retention| image:: device-details/special_sonosfet/sonos-data-retention.svg
+.. |schematic-sonos-cell| image:: device-details/special_sonosfet/schematic-sonos-cell.svg
+.. |cross-section-sonos-cell| image:: device-details/special_sonosfet/cross-section-sonos-cell.svg
+
+
+Generic resistors
-----------------
Generic resistors are supported in the PDK but are not recommended for analog applications. Resistor values will be extracted from the layout as long as the resistor layer is utilized, for LVS against schematic elements.
@@ -1242,117 +1214,145 @@
.. |symbol-res_xhigh_po| image:: device-details/res_xhigh/symbol-res_xhigh_po.svg
-SONOS cells
------------
+MiM capacitors
+--------------
-The SKY130 process currently supports two SONOS flash memory cells:
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
-- The original cell is supported in the S8PFHD, S8PHRC and S8PFN-20 technology options, with operating temperatures from -55°C to +155°C
-- The “star” cell is supported in the S8PHIRS technology option. Its cell size is approximately 25% smaller than the original cell, but its temperature range is restricted to -40°C to +125°C.
-
-Spice models for the memory cells exist for multiple conditions:
-
-
-.. include:: device-details/special_sonosfet/special_sonosfet-table0.rst
-
-
-
-Program and Erase characteristics are described in more detail in the ***S8 Nonvolatile Technology Spec*** (001-08712), and summarized below:
-
-
-.. include:: device-details/special_sonosfet/special_sonosfet-table1.rst
-
-
-
-Endurance behavior is illustrated below (100K cycles guaranteed):
-
-|sonos-erase-program|
-
-Data retention behavior is shown below at 85C\ |sonos-data-retention|
-
-E-test parameters are summarized below for both original and star cells:
-
-
-.. include:: device-details/special_sonosfet/special_sonosfet-table2.rst
-
-
-
-The schematic for the 2-T SONOS memory cell is shown below:
-
-|schematic-sonos-cell|
-
-The cross-section of the 2-T SONOS cell is shown below.
-
-|cross-section-sonos-cell|
-
-.. |sonos-erase-program| image:: device-details/special_sonosfet/sonos-erase-program.svg
-.. |sonos-data-retention| image:: device-details/special_sonosfet/sonos-data-retention.svg
-.. |schematic-sonos-cell| image:: device-details/special_sonosfet/schematic-sonos-cell.svg
-.. |cross-section-sonos-cell| image:: device-details/special_sonosfet/cross-section-sonos-cell.svg
-
-
-SRAM cells
-----------
-
-The SKY130 process currently supports only single-port SRAM’s, which are contained in hard-IP libraries. These cells are constructed with smaller design rules (Table 9), along with OPC (optical proximity correction) techniques, to achieve small memory cells. Use of the memory cells or their devices outside the specific IP is prohibited. The schematic for the SRAM is shown below in Figure 10. This cell is available in the S8 IP offerings and is monitored at e-test through the use of “pinned out” devices within the specific arrays.
-
-|figure-10-schematics-of-the-single-port-sram|
-
-**Figure 10. Schematics of the Single Port SRAM.**
-
-A Dual-Port SRAM is currently being designed using a similar approach. Compilers for the SP and DP SRAM’s will be available end-2019.
+- Cell Name: :cell:`sky130_fd_pr__cap_mim_m3__base`, :cell:`sky130_fd_pr__cap_mim_m4__base`
+- Model Names: :model:`sky130_fd_pr__model__cap_mim`, :model:`sky130_fd_pr__cap_mim_m4`
Operating Voltages where SPICE models are valid
-- :math:`V_{DS} = 0` to 1.8V
-- :math:`V_{GS} = 0` to 1.8V
-- :math:`V_{BS} = 0` to -1.8V
+- :math:`|V_{c0} – V_{c1}| = 0` to 5.0V
Details
~~~~~~~
-N-pass FET (SRAM)
-^^^^^^^^^^^^^^^^^
+The MiM capacitor is constructed using a thin dielectric over metal, followed by a thin conductor layer on top of the dielectric. There are two possible constructions:
+
+- CAPM over Metal-3
+- CAP2M over Metal-4
+
+The constructions are identical, and the capacitors may be stacked to maximize total capacitance.
+
+Electrical specs are listed below:
+
+
+.. include:: device-details/cap_mim/cap_mim-table0.rst
+
+
+
+The symbol for the MiM capacitor is shown below. Note that the cap model is a sub-circuit which accounts for the parasitic contact resistance and the parasitic capacitance from the bottom plate to substrate.
+
+|symbol-cap_mim|
+
+Cell name
+
+M \* W \* L
+
+Calc capacitance
+
+The cross-section of the “stacked” MiM capacitor is shown below:
+
+|cross-section-cap_mim|
+
+.. |symbol-cap_mim| image:: device-details/cap_mim/symbol-cap_mim.svg
+.. |cross-section-cap_mim| image:: device-details/cap_mim/cross-section-cap_mim.svg
+
+
+Vertical Parallel Plate (VPP) capacitors
+----------------------------------------
Spice Model Information
~~~~~~~~~~~~~~~~~~~~~~~
-- Cell Name: :cell:`sky130_fd_pr__nfet_01v8`
-- Model Name (SRAM): :model:`sky130_fd_pr__special_nfet_pass`
+- Cell Name: :cell:`sky130_fd_pr__cap_vpp_XXpXxYYpY_{MM}(_shield(SS)*)(_float(FF)*)(_(VVVV))`
+- Model Names: :model:`sky130_fd_pr__cap_vpp_*`
+
+ - X and Y are size dimentions
+ - MM refers to the layers which are used for the capacitance
+ - SS refers to the layers which are used as shields (`noshield` when no shield is used)
+ - FF refers to the layers which are floating.
+ - VVVVV refers to the "variant" when there are multiple devices of the same configuration
+
+Operating Voltages where SPICE models are valid
+
+- :math:`|V_{c0} – V_{c1}| = 0` to 5.5V
+
+Details
+~~~~~~~
+
+The VPP caps utilize the tight spacings of the metal lines to create capacitors using the available metal layers. The fingers go in opposite directions to minimize alignment-related variability, and the capacitor sits on field oxide to minimize silicon capacitance effects. A schematic diagram of the layout is shown below:
+
+.. todo::
+
+ M3
+
+ **M2**
+
+ LI
+
+ M1
+
+ LAYOUT of M2, M3, M4
+
+ LAYOUT of LI and M1 (with POLY sheet)
+
+ **POLY**
+
+ **M4**
+
+These capacitors are fixed-size, and they can be connected together to multiply the effective capacitance of a given node. There are two different constructions.
+
+Parallel VPP Capacitors
+^^^^^^^^^^^^^^^^^^^^^^^
+
+These are older versions, where stacked metal lines run parallel:
-.. include:: device-details/special_sram/special_sram-table0.rst
+- :model:`sky130_fd_pr__cap_vpp_08p6x07p8_m1m2_noshield` (M1 \|\| M2 only, 7.84 x 8.58)
+- :model:`sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_noshield_o2` (M1 \|\| M2 only, 4.38 x 4.59)
+- :model:`sky130_fd_pr__cap_vpp_02p4x04p6_m1m2_noshield` (M1 \|\| M2 only, 2.19 x 4.59)
+- :model:`sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_noshield` (M1 :sub:`┴` M2, 4.4 x 4.6, 4 quadrants)
+- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_m1m2_noshield` (M1 :sub:`┴` M2, 11.5 x 11.7, 4 quadrants)
+- :model:`sky130_fd_pr__cap_vpp_44p7x23p1_pol1m1m2m3m4m5_noshield`
+- :model:`sky130_fd_pr__cap_vpp_02p7x06p1_m1m2m3m4_shieldl1_fingercap` (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 5.0)
+- :model:`sky130_fd_pr__cap_vpp_02p9x06p1_m1m2m3m4_shieldl1_fingercap2` (M1 \|\| M2 \|\| M3 \|\| M4, 2.85 x 5.0)
+- :model:`sky130_fd_pr__cap_vpp_02p7x11p1_m1m2m3m4_shieldl1_fingercap` (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 10.0)
+- :model:`sky130_fd_pr__cap_vpp_02p7x21p1_m1m2m3m4_shieldl1_fingercap` (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 20.0)
+- :model:`sky130_fd_pr__cap_vpp_02p7x41p1_m1m2m3m4_shieldl1_fingercap` (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 40.0)
+
+The symbol for these capacitors is shown below. The terminals c0 and c1 represent the two sides of the capacitor, with b as the body (sub or well).
+
+|symbol-cap_vpp-parallel|
+
+Perpendicular VPP Capacitors
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+These are newer versions, where stacked metal lines run perpendicular and there are shields on top and bottom:
+
+- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3m4_shieldm5` (11.5x11.7, with M5 shield)
+- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3m4_shieldpom5` (11.5x11.7, with poly and M5 shield)
+- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3m4_shieldl1m5` (11.5x11.7, with LI and M5 shield)
+- :model:`sky130_fd_pr__cap_vpp_04p4x04p6_m1m2m3_shieldl1m5_floatm4` (4.4x4.6, M3 float, LI / M5 shield)
+- :model:`sky130_fd_pr__cap_vpp_08p6x07p8_m1m2m3_shieldl1m5_floatm4` (8.6x7.9, M3 float, LI / M5 shield)
+- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3_shieldl1m5_floatm4` (11.5x11.7, M3 float, LI / M5 shield)
+- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3_shieldm4` (11.5x11.7, with M4 shield)
+- :model:`sky130_fd_pr__cap_vpp_06p8x06p1_l1m1m2m3_shieldpom4` (6.8x6.1, with poly and M4 shield)
+- :model:`sky130_fd_pr__cap_vpp_06p8x06p1_m1m2m3_shieldl1m4` (6.8x6.1, with LI and M4 shield)
+- :model:`sky130_fd_pr__cap_vpp_11p3x11p8_l1m1m2m3m4_shieldm5` (11.5x11.7, over 2 :model:`sky130_fd_pr__nfet_05v0_nvt` of 10/4 each)
+
+The symbol for these capacitors is shown below. The terminals c0 and c1 are the two capacitor terminals, “top” represents the top shield and “sub” the bottom shield.
+
+|symbol-cap_vpp-perpendicular|
+
+The capacitors are fixed-size elements and must be used as-is; they can be used in multiples.
+.. include:: device-details/cap_vpp/cap_vpp-table0.rst
-N-latch FET (SRAM)
-^^^^^^^^^^^^^^^^^^
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
-- Cell Name: :cell:`sky130_fd_pr__nfet_01v8`
-- Model Name (SRAM): :model:`sky130_fd_pr__special_nfet_latch`
-
-
-.. include:: device-details/special_sram/special_sram-table1.rst
-
-
-
-P-latch FET (SRAM)
-^^^^^^^^^^^^^^^^^^
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
-- Cell Name: :cell:`sky130_fd_pr__pfet_01v8`
-- Model Name (SRAM): :model:`sky130_fd_pr__special_pfet_pass`
-
-
-.. include:: device-details/special_sram/special_sram-table2.rst
-
-
-
-.. |figure-10-schematics-of-the-single-port-sram| image:: device-details/special_sram/figure-10-schematics-of-the-single-port-sram.svg
-
+.. |symbol-cap_vpp-parallel| image:: device-details/cap_vpp/symbol-cap_vpp-parallel.svg
+.. |symbol-cap_vpp-perpendicular| image:: device-details/cap_vpp/symbol-cap_vpp-perpendicular.svg
diff --git a/docs/rules/device-details/cap_mim/index.rst b/docs/rules/device-details/cap_mim/index.rst
index 6a3958f..16ed45f 100644
--- a/docs/rules/device-details/cap_mim/index.rst
+++ b/docs/rules/device-details/cap_mim/index.rst
@@ -1,5 +1,5 @@
-MiM Capacitor
--------------
+MiM capacitors
+--------------
Spice Model Information
~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/rules/device-details/cap_var/index.rst b/docs/rules/device-details/cap_var/index.rst
index 3209cee..9383211 100644
--- a/docs/rules/device-details/cap_var/index.rst
+++ b/docs/rules/device-details/cap_var/index.rst
@@ -1,5 +1,5 @@
-Varactors
----------
+1.8V accumulation-mode MOS varactors
+------------------------------------
Spice Model Information
~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/rules/device-details/esd_nfet/index.rst b/docs/rules/device-details/esd_nfet/index.rst
index 1d57c06..8f3e89c 100644
--- a/docs/rules/device-details/esd_nfet/index.rst
+++ b/docs/rules/device-details/esd_nfet/index.rst
@@ -1,4 +1,4 @@
-NMOS ESD FET
+ESD NMOS FET
------------
Spice Model Information
diff --git a/docs/rules/device-details/nfet_05v0_nvt/index.rst b/docs/rules/device-details/nfet_05v0_nvt/index.rst
index a44a233..e516f22 100644
--- a/docs/rules/device-details/nfet_05v0_nvt/index.rst
+++ b/docs/rules/device-details/nfet_05v0_nvt/index.rst
@@ -4,7 +4,7 @@
Spice Model Information
~~~~~~~~~~~~~~~~~~~~~~~
-- Cell Name: :cell:`sky130_fd_pr__nfet_01v8`
+- Cell Name: :cell:`sky130_fd_pr__nfet_05v0_nvt`
- Model Name: :model:`sky130_fd_pr__nfet_05v0_nvt`
Operating Voltages where SPICE models are valid for :model:`sky130_fd_pr__nfet_05v0_nvt`
diff --git a/docs/rules/device-details/nfet_20v0_zvt/index.rst b/docs/rules/device-details/nfet_20v0_zvt/index.rst
index f02630c..a1e7648 100644
--- a/docs/rules/device-details/nfet_20v0_zvt/index.rst
+++ b/docs/rules/device-details/nfet_20v0_zvt/index.rst
@@ -1,4 +1,4 @@
-20V NMOS zero-VT FET
+20V zero-VT NMOS FET
--------------------
Spice Model Information
diff --git a/docs/rules/device-details/npn_05v0/index.rst b/docs/rules/device-details/npn_05v0/index.rst
index 7ec820d..771e840 100644
--- a/docs/rules/device-details/npn_05v0/index.rst
+++ b/docs/rules/device-details/npn_05v0/index.rst
@@ -1,5 +1,5 @@
-Bipolar (NPN)
--------------
+Bipolar NPN transistor
+----------------------
Spice Model Information
~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/rules/device-details/pnp_05v0/index.rst b/docs/rules/device-details/pnp_05v0/index.rst
index 0ffc275..38ba1dc 100644
--- a/docs/rules/device-details/pnp_05v0/index.rst
+++ b/docs/rules/device-details/pnp_05v0/index.rst
@@ -1,5 +1,5 @@
-Bipolar (PNP)
--------------
+Bipolar PNP transistor
+----------------------
Spice Model Information
~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/rules/device-details/res_generic/index.rst b/docs/rules/device-details/res_generic/index.rst
index f565c73..98d616d 100644
--- a/docs/rules/device-details/res_generic/index.rst
+++ b/docs/rules/device-details/res_generic/index.rst
@@ -1,4 +1,4 @@
-Generic Resistors
+Generic resistors
-----------------
Generic resistors are supported in the PDK but are not recommended for analog applications. Resistor values will be extracted from the layout as long as the resistor layer is utilized, for LVS against schematic elements.
diff --git a/docs/rules/layers/table-f2a-lvs-key.rst b/docs/rules/layers/table-f2a-lvs-key.rst
index 5b1f28a..b923848 100644
--- a/docs/rules/layers/table-f2a-lvs-key.rst
+++ b/docs/rules/layers/table-f2a-lvs-key.rst
@@ -1,4 +1,5 @@
Explanation of symbols:
+
* ``-`` = Layer illegal for the device
* ``+`` = Layer allowed to overlap
* ``D`` = DRAWN indicates that a layer is drawn by Design.
diff --git a/docs/rules/layers/table-f2b-mask-key.rst b/docs/rules/layers/table-f2b-mask-key.rst
index ddbb215..6ebbc21 100644
--- a/docs/rules/layers/table-f2b-mask-key.rst
+++ b/docs/rules/layers/table-f2b-mask-key.rst
@@ -1,4 +1,5 @@
Explanation of symbols:
+
* ``-`` = Layer not created for the device
* ``+`` = Layer allowed to overlap
* ``C`` = CREATED
diff --git a/docs/rules/summary.rst b/docs/rules/summary.rst
index 0e99e4e..7ad4313 100644
--- a/docs/rules/summary.rst
+++ b/docs/rules/summary.rst
@@ -1,5 +1,5 @@
-Summry of Key Periphery Rules
-=============================
+Summary of Key Periphery Rules
+==============================
.. csv-table:: Table F3a: Front end layers (Low Voltage Devices)
:file: summary/table-f3a-font-end-low-voltage.csv
diff --git a/environment.yml b/environment.yml
index 320a1a5..cf23226 100644
--- a/environment.yml
+++ b/environment.yml
@@ -25,4 +25,4 @@
- iverilog
# Packages installed from PyPI
- pip:
- - -r file:requirements.txt
+ - -r requirements.txt
diff --git a/libraries/sky130_fd_pr_reram/latest b/libraries/sky130_fd_pr_reram/latest
new file mode 160000
index 0000000..48c8310
--- /dev/null
+++ b/libraries/sky130_fd_pr_reram/latest
@@ -0,0 +1 @@
+Subproject commit 48c8310e464157d797c78cb2e6d6b5a21d710c20
diff --git a/libraries/sky130_fd_pr_reram/v0.0.9 b/libraries/sky130_fd_pr_reram/v0.0.9
new file mode 160000
index 0000000..1ed5750
--- /dev/null
+++ b/libraries/sky130_fd_pr_reram/v0.0.9
@@ -0,0 +1 @@
+Subproject commit 1ed57501be4b8b7816942b7eac6f864910025799
diff --git a/libraries/sky130_fd_pr_reram/v2.0.1 b/libraries/sky130_fd_pr_reram/v2.0.1
new file mode 160000
index 0000000..21212f5
--- /dev/null
+++ b/libraries/sky130_fd_pr_reram/v2.0.1
@@ -0,0 +1 @@
+Subproject commit 21212f530de3b071e4737a7622ce3c7dce1527bb
diff --git a/libraries/sky130_fd_pr_reram/v2.0.2 b/libraries/sky130_fd_pr_reram/v2.0.2
new file mode 160000
index 0000000..ef3ec3e
--- /dev/null
+++ b/libraries/sky130_fd_pr_reram/v2.0.2
@@ -0,0 +1 @@
+Subproject commit ef3ec3edd3d30a35ff04011fd3afc8f2cdd1d06f
diff --git a/libraries/sky130_fd_pr_reram/v2.0.3 b/libraries/sky130_fd_pr_reram/v2.0.3
new file mode 160000
index 0000000..d3c4505
--- /dev/null
+++ b/libraries/sky130_fd_pr_reram/v2.0.3
@@ -0,0 +1 @@
+Subproject commit d3c4505de8ec4c52fe70c276b351929297ffcd6e
diff --git a/scripts/make/git.mk b/scripts/make/git.mk
index e1a862e..c36a296 100644
--- a/scripts/make/git.mk
+++ b/scripts/make/git.mk
@@ -21,19 +21,24 @@
$(error "Version value could not be determined. Make sure you fetch the tags.")
endif
-submodules: libraries/sky130_fd_sc_hd/$(SUBMODULE_VERSION)/.git libraries/sky130_fd_sc_hdll/$(SUBMODULE_VERSION)/.git libraries/sky130_fd_sc_hs/$(SUBMODULE_VERSION)/.git libraries/sky130_fd_sc_ms/$(SUBMODULE_VERSION)/.git libraries/sky130_fd_sc_ls/$(SUBMODULE_VERSION)/.git
+LIBRARIES = $(sort $(notdir $(wildcard libraries/sky130_*)))
-libraries/sky130_fd_sc_hd/%/.git: .gitmodules
- git submodule update --init $(@D)
+LIBS_DOT_GIT = $(addsuffix /$(SUBMODULE_VERSION)/.git,$(addprefix libraries/,$(LIBRARIES)))
-libraries/sky130_fd_sc_hdll/%/.git: .gitmodules
- git submodule update --init $(@D)
+libraries-info:
+ @echo "The following libraries exist:"
+ @for L in $(LIBRARIES); do \
+ LD=libraries/$$L/$(SUBMODULE_VERSION); \
+ echo " * $$L"; \
+ echo " $$(git submodule status $$LD)"; \
+ done
+ @echo $(LIBS_DOT_GIT)
-libraries/sky130_fd_sc_hs/%/.git: .gitmodules
- git submodule update --init $(@D)
+submodules: $(LIBS_DOT_GIT)
-libraries/sky130_fd_sc_ms/%/.git: .gitmodules
- git submodule update --init $(@D)
+define LIB_template
+libraries/$(1)/%/.git: .gitmodules
+ git submodule update --init $$(@D)
+endef
-libraries/sky130_fd_sc_ls/%/.git: .gitmodules
- git submodule update --init $(@D)
+$(foreach lib,$(LIBRARIES), $(eval $(call LIB_template,$(lib))))
diff --git a/scripts/python-skywater-pdk/skywater_pdk/liberty.py b/scripts/python-skywater-pdk/skywater_pdk/liberty.py
index 6cbda80..77f2bb5 100755
--- a/scripts/python-skywater-pdk/skywater_pdk/liberty.py
+++ b/scripts/python-skywater-pdk/skywater_pdk/liberty.py
@@ -31,12 +31,15 @@
from typing import Tuple, List, Dict
+from math import frexp, log2
+
from . import sizes
from .utils import sortable_extracted_numbers
debug = False
+LOG2_10 = log2(10)
class TimingType(enum.IntFlag):
"""
@@ -766,6 +769,15 @@
>>> liberty_float(1)
'1.0000000000'
+ >>> liberty_float(1e9)
+ '1000000000.0'
+
+ >>> liberty_float(1e10)
+ '1.000000e+10'
+
+ >>> liberty_float(1e15)
+ '1.000000e+15'
+
>>> liberty_float(True)
Traceback (most recent call last):
...
@@ -792,36 +804,25 @@
"""
try:
- f2 = float(f)
+ r = float(f)
except (ValueError, TypeError):
- f2 = None
+ r = None
if isinstance(f, bool):
- f2 = None
+ r = None
- if f is None or f2 != f:
+ if f is None or r != f:
raise ValueError("%r is not a float" % f)
- WIDTH = len(str(0.0083333333))
+ width = 11
- s = json.dumps(f)
- if 'e' in s:
- a, b = s.split('e')
- if '.' not in a:
- a += '.'
- while len(a)+len(b)+1 < WIDTH:
- a += '0'
- s = "%se%s" % (a, b)
- elif '.' in s:
- while len(s) < WIDTH:
- s += '0'
+ mag = int(frexp(r)[1]/LOG2_10)
+ if mag > 9:
+ return f'%{width}e' % r
+ if mag < 0:
+ return f"%{width+1}.{width-1}f" % r
else:
- if len(s) < WIDTH:
- s += '.'
- while len(s) < WIDTH:
- s += '0'
- return s
-
+ return f"%{width+1}.{width-mag-1}f" % r
LIBERTY_ATTRIBUTE_TYPES = {
'boolean': liberty_bool,
diff --git a/third_party/make-env b/third_party/make-env
index 9b07ad2..33b80bd 160000
--- a/third_party/make-env
+++ b/third_party/make-env
@@ -1 +1 @@
-Subproject commit 9b07ad2bb62fbf8af789c9e4669715c974b4912d
+Subproject commit 33b80bd32c30fb8affd0fd5cda544d1bca075593
