| ,General (CAP.-), |
| .X.1,No capacitance is extracted due to contacts. (This is a generic layout extraction tool limitation.), |
| ,, |
| ,MOS Devices (MOS.-), |
| .mos.1,area between poly and diff should not have capacitance extracted., |
| .mos.2,li within .055um will not have fringing capacitance (npcon.4 = 0.055 for S8), |
| .mos.3,there will be no fringing caps between gates ( as capacitance is shielded by the LICON and MCON)., |
| .mos.4,All 20V NMOS ISO DEFETs will have the parasitic diodes included in the models., |
| .mos.5,All 20V NMOS ISO DEFETs will have the parasitic diode included in the models.,This model also includes the 5th terminal Drain-Psub diode (DeepNwell - Psub). |
| .mos.6,All 20V PMOS DEFETs will have the parasitic DeepNwell-Psub diode included in the CAD extraction., |
| .mos.7,The only 20V DEFET instance parameter that the model uses from CAD extraction is m-factor.,The model will over-write all other instance parameters from CAD extraction. |
| ,, |
| ,Resistors (RES.-), |
| .res.1,short devices must not have capacitance calculated across the device., |
| .res.2,fuse devices must have capacitance extracted., |
| .res.3,poly resistors that are not the precision poly resistors (xhrpoly_X_X) must have capacitance extracted., |
| .res.4,metops that are merged must have capacitance extracted., |
| .res.5,parasitic resistors for diff/nwell must have the junction diode extracted., |
| .res.6,Poly precision resistors must not have the poly-psub parasitic capacitance extracted (RCX should also exclude head/tail poly-psub capacitance)., |
| .res.7,"For Poly precision resistors xhrpoly_X_1, the device recognition layer is defined by growing the poly.rs AND rpm.dg layers 0.50 um(head/tail distance from ID layer) in all directions. Poly-Field/Diff/Well, and Poly-Poly, Poly-Li will not have capacitance extracted inside this device recognition layer.", |
| .res.8,"For Poly precision resistors xhrpoly_X_2, the device recognition layer is defined by growing the poly.rs AND rpm.dg layers 1.18 um(head/tail distance from ID layer) in all directions. Poly-Field/Diff/Well, and Poly-Poly, Poly-Li will not have capacitance extracted inside this device recognition layer.", |
| ,, |
| ,Capacitors (PASSIVES.-), |
| .cnwvc.1,"capacitance will not be extracted for field, diff, Poly, Li, M1, M2 up to 0.465u away from device\n recognition layer (as defined in LVS table of TDR)", |
| .cmimc.1,"capacitance will not be extracted between M2 to field, diff, Poly, Li, M1 up to 0.14u away from device\n recognition layer (intersection of M2 overlapping CAPM that's connected to VIA2, 3-terminal MiM only)", |
| .crfesd.1,"capacitance will not be extracted for field, diff, Poly, Li, M1, M2 up to 0.4u away from device recognition layers (diode terminals)", |
| .xcmvpp.1," For Cap extraction of xcmvpp11p5x11p7_polym50p4shield, the metal5 exposed for metal5-metal5 capacitance extraction is an extra 0.4um from the extraction of xcmvpp11p5x11p7_polym5shield. For any layer below metal5, the capcitance extraction of xcmvpp11p5x11p7_polym50p4shield is the same as xcmvpp11p5x11p7_polym5shield (Note: for the unit cel xcmvpp11p5x11p7_polym50p4shield metal5 is pulled in 0.4um from the cell edge)", |
| ,, |
| ,Bipolar Devices, |
| ,none, |
