)]}'
{
  "commit": "3ac9f24a1bdf3e1ca388d643bf547e7acc1a03e9",
  "tree": "caa50eeecc05f88f9625214c15b5784970b23714",
  "parents": [
    "3f373a2b99a2f009e3f54138bfe0e039f18cfb95",
    "d1de6e82feba6e1ac3ae2ac7bfdf2a12f9e68ff5"
  ],
  "author": {
    "name": "Tim Ansell",
    "email": "me@mith.ro",
    "time": "Mon Oct 05 20:12:03 2020 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon Oct 05 20:12:03 2020 -0700"
  },
  "message": "Merge pull request #166 from mithro/verilog-fix-2\n\nverilog: Fixing usage of cell reserved word.",
  "tree_diff": []
}