infra: Rework labeler.yml file. Convert to the other style of YAML lists which matches the documentation at https://github.com/actions/labeler#basic-examples and https://github.com/actions/labeler#common-examples Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
diff --git a/.github/labeler.yml b/.github/labeler.yml index e3c99a4..ca56095 100644 --- a/.github/labeler.yml +++ b/.github/labeler.yml
@@ -1,64 +1,105 @@ -documentation: ["*.rst", "docs"] +documentation: + - *.rst + - docs + - docs/* + - docs/**/* -files-definition: ["definition.json"] +files-definition: + - definition.json -files-layout-gds: ["*Makefile"] +files-layout-gds: + - *.gds +files-layout-lef-magic: + - *.magic.lef +files-layout-lef: + - *.lef +files-layout-tlef: + - *.tlef -files-layout-gds: ["*.gds"] -files-layout-lef-magic: ["*.magic.lef"] -files-layout-lef: ["*.lef"] -files-layout-tlef: ["*.tlef"] - -files-model-behavioral-verilog: ["*.behavioral.v"] -files-model-functional-verilog: ["*.functional.v"] -files-model-spice: ["*.spice"] +files-model-behavioral-verilog: + - *.behavioral.v +files-model-functional-verilog: + - *.functional.v +files-model-spice: + - *.spice # files-model-verilog -files-netlist-cdl: ["*.cdl"] -files-netlist-tsv: ["*.netlist.tsv"] +files-netlist-cdl: + - *.cdl +files-netlist-tsv: + - *.netlist.tsv -files-powerpins: ["*.pp.*"] +files-powerpins: + - *.pp.* -files-schematic-svg: ["*.schematic.svg"] +files-schematic-svg: + - *.schematic.svg -files-symbol-svg: ["*.symbol.svg"] -files-symbol-verilog: ["*.symbol.v"] +files-symbol-svg: + - *.symbol.svg +files-symbol-verilog: + - *.symbol.v -files-timing-json: ["*.lib.json"] -# files-timing-liberty: ["*.lib"] +files-timing-json: + - *.lib.json +# files-timing-liberty: +# - *.lib -files-testbench-verilog: ["*.tb.v"] +files-testbench-verilog: + - *.tb.v -infrastructure: [".github", "travis", "kokoro"] +infrastructure: + - .github/* + - .github/**/* + - *travis* + - *kokoro* -lib-sky130_ef_io: ["sky130_fd_ef_io"] +lib-sky130_ef_io: + - sky130_fd_ef_io -lib-sky130_fd_pr_base: ["sky130_fd_pr_base"] -lib-sky130_fd_pr_rf: ["sky130_fd_pr_rf"] -lib-sky130_fd_pr_rf2: ["sky130_fd_pr_rf2"] +lib-sky130_fd_pr_base: + - sky130_fd_pr_base +lib-sky130_fd_pr_rf: + - sky130_fd_pr_rf +lib-sky130_fd_pr_rf2: + - sky130_fd_pr_rf2 -lib-sky130_fd_sc_hd: ["sky130_fd_sc_hd"] -lib-sky130_fd_sc_hdll: ["sky130_fd_sc_hdll"] -lib-sky130_fd_sc_hs: ["sky130_fd_sc_hs"] -lib-sky130_fd_sc_hvl: ["sky130_fd_sc_hvl"] -lib-sky130_fd_sc_lp: ["sky130_fd_sc_lp"] -lib-sky130_fd_sc_ls: ["sky130_fd_sc_ls"] -lib-sky130_fd_sc_ms: ["sky130_fd_sc_ms"] +lib-sky130_fd_sc_hd: + - sky130_fd_sc_hd +lib-sky130_fd_sc_hdll: + - sky130_fd_sc_hdll +lib-sky130_fd_sc_hs: + - sky130_fd_sc_hs +lib-sky130_fd_sc_hvl: + - sky130_fd_sc_hvl +lib-sky130_fd_sc_lp: + - sky130_fd_sc_lp +lib-sky130_fd_sc_ls: + - sky130_fd_sc_ls +lib-sky130_fd_sc_ms: + - sky130_fd_sc_ms -lib-sky130_fd_sp_flash: ["sky130_fd_sp_flash"] -lib-sky130_fd_sp_sram: ["sky130_fd_sp_sram"] +lib-sky130_fd_sp_flash: + - sky130_fd_sp_flash +lib-sky130_fd_sp_sram: + - sky130_fd_sp_sram -lib-sky130_osu_sc: ["sky130_osu_sc"] +lib-sky130_osu_sc: + - sky130_osu_sc* # scripts-documentation -scripts-python: ["*.py"] -scripts-python-liberty: ["liberty.py", "corners.py"] +scripts-python: + - *.py +scripts-python-liberty: + - liberty.py + - corners.py scripts-python-verilog: - - "skywater_pdk/verilog" # Script itself - - "*.blackbox.v" # Generated blackbox files - - "*.symbol.v" # Generated symbol files - - "*.tb.v" # Generated test bench - - "*_[0-9].v" # Generated strength driver wrappers + - skywater_pdk/verilog/* # Script itself + - skywater_pdk/verilog/**/* # Script itself + - *.blackbox.v # Generated blackbox files + - *.symbol.v # Generated symbol files + - *.tb.v # Generated test bench + - *_[0-9].v # Generated strength driver wrappers # tools-BAG # tools-Cadence-Innovus