commit cbc75f4e3e8efb0c81b36e04e4d46f7edf63d45b
author Tim 'mithro' Ansell <tansell@google.com> Mon Jun 29 15:16:30 2020 -0700
committer Tim 'mithro' Ansell <tansell@google.com> Mon Jun 29 15:16:30 2020 -0700
tree 8758122d3844486a2ec3d01d816276e9032cea10
parent 066ba9909274caaad67c0b0bfd4e83664cf30755

Fixes.

scripts/python-skywater-pdk/generate_symbols.sh

diff --git a/scripts/python-skywater-pdk/generate_symbols.sh b/scripts/python-skywater-pdk/generate_symbols.sh
index 7a7c86b..453679e 100755
--- a/scripts/python-skywater-pdk/generate_symbols.sh
+++ b/scripts/python-skywater-pdk/generate_symbols.sh
@@ -20,6 +20,19 @@
 for LIB in $1/skywater-pdk/libraries/*; do
 	LIBNAME=$(basename $LIB)
 
+	find $LIB -name \*.schematic.svg -delete
+	find $LIB -name \*.v -print | grep 'cells' | grep -v 'beha' \
+		| parallel -v symbolator --libname $LIBNAME --title -t --input \{\} \
+		; RETCODE=$?
+	if [ $RETCODE -ne 0 ]; then
+		echo "FAILURE on $LIB"
+		exit
+	fi
+done
+
+for LIB in $1/skywater-pdk/libraries/*; do
+	LIBNAME=$(basename $LIB)
+
 	find $LIB -name \*.symbol.svg -delete
 	find $LIB -name \*.symbol.v -print \
 		| parallel -v symbolator --libname $LIBNAME --title -t --input \{\} \

scripts/python-skywater-pdk/generate_verilog_blackbox.py

diff --git a/scripts/python-skywater-pdk/generate_verilog_blackbox.py b/scripts/python-skywater-pdk/generate_verilog_blackbox.py
index 37b7ca4..7de74c9 100755
--- a/scripts/python-skywater-pdk/generate_verilog_blackbox.py
+++ b/scripts/python-skywater-pdk/generate_verilog_blackbox.py
@@ -846,6 +846,11 @@
             f,
             "Verilog primitive definition.",
             define_data)
+
+        f.write("`ifdef NO_PRIMITIVES\n")
+        f.write(f'`include "./{define_data["file_prefix"]}.blackbox.v"\n')
+        f.write('`else\n')
+
         f.write(f"primitive {define_data['verilog_name']} (")
         write_verilog_ports(f, define_data['ports'])
 
@@ -894,6 +899,7 @@
             f.write('\n')
         f.write('    endtable\n')
         f.write('endprimitive\n')
+        f.write('`endif // NO_PRIMITIVES\n')
         write_verilog_footer(f)
 
 
@@ -1154,7 +1160,7 @@
         f.write('`ifdef FUNCTIONAL\n')
         f.write(f'`include "{define_data["file_prefix"]}.pp.functional.v"\n')
         f.write('`else  // FUNCTIONAL\n')
-        f.write(f'`include "{define_data["file_prefix"]}.pp.behavioural.v"\n')
+        f.write(f'`include "{define_data["file_prefix"]}.pp.behavioral.v"\n')
         f.write('`endif // FUNCTIONAL\n')
         f.write('\n')
         f.write('`else  // USE_POWER_PINS\n')
@@ -1162,7 +1168,7 @@
         f.write('`ifdef FUNCTIONAL\n')
         f.write(f'`include "{define_data["file_prefix"]}.functional.v"\n')
         f.write('`else  // FUNCTIONAL\n')
-        f.write(f'`include "{define_data["file_prefix"]}.behavioural.v"\n')
+        f.write(f'`include "{define_data["file_prefix"]}.behavioral.v"\n')
         f.write('`endif // FUNCTIONAL\n')
         f.write('\n')
         f.write('`endif // USE_POWER_PINS\n')