Fixes.
diff --git a/scripts/python-skywater-pdk/generate_symbols.sh b/scripts/python-skywater-pdk/generate_symbols.sh
index 0b0410a..0f31470 100755
--- a/scripts/python-skywater-pdk/generate_symbols.sh
+++ b/scripts/python-skywater-pdk/generate_symbols.sh
@@ -11,13 +11,13 @@
find $1/skywater-pdk/ -name *.tb.v -delete
find $1/skywater-pdk/ -name *.blackbox.v -delete
find $1/skywater-pdk/ -name *.symbol.v -delete
-#find $1/skywater-pdk/ -name *.svg -delete
+find $1/skywater-pdk/ -name *.svg -delete
./generate_verilog_blackbox.py $1/skywater-pdk/libraries/*/*/models/*
./generate_verilog_blackbox.py $1/skywater-pdk/libraries/*/*/cells/*
-exit
+#exit
-(cd $1/ ; git diff --no-renames --name-only --diff-filter=D -z | xargs -0 git checkout --)
+#(cd $1/ ; git diff --no-renames --name-only --diff-filter=D -z | xargs -0 git checkout --)
for LIB in $1/skywater-pdk/libraries/*; do
LIBNAME=$(basename $LIB)
diff --git a/scripts/python-skywater-pdk/generate_verilog_blackbox.py b/scripts/python-skywater-pdk/generate_verilog_blackbox.py
index 9e43542..8f9f2ed 100755
--- a/scripts/python-skywater-pdk/generate_verilog_blackbox.py
+++ b/scripts/python-skywater-pdk/generate_verilog_blackbox.py
@@ -21,6 +21,8 @@
from collections import defaultdict
+from skywater_pdk.sizes import parse_size
+
copyright_header = """\
/**
* Copyright 2020 The SkyWater PDK Authors
@@ -487,20 +489,20 @@
f.seek(current_pos+1)
-def drive_strengths(basename, cellpath):
- drives = []
+def transistor_sizes(basename, cellpath):
+ sizes = []
for f in os.listdir(cellpath):
if not f.endswith('.gds'):
continue
f = f.split('.', 1)[0]
libname, modname = f.split('__', 1)
- drive = modname.replace(basename, '')
- if not drive:
+ size = modname.replace(basename, '')
+ if not size:
continue
- assert drive.startswith('_'), drive
- drives.append(drive[1:])
- return drives
+ assert size.startswith('_'), size
+ sizes.append(size)
+ return [parse_size(s) for s in sizes]
def wrap(s, i=''):
return "\n".join(textwrap.wrap(s, initial_indent=' * '+i, subsequent_indent=' * '+i))
@@ -1032,25 +1034,25 @@
f.write('\n')
-def write_drive_wrapper(drive, cellpath, define_data):
- outpath = os.path.join(cellpath, f'{define_data["file_prefix"]}_{drive}.v')
+def write_size_wrapper(size, cellpath, define_data):
+ outpath = os.path.join(cellpath, f'{define_data["file_prefix"]}{size.suffix}.v')
#assert not os.path.exists(outpath), outpath
print("Creating", outpath)
with open(outpath, "w+") as f:
write_verilog_header(
f,
- f"Verilog wrapper for {define_data['name']} drive {drive}.",
+ f"Verilog wrapper for {define_data['name']} having {str(size)}.",
define_data)
f.write(f'`include "{define_data["file_prefix"]}.v"\n')
f.write('\n')
f.write('`ifdef USE_POWER_PINS\n')
f.write('/*********************************************************/\n')
- write_verilog_wrapper(f, '_'+drive, False, pp_ports(define_data), define_data)
+ write_verilog_wrapper(f, size.suffix, False, pp_ports(define_data), define_data)
f.write('/*********************************************************/\n')
f.write('`else // If not USE_POWER_PINS\n')
f.write('/*********************************************************/\n')
- write_verilog_wrapper(f, '_'+drive, True, nonpp_ports(define_data), define_data)
+ write_verilog_wrapper(f, size.suffix, True, nonpp_ports(define_data), define_data)
f.write('/*********************************************************/\n')
f.write('`endif // USE_POWER_PINS\n')
write_verilog_footer(f)
@@ -1076,8 +1078,8 @@
write_symbol_pp(cellpath, define_data)
if define_data['type'] == 'cell':
- for d in drive_strengths(define_data['name'], cellpath):
- write_drive_wrapper(d, cellpath, define_data)
+ for d in transistor_sizes(define_data['name'], cellpath):
+ write_size_wrapper(d, cellpath, define_data)
if define_data['type'] == 'primitive':
write_primitive(cellpath, define_data)
