Title: M0S8 ACTIVE ESD DESIGN RULES (ESD MTDR)

`APPENDIX A: MTDR & CAD Definitions 5 <#appendix-a-mtdr-cad-definitions>`__
`Section A1: MTDR Definitions 5 <#section-a1-mtdr-definitions>`__
`Section A2: CAD Definitions 5 <#section-a2-cad-definitions>`__

`APPENDIX B. ESD Design Rules 6 <#appendix-b.-esd-design-rules>`__
`Section B1: Primary ESD Network Integration Rules 6 <#section-b1-primary-esd-network-integration-rules>`__
`Section B2: Secondary ESD Block Integration Rules 9 <#section-b2-secondary-esd-block-integration-rules>`__
`Section B3: Regulated/Internal Supply ESD Integration Rules 11 <#section-b3-regulatedinternal-supply-esd-integration-rules>`__

`APPENDIX C: Miscellaneous Rules 11 <#appendix-c-miscellaneous-rules>`__
`Section C1: Miscellaneous Rules 11 <#section-c1-miscellaneous-rules>`__

Purpose/Scope
=============

Purpose
-------

This specification defines Active ESD design rules for m0s8.

Scope
-----

This specification is intended for use by design engineers in the development of new products in the m0s8 technology.

Critical Requirements Summary
=============================

Design engineers must provide a design database that is clean to the rules included in this specification, regardless of whether these rules are supported by the automated DRC routines or checked manually.

All manually verified design rules must be checked by design prior to submitting the spec for approval by the technology and ESD groups.

The technology and ESD groups are responsible for interpreting the rules for CAD and design, and for compliance verification based on spot-checks as necessary.

Dimensions included in the spec are drawn = final.

Operating Procedures and Responsibilities
=========================================

The MTDR review process consists of the validation of latch up, ESD, and other miscellaneous design rules.

Both automated and manually verified design rules must be reviewed validated by design.

MTDR and CAD definitions are presented in Appendix A.

ESD rules are presented in Appendix B. The rules are divided into two sections: ESD block integration and miscellaneous rules.

- Section B1 provides rules for pad ring ESD networks associated with I/O’s and power supplies. It specifies the Primary ESD block integration requirements and also defines the resistances, bus widths, and interconnect requirements to connect these ESD blocks to bond pads and/or I/O buffers within an I/O, input, output, power, or ground cell.
- Section B2 specifies the Secondary (local) ESD block integration rules and defines the resistances, bus widths, and interconnect requirements to connect these ESD blocks to bond pads and/or IO buffers within an I/O and input cell.
- Section B3 specifies the Regulated (internal) ESD block integration rules.

Section C outlines additional miscellaneous rules applicable at the chip-level.

Quality Requirements
====================

All rules not checked automatically (marked as “NDRC” in this spec) must be checked manually by Design.

MTDR & CAD Definitions
======================

.. table:: Section A1: MTDR Definitions
    :name: section-a1-mtdr-definitions
    :class: ListParagraph

    +----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+
    | **Name**                                     | **Definitions (Used throughout the body of the spec)**                                                                                       |
    +----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+
    | Pad                                          | A bond pad                                                                                                                                   |
    +----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+
    | Power Supply                                 | A power net                                                                                                                                  |
    +----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+
    | Ground Supply                                | A ground net                                                                                                                                 |
    +----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+
    | Regulated/Internal Power Supply              | An internal power supply that is not bonded out in package but regulated from an external supply                                             |
    |                                              |                                                                                                                                              |
    |                                              | The net names placed in latch-up DRC form must be enclosed by a pair of square brackets.                                                     |
    +----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+
    | Primary ESD Block                            | A pad-connected ESD block that provides primary ESD protection in the IO ring                                                                |
    +----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+
    | IO Pad                                       | A pad associated with an input or IO net                                                                                                     |
    +----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+
    | ESD Resistor                                 | An ESD resistor used in the input path to a gate oxide                                                                                       |
    +----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+
    | Secondary ESD Block                          | A local ESD protection element (resistors and clamps) required for protection of input paths                                                 |
    +----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+
    | Signal Pad Diffusion or Tap                  | Any diff or tap connected to a signal pad either metallically or through a resistor of less than 10KOhm.                                     |
    |                                              |                                                                                                                                              |
    |                                              | Notes:                                                                                                                                       |
    |                                              |                                                                                                                                              |
    |                                              | 1. Only resistors labeled with text.dg as ‘10KOhm’, or connected to pwr/gnd supplies, will break the connectivity between pad and diffusion. |
    |                                              |                                                                                                                                              |
    |                                              | 2. Drain Extended FETs must be checked manually for all guard ring rules                                                                     |
    |                                              |                                                                                                                                              |
    |                                              | Legacy IP with ‘100KOhm’ text.dg label will also break the connectivity between pad and diffusion.                                           |
    +----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+

.. table:: Section A2: CAD Definitions
    :name: section-a2-cad-definitions
    :class: ListParagraph

    +---------------------------------------------+------------------------+
    | **Name**                                    | **Defining algorithm** |
    +---------------------------------------------+------------------------+
    |                                             |                        |
    +---------------------------------------------+------------------------+

.. table:: Latch-up DRC Form Descriptions

    +------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
    | **Name**                           | **Descriptions**                                                                                                                                                                     |
    +------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
    | *Gnd Nets*                         | A list of power/ground nets. Regulated Supply nets need to be enclosed between square brackets and placed in the latchup form power nets field, for example: [vpwr] vcch [vnb] vgnd. |
    |                                    |                                                                                                                                                                                      |
    | *Pwr Nets*                         |                                                                                                                                                                                      |
    +------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

ESD Design Rules
----------------

.. table:: Section B1: Primary ESD Network Integration Rules
    :name: section-b1-primary-esd-network-integration-rules
    :class: ListParagraph

    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **Rule**   | **Exempt**          | Note 1. The ESD group is responsible for documenting the ESD block used for each die pad and for defining the chip-level ESD supply bussing, boost, and trigger domains. The product team is responsible for implementing the chip-level primary ESD network. | **Use**   | **Value**   |
    |            |                     |                                                                                                                                                                                                                                                               |           |             |
    | **netio.** |                     |                                                                                                                                                                                                                                                               |           |             |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **1**      |                     | Allowable ESD public cells for the primary ESD network                                                                                                                                                                                                        | **NDRC**  | **Table 1** |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **2.1**    |                     | Maximum Vcc bus routing resistance between adjacent 10V distributed active shunt ESD blocks                                                                                                                                                                   | **NDRC**  | **110 mΩ**  |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **2.2**    | ESD Bus Domains     | Maximum Vcc bus routing resistance between any 5V pad and nearest 5V grouped active shunt ESD clamp                                                                                                                                                           | **NDRC**  | **1.0 Ω**   |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **3.1**    |                     | Maximum Vss bus routing resistance between adjacent 10V distributed active shunt ESD blocks                                                                                                                                                                   | **NDRC**  | **210 mΩ**  |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **3.2**    |                     | Maximum Vss bus routing resistance between any 5V pad and nearest 5V grouped active shunt ESD clamp                                                                                                                                                           | **NDRC**  | **1.0 Ω**   |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **4**      | Non-ESD Bus Domains | Maximum ESD bus routing resistance between any 5V pad and nearest 5V grouped active shunt ESD clamp                                                                                                                                                           | **NDRC**  | **1.0 Ω**   |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **5**      |                     | The minimum number of 10V distributed active shunt ESD blocks connected to a single trigger circuit via the “trig_s” signal                                                                                                                                   | **NDRC**  | **8**       |
    |            |                     |                                                                                                                                                                                                                                                               |           |             |
    |            |                     | **Note: not checked when the block_level switch is used**                                                                                                                                                                                                     |           |             |
    |            |                     |                                                                                                                                                                                                                                                               |           |             |
    |            |                     | **Note: this rule does not apply when run on ESD library cells**                                                                                                                                                                                              |           |             |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **6**      |                     | The maximum number of 10V distributed active shunt ESD blocks connected to a single trigger circuit via the “trig_s” signal                                                                                                                                   | **NDRC**  | **15**      |
    |            |                     |                                                                                                                                                                                                                                                               |           |             |
    |            |                     | **Note: not checked when the block_level switch is used**                                                                                                                                                                                                     |           |             |
    |            |                     |                                                                                                                                                                                                                                                               |           |             |
    |            |                     | **Note: this rule does not apply when run on ESD library cells**                                                                                                                                                                                              |           |             |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **7**      |                     | The trigger circuit output (trig_s) must not be multi-driven (i.e. trig signal from one trigger circuit must not connect to the trig signal of other trigger circuit)                                                                                         | **NDRC**  |             |
    |            |                     |                                                                                                                                                                                                                                                               |           |             |
    |            |                     | **Note: this rule does not apply when run on ESD library cells**                                                                                                                                                                                              |           |             |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **8**      |                     | The trigger circuit and the 10V distributed active shunt ESD blocks connected to that trigger circuit must have a common boost signal                                                                                                                         | **NDRC**  |             |
    |            |                     |                                                                                                                                                                                                                                                               |           |             |
    |            |                     | **Note: this rule does not apply when run on ESD library cells**                                                                                                                                                                                              |           |             |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **9**      |                     | Any routing used to extend pad pitch beyond minimum must utilize, at a minimum, the identical bussing structure and bus widths as the ESD block                                                                                                               | **NDRC**  |             |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **10**     |                     | The 10V distributed active shunt domain output driver ground supply must be strapped to the associated ESD ground at every IO block                                                                                                                           | **NDRC**  |             |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **10.1**   |                     | Maximum ground supply resistance between the 10V distributed active shunt domain output driver source and 10V distributed active shunt ESD block                                                                                                              | **NDRC**  | **0.5 Ω**   |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **11**     |                     | The 10V distributed active shunt domain output driver power supply must be strapped to its associated ESD supply at every IO block                                                                                                                            | **NDRC**  |             |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **11.1**   |                     | Maximum power supply resistance between the 10V distributed active shunt output driver source and 10V distributed active shunt ESD block                                                                                                                      | **NDRC**  | **0.5 Ω**   |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **12**     |                     | Each pad associated with a 10V distributed active shunt ESD block must connect directly to that ESD block in metal                                                                                                                                            | **NDRC**  |             |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **12.1**   |                     | Maximum total resistance between pad and the 10V distributed active shunt ESD block                                                                                                                                                                           | **NDRC**  | **0.1 Ω**   |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **12.2**   |                     | Minimum metal width of each metal layer in any path between pad and the ESD block                                                                                                                                                                             | **NDRC**  | **Table 2** |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **12.3**   |                     | Minimum number of contacts for each contact layer in any path between pad and any primary ESD block                                                                                                                                                           | **NDRC**  | **Table 3** |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **13**     |                     | The maximum resistance from any ground pad to the nearest B2B diode down to Met1.                                                                                                                                                                             | **LuRes** | **2Ω**      |
    |            |                     |                                                                                                                                                                                                                                                               |           |             |
    |            |                     | Allowable B2B diodes:                                                                                                                                                                                                                                         |           |             |
    |            |                     |                                                                                                                                                                                                                                                               |           |             |
    |            |                     | -  s8iom0s8_top_b2b_diode                                                                                                                                                                                                                                     |           |             |
    |            |                     | -  s8iom0S8_top_lvc_b2b_wopad                                                                                                                                                                                                                                 |           |             |
    |            |                     | -  s8_esd_gnd2gnd_120x2_lv_isosub                                                                                                                                                                                                                             |           |             |
    |            |                     | -  s8atlasana_esd_gnd2gnd_120x2_lv_isosub                                                                                                                                                                                                                     |           |             |
    |            |                     | -  s8fpiom0s8_esd_gnd2gnd_180x2_lv_dnwl                                                                                                                                                                                                                       |           |             |
    |            |                     |                                                                                                                                                                                                                                                               |           |             |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **14**     |                     | Each independent on-chip ground pad, including substrate pads, must metallically connect to at least one B2B diode                                                                                                                                            | **LuRes** |             |
    |            |                     |                                                                                                                                                                                                                                                               |           |             |
    |            |                     | Allowable B2B diodes:                                                                                                                                                                                                                                         |           |             |
    |            |                     |                                                                                                                                                                                                                                                               |           |             |
    |            |                     | -  s8iom0s8_top_b2b_diode                                                                                                                                                                                                                                     |           |             |
    |            |                     | -  s8iom0S8_top_lvc_b2b_wopad                                                                                                                                                                                                                                 |           |             |
    |            |                     | -  s8_esd_gnd2gnd_120x2_lv_isosub                                                                                                                                                                                                                             |           |             |
    |            |                     | -  s8atlasana_esd_gnd2gnd_120x2_lv_isosub                                                                                                                                                                                                                     |           |             |
    |            |                     | -  s8fpiom0s8_esd_gnd2gnd_180x2_lv_dnwl                                                                                                                                                                                                                       |           |             |
    |            |                     |                                                                                                                                                                                                                                                               |           |             |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+
    | **15**     |                     | Maximum metal resistance from one end of the bus (power, ground) to another                                                                                                                                                                                   | **NDRC**  | **5Ω**      |
    +------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-------------+

.. table:: Table 1 – Allowable Primary ESD Blocks

    +----------+----------+--------------+---------------------------------------+----------------------------------------------+
    | Pad Type | DDC      | Library      | Cell Name                             | Description                                  |
    +----------+----------+--------------+---------------------------------------+----------------------------------------------+
    | 10V      | s8esdg4  | s8esdg4_net  | s8esdg4_net_io_b                      | 10V TX/RX signal pad                         |
    +----------+----------+--------------+---------------------------------------+----------------------------------------------+
    | 10V      | s8esdg4  | s8esdg4_net  | s8esdg4_net_10v_clamp                 | 10V supply pad                               |
    +----------+----------+--------------+---------------------------------------+----------------------------------------------+
    | 10V      | s8esdg4  | s8esdg4_trig | s8esdtrig_trig_top_b                  | 10V distributed active shunt trigger circuit |
    +----------+----------+--------------+---------------------------------------+----------------------------------------------+
    | 5V       | s8iom0s8 | s8iom0s8     | s8iom0s8_top_gpio                     | 5V GPIO driver with ESD block                |
    +----------+----------+--------------+---------------------------------------+----------------------------------------------+
    | 5V       | s8iom0s8 | s8iom0s8     | s8iom0s8_top_sio                      | 5V SIO driver with ESD block                 |
    +----------+----------+--------------+---------------------------------------+----------------------------------------------+
    | 5V       | s8iom0s8 | s8iom0s8     | s8iom0s8_top_vss                      | Includes 5V HV ESD clamp                     |
    +----------+----------+--------------+---------------------------------------+----------------------------------------------+
    | 5V       | s8iom0s8 | s8iom0s8     | s8iom0s8_top_vcc                      | Includes two 1.8V LV clamps                  |
    +----------+----------+--------------+---------------------------------------+----------------------------------------------+
    | 5V       | s8iom0s8 | s8iom0s8     | s8iom0s8_top_vdd                      | Includes two 1.8V LV clamps                  |
    +----------+----------+--------------+---------------------------------------+----------------------------------------------+
    | 5V       | s8iom0s8 | s8iom0s8     | s8iom0s8_top_vddnp                    | Includes 5V HV ESD clamp                     |
    +----------+----------+--------------+---------------------------------------+----------------------------------------------+
    | 5V       | s8iom0s8 | s8iom0s8     | s8iom0s8_top_vddc                     | Includes 5V HV ESD clamp                     |
    +----------+----------+--------------+---------------------------------------+----------------------------------------------+
    | 5V       | s8iom0s8 | s8iom0s8     | s8iom0s8_top_vssc                     | Includes two 1.8V LV clamps and B2B diode    |
    +----------+----------+--------------+---------------------------------------+----------------------------------------------+
    | 1.8V     | s8framio | s8framio     | s8framio_esd_paddiode2pwr_100_lv      | LV diode clamps for FRS8 products            |
    +----------+----------+--------------+---------------------------------------+----------------------------------------------+
    | 1.8V     | s8framio | s8framio     | s8framio_esd_paddiode2gnd_100_dnwl_lv | LV diode clamps for FRS8 products            |
    +----------+----------+--------------+---------------------------------------+----------------------------------------------+

.. table:: Table 1a: Pin Table for SHV ESD Clamps

    +----------+---------+--------------------------+-----------------+
    | Pad Type | **DDC** | **Cell Name**            | **Description** |
    +----------+---------+--------------------------+-----------------+
    | 21V      | s8usbpd | s8usbpd_esd_iec_21v_30x4 | 21V IEC Clamp   |
    +----------+---------+--------------------------+-----------------+
    | 32V      | s8usbpd | s8usbpd_esd_hbm_32v_10x4 | 32V HBM Clamps  |
    +----------+---------+--------------------------+-----------------+
    | 21V      | s8usbpd | s8usbpd_esd_hbm_21v_10x4 | 21V HBM Clamps  |
    +----------+---------+--------------------------+-----------------+
    | 21V      | s8usbpd | s8usbpd_esd_cdm_uhv      | HV CDM Clamp    |
    +----------+---------+--------------------------+-----------------+


.. table:: Table 2 – Primary ESD Block Minimum Metal Interconnect Width Requirements

    +----------+------+------+-----+-----+-------+
    | Pad Type | M1   | M2   | M3  | M4  | M5    |
    +----------+------+------+-----+-----+-------+
    | All      | 12µm | 12µm | 6µm | 6µm | 2.5µm |
    +----------+------+------+-----+-----+-------+

.. table::  Table 3 – Primary ESD Block Minimum Contact Interconnect Requirements

    +--------------+-----------+----------+---------+----------+----------+----------+
    | **Pad Type** | **licon** | **mcon** | **via** | **via2** | **via3** | **via4** |
    +--------------+-----------+----------+---------+----------+----------+----------+
    | All          | 400       | 250      | 90      | 70       | 70       | 8        |
    +--------------+-----------+----------+---------+----------+----------+----------+

.. table:: Section B2: Secondary ESD Block Integration Rules
    :name: section-b2-secondary-esd-block-integration-rules
    :class: ListParagraph

    +------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+-------------+
    | **Rule**   | **Exempt** | Note: Secondary (local) ESD blocks are associated with input paths from the pad to input buffers or any gate oxide                                                                                                                                                                                          | **Use**  | **Value**   |
    |            |            |                                                                                                                                                                                                                                                                                                             |          |             |
    | **blkio.** |            |                                                                                                                                                                                                                                                                                                             |          |             |
    +------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+-------------+
    | **1**      |            | Allowable ESD IP for secondary ESD blocks                                                                                                                                                                                                                                                                   | **NDRC** | **Table 4** |
    +------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+-------------+
    | **2**      |            | An ESD resistor must be connected between any IO pad and pass/transmission and/or input buffer gates                                                                                                                                                                                                        | **NDRC** |             |
    |            |            |                                                                                                                                                                                                                                                                                                             |          |             |
    |            |            | Exemptions:                                                                                                                                                                                                                                                                                                 |          |             |
    |            |            |                                                                                                                                                                                                                                                                                                             |          |             |
    |            |            | - s8tsafeg7xl_mux_low_res_top                                                                                                                                                                                                                                                                               |          |             |
    |            |            |                                                                                                                                                                                                                                                                                                             |          |             |
    +------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+-------------+
    | **3**      |            | Secondary ESD blocks must be placed at the input buffer gates if the resistance from pad to input is <10K ohms                                                                                                                                                                                              | **NDRC** |             |
    +------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+-------------+
    |            | **3a**     | Secondary ESD blocks are not required if the input path consists of an ESD resistor AND series pass/transmission gate(s)                                                                                                                                                                                    | **NDRC** |             |
    +------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+-------------+
    | **3.1**    |            | The secondary ESD block must connect to the same power supply and ground supply as the input buffers                                                                                                                                                                                                        | **NDRC** |             |
    +------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+-------------+
    |            | **3.1a**   | If the input gate voltage swing exceeds the input stage power supply, the secondary ESD block may be connected to an intermediate power supply at the discretion of the ESD Group                                                                                                                           | **NDRC** |             |
    +------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+-------------+
    | **3.2**    |            | Maximum power supply interconnect resistance (R1) between secondary ESD block cathode and input buffer power supply based on the following conditions (Figure 1):                                                                                                                                           | **NDRC** | **1 Ω**     |
    |            |            |                                                                                                                                                                                                                                                                                                             |          |             |
    |            |            | a. If the local diode power supply connection is in the primary current path (Condition a)                                                                                                                                                                                                                  |          | **5 Ω**     |
    |            |            | b. If the local diode power supply connection is not in the primary current path (Condition b)                                                                                                                                                                                                              |          |             |
    |            |            |                                                                                                                                                                                                                                                                                                             |          |             |
    |            |            | **Note: If the power supply connections to the input block use the input block power bussing as a feedthrough to other blocks, the connection is considered to be in the primary current path. Condition b is desired, as it limits the maximum voltage across the input buffer gate during ESD events.**   |          |             |
    +------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+-------------+
    |            | **3.2a**   | If condition 3.1a exists, rule 3.2 is exempted.                                                                                                                                                                                                                                                             | **NDRC** |             |
    +------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+-------------+
    | **3.3**    |            | Maximum ground supply interconnect resistance (R2) between secondary ESD block anode and input buffer ground supply based on the following conditions (Figure 1):                                                                                                                                           | **NDRC** | **1 Ω**     |
    |            |            |                                                                                                                                                                                                                                                                                                             |          |             |
    |            |            | a. If the local diode power supply connection is in the primary current path (Condition a)                                                                                                                                                                                                                  |          | **5 Ω**     |
    |            |            | b. If the local diode power supply connection is not in the primary current path (Condition b)                                                                                                                                                                                                              |          |             |
    |            |            |                                                                                                                                                                                                                                                                                                             |          |             |
    |            |            | **Note: If the ground supply connections to the input block use the input block ground bussing as a feedthrough to other blocks, the connection is considered to be in the primary current path. Condition b is desired, as it limits the maximum voltage across the input buffer gate during ESD events.** |          |             |
    +------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+-------------+
    | **4**      |            | Minimum metal width for any metal layer in all paths connecting from IO pad to the secondary ESD block                                                                                                                                                                                                      | **NDRC** | **0.6µm**   |
    +------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+-------------+
    | **5**      |            | Minimum total number of contacts for any contact layer in all paths from IO pad to the secondary ESD block                                                                                                                                                                                                  | **NDRC** | **2**       |
    +------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+-------------+


.. table:: Table 4 – Cell Names for Secondary ESD Blocks

    +-----------------+----------+--------------+-----------------------------------------+
    | Pad Type        | DDC Name | Library Name | Cell Name                               |
    +-----------------+----------+--------------+-----------------------------------------+
    | All input paths | s8_esd   | s8_esd       | s8_esd\_ signal_5_sym_lv_local          |
    |                 |          |              | s8_esd_signal\_ 5_sym_hv_local_5term    |
    |                 |          |              | s8_esd_signal_5_sym_hv_local_5term_dnwl |
    |                 |          |              | s8_esd_localdiode_hv                    |
    |                 |          |              | s8_esd_localdiode_lv                    |
    |                 |          |              | s8_esd_res_75only_small                 |
    |                 |          |              | s8_esd_res_250only_small                |
    +-----------------+----------+--------------+-----------------------------------------+


.. figure:: Figure 1 – Local Diode Connection Resistance Rules

    |image1|


.. table:: Section B3: Regulated/Internal Supply ESD Integration Rules
    :name: section-b3-regulatedinternal-supply-esd-integration-rules
    :class: ListParagraph

    +-------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+-----------+
    | **Rule**    | **Exempt** | Note: Due to the complexities of internal supply domain ESD protection, the ESD group will document the protection scheme for each regulated/internal supply on chip. The product team is responsible for implementing the chip-level regulated ESD network. | **Use**  | **Value** |
    |             |            |                                                                                                                                                                                                                                                              |          |           |
    | **netreg.** |            |                                                                                                                                                                                                                                                              |          |           |
    +-------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+-----------+
    | **1**       |            | Allowable ESD IP Blocks for regulated/internal supply domains                                                                                                                                                                                                | **NDRC** | **Table** |
    +-------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+-----------+
    | **2**       |            | No ESD blocks are required for regulated/internal supply domains with total Pwr to Gnd capacitance of greater than                                                                                                                                           | **NDRC** | **30 nF** |
    +-------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+-----------+


.. table:: Table 5 – Cell Names for Regulated/Internal Supply Domains

    +----------+----------+--------------+-----------------------------+
    | Pad Type | DDC Name | Library Name | Cell Name                   |
    +----------+----------+--------------+-----------------------------+
    | 10V      | N/A      | N/A          | N/A                         |
    +----------+----------+--------------+-----------------------------+
    | 5V       | s8iom0s8 | s8iom0s8     | Includes two 1.8V LV clamps |
    +----------+----------+--------------+-----------------------------+


APPENDIX C: Miscellaneous Rules
-------------------------------

.. table:: Section C1: Miscellaneous Rules
    :name: section-c1-miscellaneous-rules
    :class: ListParagraph

    +----------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------------+
    | **Rule** | **Exempt** |                                                                                                                                                                                                                                                | **Use**   | **Value**        |
    | **mdr.** |            |                                                                                                                                                                                                                                                |           |                  |
    +----------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------------+
    | **1**    |            | DELETED                                                                                                                                                                                                                                        |           |                  |
    +----------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------------+
    | **2**    |            | DELETED                                                                                                                                                                                                                                        |           |                  |
    +----------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------------+
    | **3**    |            | Parasitic diodes metallically connected between external pads (i.e. – pdiff to a pad and its associated nwell connected to another pad, or ndiff to a pad and its associated pwell connected to another pad) must meet the following criteria; | **NDRC**  | 100 µm\ :sup:`2` |
    |          |            |                                                                                                                                                                                                                                                |           |                  |
    | **3.1**  |            | Minimum diffusion area:                                                                                                                                                                                                                        |           | Tables 2/3       |
    |          |            |                                                                                                                                                                                                                                                |           |                  |
    | **3.2**  |            | Minimum interconnect metal width and contact/via counts                                                                                                                                                                                        |           |                  |
    +----------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------------+
    |          | **3a**     | Exemptions: Instances covered by areaid:ed                                                                                                                                                                                                     |           |                  |
    +----------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------------+
    | **4**    |            | **ESD_At_Risk_Wells**                                                                                                                                                                                                                          | **NDRC**  |                  |
    |          |            |                                                                                                                                                                                                                                                |           |                  |
    |          |            | Defined as;                                                                                                                                                                                                                                    |           |                  |
    |          |            |                                                                                                                                                                                                                                                |           |                  |
    |          |            | 1) Nwell that contains pad connected diffusion and the well is not metallically connected (hard tied) to a Vcc net                                                                                                                             |           |                  |
    |          |            | 2) Pwell in DNW that contains pad connected diffusion and the well is not metallically connected (hard tied) to a Vss net                                                                                                                      |           |                  |
    |          |            |                                                                                                                                                                                                                                                |           |                  |
    |          |            | Equivalent resistance from the pad to the diffusion in the well must be ≥ 75Ω                                                                                                                                                                  |           |                  |
    |          |            |                                                                                                                                                                                                                                                |           |                  |
    |          |            | (See Figure below)                                                                                                                                                                                                                             |           |                  |
    |          |            |                                                                                                                                                                                                                                                |           |                  |
    |          |            | |image2|                                                                                                                                                                                                                                       |           |                  |
    |          |            |                                                                                                                                                                                                                                                |           |                  |
    |          |            | **Rule 4 – ESD_At_Risk_Wells**                                                                                                                                                                                                                 |           |                  |
    +----------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------------+
    |          | **4a**     | Exemption: Pad connected ESD diffusion – the ESD diffusion must be in a separate/isolated well, it cannot be in the same well as any other resistively isolated diffusions. (See Figure)                                                       | **NDRC**  |                  |
    |          |            |                                                                                                                                                                                                                                                |           |                  |
    |          |            | |image3|                                                                                                                                                                                                                                       |           |                  |
    |          |            |                                                                                                                                                                                                                                                |           |                  |
    |          |            | **Rule 4 – ESD_At_Risk_Wells – Exemptions**                                                                                                                                                                                                    |           |                  |
    +----------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------------+
    | **5**    |            | Minimum equivalent resistance from signal pad to n+ diffusion which is in an isolated p-well where the isolated p-well is not metallically connected to ground                                                                                 | **LuRes** | 150Ω             |
    |          |            |                                                                                                                                                                                                                                                |           |                  |
    |          |            | Exemption:                                                                                                                                                                                                                                     |           |                  |
    |          |            |                                                                                                                                                                                                                                                |           |                  |
    |          |            | -  s8uspbd_sbu_sw_top                                                                                                                                                                                                                          |           |                  |
    |          |            | -  s8subpdv2_vddd_sw_nsw                                                                                                                                                                                                                       |           |                  |
    |          |            | -  s8usbpdv2_dpdm_sw_2X2_nch                                                                                                                                                                                                                   |           |                  |
    |          |            | -  s8usbpdv2_20vconn_sw_top                                                                                                                                                                                                                    |           |                  |
    |          |            | -  s8usbpdv2_20sbu_sw_top                                                                                                                                                                                                                      |           |                  |
    |          |            |                                                                                                                                                                                                                                                |           |                  |
    +----------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------------+
    | **6**    |            | All touch products should use snapback robust ESD clamp on the power supply that drives the touch sense X-Y IO’s and the touch sense X-Y IO’s should have snapback capable licon to poly space                                                 | **NDRC**  |                  |
    +----------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------------+

.. |image0| image:: ./media/esd1.jpeg
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   :height: 0.19792in
.. |image1| image:: ./media/esd3.svf
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   :height: 2.94097in
.. |image2| image:: ./media/esd4.svf
   :width: 4.21528in
   :height: 6.68542in
.. |image3| image:: ./media/esd5.svf
   :width: 5.29028in
   :height: 6.84514in