Title: M0S8 Latch-up Design Rules (LU MTDR)

Purpose/Scope
=============

Purpose
-------

Document the Latch-up Design Rules for products using the M0S8 process.

Latch-up Generic Rules
----------------------

Signal Pad Latch-up Rules
-------------------------

Latch-up Special Cases
----------------------

Miscellaneous Rules
-------------------

Definitions and Terminology
---------------------------

Appendix A - LU DRC Form Description
------------------------------------

Appendix B1- CAD Automation Algorithm Index
-------------------------------------------

+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|           | .. rubric:: **Definitions and Terminology**                                                                                                                                                                                                                                             |
|           |    :name: definitions-and-terminology-1                                                                                                                                                                                                                                                 |
|           |    :class: ListParagraph                                                                                                                                                                                                                                                                |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.1**   | “areaid.ed” surrounds any diffusion or ESD nwell tap connected to a signal pad.                                                                                                                                                                                                         |
|           |                                                                                                                                                                                                                                                                                         |
|           | Note: algorithm does not flag devices with areaid:en that is drain extended devices.                                                                                                                                                                                                    |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.2**   | *ESD_diffusion* is defined as any diffusion or ESD_nwell_tap connected metallically or through a resistor to a pad or to Vss/Vcc that is covered by areaid.ed.                                                                                                                          |
|           |                                                                                                                                                                                                                                                                                         |
|           | Note: CAD flow generates layers ESD_PSD and ESD_NSD in VLW to identify diff directly connected to I/O Pad. It also generates layer io_res to identify ESD resistors.                                                                                                                    |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.3**   | *ESD_nwell_tap* is defined as N+ tap coincident with nwell such that N+ tap and nwell are completely surrounded by and abutting N+ diff on all edges, within areaid:ed.                                                                                                                 |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.4**   | *ESD_diode* is defined as any nwell (other than any ESD nwell tap) covered by areaid:ed and areaid:de that does not contain poly.                                                                                                                                                       |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.5**   | *esd_diff_tap_nwell* is defined as areaid.ed AND diff_tap_nwell.                                                                                                                                                                                                                        |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.6**   | *diff_tap_nwell* is defined as tap_nwell INSIDE diff_hole.                                                                                                                                                                                                                              |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.7**   | *tap_nwell* is defined as tap INSIDE nwell.                                                                                                                                                                                                                                             |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.8**   | *diff_hole* is defined as Hole( diff).                                                                                                                                                                                                                                                  |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.9**   | *ESD_NFET* is defined as (any Ndiff covered by areaid:ed abutting ESD_nwell_tap) Or (any Ndiff covered by areaid:ed abutting gate within 3.5um of ESD_nwell_tap) Or (any Ndiff abutting ESD_nwell_tap within areaid.ed) a double tap guardrings.                                        |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.10**  | *ESD_FET* is defined as (any Pdiff covered by areaid:ed within a double tap guardrings) Or ESD_NFET                                                                                                                                                                                     |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.11**  | *met_ESD_resistor* is defined as Metal resistor inside areaid:ed.                                                                                                                                                                                                                       |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.12**  | *I/O_or_Output_Pmos* is defined as ESD P+ diffusion overlapping poly and overlapping ESD source/drain diffusion connected to I/O or output net.                                                                                                                                         |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.13**  | *flare_gates* is defined as 45 degrees poly, straddling diff inside areaid:ed.                                                                                                                                                                                                          |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.14**  | *Non_Vcc_nwell* is defined as any nwell or Dnwell connected to a positive power supply through > 10Ω, or connected to Vss or connected to a signal pad.                                                                                                                                 |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.14a** | *At RISK Non_Vcc_nwell* is any nwell containing p+ diffusion connected to a positive external power supply ≥ 3.3V, where the nwell is not metallically connected to the same positive power supply.                                                                                     |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.15**  | *“RF Pins”* that require special ESD protection schemes must be reviewed by the ESD Review Board and the pin labels must use the prefix “RF\_” for pin identification. The proper label format is “RF_userPinName”.                                                                     |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.16**  | *shorted_on_die*: Two power (or ground) nets are shorted on die if they are connected on the die through metal buses.                                                                                                                                                                   |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.17**  | *shorted_thru_package*: Two power (ground) nets are shorted through package if they are not connected on the die, but connected through bond wires or package ground planes.                                                                                                            |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.18**  | *isolated_on_die*: Two power (ground) nets are isolated_on_die if they are not shorted on die, even if they are shorted through package.                                                                                                                                                |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.19**  | *internal Vcci, Vssi*: Internal power and ground supplies (Vcci or Vssi) are supplies with highest capacitance on die and usually connect to the memory array and the majority of internal circuitry. All other *isolated_on_die* supplies are labeled as Vccn or Vssn, where n=1,2…    |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.20**  | *pwell*: is defined as deep nwell not nwell.                                                                                                                                                                                                                                            |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.21**  | *Positive power supply:* Any external or regulated positive power supply (Vcc net)                                                                                                                                                                                                      |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.22**  | “areaid.ly” encloses any circuitry meeting the loose tapping rule but violating the tight tapping rule. This part of the circuitry must be placed >50um away from signal pad injection sources at the chip-level.                                                                       |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.23**  | “areaid.inj” encloses any circuitry deemed sensitive (by design team) to injected substrate carriers. This part of the circuitry must be placed >100um away from signal pad injection sources at the chip-level.                                                                        |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.24**  | Sensitive Circuitry: Circuitry that is susceptible to disturb issues associated with injected substrate carriers from signal pad connected diffusions/well. The design community must assess their design’s sensitivity to this phenomenon.                                             |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.25**  | Resistive voltage divider: A resistive connection between power and ground nets, used to produce a fraction of the power supply voltage at its output. It can be composed of any combination of poly, ESD poly, pwell, diffusion, ESD diffusion, and ESD metX (X= 1,2,3 ..n) resistors. |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.26**  | SONOS Area: DNWell outside HVI regions overlapping coreid layer overlapping tunm                                                                                                                                                                                                        |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **x.27**  | SONOS Flash Macros Array: A continuous piece of N+ diff with at least 34 poly gates                                                                                                                                                                                                     |
|           |                                                                                                                                                                                                                                                                                         |
| **x.28**  | | “areaid.sigPadDiff” encloses any diffusion connected to signal pad through < 10 KΩ resistor.                                                                                                                                                                                          |
|           | | areaid.sigPadWell encloses any well connected to signal pad.                                                                                                                                                                                                                          |
| **x.29**  | | areaid.sigPadMetNtr encloses any diffusion metallically connected to signal pad.                                                                                                                                                                                                      |
|           |                                                                                                                                                                                                                                                                                         |
|           | | diffusion connected metallically to a signal pad, need both layers (areaid.sigPadDiff, areaid.sigPadMetNtr) over those diffusions.                                                                                                                                                    |
|           | | diffusion connected to a signal pad via a resistor, need only areaid.SigPadDiff over those diffusions                                                                                                                                                                                 |
|           |                                                                                                                                                                                                                                                                                         |
|           | Signal pad diffusion is any diff or tap connected to a signal pad either metallically or through a resistor of less than 10KOhm.                                                                                                                                                        |
|           |                                                                                                                                                                                                                                                                                         |
|           | Notes:                                                                                                                                                                                                                                                                                  |
|           |                                                                                                                                                                                                                                                                                         |
|           | 1) Only resistors labeled with text.dg as ‘10KOhm’, or connected to pwr/gnd supplies, will break the connectivity between pad and diffusion.                                                                                                                                            |
|           |                                                                                                                                                                                                                                                                                         |
|           | 2) Drain Extended FETs must be checked manually for all guard ring rules                                                                                                                                                                                                                |
|           |                                                                                                                                                                                                                                                                                         |
|           | 3) Legacy IP with ‘100KOhm’ text.dg label will also break the connectivity between pad and diffusion.                                                                                                                                                                                   |
|           |                                                                                                                                                                                                                                                                                         |
|           | SHV: Super High Voltage. SHV nets correspond to any net which is connected to higher than 5.5V supply or signal pad.                                                                                                                                                                    |
+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **CAD switch**        | **Description**                                                                                                                                                        |
+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| local_sub             | Creates an isolated substrate in the places where areaid.substrateCut is drawn.                                                                                        |
+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| block_level           | Promote block pins to be treated like pad connections. Switch should be used at the level of IP Blocks that contain pins which get connected to pad at a higher level. |
|                       |                                                                                                                                                                        |
|                       | NOTE: Use of the block-level switch checks the following rules: Section 2, Rules 7 and 8. All other rules are not affected.                                            |
+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| OLD_TAPPING_RULE_RevU | Checks tapping rules to rev \*U of the SKY130 MTDR, which was based on spacing to signal pad connected diff. To be used ONLY on legacy IP blocks to avoid IP rework.       |
+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| ACTIVE_ESD            | Used with active ESD methodology.                                                                                                                                      |
+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **CAD LuRes switch** | **Description**                                                                                                                                            |
+----------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
| block_level          | Promote block pins to be treated like pad connections. Switch should be used for IP Blocks that contain pins which get connected to pad at a higher level. |
|                      |                                                                                                                                                            |
|                      | NOTE: Use of the block_level switch affects the following rules:                                                                                           |
|                      |                                                                                                                                                            |
|                      | Section 2 Rule 5 and Rule 15. At the IP block level this is used for information purposes only.                                                            |
+----------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| **text.dg Label**    | **Description**                                                                                                                                                                                               |
+----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| probe-only           | Identifies bond pads used only for un-bonded pads (characterization/probe) without ESD protection                                                                                                             |
+----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| 10KOhm               | Identifies minimum of 10 KΩ resistance between signal pad and diffusion. Used to break signal pad to diff connectivity (Sect 4, rule 1)                                                                       |
+----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| 250Ohm               | Identifies deep nwells resistively isolated from bond pads by a minimum of 250 Ω. Allows exemption from grounded DNW rule (Sect 2, rule 2.1b)                                                                 |
|                      |                                                                                                                                                                                                               |
| 1KOhm                | Identifies deep nwells resistively isolated from bond pads by a minimum of 1000 Ω. Allows exemption from grounded DNW rule (Sect 13, rule 1)                                                                  |
+----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| leaker               | Used to identify a resistive pull-down leaker arrangement between I/O, power and ground nets.                                                                                                                 |
+----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| pwr_bias & gnd_bias  | Used to short resistor dividers for certain rule checks. Text must be placed over appropriate resistors.                                                                                                      |
|                      |                                                                                                                                                                                                               |
| openRes              | During latchup checks, resistors short the two nets for their true connectivity.  Resistors texted as openRes in text.dg will open the resistor terminals.                                                    |
+----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| switched_power       | Identifies the switched power output of a p-channel switch. Label needs to be placed over the metal1 that connects the drain of the p-channel switch.                                                         |
+----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| switch_to_global_bus | Identifies the gates of pass transistors that connect a pad to a common global bus. Use this label ONLY when several pads on a chip connect to the common global bus causing short circuits between the pads. |
+----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-------+---------------------------------------------------+-----------+----------------------+----------+
|       | .. rubric:: **Section 1: Latch-up Generic Rules** |           | **Design Signature** |          |
|       |    :name: section-1-latch-up-generic-rules        |           |                      |          |
|       |    :class: ListParagraph                          |           |                      |          |
+-------+---------------------------------------------------+-----------+----------------------+----------+
|       |                                                   | **Value** | **Initials**         | **Date** |
+-------+---------------------------------------------------+-----------+----------------------+----------+
| **1** | DELETED                                           |           |                      |          |
+-------+---------------------------------------------------+-----------+----------------------+----------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+-------+
| Note: All IP blocks will be checked to the 6 µm tapping rule (except rule 2.1) regardless of spacing to signal pad diff. If the 6µm tapping rule cannot be met for certain diffusions in the IP block due to concerns of die area increase, then areaid.ltd can be drawn over that portion of diffusion that violates the 6µm tapping rule. Usage of areaid.ltd triggers the 15 µm tapping rule checks in that region during verification at IP block level. | **SPACE**                                                                                                                                                                                                            |                                 |       |
|                                                                                                                                                                                                                                                                                                                                                                                                                                                              |                                                                                                                                                                                                                      |                                 |       |
| Usage of areaid.ly on an IP block helps chip-level integrators in the floor-planning stage to assist in placement of IP blocks. Designers should use the areaid.ltd with discretion and not blanket the whole IP block to overcome the 6 µm tapping rule. While strongly discouraged, frozen/legacy IP blocks can default to the original, proximity-based tapping checks by using the “OLD_TAPPING_RULE_RevU” switch.                                       |                                                                                                                                                                                                                      |                                 |       |
|                                                                                                                                                                                                                                                                                                                                                                                                                                                              |                                                                                                                                                                                                                      |                                 |       |
| Note2: CADflow algorithm treats nwell in isolated PWELL or PSUB as a barrier. Distance check goes around the nwell.                                                                                                                                                                                                                                                                                                                                          |                                                                                                                                                                                                                      |                                 |       |
|                                                                                                                                                                                                                                                                                                                                                                                                                                                              |                                                                                                                                                                                                                      |                                 |       |
| Note3: This check is for diffusion metallically connected to signal pad only.                                                                                                                                                                                                                                                                                                                                                                                |                                                                                                                                                                                                                      |                                 |       |
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+-------+
|                                                                                                                                                                                                                                                                                                                                                                                                                                                              | < 50µm from signal pad diff\*                                                                                                                                                                                        | >/= 50µm from signal pad diff\* |       |
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+-------+
| 2                                                                                                                                                                                                                                                                                                                                                                                                                                                            | Max spacing from center of ptap licon to any part of ndiff within the same psub or pwell                                                                                                                             | 6 µm                            | 15 µm |
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+-------+
| 2.1                                                                                                                                                                                                                                                                                                                                                                                                                                                          | Max spacing from center of ptap licon to any part of ndiff within the same isolated pwell (in deep nwell) where the deep nwell, or any nwell that abuts it, does NOT contain a positive power supply connected pdiff | 15 µm                           | 15 µm |
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+-------+
| *Exemptions to (2): ESD diffusion;*                                                                                                                                                                                                                                                                                                                                                                                                                          |                                                                                                                                                                                                                      |                                 |       |
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+-------+
| **3**                                                                                                                                                                                                                                                                                                                                                                                                                                                        | Max spacing from center of N+ tap licon to any part of P+ diff within the same Nwell or DNW                                                                                                                          | 6 µm                            | 15 µm |
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+-------+
| *Exemptions to (3): ESD diffusion;*                                                                                                                                                                                                                                                                                                                                                                                                                          |                                                                                                                                                                                                                      |                                 |       |
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+-------+
|                                                                                                                                                                                                                                                                                                                                                                                                                                                              |                                                                                                                                                                                                                      |                                 |       |
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+-------+

Notes: (a) \* Pad diff is any diff directly connected in metal to a signal pad.

+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+--------------+----------+
|       |                                                                                                                                                                                             | **Value** | **Initials** | **Date** |
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+--------------+----------+
| **4** | Minimum distance from diffusion metallically connected to a signal pad to the closest cell in a memory core.                                                                                | 50 µm     | **DRC**      |          |
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+--------------+----------+
| **5** | Minimum space between                                                                                                                                                                       | 3 µm      | **DRC**      |          |
|       |                                                                                                                                                                                             |           |              |          |
|       | ndiff to unrelated ndiff within a common psub or common pwell                                                                                                                               |           |              |          |
|       |                                                                                                                                                                                             |           |              |          |
|       | pdiff to unrelated pdiff within a common nwell or common deep nwell                                                                                                                         |           |              |          |
|       |                                                                                                                                                                                             |           |              |          |
|       | metallically connected to separate pads or external nets (ground, power or signal)                                                                                                          |           |              |          |
|       |                                                                                                                                                                                             |           |              |          |
|       | Exemptions:                                                                                                                                                                                 |           |              |          |
|       |                                                                                                                                                                                             |           |              |          |
|       | 1)  FETs covered by areaid:ed                                                                                                                                                               |           |              |          |
|       | 2)  FETs in the s8_esd library                                                                                                                                                              |           |              |          |
|       | 3)  Diffs connected to probe-Only pads identified by “probe-only” in text.dg layer                                                                                                          |           |              |          |
|       | 4)  Source and drain diffs associated with a single FET element (connected across poly gates), whether that FET element is built in single or multiple active regions                       |           |              |          |
|       | 5)  s8usbpd_300msw_nsw                                                                                                                                                                      |           |              |          |
|       | 6)  s8fpiom0s8_top_lvc_b2b_wopad                                                                                                                                                            |           |              |          |
|       | 7)  s8fpiom0s8_top_hvclamp_wopad                                                                                                                                                            |           |              |          |
|       | 8)  s8usbpd_sbu_sw_top                                                                                                                                                                      |           |              |          |
|       | 9)  s8usbpd_vddd_sw_nsw                                                                                                                                                                     |           |              |          |
|       | 10) s8anatk_hvldo_top_gating_aup                                                                                                                                                            |           |              |          |
|       | 11) s8srsscore_vccd_switch                                                                                                                                                                  |           |              |          |
|       | 12) s8subpdv2_vddd_sw_nsw                                                                                                                                                                   |           |              |          |
|       | 13) s8usbpdv2_dpdm_sw_2X2_nch                                                                                                                                                               |           |              |          |
|       | 14) s8usbpdv2_vddd_sw_top                                                                                                                                                                   |           |              |          |
|       | 15) mmiolib_top_hvclamp_wopad                                                                                                                                                               |           |              |          |
|       | 16) mmiolib_top_lvc_b2b_wopad                                                                                                                                                               |           |              |          |
|       | 17) mmiolib_top_lvclamp_wopad                                                                                                                                                               |           |              |          |
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+--------------+----------+
| **7** | Minimum distance from diffusion metallically connected to a signal pad to sensitive circuitry (marked by areaid.inj). ONLY the circuitry deemed sensitive should be enclosed by this layer. | 100 µm    | **NDRC**     |          |
|       |                                                                                                                                                                                             |           |              |          |
|       | Note: DELETED                                                                                                                                                                               |           |              |          |
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+--------------+----------+
| **9** | Deleted – This rule addressed an ESD concern, moved to “M0S8 Active ESD Design Rules (ESD MTDR)” spec – 001-67310                                                                           |           |              |          |
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+--------------+----------+

+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
|          | .. rubric:: **Section 4: Signal Pad Latch-up Rules**                                                                                                                                                                                                                                                  |           | **Design Signature** |           |
|          |    :name: section-4-signal-pad-latch-up-rules                                                                                                                                                                                                                                                         |           |                      |           |
|          |    :class: ListParagraph                                                                                                                                                                                                                                                                              |           |                      |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
|          |                                                                                                                                                                                                                                                                                                       | **Value** | **Initials**         | **Date**  |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
| **1**    | DELETED                                                                                                                                                                                                                                                                                               | **DEF**   |                      |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
| **1.1**  | These are the allowed guard ring scenarios:                                                                                                                                                                                                                                                           |           | **DRC**              |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | |latchup1|                                                                                                                                                                                                                                                                                            |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemptions:                                                                                                                                                                                                                                                                                           |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 1.  Pad-Pwr ESD Diodes                                                                                                                                                                                                                                                                                |           |                      |           |
|          | 2.  Drain Extended Fets (devices covered by areaid.en)                                                                                                                                                                                                                                                |           |                      |           |
|          | 3.  s8esdg4_net_d1_420_aup                                                                                                                                                                                                                                                                            |           |                      |           |
|          | 4.  s8esdg4_net_d2_360_sub_aup                                                                                                                                                                                                                                                                        |           |                      |           |
|          | 5.  s8esdg4_net_d4_60_aup                                                                                                                                                                                                                                                                             |           |                      |           |
|          | 6.  s8usbpd_esd_cdm_uhv                                                                                                                                                                                                                                                                               |           |                      |           |
|          | 7.  s8usbpd_csa_top                                                                                                                                                                                                                                                                                   |           |                      |           |
|          | 8.  s8usbpd_ngdo_top                                                                                                                                                                                                                                                                                  |           |                      |           |
|          | 9.  s8usbpdv2_csa_top                                                                                                                                                                                                                                                                                 |           |                      |           |
|          | 10. s8usbpd_esd_21v_vbus_iec                                                                                                                                                                                                                                                                          |           |                      |           |
|          | 11. s8usbpdv2_20vconn_sw_300ma_ocp_switch2                                                                                                                                                                                                                                                            |           |                      |           |
|          | 12. s8usbpdv2_esd_21v_hbm                                                                                                                                                                                                                                                                             |           |                      |           |
|          | 13. s8rf_n20vhv1_aup                                                                                                                                                                                                                                                                                  |           |                      |           |
|          | 14. s8usbpd_esd_shv_iec                                                                                                                                                                                                                                                                               |           |                      |           |
|          | 15. s8usbpd_esd_shv_sbu_iec                                                                                                                                                                                                                                                                           |           |                      |           |
|          | 16. s8usbpd_pgdo_pu_top                                                                                                                                                                                                                                                                               |           |                      |           |
|          | 17. s8usbpd_pdgo_top                                                                                                                                                                                                                                                                                  |           |                      |           |
|          | 18. s8usbpd_ea_top                                                                                                                                                                                                                                                                                    |           |                      |           |
|          | 19. s8usbpdv2_esd_shv_iec_sbu                                                                                                                                                                                                                                                                         |           |                      |           |
|          | 20. \***s8usbpdv2_20sbu_sw_ovp_ngate                                                                                                                                                                                                                                                                  |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
| **2**    | All signal pad connected N+ diffusion or N+ tap in Nwell must be separated from internal circuitry and any P+ diffusion by a pair of guard rings (See Figure 1).                                                                                                                                      |           | **DRC**              |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemptions:                                                                                                                                                                                                                                                                                           |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 1. s8esdg4_net_d1_420_aup                                                                                                                                                                                                                                                                             |           |                      |           |
|          | 2. s8esdg4_net_d2_360_sub_aup                                                                                                                                                                                                                                                                         |           |                      |           |
|          | 3. s8esdg4_net_d4_60_aup                                                                                                                                                                                                                                                                              |           |                      |           |
|          | 4. s8blerf_top                                                                                                                                                                                                                                                                                        |           |                      |           |
|          | 5. s8usbpd_esd_cdm_uhv                                                                                                                                                                                                                                                                                |           |                      |           |
|          | 6. s8usbpd_csa_top                                                                                                                                                                                                                                                                                    |           |                      |           |
|          | 7. s8usbpd_ngdo_top                                                                                                                                                                                                                                                                                   |           |                      |           |
|          | 8. s8usbpdv2_csa_top                                                                                                                                                                                                                                                                                  |           |                      |           |
|          | 9. s8usbpd_esd_21v_vbus_iec                                                                                                                                                                                                                                                                           |           |                      |           |
|          | 10. s8usbpdv2_20vconn_sw_300ma_ocp_switch2                                                                                                                                                                                                                                                            |           |                      |           |
|          | 11. s8usbpdv2_esd_21v_hbm                                                                                                                                                                                                                                                                             |           |                      |           |
|          | 12. device s8rf_n20vhv1_aup                                                                                                                                                                                                                                                                           |           |                      |           |
|          | 13. s8usbpd_esd_shv_iec                                                                                                                                                                                                                                                                               |           |                      |           |
|          | 14. s8usbpd_esd_shv_sbu_iec                                                                                                                                                                                                                                                                           |           |                      |           |
|          | 15. s8usbpd_pgdo_pu_top                                                                                                                                                                                                                                                                               |           |                      |           |
|          | 16. s8usbpd_pdgo_top                                                                                                                                                                                                                                                                                  |           |                      |           |
|          | 17. s8usbpd_ea_top                                                                                                                                                                                                                                                                                    |           |                      |           |
|          | 18. s8usbpdv2_esd_shv_iec_sbu                                                                                                                                                                                                                                                                         |           |                      |           |
|          | 19. \***s8usbpdv2_20sbu_sw_ovp_ngate                                                                                                                                                                                                                                                                  |           |                      |           |
|          | 20. \***s8usbpdv2_20vconn_sw_300ma_ovp_ngate                                                                                                                                                                                                                                                          |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
| **2.1**  | (A) For signal pad connected ndiff in psub or ntap in nwell, inner guard ring is P+ tap in substrate connected metallically to a ground supply and outer guard ring is N+ tap in nwell connected metallically to a positive external power supply.                                                    |           | **DRC**              |           |
|          | (B) For signal pad connected ndiff in pwell, inner guard ring is P+ tap in pwell connected metallically to a ground supply or vnb and outer guard ring is N+ tap in dnwell connected metallically to a positive external power supply.                                                                |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Note: DELETED.                                                                                                                                                                                                                                                                                        |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemptions to (A)                                                                                                                                                                                                                                                                                     |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | - s8iom0s8_top_tp2                                                                                                                                                                                                                                                                                    |           |                      |           |
|          | - s8usbpd_esd_cdm_uhv                                                                                                                                                                                                                                                                                 |           |                      |           |
|          | - s8usbpd_csa_top                                                                                                                                                                                                                                                                                     |           |                      |           |
|          | - s8usbpd_ngdo_top                                                                                                                                                                                                                                                                                    |           |                      |           |
|          | - s8usbpd_esd_21v_vbus_iec                                                                                                                                                                                                                                                                            |           |                      |           |
|          | - s8usbpdv2_20vconn_sw_300ma_ocp_switch2                                                                                                                                                                                                                                                              |           |                      |           |
|          | - s8usbpdv2_esd_21v_hbm                                                                                                                                                                                                                                                                               |           |                      |           |
|          | - s8rf_n20vhv1_aup                                                                                                                                                                                                                                                                                    |           |                      |           |
|          | - s8usbpdv2_csa_esd_hbm_21v_10x4                                                                                                                                                                                                                                                                      |           |                      |           |
|          | - s8usbpdv2_csa_top                                                                                                                                                                                                                                                                                   |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemptions to (B)                                                                                                                                                                                                                                                                                     |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | (1) If the ndiff and pwell that contains the ndiff are shorted together, the inner guard ring is P+ tap in pwell connected to signal pad. The outer guard ring is N+ tap in dnwell connected metallically to a positive external power supply.                                                        |           |                      |           |
|          | (2) If the signal pad connected ndiff in pwell is after an approved ESD resistor, the inner guard ring is P+ tap in pwell connected to a ground supply, vnb, or the source or drain of the NFET. The outer guard ring is N+ tap in dnwell connected metallically to a positive external power supply. |           |                      |           |
|          | (3) If the pwell that contains the pad connected ndiff is not connected to Vss, and there are no grounded ndiff in the pwell, then the inner guard ring is ptap connected to an internal signal.                                                                                                      |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | An internal signal is a signal that is not directly connected to a pad, it is the source or drain of another FET.                                                                                                                                                                                     |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | (4) s8iom0s8_top_tp2                                                                                                                                                                                                                                                                                  |           |                      |           |
|          | (5) s8usbpdv2_20sbu_sw_ls_unit                                                                                                                                                                                                                                                                        |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
| **2.1a** | Signal pad connected deep nwell is not allowed.                                                                                                                                                                                                                                                       |           | **DRC**              |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 1.  s8usbpd_esd_21v_vbus_iec                                                                                                                                                                                                                                                                          |           |                      |           |
|          | 2.  s8usbpdv2_20vconn_sw_300ma_ocp_switch2                                                                                                                                                                                                                                                            |           |                      |           |
|          | 3.  s8usbpdv2_esd_21v_hbm                                                                                                                                                                                                                                                                             |           |                      |           |
|          | 4.  s8rf_n20vhv1_aup                                                                                                                                                                                                                                                                                  |           |                      |           |
|          | 5.  s8usbpdv2_csa_esd_hbm_21v_10x4                                                                                                                                                                                                                                                                    |           |                      |           |
|          | 6.  s8usbpdv2_csa_top                                                                                                                                                                                                                                                                                 |           |                      |           |
|          | 7.  s8usbpd_esd_shv_iec                                                                                                                                                                                                                                                                               |           |                      |           |
|          | 8.  s8usbpd_esd_shv_sbu_iec                                                                                                                                                                                                                                                                           |           |                      |           |
|          | 9.  s8usbpd_pgdo_pu_top                                                                                                                                                                                                                                                                               |           |                      |           |
|          | 10. s8usbpd_pdgo_top                                                                                                                                                                                                                                                                                  |           |                      |           |
|          | 11. s8usbpd_ea_top                                                                                                                                                                                                                                                                                    |           |                      |           |
|          | 12. s8usbpdv2_esd_shv_iec_sbu                                                                                                                                                                                                                                                                         |           |                      |           |
|          | 13. \***s8usbpdv2_20sbu_sw_ovp_ngate                                                                                                                                                                                                                                                                  |           |                      |           |
|          | 14. \***s8usbpdv2_20vconn_sw_300ma_ovp_ngate                                                                                                                                                                                                                                                          |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
| **2.1b** | Deep nwell tied to ground through a resistance of < 250 Ω is not allowed. Only resistors labeled with text.dg as ‘250Ohm’ will break the connectivity between ground and deep nwell                                                                                                                   |           | **DRC**              |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemptions:                                                                                                                                                                                                                                                                                           |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | s8usbpd_amux_denfet_top                                                                                                                                                                                                                                                                               |           |                      |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
| **3**    | All P+ signal pad connected diffusion or ptap in pwell (or P+ tap in DNWell as part of a DE_PMOS device) must be separated from internal circuitry and any N+ diffusion by a pair of guard rings (Figure 1).                                                                                          |           | **DRC**              |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemptions:                                                                                                                                                                                                                                                                                           |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 1. s8esdg4_net_d1_420_aup                                                                                                                                                                                                                                                                             |           |                      |           |
|          | 2. s8esdg4_net_d2_360_sub_aup                                                                                                                                                                                                                                                                         |           |                      |           |
|          | 3. s8esdg4_net_d4_60_aup                                                                                                                                                                                                                                                                              |           |                      |           |
|          | 4. s8fpafeg1_io_gnd2gnd_180x2_lv_dnwl_aup                                                                                                                                                                                                                                                             |           |                      |           |
|          | 5. s8fpafeg1_io_gnd2gnd_240x1_lv_dnwl_aup                                                                                                                                                                                                                                                             |           |                      |           |
|          | 6. s8fpafeg1_io_gnd2gnd_240x2_lv_dnwl_aup_tall                                                                                                                                                                                                                                                        |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
| **3.1**  | For signal pad connected P+ diffusion, or ptap in pwell, inner guardring is N+ tap in Nwell connected metallically to a positive power supply and outer guardring is P+ tap metallically connected to external ground supply (Figure 1).                                                              |           | **DRC**              |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemptions:                                                                                                                                                                                                                                                                                           |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 1) pdiff and the nwell in which that pdiff resides are connected to the same signal pad                                                                                                                                                                                                               |           |                      |           |
|          | 2) s8_esd_localdiode_lv, s8_esd_localdiode_hv                                                                                                                                                                                                                                                         |           |                      |           |
|          | 3) Non_Vcc_nwell                                                                                                                                                                                                                                                                                      |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
| **3.2**  | Deleted – Moved to “ESD and LU Best Practices” spec – 001-44971                                                                                                                                                                                                                                       |           |                      |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
| **4**    | Each guardring must be continuously strapped in LI.                                                                                                                                                                                                                                                   |           | **DRC**              |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemptions:                                                                                                                                                                                                                                                                                           |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 1) s8ppscio_sio_pudrvr_reg_pu                                                                                                                                                                                                                                                                         |           |                      |           |
|          | 2) p3ag_gpio_amx                                                                                                                                                                                                                                                                                      |           |                      |           |
|          | 3) p3ag_gpio_ag                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 4) s8psoc3io_sio_pudrvr_reg_pu                                                                                                                                                                                                                                                                        |           |                      |           |
|          | 5) s8iom0s8_sio_pudrvr_reg_pu                                                                                                                                                                                                                                                                         |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
|          | Additionally, the guardring must be strapped in metal. The metal may be broken, but the total series resistance from any part of guardring w/o metal, to the portion of metal strap connected to supply bus must be less than 125 Ω (connected through LI).                                           |           | \____\_              | \____\_   |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Guardrings located on the interior/circuit side of the ESD resistor also require metal strapping,                                                                                                                                                                                                     |           |                      |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
| **5**    | The outer guard ring must connect to respective external power or ground pad Maximum metal resistance from outer guard ring to respective power or ground pad.                                                                                                                                        | 5 Ω       | **LuRes**            |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | a) Around diffusion connected to signal pad in metal                                                                                                                                                                                                                                                  | 10 Ω      |                      |           |
|          | b) Around diffusion connected to signal pad via ESD resistor                                                                                                                                                                                                                                          | 10 Ω      |                      |           |
|          | c) Within 50 µm of any signal pad connected diffusion, maximum resistance of any outer guard ring hook-up to its respective supply pad                                                                                                                                                                |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemptions (a) & (b):                                                                                                                                                                                                                                                                                 |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 1) psoc4able256_top                                                                                                                                                                                                                                                                                   |           |                      |           |
|          | 2) psoc4al_top                                                                                                                                                                                                                                                                                        |           |                      |           |
|          | 3) psoc4ads2_top                                                                                                                                                                                                                                                                                      |           |                      |           |
|          | 4) psoc4a_top                                                                                                                                                                                                                                                                                         |           |                      |           |
|          | 5) psoc4able_top                                                                                                                                                                                                                                                                                      |           |                      |           |
|          | 6) fpg1_top                                                                                                                                                                                                                                                                                           |           |                      |           |
|          | 7) tsg5_m_top                                                                                                                                                                                                                                                                                         |           |                      |           |
|          | 8) psoc4able256dma_top                                                                                                                                                                                                                                                                                |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemptions to (c):                                                                                                                                                                                                                                                                                    |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 1) s8usbpdv2_20vconn_sw_300ma_ovp_ngate                                                                                                                                                                                                                                                               |           |                      |           |
|          | 2) s8usbpdv2_20sbu_sw_ovp_ngate                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 3)  s8ctbm_opa                                                                                                                                                                                                                                                                                        |           |                      |           |
|          | 4)  psoc4able256_top                                                                                                                                                                                                                                                                                  |           |                      |           |
|          | 5)  psoc4able_top                                                                                                                                                                                                                                                                                     |           |                      |           |
|          | 6)  s8atlasana_top                                                                                                                                                                                                                                                                                    |           |                      |           |
|          | 7)  s8tsafg6*_top                                                                                                                                                                                                                                                                                     |           |                      |           |
|          | 8)  tsg6m_top                                                                                                                                                                                                                                                                                         |           |                      |           |
|          | 9)  m0s8gen4_top                                                                                                                                                                                                                                                                                      |           |                      |           |
|          | 10) fpg1_top                                                                                                                                                                                                                                                                                          |           |                      |           |
|          | 11) psoc4a_top                                                                                                                                                                                                                                                                                        |           |                      |           |
|          | 12) psoc4ads2_top                                                                                                                                                                                                                                                                                     |           |                      |           |
|          | 13) psoc4al_top                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 14) ccg4_top                                                                                                                                                                                                                                                                                          |           |                      |           |
|          | 15) tsg5_m_top                                                                                                                                                                                                                                                                                        |           |                      |           |
|          | 16) psoc4able256dma_top                                                                                                                                                                                                                                                                               |           |                      |           |
|          | 17) psoc4able256nr_top                                                                                                                                                                                                                                                                                |           |                      |           |
|          | 18) ccg5_top                                                                                                                                                                                                                                                                                          |           |                      |           |
|          | 19) ccg3pa_top                                                                                                                                                                                                                                                                                        |           |                      |           |
|          | 20) ccg3pa2_top                                                                                                                                                                                                                                                                                       |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | To Run LatchupRes:                                                                                                                                                                                                                                                                                    |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | In the layout toolbar select Cypress – Physical Verification – Calibre DRC/CLDRC/Latchup/Soft/Stress/StreamNets/LVL… and select “LatchupRes”.                                                                                                                                                         |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Note: This is a chip level check; however the block_level switch may be used to run this on an IP block for information only                                                                                                                                                                          |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Use NOT_GR text.dg on inner guard ring if the device has more than 2 guard rings                                                                                                                                                                                                                      |           |                      |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
| **6**    | Minimum width of strapping for outer guardring around diffusion that is metallically connected to signal pad.                                                                                                                                                                                         | 0.85 µm   | **DRC**              |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | LI                                                                                                                                                                                                                                                                                                    | 0.65 µm   |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | M1                                                                                                                                                                                                                                                                                                    |           |                      |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
| **6.1**  | Minimum width of strapping for inner guardring around diffusion that is metallically connected to signal pad.                                                                                                                                                                                         | 0.85 µm   | **DRC**              |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | LI                                                                                                                                                                                                                                                                                                    | 0.65 µm   |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | M1                                                                                                                                                                                                                                                                                                    |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemptions:                                                                                                                                                                                                                                                                                           |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 1) s8_esd_signal_40_sym_hv_2k_dnwl_aup1_b                                                                                                                                                                                                                                                             |           |                      |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
| **7**    | Minimum width of metal hooking outer guardring to power or ground bus for those elements that are metallically connected to signal pad.                                                                                                                                                               | 3 µm      | **DRC**              |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
| **8**    | Minimum number of vias connecting any two metal layers from outer guardring to power or ground bus for those elements that are metallically connected to signal pad.                                                                                                                                  | 6         | **DRC**              |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
|          | Max space between licons for strapping/width checks in rules 6,7, and 8                                                                                                                                                                                                                               | 2 µm      | **DRC**              |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
|          | Max space between mcons for strapping/width checks in rules 6,7, and 8                                                                                                                                                                                                                                | 2 µm      | **DRC**              |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
|          | Max space between vias for strapping/width checks in rules 6,7, and 8                                                                                                                                                                                                                                 | 2 µm      | **DRC**              |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
|          | Max space between vias2 for strapping/width checks in rules 6,7, and 8                                                                                                                                                                                                                                | 2 µm      | **DRC**              |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
| **9**    | Minimum width of outer guardring taps for those elements that are metallically connected to signal pad.                                                                                                                                                                                               | 0.85 µm   | **DRC**              |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
| **12**   | For all flows - Minimum spacing between:                                                                                                                                                                                                                                                              | 27 µm     | **DRC**              |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | a) pdiff, metallically connected to signal pad, and grounded ndiff                                                                                                                                                                                                                                    | 40 µm     |                      |           |
|          |    Exemption:                                                                                                                                                                                                                                                                                         |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          |    1. The following cells: s8sio_lvttl2k_io_r, s8sio_gp4k_outbuf                                                                                                                                                                                                                                      | 40 µm     |                      |           |
|          |    2. The pdiff and the nwell which it resides in are connected to the same signal pad                                                                                                                                                                                                                | 40 µm     |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | b) pwell, metallically connected to signal pad, and grounded ndiff                                                                                                                                                                                                                                    | 27 µm     |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          |    Exemption:                                                                                                                                                                                                                                                                                         | 40 µm     |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          |    If B2B cell s8fpafeg1_io_gnd2gnd_240x1_lv_dnwl_aup is used for input ESD protection, then revert to 27µm requirement.                                                                                                                                                                              | 40 µm     |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | c) pdiff, metallically connected to signal pad, and grounded nwell                                                                                                                                                                                                                                    | 40 µm     |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          |    Exemptions:                                                                                                                                                                                                                                                                                        | 27 µm     |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          |    3. The pdiff and the nwell which it resides in are connected to the same signal pad                                                                                                                                                                                                                | 40 µm     |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | d) pwell, metallically connected to signal pad, and grounded nwell                                                                                                                                                                                                                                    | 40 µm     |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemption:                                                                                                                                                                                                                                                                                            | 40 µm     |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | s8fpafeg1_io_gnd2gnd_180x1_lv_dnwl_aup, s8fpafeg1_io_gnd2gnd_240x1_lv_dnwl_aup                                                                                                                                                                                                                        | 33 µm     |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | e) ndiff, metallically connected to signal pad, and positive power supply connected pdiff                                                                                                                                                                                                             | 16.75 µm  |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemptions:                                                                                                                                                                                                                                                                                           | 27 µm     |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 4. The ndiff and the pwell which it resides in are connected to the same signal pad                                                                                                                                                                                                                   | 40 µm     |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | f) nwell, metallically connected to signal pad, and positive power supply connected pdiff                                                                                                                                                                                                             |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemptions:                                                                                                                                                                                                                                                                                           |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | \***s8usbpdv2_20sbu_sw_ovp_ngate                                                                                                                                                                                                                                                                      |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | g) ndiff, metallically connected to signal pad, and positive power supply connected pwell                                                                                                                                                                                                             |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemptions:                                                                                                                                                                                                                                                                                           |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 5. The ndiff and the pwell which it resides in are connected to the same signal pad                                                                                                                                                                                                                   |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | h) nwell, metallically connected to signal pad, and positive power supply connected pwell                                                                                                                                                                                                             |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | i) pdiff, metallically connected to signal pad, and ndiff, metallically connected to a different signal pad                                                                                                                                                                                           |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | j) pdiff, metallically connected to signal pad, and nwell metallically connected to a different signal pad                                                                                                                                                                                            |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemptions:                                                                                                                                                                                                                                                                                           |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 6. The pdiff and the nwell which it resides in are connected to the same signal pad                                                                                                                                                                                                                   |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | k) pwell, metallically connected to signal pad, and ndiff metallically connected to a different signal pad                                                                                                                                                                                            |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemption:                                                                                                                                                                                                                                                                                            |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | If B2B cell s8fpafeg1_io_gnd2gnd_240x1_lv_dnwl_aup is used for input ESD protection, then revert to 27µm requirement.                                                                                                                                                                                 |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | l) pwell, metallically connected to signal pad, and nwell metallically connected to a different signal pad                                                                                                                                                                                            |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | m) ndiff, metallically connected to signal pad, and pdiff in an *At RISK Non_Vcc_nwell* (x.14a)                                                                                                                                                                                                       |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemptions:                                                                                                                                                                                                                                                                                           |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 7.  The ndiff and pdiff are metallically or resistively connected to the same net – default to the 27µm rule                                                                                                                                                                                          |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 8.  The *At RISK Non_Vcc_nwell* contains pdiff metallically or resistively connected to the signal pad connected ndiff                                                                                                                                                                                |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 9.  The ndiff and the pwell which it resides in are connected to the same signal pad                                                                                                                                                                                                                  |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 10. The *At RISK Non_Vcc_nwell* contains pdiff metallically or resistively connected to the *At RISK Non_Vcc_nwell*                                                                                                                                                                                   |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | n) ndiff, metallically connected to signal pad, and *At RISK Non_Vcc_nwell* (x.14a)                                                                                                                                                                                                                   |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemptions:                                                                                                                                                                                                                                                                                           |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 11. The *At RISK Non_Vcc_nwell* contains pdiff locally shorted to the *At RISK Non_Vcc_nwell* on die in metal through ≤ 1Ω                                                                                                                                                                            |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 12. The *At RISK Non_Vcc_nwell* contains pdiff metallically or resistively connected to the signal pad connected ndiff                                                                                                                                                                                |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 13. The ndiff and the pwell which it resides in are connected to the same signal pad                                                                                                                                                                                                                  |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 14. The *At RISK Non_Vcc_nwell* contains pdiff metallically or resistively connected to the *At RISK Non_Vcc_nwell*                                                                                                                                                                                   |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Note: Each pdiff must be checked independently. If any pdiff fails to meet the criteria in 1) or 2) then this spacing rule must be met                                                                                                                                                                |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | o) pdiff, metallically connected to signal pad, and nwell connected to 1.8V (LV) or lower                                                                                                                                                                                                             |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemptions:                                                                                                                                                                                                                                                                                           |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 15. atlas_top                                                                                                                                                                                                                                                                                         |           |                      |           |
|          | 16. fpg1_top                                                                                                                                                                                                                                                                                          |           |                      |           |
|          | 17. ccg2_top                                                                                                                                                                                                                                                                                          |           |                      |           |
|          | 18. ccg4_top                                                                                                                                                                                                                                                                                          |           |                      |           |
|          | 19. s8sarmux_top                                                                                                                                                                                                                                                                                      |           |                      |           |
|          | 20. s8usbfsm0s8_top                                                                                                                                                                                                                                                                                   |           |                      |           |
|          | 21. psoc4a_top                                                                                                                                                                                                                                                                                        |           |                      |           |
|          | 22. psoc4al_top                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 23. psoc4ads2_top                                                                                                                                                                                                                                                                                     |           |                      |           |
|          | 24. psoc4able_top                                                                                                                                                                                                                                                                                     |           |                      |           |
|          | 25. psoc4able256_top                                                                                                                                                                                                                                                                                  |           |                      |           |
|          | 26. psoc4able256dma_top                                                                                                                                                                                                                                                                               |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | p) pwell, metallically connected to signal pad, and nwell connected to 1.8V (LV) or lower                                                                                                                                                                                                             |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemptions:                                                                                                                                                                                                                                                                                           |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 27. s8fpafeg1_top                                                                                                                                                                                                                                                                                     |           |                      |           |
|          | 28. s8fpafeg1_io_rx_2x1                                                                                                                                                                                                                                                                               |           |                      |           |
|          | 29. s8tnvra_psoc3_osc32a_p3                                                                                                                                                                                                                                                                           |           |                      |           |
|          | 30. m0s8gen4_top                                                                                                                                                                                                                                                                                      |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Rule 12 Notes:                                                                                                                                                                                                                                                                                        |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 1) If nwell can be externally grounded (i.e. customer driven) then grounded nwell rules must be followed.                                                                                                                                                                                             |           |                      |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
| **13**   | Outer n-type guardrings around signal pad n-type injectors must not contain any PMOS device                                                                                                                                                                                                           |           | **DRC**              |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | i.e. PMOS is not allowed between the inner tap ring and the outer tap ring; PMOS is not allowed in the shared well of the outer ntap ring                                                                                                                                                             |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Exemption:                                                                                                                                                                                                                                                                                            |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 1) s8p3ana_upper_region_nopumps                                                                                                                                                                                                                                                                       |           |                      |           |
|          | 2) s8tkm0s8_mux_no0                                                                                                                                                                                                                                                                                   |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
| **14**   | Diffusion resistors are not allowed within guardrings around signal pad diffusions. Exception is when resistance of a source/drain is modeled as a diffusion resistor (i.e. diff.res is drawn over srcdrn region).                                                                                    |           | **DRC**              |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | i.e. Diff resistor is not allowed between the inner tap ring and the outer tap ring; Diff resistor is not allowed in the shared well of the outer ntap ring.                                                                                                                                          |           |                      |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+
| **15**   | Any circuitry within 100µm of any diff, or tap metallically connected to a signal pad must have its source and body shorted locally. (Shorted locally implies source/body connected at the FET in metal. No separate routes for source and body)                                                      |           | \____\_              | **LuRes** |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | LatchupRes measures the resistance between source/body of FETs identified in this rule.                                                                                                                                                                                                               |           |                      | \____\_   |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | To Run LatchupRes:                                                                                                                                                                                                                                                                                    |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | In the layout toolbar select Cypress – Physical Verification – Calibre DRC/CLDRC/Latchup/Soft/Stress/StreamNets/LVL… and select “LatchupRes”.                                                                                                                                                         |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | The LatchupRes results must be reviewed by the Design team and any anomalous high resistance values **(above 100 Ω**) corrected via layout. Initial and date here indicating completion of this activity.                                                                                             |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | The final results must be available and presented at the MTDR Layout Review.                                                                                                                                                                                                                          |           |                      |           |
|          |                                                                                                                                                                                                                                                                                                       |           |                      |           |
|          | Note: This is a chip level check; however, the block_level switch may be used to run this on an IP block for information only.                                                                                                                                                                        |           |                      |           |
+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+----------------------+-----------+

|latchup2|

**Figure 1 – Signal Pad Connected Diff Guard-ring Construction**

+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+----------------------+----------+
|        | .. rubric:: **Section 5: Latch-up Special Cases**                                                                                                                                                                                                                                                                                 |                         | **Design Signature** |          |
|        |    :name: section-5-latch-up-special-cases                                                                                                                                                                                                                                                                                        |                         |                      |          |
|        |    :class: ListParagraph                                                                                                                                                                                                                                                                                                          |                         |                      |          |
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+----------------------+----------+
|        |                                                                                                                                                                                                                                                                                                                                   | **Value**               | **Initials**         | **Date** |
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+----------------------+----------+
| **1**  | *At RISK Non_Vcc_nwell* (x.14a) must adhere to the rules in this section.                                                                                                                                                                                                                                                         | **DEF**                 |                      |          |
|        |                                                                                                                                                                                                                                                                                                                                   |                         |                      |          |
|        | Exemptions:                                                                                                                                                                                                                                                                                                                       |                         |                      |          |
|        |                                                                                                                                                                                                                                                                                                                                   |                         |                      |          |
|        | 1) If the pdiff and the Non_Vcc_nwell that contains it are locally shorted on die in metal through ≤ 1Ω                                                                                                                                                                                                                           |                         |                      |          |
|        | 2) If the *At RISK Non_Vcc_nwell* is > 50µm from a signal pad metallically connected ndiff or nwell                                                                                                                                                                                                                               |                         |                      |          |
|        | 3) Cells:                                                                                                                                                                                                                                                                                                                         |                         |                      |          |
|        |                                                                                                                                                                                                                                                                                                                                   |                         |                      |          |
|        | s8bbcnv_psoc5_top_18                                                                                                                                                                                                                                                                                                              |                         |                      |          |
|        |                                                                                                                                                                                                                                                                                                                                   |                         |                      |          |
|        | p3ag_p_sio                                                                                                                                                                                                                                                                                                                        |                         |                      |          |
|        |                                                                                                                                                                                                                                                                                                                                   |                         |                      |          |
|        | Any updates to this IP must be reviewed with the ESD/LU group                                                                                                                                                                                                                                                                     |                         |                      |          |
|        |                                                                                                                                                                                                                                                                                                                                   |                         |                      |          |
|        | Notes:                                                                                                                                                                                                                                                                                                                            |                         |                      |          |
|        |                                                                                                                                                                                                                                                                                                                                   |                         |                      |          |
|        | 1) For exemption, CAD flow checks for source/body locally shorted in metal. It is the Design Team’s responsibility to validate resistance measurement.                                                                                                                                                                            |                         |                      |          |
|        | 2) A flat file can be obtained from the CAD group to help identify Non_Vcc_nwells                                                                                                                                                                                                                                                 |                         |                      |          |
|        |                                                                                                                                                                                                                                                                                                                                   |                         |                      |          |
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+----------------------+----------+
| **1a** | This Nwell must be guardringed by a P+ tap inner ring connected to Vss and continuously strapped in li.                                                                                                                                                                                                                           |                         | **DRC**              |          |
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+----------------------+----------+
|        | Additionally, the guardring must be strapped in Met. The Met may be broken, but the total series resistance from any part of guardring w/o met to the portion of met strap connected to supply bus must be less than 125 Ω (connected through li).                                                                                |                         | \____\_              | \____\_  |
|        |                                                                                                                                                                                                                                                                                                                                   |                         |                      |          |
|        | Note: Guard Ring can be shared with other guard rings.                                                                                                                                                                                                                                                                            |                         |                      |          |
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+----------------------+----------+
| **1b** | This Nwell must further be guardringed by an N+ tap/Nwell outer ring connected to a positive external power supply and continuously strapped in li.                                                                                                                                                                               |                         | **DRC**              |          |
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+----------------------+----------+
|        | Additionally, the guardring must be strapped in Met. The Met may be broken, but the total series resistance from any part of guardring w/o met to the portion of met strap connected to supply bus must be less than 125 Ω (connected through li).                                                                                |                         | \____\_              | \____\_  |
|        |                                                                                                                                                                                                                                                                                                                                   |                         |                      |          |
|        | Note: Guard Ring can be shared with other guard rings.                                                                                                                                                                                                                                                                            |                         |                      |          |
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+----------------------+----------+
| **2**  | If inherent parasitic PNP bipolar transistor is used, surround the device or blocks of devices by an inner P+ tap guardring tied to Vss. Additionally, this structure must be guardringed by a N+ tap/Nwell outer guardring connected to a positive power supply. Both rings must be continuously strapped in li.                 |                         | **DRC**              |          |
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+----------------------+----------+
|        | Additionally, the guardrings must be strapped in Met. The Met may be broken, but the total series resistance from any part of guardring w/o met to the portion of met strap connected to supply bus must be less than 125 Ω (connected through li).                                                                               |                         | \____\_              | \____\_  |
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+----------------------+----------+
|        | Max space between licons for rules 1a, 1b and 2                                                                                                                                                                                                                                                                                   | 2 µm                    | **DRC**              |          |
|        |                                                                                                                                                                                                                                                                                                                                   |                         |                      |          |
|        | **Exemption**:                                                                                                                                                                                                                                                                                                                    |                         |                      |          |
|        |                                                                                                                                                                                                                                                                                                                                   |                         |                      |          |
|        | s8p3ana_top                                                                                                                                                                                                                                                                                                                       |                         |                      |          |
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+----------------------+----------+
| **5**  | For SEL immunity, all source and body connections must be shorted locally if the source and body are at the same DC potential. (Shorted locally implies source/body connected at the FET in metal - no separate routes for source and body). Any anomalous high resistance values (above 1000 Ω) need to be corrected via layout. | **LuRes**               |                      |          |
|        |                                                                                                                                                                                                                                                                                                                                   |                         |                      |          |
| **6**  | All not intended-to-use body bias circuitry source and body connections must be shorted locally. Initial and date here on completion of this activity.                                                                                                                                                                            | ----------- ----------- |                      |          |
|        |                                                                                                                                                                                                                                                                                                                                   |                         |                      |          |
| **7**  | Any At Risk Non-Vcc nwell which has P+ diffusion connected to a power supply 3.3V or higher should have its own P+ tap ring connected to ground and there should not be any N+ diffusion between the P+ diffusion in the At Risk Non-Vcc nwell and the P+ tap ring.                                                               | **DRC**                 |                      |          |
|        |                                                                                                                                                                                                                                                                                                                                   |                         |                      |          |
|        | Exemptions:                                                                                                                                                                                                                                                                                                                       | **DRC**                 |                      |          |
|        |                                                                                                                                                                                                                                                                                                                                   |                         |                      |          |
|        | s8p3iomacro_gpio_macro                                                                                                                                                                                                                                                                                                            |                         |                      |          |
|        | s8p3iomacro_gpio_macro_ao                                                                                                                                                                                                                                                                                                         |                         |                      |          |
|        | s8p3iomacro_sio_macro                                                                                                                                                                                                                                                                                                             |                         |                      |          |
|        |                                                                                                                                                                                                                                                                                                                                   |                         |                      |          |
|        | Grounded nwell requires a substrate tap ring around it metallically connected to the ground.                                                                                                                                                                                                                                      |                         |                      |          |
|        |                                                                                                                                                                                                                                                                                                                                   |                         |                      |          |
|        | Exemptions:                                                                                                                                                                                                                                                                                                                       |                         |                      |          |
|        |                                                                                                                                                                                                                                                                                                                                   |                         |                      |          |
|        | s8iom0s8_top_lvc_b2b_wopad                                                                                                                                                                                                                                                                                                        |                         |                      |          |
|        | s8iom0s8_top_lvclamp                                                                                                                                                                                                                                                                                                              |                         |                      |          |
|        | s8atlasana_esd_gnd2gnd_sub_dnwl                                                                                                                                                                                                                                                                                                   |                         |                      |          |
|        | s8fpafeg1_tk_lvc_b2b_wopad                                                                                                                                                                                                                                                                                                        |                         |                      |          |
|        |                                                                                                                                                                                                                                                                                                                                   |                         |                      |          |
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+----------------------+----------+

+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-----------------------+----------+
|         | .. rubric:: **Section 11: Miscellaneous Rules**                                                                                                                                                                                                                                                                                   |           | **Design Signature**  |          |
|         |    :name: section-11-miscellaneous-rules                                                                                                                                                                                                                                                                                          |           |                       |          |
|         |    :class: ListParagraph                                                                                                                                                                                                                                                                                                          |           |                       |          |
+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-----------------------+----------+
|         |                                                                                                                                                                                                                                                                                                                                   | **Value** | **Initials**          | **Date** |
+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-----------------------+----------+
| **1**   | **SoftConn Rules**                                                                                                                                                                                                                                                                                                                |           |                       |          |
+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-----------------------+----------+
| **1.1** | Nwell must be connected to Ntap at least once.                                                                                                                                                                                                                                                                                    |           | **DRC**               |          |
+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-----------------------+----------+
| **1.2** | Substrate containing diffusion must be connected to Ptap at least once                                                                                                                                                                                                                                                            |           | **DRC**               |          |
+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-----------------------+----------+
| **1.3** | Isolated Pwell must be connected to Ptap at least once.                                                                                                                                                                                                                                                                           |           | **DRC**               |          |
+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-----------------------+----------+
| **1.4** | Ptap net in isolated Pwell does not conflict with substrate majority connection.                                                                                                                                                                                                                                                  |           | **DRC**               |          |
+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-----------------------+----------+
| **2**   | Deleted                                                                                                                                                                                                                                                                                                                           |           |                       |          |
+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-----------------------+----------+
| **3**   | All top-level pads must be listed as a vcc, vss or io nets in the DRC/LU form. Note 1: Pads marked with “probe-only” text.dg label are exempt from this rule                                                                                                                                                                      |           | **DRC**               |          |
|         |                                                                                                                                                                                                                                                                                                                                   |           |                       |          |
|         | Note 2: pad.dg inside padvia does not apply to this check                                                                                                                                                                                                                                                                         |           |                       |          |
+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-----------------------+----------+
| **4**   | Minimum width of non-ESD PFET or NFET connected to separate bond pads                                                                                                                                                                                                                                                             | 2000 µm   | **DRC**               |          |
|         |                                                                                                                                                                                                                                                                                                                                   |           |                       |          |
| **5**   | (i.e. source = pad1 and drain = pad2)                                                                                                                                                                                                                                                                                             |           | **LuRes**             |          |
|         |                                                                                                                                                                                                                                                                                                                                   |           |                       |          |
| **6**   | Exemptions:                                                                                                                                                                                                                                                                                                                       |           | **\_____\_ \_____\_** |          |
|         |                                                                                                                                                                                                                                                                                                                                   |           |                       |          |
| **7**   | s8iom0s8/s8iom0s8_top_gpio                                                                                                                                                                                                                                                                                                        |           | **NDRC**              |          |
|         | s8iom0s8/s8iom0s8_top_xres                                                                                                                                                                                                                                                                                                        |           | **----- ------**      |          |
|         | s8iom0s8/s8iom0s8_top_power_hvc_wpad                                                                                                                                                                                                                                                                                              |           | **NDRC**              |          |
|         | s8iom0s8/s8iom0s8_top_ground_hvc_wpad                                                                                                                                                                                                                                                                                             |           | **----- -------**     |          |
|         | s8iom0s8/s8iom0s8_top_hvclamp_wopad                                                                                                                                                                                                                                                                                               |           |                       |          |
|         | s8iom0s8/s8iom0s8_top_power_lvc_wpad                                                                                                                                                                                                                                                                                              |           |                       |          |
|         | s8iom0s8/s8iom0s8_top_ground_lvc_wpad                                                                                                                                                                                                                                                                                             |           |                       |          |
|         | s8iom0s8/s8iom0s8_top_lvc_b2b_wopad                                                                                                                                                                                                                                                                                               |           |                       |          |
|         | s8iom0s8/s8iom0s8_top_lvclamp                                                                                                                                                                                                                                                                                                     |           |                       |          |
|         | s8iom0s8/s8iom0s8_analog_pad                                                                                                                                                                                                                                                                                                      |           |                       |          |
|         | s8iom0s8/s8iom0s8_top_xres_2                                                                                                                                                                                                                                                                                                      |           |                       |          |
|         | s8ctbm/ s8ctbm_NFET_con_diff_abt_260                                                                                                                                                                                                                                                                                              |           |                       |          |
|         | s8ctbm/s8ctbm_PFET_con_diff_abt_520                                                                                                                                                                                                                                                                                               |           |                       |          |
|         | s8usbpd_sbu_sw_top                                                                                                                                                                                                                                                                                                                |           |                       |          |
|         |                                                                                                                                                                                                                                                                                                                                   |           |                       |          |
|         | For SEL immunity, all source and body connections must be shorted locally if the source and body are at the same DC potential. (Shorted locally implies source/body connected at the FET in metal - no separate routes for source and body). Any anomalous high resistance values (above 1000 Ω) need to be corrected via layout. |           |                       |          |
|         |                                                                                                                                                                                                                                                                                                                                   |           |                       |          |
|         | All not intended-to-use body bias circuitry source and body connections must be shorted locally. Initial and date here on completion of this activity.                                                                                                                                                                            |           |                       |          |
|         |                                                                                                                                                                                                                                                                                                                                   |           |                       |          |
|         | Any IP with no substrate tap (compliant to substrate isolation methodology) needs to have areaid.inj layer and placed at least 100µm away from signal pad connected diffusion                                                                                                                                                     |           |                       |          |
|         |                                                                                                                                                                                                                                                                                                                                   |           |                       |          |
|         | Any row of I/O’s need to end with a power pad or with an end cap cell which consists of a substrate tap and NW guard bars                                                                                                                                                                                                         |           |                       |          |
+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+-----------------------+----------+

+-----------+------------------------------------------------------------------------------------------------------+-----------------+----------------------+----------+
|           | .. rubric:: **Section 12: Areaid Rules**                                                             |                 | **Design Signature** |          |
|           |    :name: section-12-areaid-rules                                                                    |                 |                      |          |
|           |    :class: ListParagraph                                                                             |                 |                      |          |
+-----------+------------------------------------------------------------------------------------------------------+-----------------+----------------------+----------+
|           |                                                                                                      | **Value**       | **Initials**         | **Date** |
+-----------+------------------------------------------------------------------------------------------------------+-----------------+----------------------+----------+
| **12**    | **Areaid Rules**                                                                                     |                 |                      |          |
+-----------+------------------------------------------------------------------------------------------------------+-----------------+----------------------+----------+
| **12.1a** | areaid.sigPadDiff cannot straddle nsrcdrn, psrcdrn, N+tap, or P+tap                                  |                 | **DRC**              |          |
+-----------+------------------------------------------------------------------------------------------------------+-----------------+----------------------+----------+
| **12.1b** | areaid.sigPadWell cannot straddle nwell                                                              |                 | **DRC**              |          |
+-----------+------------------------------------------------------------------------------------------------------+-----------------+----------------------+----------+
| **12.1c** | areaid.sigPadMetNtr cannot straddle nwell, nsrcdrn, psrcdrn, N+tap, or P+tap                         |                 | **DRC**              |          |
+-----------+------------------------------------------------------------------------------------------------------+-----------------+----------------------+----------+
| **12.2a** | nsrcdrn, psrcdrn, N+tap, or P+tap connected to a signal pad (ioNet), is not inside areaid.sigPadDiff | **Recommended** | **DRC**              |          |
+-----------+------------------------------------------------------------------------------------------------------+-----------------+----------------------+----------+
| **12.2b** | Nwell connected to signal pad (ioNet), is not inside areaid.sigPadWell                               | **Recommended** | **DRC**              |          |
+-----------+------------------------------------------------------------------------------------------------------+-----------------+----------------------+----------+

+-------+-----------------------------------------------------------------------------------------------------------------------------------+-----------+-----------------------+----------+
|       | .. rubric:: **Section 13: Super High Voltage (SHV) Rules**                                                                        |           | **Design Signature**  |          |
|       |    :name: section-13-super-high-voltage-shv-rules                                                                                 |           |                       |          |
|       |    :class: ListParagraph                                                                                                          |           |                       |          |
+-------+-----------------------------------------------------------------------------------------------------------------------------------+-----------+-----------------------+----------+
|       |                                                                                                                                   | **Value** | **Initials**          | **Date** |
+-------+-----------------------------------------------------------------------------------------------------------------------------------+-----------+-----------------------+----------+
| **1** | DNW connected to ground <1000Ω is not allowed if the DNW contains SHV connected active NFETs or PFETs                             |           | **DRC**               |          |
|       |                                                                                                                                   |           |                       |          |
|       | Note: Only resistors labeled with text.dg as ‘1KOhm’ will break the connectivity between ground and deep nwell                    |           |                       |          |
+-------+-----------------------------------------------------------------------------------------------------------------------------------+-----------+-----------------------+----------+
| **2** | Minimum distance between NW/DNW connected metallically to SHV signal pad to a P+ diff/tap/PW connected to a positive power supply | 70 µm     | **DRC**               |          |
|       |                                                                                                                                   |           |                       |          |
|       | Note: Fill any intervening space with DNW connected to SHV pad and ptap tied to ground with substrate tap and NW tap collectors   |           | **NDRC**              |          |
|       |                                                                                                                                   |           |                       |          |
|       |                                                                                                                                   |           | **\_____\_ \_____\_** |          |
+-------+-----------------------------------------------------------------------------------------------------------------------------------+-----------+-----------------------+----------+
| **3** | Minimum distance between PW connected metallically to SHV signal pad to any N+ diff/tap/NW/DNW connected to a ground              | 100 µm    | **DRC**               |          |
|       |                                                                                                                                   |           |                       |          |
|       | If ntype and its associated ptap are connected to the same ground in metal within 5 Ω (resistance not checked by DRC)             | 150 µm    |                       |          |
|       |                                                                                                                                   |           |                       |          |
|       | If ntype and its associated ptap are **not** connected to the same ground in metal within 5 Ω (resistance not checked by DRC)     |           |                       |          |
+-------+-----------------------------------------------------------------------------------------------------------------------------------+-----------+-----------------------+----------+
| 4     | Minimum distance between SHV ESD clamp to any diff/tap/well metallically connected to signal pad                                  | 70 µm     | **DRC**               |          |
|       |                                                                                                                                   |           |                       |          |
|       | Note: SHV ESD clamps are listed in the Appendix A                                                                                 |           |                       |          |
+-------+-----------------------------------------------------------------------------------------------------------------------------------+-----------+-----------------------+----------+

APPENDIX A – LU DRC Form Description

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APPENDIX B1 – CAD Automation Algorithm Index

TO BE FILLED BY CAD.

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