diff --git a/.gitignore b/.gitignore
index b2dedd9..72dd68d 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,2 +1,4 @@
 _build
 env
+.DS_Store
+.vscode
diff --git a/docs/notes.rst b/docs/notes.rst
index fec9807..173e105 100644
--- a/docs/notes.rst
+++ b/docs/notes.rst
@@ -350,13 +350,13 @@
 +---------+----------------+------------------------------------------------------------------+
 | 1139    | Cadence Models | Remove ELDO models (and correct name from HSPICE)                |
 +---------+----------------+------------------------------------------------------------------+
-| 970     | Documentation  | Create SKY130 PDK User's Guide                                       |
+| 970     | Documentation  | Create SKY130 PDK User's Guide                                   |
 +---------+----------------+------------------------------------------------------------------+
 | 1148    | Documentation  | Document FET sa/sb/sd                                            |
 +---------+----------------+------------------------------------------------------------------+
-| 1061    | LVS            | SKY130 xRC enablement                                                |
+| 1061    | LVS            | SKY130 xRC enablement                                            |
 +---------+----------------+------------------------------------------------------------------+
-| 1152    | LVS            | Combine Calibre LVS and xRC decks for SKY130                         |
+| 1152    | LVS            | Combine Calibre LVS and xRC decks for SKY130                     |
 +---------+----------------+------------------------------------------------------------------+
 
 .. _virtuoso-library-3:
@@ -460,7 +460,7 @@
 +---------+---------------+---------------------------------------------------------------------------+
 | 1051    | Cadence       | Fix techfile warnings in LayoutXL                                         |
 +---------+---------------+---------------------------------------------------------------------------+
-| 969     | Document      | Create SKY130 Release Notes                                                   |
+| 969     | Document      | Create SKY130 Release Notes                                               |
 +---------+---------------+---------------------------------------------------------------------------+
 | 940     | DRC           | Create DRC runset + documentation                                         |
 +---------+---------------+---------------------------------------------------------------------------+
@@ -468,7 +468,7 @@
 +---------+---------------+---------------------------------------------------------------------------+
 | 1058    | LVS           | Digital cell: complete LVS                                                |
 +---------+---------------+---------------------------------------------------------------------------+
-| 1061    | LVS           | SKY130 xRC enablement                                                         |
+| 1061    | LVS           | SKY130 xRC enablement                                                     |
 +---------+---------------+---------------------------------------------------------------------------+
 | 800     | PDK Build     | Update PDK build scripts to separate PDK and IP                           |
 +---------+---------------+---------------------------------------------------------------------------+
@@ -478,7 +478,7 @@
 +---------+---------------+---------------------------------------------------------------------------+
 | 874     | PDK Qual      | Model qualification: migrate C9 resistor testbench                        |
 +---------+---------------+---------------------------------------------------------------------------+
-| 1062    | PDK Qual      | SKY130 BJT simulations                                                        |
+| 1062    | PDK Qual      | SKY130 BJT simulations                                                    |
 +---------+---------------+---------------------------------------------------------------------------+
 
 .. _virtuoso-library-4:
diff --git a/docs/release_notes/libraries/sky130_fd_sc_hdll/V0.1.0/release_notes.rst b/docs/release_notes/libraries/sky130_fd_sc_hdll/V0.1.0/release_notes.rst
index 4db449f..e132faa 100644
--- a/docs/release_notes/libraries/sky130_fd_sc_hdll/V0.1.0/release_notes.rst
+++ b/docs/release_notes/libraries/sky130_fd_sc_hdll/V0.1.0/release_notes.rst
@@ -1,21 +1,13 @@
 |logo|
 
 SCS8HDLL Release Notes
+=======================
 Revision 0.1.2
+-----------------------
 December 27, 2019
+-----------------------
 
 
-Table of Contents
-=================
-
-
-Table of Figures
-================
-
-
-Table of Tables
-===============
-
 
 Revision History
 ================
@@ -179,232 +171,7 @@
 
 The following is a list of known issues with the V0.1.0 IP:
 
-Overview
-========
-
-The SkyWater SCS8HDLL Release Notes contain information regarding the high density low leakage standard cells available from SkyWater for this technology and its known limitations.
-
-IP Usage
-========
-
-The SCS8HDLL IP contains a variation of high density standard cells with lower leakage power than SCS8HD.
-
-The scs8_hdll library contains two OA libraries, including a techLib reference library. The only library the designer will need to use for the high density low leakage standard cells is scs8hdll. The remaining libraries are necessary as references to this one only.
-
-A list of high density standard cells is not available in V0.1.0. For additional information, please contact SkyWater Technology.
-
-Digital PDK
-===========
-
-1. .. rubric:: Synthesis
-      :name: synthesis
-
-   1. .. rubric:: Requirements
-         :name: requirements
-
--  Liberty file: $SW_PDK_ROOT/s8_ip/scs8hdll/lib/scs8hdll_ss_1.60v_100C.lib
-
--  Tech lef: $SW_PDK_ROOT/s8_ip/tech/lef/s8phirs-10r.tlef
-
--  Standard Cell LEF: $SW_PDK_ROOT/s8_ip/scs8hdll/scs8hdll.lef
-
-   2. .. rubric:: Execution
-         :name: execution
-
-The simple “sv_interfaces” design example was used as the RTL base. Genus synthesized a netlist. The netlist was visually inspected to see what types of standard-cells were included; netlist included DFF, NAND, XNOR, etc.  No effort was spent analyzing performance, power, or area (PPA) nor whether the SDC was consumed correctly.  Intent was just to verify that a structured netlist was generated.  Numerous reports were generated during the synthesis process (area, gates, check_design, etc).  A quick inspection of the report files was done just to see that no gross errors were present due to input-file consumption.
-
-2. .. rubric:: Simulation
-      :name: simulation
-
-   3. .. rubric:: Requirements
-         :name: requirements-1
-
--  Standard Cell Verilog Models: $SW_PDK_ROOT/s8_ip/scs8hdll/verilog/*.v
-
-   4. .. rubric:: Execution
-         :name: execution-1
-
-The simulation was run with both the RTL and the netlist instantiated in the testbench side-by-side.  Visual inspection of the waveforms of the two modules revealed that they appeared the same.  Whereas the netlist is consumed as gates by the simulator, no effort for SDF-annotated simulation was expended.
-
-Place and Route
----------------
-
-.. _requirements-2:
-
-Requirements
-~~~~~~~~~~~~
-
--  Liberty files: $SW_PDK_ROOT/s8_ip/scs8hdll/lib/*.lib
-
--  Tech lef: $SW_PDK_ROOT/s8_ip/tech/s8phirs-10r.tlef
-
--  Standard Cell LEF: $SW_PDK_ROOT/s8_ip/scs8hdll/lef/scs8hdll.lef
-
--  Standard Cell GDS: $SW_PDK_ROOT/s8_ip/scs8hdll/gds/scs8hdll.gds
-
--  GDS Layer Map: $SW_PDK_ROOT/s8_ip/tech/s8_innovus.layermap
-
--  Metal Fill Rules: Next Release
-
-   6. .. rubric:: Execution
-         :name: execution-2
-
-The synthesized netlist was read into Innovus. The following steps were performed:
-
--  Floorplanning
-
--  Power Routing
-
--  Global Routing and Initial Timing
-
--  Clock Tree Insertion
-
--  Detail Routing
-
--  Metal Fill Insertion
-
--  Timing Analysis
-
--  DRC and LVS Verification
-
-   7. .. rubric:: Innovus Addenda
-         :name: innovus-addenda
-
--  To add tap cells at the ends of every row:
-
-   -  *source $SW_PDK_ROOT/s8_ip/scs8hd/scripts/add_tap.tcl*
-
--  To stream out gds:
-
-   -  *write_stream <gds file> -map_file $SW_PDK_ROOT/s8_ip/tech/s8_innovus.layermap -lib_name DesignLib -unit 1000 -mode ALL -merge $SW_PDK_ROOT/s8_ip/scs8hdll/gds/scs8hdll.gds*
-
--  To write out a netlist for Calibre LVS:
-
-   -  *write_netlist <netlist for lvs> -phys -exclude_leaf_cells*
-
--  To create a pin text file for Calibre LVS:
-
-   -  *source $SW_PDK_ROOT/s8/scs8hdll/scripts/lvstext.tcl*
-
-Future Plans
-~~~~~~~~~~~~
-
-Support is planned for a future release for the following items:
-
--  Cadence Voltus power integrity tools
-
--  Innovus OA-based flow: the current flow is LEF-based.
-
--  Memories: in development.
-
--  *
-   *
-
-DRC
----
-
-.. _requirements-3:
-
-Requirements
-~~~~~~~~~~~~
-
--  Calibre Rundecks: $SW_PDK_ROOT/s8/DRC/Calibre/*Rules\*
-
-**Calibre** DRC Rundecks
-~~~~~~~~~~~~~~~~~~~~~~~~
-
-Five Calibre rundecks are available:
-
-1. drcRules: General DRC rundeck
-
-2. softRules: ERC rundeck
-
-3. stressRules: Sealring checks
-
-4. latchupRules: Latch-up and antenna checks
-
-5. fillRules: Metal fill rundeck is being developed
-
-A clean run for the top 4 rundecks is required for every design.
-
-The metal fill deck is for timing purposes and can be loaded into Quantus; the final metal fill will be added at tapeout.
-
-There is an additional rundeck called cldrcRules.
-
-This rundeck converts all layers to a version ready for tapeout. It also adds in the final metal fill. This rundeck will usually be used at the Foundry only as part of final tapeout process.
-
-.. _execution-3:
-
-**Execution**
-~~~~~~~~~~~~~
-
-Calibre DRC can be run from within Calibre DESIGNRev:
-
-1. Load the GDS written out from Innovus.
-
-2. Launch “Verification -> Run nmDRC”.
-
-3. At “Rules -> DRC Rules File” enter “$PDK_HOME/DRC/Calibre/<rundeck_name>”.
-
-4. At “Rules -> DRC Run Directory” enter the local directory name with the title of the rundeck, i.e. “<local path>/drc” or “<local path>/stress”.
-
-5. At “Inputs” press “Export from layout viewer”.
-
-6. Click “Run DRC”.
-
-LVS
----
-
-.. _requirements-4:
-
-Requirements
-~~~~~~~~~~~~
-
--  Calibre Rundeck: $SW_PDK_ROOT/s8/LVS/Calibre/lvsRules
-
-**Generate** Spice Netlist
-~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-One of the Innovus Addenda (shown above) explained how to write out a netlist for Calibre LVS. Below are the steps needed to convert this netlist to spice.
-
-1. FILLER cells must be removed from the verilog. This awk script can be used:
-
-   *awk -f $SW_PDK_ROOT/s8_ip/scs8hdll/scripts/remove_FILLERS.k <netlist with fillers> > <netlist without fillers>*
-
-2. The netlist can next be converted to spice with this script:
-
-   *v2lvs -v <verilog without fillers> -lsp $SW_PDK_ROOT/s8_ip/scs8hdll/cdl/scs8hdll.cdl -s $SW_PDK_ROOT/s8_ip/scs8hdll/cdl/scs8hdll.cdl -o <spice for LVS>*
-
-.. _execution-4:
-
-Execution
-~~~~~~~~~
-
-Calibre LVS can be run from within Calibre DESIGNRev:
-
-1. Load the GDS that was written out from Innovus.
-
-2. Launch “Verification -> Run nmLVS”.
-
-3. At “Rules -> LVS Rules File” enter “$PDK_HOME/DRC/Calibre/lvsRules”.
-
-4. At “Rules -> LVS Run Directory” enter “<local path>/lvs”.
-
-5. At “Inputs” in the “Layout” tab:
-
-   a. Press “Export from layout viewer”.
-
-   b. Enter the “Top Cell” name.
-
-6. At “Inputs” in the “Netlist” tab enter the “Spice Files:” with the spice for LVS that was created above.
-
-7. At “Input” in the “H-Cells” tab press “Use H-Cells file” and enter “$SW_PDK_ROOT/s8_ip/scs8hdll/cdl/scs8hdll.hcell”
-
-8. At the top press “Setup -> LVS Options”.
-
-9. At “LVS Options” in the “Include” tab in the top white space enter the path to the pin text file that was created in the Innovus Addenda.
 
-Click “Run LVS”.
 
 .. |logo| image:: ./media/image1.png
    :width: 3.5in
diff --git a/docs/release_notes/libraries/sky130_fd_sc_hs/V0.0.0/release_notes.rst b/docs/release_notes/libraries/sky130_fd_sc_hs/V0.0.0/release_notes.rst
index 3ee74cc..32acc37 100644
--- a/docs/release_notes/libraries/sky130_fd_sc_hs/V0.0.0/release_notes.rst
+++ b/docs/release_notes/libraries/sky130_fd_sc_hs/V0.0.0/release_notes.rst
@@ -1,20 +1,11 @@
 |logo|
 
 SCS8HS Release Notes
+=======================
 Revision 0.0.2
+-----------------------
 December 27, 2019
-
-
-Table of Contents
-=================
-
-
-Table of Figures
-================
-
-
-Table of Tables
-===============
+-----------------------
 
 
 Revision History
@@ -177,230 +168,7 @@
 
 There are no known issues with the V0.0.0 HS standard cell IP.
 
-Overview
-========
-
-The SkyWater SCS8HS Release Notes contain information regarding the high speed standard cells available from SkyWater for this technology and its known limitations.
-
-IP Usage
-========
-
-The SCS8HS IP contains a variation of standard cells that utilize low voltage high speed logic blocks in the SKY130 technology.
-
-The scs8_hs library contains two OA libraries, including a techLib reference library. The only library the designer will need to use for the high speed standard cells is scs8hs. The remaining libraries are necessary as references to this one only.
-
-A list of high speed standard cells is not available in V0.0.0. For additional information, please contact SkyWater Technology Foundry.
-
-Digital PDK
-===========
-
-1. .. rubric:: Synthesis
-      :name: synthesis
-
-   1. .. rubric:: Requirements
-         :name: requirements
-
--  Liberty file: $SW_IP_HOME/scs8hs/lib/ scs8hs_ss_1.60v_100C.lib
-
--  Tech lef: $SW_IP_HOME/tech/lef/s8phirs-10r.tlef
-
--  Standard Cell LEF: $SW_IP_HOME/scs8hs/lef/scs8hs.lef
-
-   2. .. rubric:: Execution
-         :name: execution
-
-The simple “sv_interfaces” design example was used as the RTL base. Genus synthesized a netlist. The netlist was visually inspected to see what types of standard-cells were included; netlist included DFF, NAND, XNOR, etc.  No effort was spent analyzing performance, power, or area (PPA) nor whether the SDC was consumed correctly.  Intent was just to verify that a structured netlist was generated.  Numerous reports were generated during the synthesis process (area, gates, check_design, etc).  A quick inspection of the report files was done just to see that no gross errors were present due to input-file consumption.
-
-2. .. rubric:: Simulation
-      :name: simulation
-
-   3. .. rubric:: Requirements
-         :name: requirements-1
-
--  Standard Cell Verilog Models: $SW_IP_HOME/scs8hs/verilog/*.v
-
-   4. .. rubric:: Execution
-         :name: execution-1
-
-The simulation was run with both the RTL and the netlist instantiated in the testbench side-by-side.  Visual inspection of the waveforms of the two modules revealed that they appeared the same.  Whereas the netlist is consumed as gates by the simulator, no effort for SDF-annotated simulation was expended.
-
-Place and Route
----------------
-
-.. _requirements-2:
-
-Requirements
-~~~~~~~~~~~~
-
--  Liberty files: $SW_IP_HOME/scs8hs/lib/*.lib
-
--  Tech lef: $SW_IP_HOME/tech/lef/s8phirs-10r.tlef
-
--  Standard Cell LEF: $SW_IP_HOME/scs8hs/lef/scs8hs.lef
-
--  Standard Cell GDS: $SW_IP_HOME/scs8hs/gds/scs8hs.gds
-
--  GDS Layer Map: $SW_IP_HOME/scs8hs/tech/s8_innovus.layermap
-
--  Metal Fill Rules: Next Release
-
-   6. .. rubric:: Execution
-         :name: execution-2
-
-The synthesized netlist was read into Innovus. The following steps were performed:
-
--  Floorplanning
-
--  Power Routing
-
--  Global Routing and Initial Timing
-
--  Clock Tree Insertion
-
--  Detail Routing
-
--  Metal Fill Insertion
-
--  Timing Analysis
-
--  DRC and LVS Verification
-
-   7. .. rubric:: Innovus Addenda
-         :name: innovus-addenda
-
--  This tcl can be used to add tap cells:
-
-   -  *source $SW_IP_HOME/s8/scs8hs/scripts/add_taps.tcl*
-
--  This tcl can be used to stream out gds:
-
-   -  *write_stream <gds file> -map_file $SW_IP_HOME/tech/s8_innovus.layermap -lib_name DesignLib -unit 1000 -mode ALL -merge $SW_IP_HOME/scs8hs/gds/scs8hs.gds*
-
--  To write out a netlist for Calibre LVS:
-
-   -  *write_netlist <netlist for lvs> -phys -exclude_leaf_cells*
-
--  To create a pin text file for Calibre LVS:
-
-   -  *source $SW_IP_HOME/s8/scs8hs/scripts/lvstext.tcl*
-
-Future Plans
-~~~~~~~~~~~~
-
-Support is planned for a future release for the following items:
-
--  Cadence Voltus power integrity tools
-
--  Innovus OA-based flow: the current flow is LEF-based.
-
--  *
-   *
-
-DRC
----
-
-.. _requirements-3:
-
-Requirements
-~~~~~~~~~~~~
-
--  Calibre Rundecks: $SW_IP_HOME/s8/DRC/Calibre/*Rules\*
-
-**Calibre** DRC Rundecks
-~~~~~~~~~~~~~~~~~~~~~~~~
-
-Five Calibre rundecks are available:
-
-1. drcRules: General DRC rundeck
-
-2. softRules: ERC rundeck
-
-3. stressRules: Sealring checks
-
-4. latchupRules: Latch-up and antenna checks
-
-5. fillRules: Metal fill rundeck is being developed
-
-A clean run for the top 4 rundecks is required for every design.
-
-The metal fill deck is for timing purposes and can be loaded into Quantus; the final metal fill will be added at tapeout.
-
-There is an additional rundeck called cldrcRules.
-
-This rundeck converts all layers to a version ready for tapeout. It also adds in the final metal fill. This rundeck will usually be used at the Foundry only.
-
-.. _execution-3:
-
-**Execution**
-~~~~~~~~~~~~~
-
-Calibre DRC can be run from within Calibre DESIGNRev:
-
-1. Load the GDS written out from Innovus.
-
-2. Launch “Verification -> Run nmDRC”.
-
-3. At “Rules -> DRC Rules File” enter “$PDK_HOME/DRC/Calibre/<rundeck_name>”.
-
-4. At “Rules -> DRC Run Directory” enter the local directory name with the title of the rundeck, i.e. “<local path>/drc” or “<local path>/stress”.
-
-5. At “Inputs” press “Export from layout viewer”.
-
-6. Click “Run DRC”.
-
-LVS
----
-
-.. _requirements-4:
-
-Requirements
-~~~~~~~~~~~~
-
--  Calibre Rundeck: $SW_IP_HOME/s8/LVS/Calibre/lvsRules
-
-**Generate** Spice Netlist
-~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-One of the Innovus Addenda (shown above) explained how to write out a netlist for Calibre LVS. Below are the steps needed to convert this netlist to spice.
-
-1. FILLER cells must be removed from the verilog. This awk script can be used:
-
-   *awk -f $SW_IP_HOME/scs8hs/scripts/remove_FILLERS.k <netlist with fillers> > <netlist without fillers>*
-
-2. The netlist can next be converted to spice with this script:
-
-   *v2lvs -v <verilog without fillers> -lsp $SW_IP_HOME/scs8hs/cdl/scs8hs.cdl -s $SW_IP_HOME/scs8hs/cdl/scs8hs.cdl -o <spice for LVS>*
-
-.. _execution-4:
-
-Execution
-~~~~~~~~~
-
-Calibre LVS can be run from within Calibre DESIGNRev:
-
-1. Load the GDS that was written out from Innovus.
-
-2. Launch “Verification -> Run nmLVS”.
-
-3. At “Rules -> LVS Rules File” enter “$PDK_HOME/DRC/Calibre/lvsRules”.
-
-4. At “Rules -> LVS Run Directory” enter “<local path>/lvs”.
-
-5. At “Inputs” in the “Layout” tab:
-
-   a. Press “Export from layout viewer”.
-
-   b. Enter the “Top Cell” name.
-
-6. At “Inputs” in the “Netlist” tab enter the “Spice Files:” with the spice for LVS that was created above.
-
-7. At “Input” in the “H-Cells” tab press “Use H-Cells file” and enter “$SW_IP_HOME/scs8hs/cdl/scs8hs.hcell”
-
-8. At the top press “Setup -> LVS Options”.
-
-9. At “LVS Options” in the “Include” tab in the top white space enter the path to the pin text file that was created in the Innovus Addenda.
 
-Click “Run LVS”.
 
 .. |logo| image:: ./media/image1.png
    :width: 3.5in
diff --git a/docs/release_notes/libraries/sky130_fd_sc_hvl/V0.0.1/release_notes.rst b/docs/release_notes/libraries/sky130_fd_sc_hvl/V0.0.1/release_notes.rst
index 70dac59..8c4016d 100644
--- a/docs/release_notes/libraries/sky130_fd_sc_hvl/V0.0.1/release_notes.rst
+++ b/docs/release_notes/libraries/sky130_fd_sc_hvl/V0.0.1/release_notes.rst
@@ -1,20 +1,11 @@
 |logo|
 
 SCS8HVL Release Notes
+=======================
 Revision 0.0.2
+-----------------------
 December 27, 2019
-
-
-Table of Contents
-=================
-
-
-List of Figures
-===============
-
-
-List of Tables
-==============
+-----------------------
 
 
 Revision History
diff --git a/docs/release_notes/libraries/sky130_fd_sc_lp/V0.0.0/release_notes.rst b/docs/release_notes/libraries/sky130_fd_sc_lp/V0.0.0/release_notes.rst
index 5f7f34c..adbe7d7 100644
--- a/docs/release_notes/libraries/sky130_fd_sc_lp/V0.0.0/release_notes.rst
+++ b/docs/release_notes/libraries/sky130_fd_sc_lp/V0.0.0/release_notes.rst
@@ -1,18 +1,11 @@
 |logo|
 
 SCS8LP Release Notes
+=======================
 Revision 0.0.2
+-----------------------
 December 27, 2019
-
-
-Table of Contents
-=================
-
-Table of Figures
-================
-
-Table of Tables
-===============
+-----------------------
 
 Revision History
 ================
@@ -170,223 +163,7 @@
 
 There are no known issues with the V0.0.0 LP standard cell IP.
 
-Overview
-========
-
-The SkyWater SCS8LP Release Notes contain information regarding the low power standard cells available from SkyWater for this technology and its known limitations.
-
-Digital PDK
-===========
-
-1. .. rubric:: Synthesis
-      :name: synthesis
-
-   1. .. rubric:: Requirements
-         :name: requirements
-
--  Liberty file: $SW_IP_HOME/scs8lp/lib/scs8lp_ss_1.60v_100C.lib
-
--  Tech lef: $SW_IP_HOME/tech/lef/s8phirs-10r.tlef
-
--  Standard Cell LEF: $SW_IP_HOME/scs8lp/scs8lp.lef
-
-   2. .. rubric:: Execution
-         :name: execution
-
-The simple “sv_interfaces” design example was used as the RTL base. Genus synthesized a netlist. The netlist was visually inspected to see what types of standard-cells were included; netlist included DFF, NAND, XNOR, etc.  No effort was spent analyzing performance, power, or area (PPA) nor whether the SDC was consumed correctly.  Intent was just to verify that a structured netlist was generated.  Numerous reports were generated during the synthesis process (area, gates, check_design, etc).  A quick inspection of the report files was done just to see that no gross errors were present due to input-file consumption.
-
-Simulation
-----------
-
-.. _requirements-1:
-
-Requirements
-~~~~~~~~~~~~
-
--  Standard Cell Verilog Models: $SW_IP_HOME/scs8lp/verilog/*.v
-
-   3. .. rubric:: Execution
-         :name: execution-1
-
-The simulation was run with both the RTL and the netlist instantiated in the testbench side-by-side.  Visual inspection of the waveforms of the two modules revealed that they appeared the same.  Whereas the netlist is consumed as gates by the simulator, no effort for SDF-annotated simulation was expended.
-
-Place and Route
----------------
-
-.. _requirements-2:
-
-Requirements
-~~~~~~~~~~~~
-
--  Liberty files: $SW_IP_HOME/scs8lp/lib/*.lib
-
--  Tech lef: $SW_IP_HOME/tech/lef/s8phirs-10r.tlef
-
--  Standard Cell LEF: $SW_IP_HOME/scs8lp/lef/scs8lp.lef
-
--  Standard Cell GDS: $SW_IP_HOME/scs8lp/gds/scs8lp.gds
-
--  GDS Layer Map: $SW_IP_HOME/scs8lp/tech/s8_innovus.layermap
-
--  Metal Fill Rules: Next Release
-
-   5. .. rubric:: Execution
-         :name: execution-2
-
-The synthesized netlist was read into Innovus. The following steps were performed:
-
--  Floorplanning
-
--  Power Routing
-
--  Global Routing and Initial Timing
-
--  Clock Tree Insertion
-
--  Detail Routing
-
--  Metal Fill Insertion
-
--  Timing Analysis
-
--  DRC and LVS Verification
-
-   6. .. rubric:: Innovus Addenda
-         :name: innovus-addenda
-
--  This tcl can be used to add tap cells:
-
-   -  *source $PDK_HOME/scs8lp/scripts/add_taps.tcl*
-
--  This tcl can be used to stream out gds:
-
-   -  *write_stream <gds file> -map_file $SW_IP_HOME/tech/s8_innovus.layermap -lib_name DesignLib -unit 1000 -mode ALL -merge $SW_IP_HOME/scs8lp/gds/scs8lp.gds*
-
--  To write out a netlist for Calibre LVS:
-
-   -  *write_netlist <netlist for lvs> -phys -exclude_leaf_cells*
-
--  To create a pin text file for Calibre LVS:
-
-   -  *source $PDK_HOME/scs8lp/scripts/lvstext.tcl*
-
-Future Plans
-~~~~~~~~~~~~
-
-Support is planned for a future release for the following items:
-
--  Cadence Voltus power integrity tools
-
--  Innovus OA-based flow: the current flow is LEF-based.
-
--  *
-   *
-
-DRC
----
-
-.. _requirements-3:
-
-Requirements
-~~~~~~~~~~~~
-
--  Calibre Rundecks: $PDK_HOME/DRC/Calibre/*Rules\*
-
-**Calibre** DRC Rundecks
-~~~~~~~~~~~~~~~~~~~~~~~~
-
-Five Calibre rundecks are available:
-
-1. drcRules: General DRC rundeck
-
-2. softRules: ERC rundeck
-
-3. stressRules: Sealring checks
-
-4. latchupRules: Latch-up and antenna checks
-
-5. fillRules: Metal fill rundeck is being developed
-
-A clean run for the top 4 rundecks is required for every design.
-
-The metal fill deck is for timing purposes and can be loaded into Quantus; the final metal fill will be added at tapeout.
-
-There is an additional rundeck called cldrcRules.
-
-This rundeck converts all layers to a version ready for tapeout. It also adds in the final metal fill. This rundeck will usually be used at the Foundry only as part of final tapeout process.
-
-.. _execution-3:
-
-**Execution**
-~~~~~~~~~~~~~
-
-Calibre DRC can be run from within Calibre DESIGNRev:
-
-1. Load the GDS written out from Innovus.
-
-2. Launch “Verification -> Run nmDRC”.
-
-3. At “Rules -> DRC Rules File” enter “$PDK_HOME/DRC/Calibre/<rundeck_name>”.
-
-4. At “Rules -> DRC Run Directory” enter the local directory name with the title of the rundeck, i.e. “<local path>/drc” or “<local path>/stress”.
-
-5. At “Inputs” press “Export from layout viewer”.
-
-6. Click “Run DRC”.
-
-LVS
----
-
-.. _requirements-4:
-
-Requirements
-~~~~~~~~~~~~
-
--  Calibre Rundeck: $PDK_HOME/LVS/Calibre/lvsRules
-
-**Generate** Spice Netlist
-~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-One of the Innovus Addenda (shown above) explained how to write out a netlist for Calibre LVS. Below are the steps needed to convert this netlist to spice.
-
-1. FILLER cells must be removed from the verilog. This awk script can be used:
-
-   *awk -f $SW_IP_HOME/scs8lp/scripts/remove_FILLERS.k <netlist with fillers> > <netlist without fillers>*
-
-2. The netlist can next be converted to spice with this script:
-
-   *v2lvs -v <verilog without fillers> -lsp $SW_IP_HOME/scs8lp/cdl/scs8lp.cdl -s $SW_IP_HOME/scs8lp/cdl/scs8lp.cdl -o <spice for LVS>*
-
-.. _execution-4:
-
-Execution
-~~~~~~~~~
-
-Calibre LVS can be run from within Calibre DESIGNRev:
-
-1. Load the GDS that was written out from Innovus.
-
-2. Launch “Verification -> Run nmLVS”.
-
-3. At “Rules -> LVS Rules File” enter “$PDK_HOME/DRC/Calibre/lvsRules”.
-
-4. At “Rules -> LVS Run Directory” enter “<local path>/lvs”.
-
-5. At “Inputs” in the “Layout” tab:
-
-   a. Press “Export from layout viewer”.
-
-   b. Enter the “Top Cell” name.
-
-6. At “Inputs” in the “Netlist” tab enter the “Spice Files:” with the spice for LVS that was created above.
-
-7. At “Input” in the “H-Cells” tab press “Use H-Cells file” and enter “$SW_IP_HOME/scs8lp/cdl/scs8lp.hcell”
-
-8. At the top press “Setup -> LVS Options”.
-
-9. At “LVS Options” in the “Include” tab in the top white space enter the path to the pin text file that was created in the Innovus Addenda.
 
-Click “Run LVS”.
 
 .. |logo| image:: ./media/image1.png
    :width: 3.5in
diff --git a/docs/release_notes/libraries/sky130_fd_sc_ls/V0.1.0/release_notes.rst b/docs/release_notes/libraries/sky130_fd_sc_ls/V0.1.0/release_notes.rst
index 666ffec..6870282 100644
--- a/docs/release_notes/libraries/sky130_fd_sc_ls/V0.1.0/release_notes.rst
+++ b/docs/release_notes/libraries/sky130_fd_sc_ls/V0.1.0/release_notes.rst
@@ -1,111 +1,15 @@
 |logo|
 
 SCS8LS Release Notes
-
+=======================
 Revision 0.1.2
-
+-----------------------
 December 27, 2019
-
+-----------------------
 **NOTICE**
 
    This document contains confidential information that is proprietary to SkyWater Technology. No part of its contents may be used, copied, disclosed or conveyed to any party in any manner whatsoever without prior written permission from SkyWater.
 
-Table of Contents
-=================
-
-`Table of Contents 1 <#table-of-contents>`__
-
-`Table of Figures 2 <#_Toc518557146>`__
-
-`Table of Tables 2 <#_Toc518557147>`__
-
-`1 Revision History 3 <#_Toc518557148>`__
-
-`2 Reference Documents 4 <#_Toc417288790>`__
-
-`3 V0.1.1 Updates and Known Limitations (2019/03/28) 5 <#v0.1.1-updates-and-known-limitations-20190328>`__
-
-`3.1 Supported Tool Versions 5 <#supported-tool-versions>`__
-
-`3.2 V0.1.1 Bug List 5 <#v0.1.1-bug-list>`__
-
-`3.3 V0.1.1 Known Limitations 6 <#v0.1.1-known-limitations>`__
-
-`4 V0.1.0 Updates and Known Limitations (2018/04/25) 7 <#v0.1.0-updates-and-known-limitations-20180425>`__
-
-`4.1 Supported Tool Versions 7 <#supported-tool-versions-1>`__
-
-`4.2 V0.1.0 Bug List 7 <#v0.1.0-bug-list>`__
-
-`4.3 V0.1.0 Known Limitations 8 <#v0.1.0-known-limitations>`__
-
-`5 Overview 9 <#overview>`__
-
-`5.1 IP Version Numbering 9 <#ip-version-numbering>`__
-
-`5.2 IP Directory Structure 10 <#ip-directory-structure>`__
-
-`6 IP Installation 11 <#ip-installation>`__
-
-`7 IP Usage 12 <#ip-usage>`__
-
-`8 Digital PDK 18 <#digital-pdk>`__
-
-`8.1 Synthesis 18 <#synthesis>`__
-
-`8.1.1 Requirements 18 <#requirements>`__
-
-`8.1.2 Execution 18 <#execution>`__
-
-`8.2 Simulation 18 <#simulation>`__
-
-`8.2.1 Requirements 18 <#requirements-1>`__
-
-`8.2.2 Execution 18 <#execution-1>`__
-
-`8.3 Place and Route 19 <#place-and-route>`__
-
-`8.3.1 Requirements 19 <#requirements-2>`__
-
-`8.3.2 Execution 19 <#execution-2>`__
-
-`8.3.3 Innovus Addenda 19 <#innovus-addenda>`__
-
-`8.3.4 Future Plans 19 <#future-plans>`__
-
-`8.4 DRC 20 <#drc>`__
-
-`8.4.1 Requirements 20 <#requirements-3>`__
-
-`8.4.2 Calibre DRC Rundecks 20 <#calibre-drc-rundecks>`__
-
-`8.4.3 Execution 20 <#execution-3>`__
-
-`8.5 LVS 21 <#lvs>`__
-
-`8.5.1 Requirements 21 <#requirements-4>`__
-
-`8.5.2 Generate Spice Netlist 21 <#generate-spice-netlist>`__
-
-`8.5.3 Execution 21 <#execution-4>`__
-
-Table of Figures
-================
-
-No table of figures entries found.
-
-Table of Tables
-===============
-
-`Table 1: Supported tool versions for SCS8LS V0.1.1 5 <#_Toc518557135>`__
-
-`Table 2: Bugs addressed in V0.1.1 5 <#_Toc518557136>`__
-
-`Table 1: Supported tool versions for SCS8LS V0.1.0 7 <#_Ref500277360>`__
-
-`Table 2: Bugs addressed in V0.1.0 7 <#_Ref509560110>`__
-
-`Table 3: List of Standard Cells 14 <#_Toc518557139>`__
 
 Revision History
 ================
@@ -267,244 +171,7 @@
 
 The following is a list of known issues with the V0.1.0 IP:
 
-Overview
-========
-
-The SkyWater SCS8LS Release Notes contain information regarding the low voltage low speed standard cells available from SkyWater for this technology and its known limitations.
-
-IP Usage
-========
-
-The SCS8LS IP contains a variation of standard cells with low voltage, low speed, and lower leakage from high threshold voltage FETs. These cells function at voltage supplies between 1.20V and 1.95V, but the timing and power models are valid from 1.60V up to 1.95V. The low to high level shifter cells are capable of shifting from 1.2V to 1.95V. It also contains sleep transistors.
-
-The scs8_hd library contains two OA libraries, including a techLib reference library. The only library the designer will need to use for the low speed standard cells is scs8ls. The other library is necessary as reference to this one only.
-
-The top level cells of interest are described in table 3 on the following pages.
-
-Table 3: List of Standard Cells
-
-|image2|
-
-|image3|
-
-|image4|
-
-|image5|
-
-For additional information, please contact SkyWater Technology.
-
-Digital PDK
-===========
-
-1. .. rubric:: Synthesis
-      :name: synthesis
-
-   1. .. rubric:: Requirements
-         :name: requirements
-
--  Liberty file: $SW_PDK_ROOT/s8_ip/scs8ls/lib/scs8ls_ss_1.60v_100C.lib
-
--  Tech lef: $SW_PDK_ROOT/s8_ip/tech/s8phirs-10r.tlef
-
--  Standard Cell LEF: $SW_PDK_ROOT/s8_ip/scs8ls/scs8ls.lef
-
-   2. .. rubric:: Execution
-         :name: execution
-
-The simple “sv_interfaces” design example was used as the RTL base. Genus synthesized a netlist. The netlist was visually inspected to see what types of standard-cells were included; netlist included DFF, NAND, XNOR, etc.  No effort was spent analyzing performance, power, or area (PPA) nor whether the SDC was consumed correctly.  Intent was just to verify that a structured netlist was generated.  Numerous reports were generated during the synthesis process (area, gates, check_design, etc).  A quick inspection of the report files was done just to see that no gross errors were present due to input-file consumption.
-
-2. .. rubric:: Simulation
-      :name: simulation
-
-   3. .. rubric:: Requirements
-         :name: requirements-1
-
--  Standard Cell Verilog Models: $SW_PDK_ROOT/s8_ip/scs8ls/verilog/*.v
-
-   4. .. rubric:: Execution
-         :name: execution-1
-
-The simulation was run with both the RTL and the netlist instantiated in the testbench side-by-side.  Visual inspection of the waveforms of the two modules revealed that they appeared the same.  Whereas the netlist is consumed as gates by the simulator, no effort for SDF-annotated simulation was expended.
-
-Place and Route
----------------
-
-.. _requirements-2:
-
-Requirements
-~~~~~~~~~~~~
-
--  Liberty files: $SW_PDK_ROOT/s8_ip/scs8ls/lib/*.lib
-
--  Tech lef: $SW_PDK_ROOT/s8_ip/tech/s8phirs-10r.tlef
-
--  Standard Cell LEF: $SW_PDK_ROOT/s8_ip/scs8ls/lef/scs8ls.lef
-
--  Standard Cell GDS: $SW_PDK_ROOT/s8_ip/scs8ls/gds/scs8ls.gds
-
--  GDS Layer Map: $SW_PDK_ROOT/s8_ip/scs8ls/tech/s8_innovus.layermap
-
--  Metal Fill Rules: Next Release
-
-   6. .. rubric:: Execution
-         :name: execution-2
-
-The synthesized netlist was read into Innovus. The following steps were performed:
-
--  Floorplanning
-
--  Power Routing
-
--  Global Routing and Initial Timing
-
--  Clock Tree Insertion
-
--  Detail Routing
-
--  Metal Fill Insertion
-
--  Timing Analysis
-
--  DRC and LVS Verification
-
-Innovus Addenda
-~~~~~~~~~~~~~~~
-
--  To add tap cells at the ends of every row:
-
-   -  *source $SW_PDK_ROOT/s8_ip/scs8hd/scripts/add_tap.tcl*
-
--  To stream out gds:
-
-   -  *write_stream <gds file> -map_file $SW_PDK_ROOT/s8_ip/tech/s8_innovus.layermap -lib_name DesignLib -unit 1000 -mode ALL -merge $SW_PDK_ROOT/s8_ip/scs8ls/gds/scs8ls.gds*
-
--  To write out a netlist for Calibre LVS:
-
-   -  *write_netlist <netlist for lvs> -phys -exclude_leaf_cells*
-
--  To create a pin text file for Calibre LVS:
-
-   -  *source $SW_PDK_ROOT/s8_ip/scs8ls/scripts/lvstext.tcl*
-
-Future Plans
-~~~~~~~~~~~~
-
-Support is planned for a future release for the following items:
-
--  Cadence Voltus power integrity tools
-
--  Innovus OA-based flow: the current flow is LEF-based.
-
--  Memories: in development.
-
-*
-*
-
-DRC
----
-
-.. _requirements-3:
-
-Requirements
-~~~~~~~~~~~~
-
--  Calibre Rundecks: $SW_PDK_ROOT/s8/DRC/Calibre/*Rules\*
-
-**Calibre** DRC Rundecks
-~~~~~~~~~~~~~~~~~~~~~~~~
-
-Five Calibre rundecks are available:
-
-1. drcRules: General DRC rundeck
-
-2. softRules: ERC rundeck
-
-3. stressRules: Sealring checks
-
-4. latchupRules: Latch-up and antenna checks
-
-5. fillRules: Metal fill rundeck is being developed
-
-A clean run for the top 4 rundecks is required for every design.
-
-The metal fill deck is for timing purposes and can be loaded into Quantus; the final metal fill will be added at tapeout.
-
-There is an additional rundeck called cldrcRules.
-
-This rundeck converts all layers to a version ready for tapeout. It also adds in the final metal fill. This rundeck will usually be used at the Foundry only as part of final tapeout process.
-
-.. _execution-3:
-
-**Execution**
-~~~~~~~~~~~~~
-
-Calibre DRC can be run from within Calibre DESIGNRev:
-
-1. Load the GDS written out from Innovus.
-
-2. Launch “Verification -> Run nmDRC”.
-
-3. At “Rules -> DRC Rules File” enter “$PDK_HOME/DRC/Calibre/<rundeck_name>”.
-
-4. At “Rules -> DRC Run Directory” enter the local directory name with the title of the rundeck, i.e. “<local path>/drc” or “<local path>/stress”.
-
-5. At “Inputs” press “Export from layout viewer”.
-
-6. Click “Run DRC”.
-
-LVS
----
-
-.. _requirements-4:
-
-Requirements
-~~~~~~~~~~~~
-
--  Calibre Rundeck: $SW_PDK_ROOT/s8/LVS/Calibre/lvsRules
-
-**Generate** Spice Netlist
-~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-One of the Innovus Addenda (shown above) explained how to write out a netlist for Calibre LVS. Below are the steps needed to convert this netlist to spice.
-
-1. FILLER cells must be removed from the verilog. This awk script can be used:
-
-   *awk -f $SW_PDK_ROOT/s8_ip/scs8ls/scripts/remove_FILLERS.k <netlist with fillers> > <netlist without fillers>*
-
-2. The netlist can be converted to spice with this script:
-
-   *v2lvs -v <verilog without fillers> -lsp $SW_PDK_ROOT/s8_ip/scs8ls/cdl/scs8ls.cdl -s $SW_PDK_ROOT/s8_ip/scs8ls/cdl/scs8ls.cdl -o <spice for LVS>*
-
-.. _execution-4:
-
-Execution
-~~~~~~~~~
-
-Calibre LVS can be run from within Calibre DESIGNRev:
-
-1. Load the GDS that was written out from Innovus.
-
-2. Launch “Verification -> Run nmLVS”.
-
-3. At “Rules -> LVS Rules File” enter “$PDK_HOME/DRC/Calibre/lvsRules”.
-
-4. At “Rules -> LVS Run Directory” enter “<local path>/lvs”.
-
-5. At “Inputs” in the “Layout” tab:
-
-   a. Press “Export from layout viewer”.
-
-   b. Enter the “Top Cell” name.
-
-6. At “Inputs” in the “Netlist” tab enter the “Spice Files:” with the spice for LVS that was created above.
-
-7. At “Input” in the “H-Cells” tab press “Use H-Cells file” and enter “$SW_PDK_ROOT/s8_ip/scs8ls/cdl/scs8ls.hcell”
-
-8. At the top press “Setup -> LVS Options”.
-
-9. At “LVS Options” in the “Include” tab in the top white space enter the path to the pin text file that was created in the Innovus Addenda.
 
-Click “Run LVS”.
 
 .. |logo| image:: ./media/image1.png
    :width: 3.5in
@@ -512,15 +179,4 @@
 .. |81 prBOunduy_ceII npc_dr avng rve| image:: ./media/image3.png
    :width: 6.97in
    :height: 4.60039in
-.. |image2| image:: ./media/image4.emf
-   :width: 6.5in
-   :height: 6.19048in
-.. |image3| image:: ./media/image5.emf
-   :width: 6.5in
-   :height: 7.89286in
-.. |image4| image:: ./media/image6.emf
-   :width: 6.5in
-   :height: 5.87128in
-.. |image5| image:: ./media/image7.emf
-   :width: 6.5in
-   :height: 5.38571in
+
diff --git a/docs/release_notes/libraries/sky130_fd_sc_ms/V0.0.0/release_notes.rst b/docs/release_notes/libraries/sky130_fd_sc_ms/V0.0.0/release_notes.rst
index 30cdf04..f0d13a2 100644
--- a/docs/release_notes/libraries/sky130_fd_sc_ms/V0.0.0/release_notes.rst
+++ b/docs/release_notes/libraries/sky130_fd_sc_ms/V0.0.0/release_notes.rst
@@ -1,109 +1,15 @@
 |logo|
 
 SCS8MS Release Notes
-
+====================
 Revision 0.0.2
-
+-----------------------
 December 27, 2019
-
+-----------------------
 **NOTICE**
 
    This document contains confidential information that is proprietary to SkyWater Technology. No part of its contents may be used, copied, disclosed or conveyed to any party in any manner whatsoever without prior written permission from SkyWater.
 
-Table of Contents
-=================
-
-`Table of Contents 1 <#table-of-contents>`__
-
-`Table of Figures 2 <#_Toc518558093>`__
-
-`Table of Tables 2 <#_Toc518558094>`__
-
-`1 Revision History 3 <#_Toc518558095>`__
-
-`2 Reference Documents 4 <#_Toc417288790>`__
-
-`3 V0.0.1 Updates and Known Limitations (2019/03/28) 5 <#v0.0.1-updates-and-known-limitations-20190328>`__
-
-`3.1 Supported Tool Versions 5 <#supported-tool-versions>`__
-
-`3.2 V0.0.1 Bug List 5 <#v0.0.1-bug-list>`__
-
-`3.3 V0.0.1 Known Limitations 6 <#v0.0.1-known-limitations>`__
-
-`4 V0.0.0 Updates and Known Limitations (2018/03/30) 7 <#v0.0.0-updates-and-known-limitations-20180330>`__
-
-`4.1 Supported Tool Versions 7 <#supported-tool-versions-1>`__
-
-`4.2 V0.0.0 Bug List 7 <#v0.0.0-bug-list>`__
-
-`4.3 V0.0.0 Known Limitations 8 <#v0.0.0-known-limitations>`__
-
-`5 Overview 9 <#overview>`__
-
-`5.1 IP Version Numbering 9 <#ip-version-numbering>`__
-
-`5.2 IP Directory Structure 10 <#ip-directory-structure>`__
-
-`6 IP Installation 11 <#ip-installation>`__
-
-`7 IP Usage 12 <#ip-usage>`__
-
-`8 Digital PDK 13 <#digital-pdk>`__
-
-`8.1 Synthesis 13 <#synthesis>`__
-
-`8.1.1 Requirements 13 <#requirements>`__
-
-`8.1.2 Execution 13 <#execution>`__
-
-`8.2 Simulation 13 <#simulation>`__
-
-`8.2.1 Requirements 13 <#requirements-1>`__
-
-`8.2.2 Execution 13 <#execution-1>`__
-
-`8.3 Place and Route 14 <#place-and-route>`__
-
-`8.3.1 Requirements 14 <#requirements-2>`__
-
-`8.3.2 Execution 14 <#execution-2>`__
-
-`8.3.3 Innovus Addenda 14 <#innovus-addenda>`__
-
-`8.3.4 Future Plans 14 <#future-plans>`__
-
-`8.4 DRC 15 <#drc>`__
-
-`8.4.1 Requirements 15 <#requirements-3>`__
-
-`8.4.2 Calibre DRC Rundecks 15 <#calibre-drc-rundecks>`__
-
-`8.4.3 Execution 15 <#execution-3>`__
-
-`8.5 LVS 16 <#lvs>`__
-
-`8.5.1 Requirements 16 <#requirements-4>`__
-
-`8.5.2 Generate Spice Netlist 16 <#generate-spice-netlist>`__
-
-`8.5.3 Execution 16 <#execution-4>`__
-
-Table of Figures
-================
-
-No table of figures entries found.
-
-Table of Tables
-===============
-
-`Table 1: Supported tool versions for SCS8MS V0.0.1 5 <#_Toc518558087>`__
-
-`Table 2: Bugs addressed in V0.0.1 5 <#_Toc518556596>`__
-
-`Table 1: Supported tool versions for SCS8MS V0.0.0 7 <#_Ref500277360>`__
-
-`Table 2: Bugs addressed in V0.0.0 7 <#_Ref509560110>`__
 
 Revision History
 ================
@@ -127,6 +33,7 @@
 | 1.      | V1.0.1           | sw_s8_pdk_Release_Notes_V1.0.1.pdf |
 +---------+------------------+------------------------------------+
 
+
 V0.0.1 Updates and Known Limitations (2019/03/28)
 =================================================
 
@@ -137,8 +44,10 @@
 
 The SCS8MS V0.0.0 IP was developed and tested with the tools listed in Table 1.
 
+
 Table 1: Supported tool versions for SCS8MS V0.0.1
 
+
 +------------------+--------------+
 | **Tool**         | **Version**  |
 +==================+==============+
@@ -163,6 +72,7 @@
 
 -  Reliability / Device aging models
 
+
 V0.0.1 Bug List
 ---------------
 
@@ -170,6 +80,7 @@
 
 Table 2 lists the bugs that were addressed in this IP release.
 
+
 Table : Bugs addressed in V0.0.1
 
 +---------+---------------+--------------------------------------------+
@@ -180,6 +91,7 @@
 | n/a     | Schematic     | Snap schematic symbols to 0.0625 snap grid |
 +---------+---------------+--------------------------------------------+
 
+
 V0.0.1 Known Limitations
 ------------------------
 
@@ -205,18 +117,19 @@
 
 scs8ms_or4_1 on the left
 
+
 V0.0.0 Updates and Known Limitations (2018/03/30)
 =================================================
 
 The V0.0.0 SCS8MS release is the initial alpha release of the SkyWater S130 (“S8”) technology SCS8MS IP. This release has been tested on a limited set of IP and contains known issues. Any known limitations with the IP are documented in the Release Notes (i.e. this document).
 
-.. _supported-tool-versions-1:
 
 Supported Tool Versions
 -----------------------
 
 The SCS8MS V0.0.0 IP was developed and tested with the tools listed in Table 1.
 
+
 Table 1: Supported tool versions for SCS8MS V0.0.0
 
 +------------------+--------------+
@@ -243,6 +156,7 @@
 
 -  Reliability / Device aging models
 
+
 V0.0.0 Bug List
 ---------------
 
@@ -250,6 +164,7 @@
 
 Table 2 lists the bugs that were addressed in this IP release.
 
+
 Table 2: Bugs addressed in V0.0.0
 
 +---------+---------------+----------------------------------+
@@ -258,6 +173,7 @@
 | 855     | Libraries     | Confirm scs8ms digital libraries |
 +---------+---------------+----------------------------------+
 
+
 V0.0.0 Known Limitations
 ------------------------
 
@@ -271,234 +187,6 @@
 
    |image2|
 
-Overview
-========
-
-The SkyWater SCS8MS Release Notes contain information regarding the low voltage high speed standard cells available from SkyWater for this technology and its known limitations.
-
-IP Usage
-========
-
-The SCS8MS IP contains a variation of standard cells that utilize low voltage high speed logic blocks in the SKY130 technology.
-
-The scs8_ms library contains two OA libraries, including a techLib reference library. The only library the designer will need to use for these standard cells is scs8ms. The remaining libraries are necessary as references to this one only.
-
-A list of these standard cells is not available in V0.0.1. For additional information, please contact SkyWater Technology.
-
-Digital PDK
-===========
-
-1. .. rubric:: Synthesis
-      :name: synthesis
-
-   1. .. rubric:: Requirements
-         :name: requirements
-
--  Liberty file: $SW_IP_HOME/scs8ms/lib/scs8ms_ss_1.60v_100C.lib
-
--  Tech lef: $SW_IP_HOME/tech/lef/s8phirs-10r.tlef
-
--  Standard Cell LEF: $SW_IP_HOME/scs8ms/scs8ms.lef
-
-   2. .. rubric:: Execution
-         :name: execution
-
-The simple “sv_interfaces” design example was used as the RTL base. Genus synthesized a netlist. The netlist was visually inspected to see what types of standard-cells were included; netlist included DFF, NAND, XNOR, etc.  No effort was spent analyzing performance, power, or area (PPA) nor whether the SDC was consumed correctly.  Intent was just to verify that a structured netlist was generated.  Numerous reports were generated during the synthesis process (area, gates, check_design, etc).  A quick inspection of the report files was done just to see that no gross errors were present due to input-file consumption.
-
-Simulation
-----------
-
-.. _requirements-1:
-
-Requirements
-~~~~~~~~~~~~
-
--  Standard Cell Verilog Models: $SW_IP_HOME/scs8ms/verilog/*.v
-
-.. _execution-1:
-
-Execution
-~~~~~~~~~
-
-The simulation was run with both the RTL and the netlist instantiated in the testbench side-by-side.  Visual inspection of the waveforms of the two modules revealed that they appeared the same.  Whereas the netlist is consumed as gates by the simulator, no effort for SDF-annotated simulation was expended.
-
-Place and Route
----------------
-
-.. _requirements-2:
-
-Requirements
-~~~~~~~~~~~~
-
--  Liberty files: $SW_IP_HOME/scs8ms/lib/*.lib
-
--  Tech lef: $SW_IP_HOME/tech/lef/s8phirs-10r.tlef
-
--  Standard Cell LEF: $SW_IP_HOME/scs8ms/lef/scs8ms.lef
-
--  Standard Cell GDS: $SW_IP_HOME/scs8ms/gds/scs8ms.gds
-
--  GDS Layer Map: $SW_IP_HOME/scs8ms/tech/s8_innovus.layermap
-
--  Metal Fill Rules: Next Release
-
-   4. .. rubric:: Execution
-         :name: execution-2
-
-The synthesized netlist was read into Innovus. The following steps were performed:
-
--  Floorplanning
-
--  Power Routing
-
--  Global Routing and Initial Timing
-
--  Clock Tree Insertion
-
--  Detail Routing
-
--  Metal Fill Insertion
-
--  Timing Analysis
-
--  DRC and LVS Verification
-
-   5. .. rubric:: Innovus Addenda
-         :name: innovus-addenda
-
--  This tcl can be used to add tap cells:
-
-   -  *source $PDK_HOME/scs8ms/scripts/add_taps.tcl*
-
--  This tcl can be used to stream out gds:
-
-   -  *write_stream <gds file> -map_file $SW_IP_HOME/tech/s8_innovus.layermap -lib_name DesignLib -unit 1000 -mode ALL -merge $SW_IP_HOME/scs8ms/gds/scs8ms.gds*
-
--  To write out a netlist for Calibre LVS:
-
-   -  *write_netlist <netlist for lvs> -phys -exclude_leaf_cells*
-
--  To create a pin text file for Calibre LVS:
-
-   -  *source $PDK_HOME/scs8ms/scripts/lvstext.tcl*
-
-Future Plans
-~~~~~~~~~~~~
-
-Support is planned for a future release for the following items:
-
--  Cadence Voltus power integrity tools
-
--  Innovus OA-based flow: the current flow is LEF-based.
-
--  *
-   *
-
-DRC
----
-
-.. _requirements-3:
-
-Requirements
-~~~~~~~~~~~~
-
--  Calibre Rundecks: $PDK_HOME/DRC/Calibre/*Rules\*
-
-**Calibre** DRC Rundecks
-~~~~~~~~~~~~~~~~~~~~~~~~
-
-Five Calibre rundecks are available:
-
-1. drcRules: General DRC rundeck
-
-2. softRules: ERC rundeck
-
-3. stressRules: Sealring checks
-
-4. latchupRules: Latch-up and antenna checks
-
-5. fillRules: Metal fill rundeck is being developed
-
-A clean run for the top 4 rundecks is required for every design.
-
-The metal fill deck is for timing purposes and can be loaded into Quantus; the final metal fill will be added at tapeout.
-
-There is an additional rundeck called cldrcRules.
-
-This rundeck converts all layers to a version ready for tapeout. It also adds in the final metal fill. This rundeck will be usually be used at the Foundry only as part of final tapeout process.
-
-.. _execution-3:
-
-**Execution**
-~~~~~~~~~~~~~
-
-Calibre DRC can be run from within Calibre DESIGNRev:
-
-1. Load the GDS written out from Innovus.
-
-2. Launch “Verification -> Run nmDRC”.
-
-3. At “Rules -> DRC Rules File” enter “$PDK_HOME/DRC/Calibre/<rundeck_name>”.
-
-4. At “Rules -> DRC Run Directory” enter the local directory name with the title of the rundeck, i.e. “<local path>/drc” or “<local path>/stress”.
-
-5. At “Inputs” press “Export from layout viewer”.
-
-6. Click “Run DRC”.
-
-LVS
----
-
-.. _requirements-4:
-
-Requirements
-~~~~~~~~~~~~
-
--  Calibre Rundeck: $PDK_HOME/LVS/Calibre/lvsRules
-
-**Generate** Spice Netlist
-~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-One of the Innovus Addenda (shown above) explained how to write out a netlist for Calibre LVS. Below are the steps needed to convert this netlist to spice.
-
-1. FILLER cells must be removed from the verilog. This awk script can be used:
-
-   *awk -f $SW_IP_HOME/scs8ms/scripts/remove_FILLERS.k <netlist with fillers> > <netlist without fillers>*
-
-2. The netlist can next be converted to spice with this script:
-
-   *v2lvs -v <verilog without fillers> -lsp $SW_IP_HOME/scs8ms/cdl/scs8ms.cdl -s $SW_IP_HOME/scs8ms/cdl/scs8ms.cdl -o <spice for LVS>*
-
-.. _execution-4:
-
-Execution
-~~~~~~~~~
-
-Calibre LVS can be run from within Calibre DESIGNRev:
-
-1. Load the GDS that was written out from Innovus.
-
-2. Launch “Verification -> Run nmLVS”.
-
-3. At “Rules -> LVS Rules File” enter “$PDK_HOME/DRC/Calibre/lvsRules”.
-
-4. At “Rules -> LVS Run Directory” enter “<local path>/lvs”.
-
-5. At “Inputs” in the “Layout” tab:
-
-   a. Press “Export from layout viewer”.
-
-   b. Enter the “Top Cell” name.
-
-6. At “Inputs” in the “Netlist” tab enter the “Spice Files:” with the spice for LVS that was created above.
-
-7. At “Input” in the “H-Cells” tab press “Use H-Cells file” and enter “$SW_IP_HOME/scs8ms/cdl/scs8ms.hcell”
-
-8. At the top press “Setup -> LVS Options”.
-
-9. At “LVS Options” in the “Include” tab in the top white space enter the path to the pin text file that was created in the Innovus Addenda.
-
-Click “Run LVS”.
 
 .. |logo| image:: ./media/image1.png
    :width: 3.5in
diff --git a/docs/release_notes/libraries/sky130_fd_sp_fmlt/latest/release_notes.rst b/docs/release_notes/libraries/sky130_fd_sp_fmlt/latest/release_notes.rst
index af1e582..9afdcde 100644
--- a/docs/release_notes/libraries/sky130_fd_sp_fmlt/latest/release_notes.rst
+++ b/docs/release_notes/libraries/sky130_fd_sp_fmlt/latest/release_notes.rst
@@ -1,16 +1,12 @@
 |logo|
 
 S8FMLT Release Notes
+====================
+
 Revision 0.1.2
+------------------
 December 27, 2019
-
-
-Table of Contents
-=================
-
-
-Table of Tables
-===============
+------------------
 
 
 Revision History
@@ -105,111 +101,8 @@
 
 The condiode element requires a .simrc file for correct CDL netlisting. The file is $PDK_HOME/VirtuosoOA/examples/simrc. The file should be copied to .simrc for automatic sourcing in the user's work area (same location as .cdsinit).
 
-Overview
-========
-
-The SkyWater S8FMLT Release Notes contain information regarding the Flash Macro available from SkyWater for this technology and its known limitations.
-
-Digital PDK
-===========
-
-DRC
----
-
-Requirements
-~~~~~~~~~~~~
-
--  Calibre Rundecks: $PDK_HOME/DRC/Calibre/*Rules\*
-
-**Calibre** DRC Rundecks
-~~~~~~~~~~~~~~~~~~~~~~~~
-
-Five Calibre rundecks are available:
-
-1. drcRules: General DRC rundeck
-
-2. softRules: ERC rundeck
-
-3. stressRules: Sealring checks
-
-4. latchupRules: Latch-up and antenna checks
-
-5. fillRules: Metal fill rundeck is being developed
-
-A clean run for the top 4 rundecks is required for every design.
-
-The metal fill deck is for timing purposes and can be loaded into Quantus; the final metal fill will be added at tapeout.
-
-There is an additional rundeck called cldrcRules.
-
-This rundeck converts all layers to a version ready for tapeout. It also adds in the final metal fill. This rundeck will usually be used at the Foundry only as part of final tapeout process.
-
-**Execution**
-~~~~~~~~~~~~~
-
-Calibre DRC can be run from within Calibre DESIGNRev:
-
-1. Load the GDS written out from Innovus.
-
-2. Launch “Verification -> Run nmDRC”.
-
-3. At “Rules -> DRC Rules File” enter “$PDK_HOME/DRC/Calibre/<rundeck_name>”.
-
-4. At “Rules -> DRC Run Directory” enter the local directory name with the title of the rundeck, i.e. “<local path>/drc” or “<local path>/stress”.
-
-5. At “Inputs” press “Export from layout viewer”.
-
-6. Click “Run DRC”.
-
-LVS
----
-
-.. _requirements-1:
-
-Requirements
-~~~~~~~~~~~~
-
-To ensure proper execution with the correct settings, Calibre LVS should be run using one of these two runsets:
-
--  Calibre LVS, standard runset: $PDK_HOME/LVS/Calibre/s8_lvs_runset
-
--  Calibre LVS, runset with custom include file: $PDK_HOME/LVS/Calibre/s8_lvs_runset_include
-
-The runsets are identical, except the second runset allows the use of a custom include file. This fill must be called “Calibre_LVS_Include” and must reside in the user’s project directory. The custom include file allows the user to specify additional LVS settings. For example, the s8fmlt_8k_sys cell requires schematic diodes to be filtered to give clean LVS; in this case, the “Calibre_LVS_Include” file should contain this line:
-
-LVS FILTER D OPEN SOURCE
-
-Both runsets load the following Calibre LVS rule file:
-
--  $PDK_HOME/LVS/Calibre/lvs_s8_opts
-
-.. _execution-1:
-
-**Execution**
-~~~~~~~~~~~~~
-
-All top level cells are LVS clean: s8fmlt_8k_sys, s8fmlt_16k_sys, and s8fmlt_32k_sys.
-
-PEX
----
-
-.. _requirements-2:
-
-Requirements
-~~~~~~~~~~~~
-
-Calibre xRC is supported. To ensure proper execution with the correct settings, Calibre xRC should be run using one of these two runsets:
-
--  Calibre xRC, standard runset: $PDK_HOME/PEX/xRC/s8_xRC_runset
-
--  Calibre LVS, runset with custom include file: $PDK_HOME/LVS/Calibre/s8_xRC_runset_include
-
-As with LVS, the “s8_xRC_runset_include” allows the use of a custom include file (“Calibre_LVS_Include”).
-
-Both runsets load the following Calibre xRC rule files:
-
--  $PDK_HOME/PEX/xRC/xrcControlFile_s8
 
 .. |logo| image:: ./media/image1.png
    :width: 3.5in
    :height: 1.04455in
+