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SCS8HDLL Release Notes
Revision 0.1.2
December 27, 2019


Table of Contents
=================


Table of Figures
================


Table of Tables
===============


Revision History
================

+--------------+------------+---------------+---------------------------------------------+
| **Revision** | **Date**   | **Author**    | **Change Description**                      |
+--------------+------------+---------------+---------------------------------------------+
| 0.0.0        | 2018/03/30 | Julia Szemiot | Initial IP release                          |
+--------------+------------+---------------+---------------------------------------------+
| 0.1.0        | 2018/04/26 | Ben Madden    | Comprehensive update                        |
+--------------+------------+---------------+---------------------------------------------+
| 0.1.1        | 2019/03/28 | SW PDK team   | Annotate possible NPC.2 drc violation,      |
|              |            |               |                                             |
|              |            |               | snap schematic symbol pins to 0.0625 grid   |
+--------------+------------+---------------+---------------------------------------------+
| 0.1.2        | 2019/12/27 | SW PDK team   | Document cleanup—header, footer, title page |
+--------------+------------+---------------+---------------------------------------------+

Reference Documents
===================

+---------+------------------+------------------------------------+
| **No.** | **Date/Version** | **Title**                          |
+=========+==================+====================================+
| 1.      | V1.0.1           | sw_s8_pdk_Release_Notes_V1.0.1.pdf |
+---------+------------------+------------------------------------+

V0.1.1 Updates and Known Limitations (2019/03/28)
=================================================

The V0.1.1 SCS8HDLL release is the latest alpha release of the SkyWater S130 (“S8”) technology SCS8HDLL IP. This release has been tested on a limited set of IP and contains known issues. Any known limitations with the IP are documented in the Release Notes (i.e. this document).

Supported Tool Versions
-----------------------

The SCS8HDLL V0.1.1 IP was developed and tested with the tools listed in Table 3.

Table 1: Supported tool versions for SCS8HDLL V0.1.1

+------------------+--------------+
| **Tool**         | **Version**  |
+==================+==============+
| Cadence Genus    | 16.23        |
+------------------+--------------+
| Cadence Incisive | 15.20.028    |
+------------------+--------------+
| Cadence Innovus  | 18.12        |
+------------------+--------------+
| Cadence Spectre  | 17.10.160    |
+------------------+--------------+
| Cadence Virtuoso | ic617.715    |
+------------------+--------------+
| Mentor Calibre   | 2017.2_37.39 |
+------------------+--------------+

The following tools are not supported yet for S130:

-  Synopsys HSPICE

-  Electromigration

-  Reliability / Device aging models

V0.1.1 Bug List
---------------

Bugtracking software is used to track tasks related to IP development. The term “bug” refers to a tracked item, and does not necessarily indicate a problem that is being fixed.

Table 4 lists the bugs that were addressed in this IP release.

Table : Bugs addressed in V0.1.1

+---------+---------------+--------------------------------------+
| **Bug** | **Component** | **Summary**                          |
+=========+===============+======================================+
| 1175    | DRC           | NPC.2 DRC Violation                  |
+---------+---------------+--------------------------------------+
| n/a     | Schematic     | Snap symbol pins to 0.0625 snap grid |
+---------+---------------+--------------------------------------+

V0.1.1 Known Limitations
------------------------

The following is a list of known issues with the V0.1.1 IP:

It’s possible that one or more NPC.2 drc violations can occur (see drawing below.) When the extent of the abutment of npc layers between two cells differs too greatly a notch can occur. This can be fixed by moving or replacing one of the cells.

This error can be prevented by making changes to the way that cells are placed by the EDA tools. This placement-postprocessing scripting fix has not been implemented at this time.

NPC.2: 0.27 min. spacing/notch of npc:

 
|81 prBOunduy_ceII npc_dr avng rve|

 
scs8ms_dfrtp_1 on the right

scs8ms_or4_1 on the left

V0.1.0 Updates and Known Limitations (2018/04/26)
=================================================

The V0.1.0 SCS8HDLL release is the latest alpha release of the SkyWater S130 (“S8”) technology SCS8HDLL IP. This release has been tested on a limited set of IP and contains known issues. Any known limitations with the IP are documented in the Release Notes (i.e. this document).

.. _supported-tool-versions-1:

Supported Tool Versions
-----------------------

The SCS8HDLL V0.1.0 IP was developed and tested with the tools listed in Table 3.

Table 3: Supported tool versions for SCS8HDLL V0.1.0

+------------------+--------------+
| **Tool**         | **Version**  |
+==================+==============+
| Cadence Genus    | 16.23        |
+------------------+--------------+
| Cadence Incisive | 15.20.028    |
+------------------+--------------+
| Cadence Innovus  | 17.1         |
+------------------+--------------+
| Cadence Spectre  | 17.10.160    |
+------------------+--------------+
| Cadence Virtuoso | ic617.715    |
+------------------+--------------+
| Mentor Calibre   | 2017.2_37.39 |
+------------------+--------------+

The following tools are not supported yet for S8:

-  Synopsys HSPICE

-  Electromigration

-  Reliability / Device aging models

V0.1.0 Bug List
---------------

Bugtracking software is used to track tasks related to IP development. The term “bug” refers to a tracked item, and does not necessarily indicate a problem that is being fixed.

Table 4 lists the bugs that were addressed in this IP release.

Table 4: Bugs addressed in V0.1.0

+---------+---------------+---------------------------+
| **Bug** | **Component** | **Summary**               |
+=========+===============+===========================+
| 1117    | Libraries     | Confirm scs8dll libraries |
+---------+---------------+---------------------------+

V0.1.0 Known Limitations
------------------------

The following is a list of known issues with the V0.1.0 IP:

Overview
========

The SkyWater SCS8HDLL Release Notes contain information regarding the high density low leakage standard cells available from SkyWater for this technology and its known limitations.

IP Usage
========

The SCS8HDLL IP contains a variation of high density standard cells with lower leakage power than SCS8HD.

The scs8_hdll library contains two OA libraries, including a techLib reference library. The only library the designer will need to use for the high density low leakage standard cells is scs8hdll. The remaining libraries are necessary as references to this one only.

A list of high density standard cells is not available in V0.1.0. For additional information, please contact SkyWater Technology.

Digital PDK
===========

1. .. rubric:: Synthesis
      :name: synthesis

   1. .. rubric:: Requirements
         :name: requirements

-  Liberty file: $SW_PDK_ROOT/s8_ip/scs8hdll/lib/scs8hdll_ss_1.60v_100C.lib

-  Tech lef: $SW_PDK_ROOT/s8_ip/tech/lef/s8phirs-10r.tlef

-  Standard Cell LEF: $SW_PDK_ROOT/s8_ip/scs8hdll/scs8hdll.lef

   2. .. rubric:: Execution
         :name: execution

The simple “sv_interfaces” design example was used as the RTL base. Genus synthesized a netlist. The netlist was visually inspected to see what types of standard-cells were included; netlist included DFF, NAND, XNOR, etc.  No effort was spent analyzing performance, power, or area (PPA) nor whether the SDC was consumed correctly.  Intent was just to verify that a structured netlist was generated.  Numerous reports were generated during the synthesis process (area, gates, check_design, etc).  A quick inspection of the report files was done just to see that no gross errors were present due to input-file consumption.

2. .. rubric:: Simulation
      :name: simulation

   3. .. rubric:: Requirements
         :name: requirements-1

-  Standard Cell Verilog Models: $SW_PDK_ROOT/s8_ip/scs8hdll/verilog/*.v

   4. .. rubric:: Execution
         :name: execution-1

The simulation was run with both the RTL and the netlist instantiated in the testbench side-by-side.  Visual inspection of the waveforms of the two modules revealed that they appeared the same.  Whereas the netlist is consumed as gates by the simulator, no effort for SDF-annotated simulation was expended.

Place and Route
---------------

.. _requirements-2:

Requirements
~~~~~~~~~~~~

-  Liberty files: $SW_PDK_ROOT/s8_ip/scs8hdll/lib/*.lib

-  Tech lef: $SW_PDK_ROOT/s8_ip/tech/s8phirs-10r.tlef

-  Standard Cell LEF: $SW_PDK_ROOT/s8_ip/scs8hdll/lef/scs8hdll.lef

-  Standard Cell GDS: $SW_PDK_ROOT/s8_ip/scs8hdll/gds/scs8hdll.gds

-  GDS Layer Map: $SW_PDK_ROOT/s8_ip/tech/s8_innovus.layermap

-  Metal Fill Rules: Next Release

   6. .. rubric:: Execution
         :name: execution-2

The synthesized netlist was read into Innovus. The following steps were performed:

-  Floorplanning

-  Power Routing

-  Global Routing and Initial Timing

-  Clock Tree Insertion

-  Detail Routing

-  Metal Fill Insertion

-  Timing Analysis

-  DRC and LVS Verification

   7. .. rubric:: Innovus Addenda
         :name: innovus-addenda

-  To add tap cells at the ends of every row:

   -  *source $SW_PDK_ROOT/s8_ip/scs8hd/scripts/add_tap.tcl*

-  To stream out gds:

   -  *write_stream <gds file> -map_file $SW_PDK_ROOT/s8_ip/tech/s8_innovus.layermap -lib_name DesignLib -unit 1000 -mode ALL -merge $SW_PDK_ROOT/s8_ip/scs8hdll/gds/scs8hdll.gds*

-  To write out a netlist for Calibre LVS:

   -  *write_netlist <netlist for lvs> -phys -exclude_leaf_cells*

-  To create a pin text file for Calibre LVS:

   -  *source $SW_PDK_ROOT/s8/scs8hdll/scripts/lvstext.tcl*

Future Plans
~~~~~~~~~~~~

Support is planned for a future release for the following items:

-  Cadence Voltus power integrity tools

-  Innovus OA-based flow: the current flow is LEF-based.

-  Memories: in development.

-  *
   *

DRC
---

.. _requirements-3:

Requirements
~~~~~~~~~~~~

-  Calibre Rundecks: $SW_PDK_ROOT/s8/DRC/Calibre/*Rules\*

**Calibre** DRC Rundecks
~~~~~~~~~~~~~~~~~~~~~~~~

Five Calibre rundecks are available:

1. drcRules: General DRC rundeck

2. softRules: ERC rundeck

3. stressRules: Sealring checks

4. latchupRules: Latch-up and antenna checks

5. fillRules: Metal fill rundeck is being developed

A clean run for the top 4 rundecks is required for every design.

The metal fill deck is for timing purposes and can be loaded into Quantus; the final metal fill will be added at tapeout.

There is an additional rundeck called cldrcRules.

This rundeck converts all layers to a version ready for tapeout. It also adds in the final metal fill. This rundeck will usually be used at the Foundry only as part of final tapeout process.

.. _execution-3:

**Execution**
~~~~~~~~~~~~~

Calibre DRC can be run from within Calibre DESIGNRev:

1. Load the GDS written out from Innovus.

2. Launch “Verification -> Run nmDRC”.

3. At “Rules -> DRC Rules File” enter “$PDK_HOME/DRC/Calibre/<rundeck_name>”.

4. At “Rules -> DRC Run Directory” enter the local directory name with the title of the rundeck, i.e. “<local path>/drc” or “<local path>/stress”.

5. At “Inputs” press “Export from layout viewer”.

6. Click “Run DRC”.

LVS
---

.. _requirements-4:

Requirements
~~~~~~~~~~~~

-  Calibre Rundeck: $SW_PDK_ROOT/s8/LVS/Calibre/lvsRules

**Generate** Spice Netlist
~~~~~~~~~~~~~~~~~~~~~~~~~~

One of the Innovus Addenda (shown above) explained how to write out a netlist for Calibre LVS. Below are the steps needed to convert this netlist to spice.

1. FILLER cells must be removed from the verilog. This awk script can be used:

   *awk -f $SW_PDK_ROOT/s8_ip/scs8hdll/scripts/remove_FILLERS.k <netlist with fillers> > <netlist without fillers>*

2. The netlist can next be converted to spice with this script:

   *v2lvs -v <verilog without fillers> -lsp $SW_PDK_ROOT/s8_ip/scs8hdll/cdl/scs8hdll.cdl -s $SW_PDK_ROOT/s8_ip/scs8hdll/cdl/scs8hdll.cdl -o <spice for LVS>*

.. _execution-4:

Execution
~~~~~~~~~

Calibre LVS can be run from within Calibre DESIGNRev:

1. Load the GDS that was written out from Innovus.

2. Launch “Verification -> Run nmLVS”.

3. At “Rules -> LVS Rules File” enter “$PDK_HOME/DRC/Calibre/lvsRules”.

4. At “Rules -> LVS Run Directory” enter “<local path>/lvs”.

5. At “Inputs” in the “Layout” tab:

   a. Press “Export from layout viewer”.

   b. Enter the “Top Cell” name.

6. At “Inputs” in the “Netlist” tab enter the “Spice Files:” with the spice for LVS that was created above.

7. At “Input” in the “H-Cells” tab press “Use H-Cells file” and enter “$SW_PDK_ROOT/s8_ip/scs8hdll/cdl/scs8hdll.hcell”

8. At the top press “Setup -> LVS Options”.

9. At “LVS Options” in the “Include” tab in the top white space enter the path to the pin text file that was created in the Innovus Addenda.

Click “Run LVS”.

.. |logo| image:: ./media/image1.png
   :width: 3.5in
   :height: 1.04455in
.. |81 prBOunduy_ceII npc_dr avng rve| image:: ./media/image3.png
   :width: 6.97in
   :height: 4.60039in