S8 PROCESS DESIGN KIT
=====================

The SkyWater SKY130 PDK User’s Guide contains information regarding the contents of the PDK.

S8 is a mature 180nm-130nm hybrid technology developed by Cypress Semiconductor that has been used for many production parts. SKY130 is now available as a foundry technology through SkyWater Technology Foundry.

Scope: Applies to SKY130 Technology family, including the SCS8hd, scs8hdll, scs8hs, scs8hvl, scs8lp, scs8ls, and scs8ms standard cell libraries.

This document is divided into several sections, detailed in Section 8.

- PDK Versioning, Directory Structure, and Installation (Sect 8.1-8.4)
- Documentation (Sect 8.5)
- Virtuoso Device Library (Sect 8.6)
- Spice Models (Sect 8.7)
- DRC/LVS Notes (Sect 8.8-8.9)

Further details on each of the above topics may be found in their respective documents

PDK Version Numbering
---------------------

The PDK version is referred to with a 3-digit number, VX.Y.Z.

* X = Milestone Release.

  - 0 indicates “alpha” level. The PDK has not undergone full qualification. Components may be immature and untested.
  - 1 indicates “beta” level. The PDK has undergone qualification testing but has not been hardware verified.
  - 2 indicates “production” level. The PDK has passed qualification testing and has been hardware verified.

* Y = Major Scheduled Release
* Z = Interim Unscheduled Release (e.g. a patch or hotfix)


PDK Directory Structure
-----------------------

The PDK Directory structure is as follows:
::

    $SW_PDK_ROOT/
    └ V1.3.0/ # $PDK_HOME
    ├ doc/
    ├ DRC/
    ├ LVS/
    ├ MODELS/
    │ └ SPECTRE
    │ └ s8phirs_10r/
    │ ├ Models/ # SKY130 models and include files
    │ └ examples/ # Example netlists
    │ └ s8x/
    │ └ Models/
    ├ PEX/
    └ VirtuosoOA/
    ├ examples/
    │ └ modules
    ├ libs/
    │ ├ s8phirs_10r/ # SKY130 Device Library
    │ ├ s8rf/
    │ ├ s8rf2/
    │ ├ s8rf2_dv/
    │ ├ tech/
    │ └ technology_library/
    ├ SKILL/
    └ techfiles/

Technology Naming Convention and Metal Stacks
---------------------------------------------

The process name SKY130 indicates that the technology is the 8th generation SONOS technology node (130nm).

The next letter refers to the metal stack:

* P = penta = 5 levels of metal
* X = metal stack independent, may be referenced by other stacks

The following letters may occur in technology descriptions:

* H = High-density Standard Cells
* I = Inductor or Inductor-Capable
* R = poly resistor
* S = SONOS shrunken cell
* 10R = supports 10V regulated supply

The SKY130 V1.3.0 PDK supports only the S8PHIRS_10R process.

PDK Installation
----------------

The PDK is supplied as a compressed tarfile (s8_V130.tgz).

The tarfile can be uncompressed and expanded with the command

tar –xvzf s8_V130.tgz

The tar command should be executed in the SkyWater PDK root directory ($SW_PDK_ROOT). The tar commands will create the directory V1.3.0, which contains the PDK files as described in Section 8.2.

The user will have to modify the module file to set the local value of $SW_PDK_ROOT, or the .cdsinit as described in section 8.6.1.2, later in this document.

Documentation
-------------

In addition to this User’s Guide, the doc directory contains additional documentation describing the SKY130 technology and other PDK components, including release notes and the documents listed here:

Document Name Description

S8 ETD 2018-03-30.pdf - E-Test Definition Spreadsheet
S8 TDR 2018-03-30.pdf - Topological Design Rules

Topological Design Rules
~~~~~~~~~~~~~~~~~~~~~~~~

The Topological Design Rules (TDR) document (S8 TDR 2018-03-30.pdf) contains all of the rules and guidelines for designing in S8PHIRS_10R. This describes the CAD and mask layers, CAD device definitions, metal stack and connectivity, core design rules, poly fill generation flow, antenna rules, Optical Proximity Correction (OPC) procedure, and Created Layer algorithms (used in CL-DRC).

E-Test Definitions
~~~~~~~~~~~~~~~~~~

The SKY130 Technology Family E Test Definitions (ETD) document includes the E Test parameters and their ranges. The column of interest in this document is the s8phirs-10r PDK flow.

Virtuoso
========

Virtuoso Device Library
-----------------------

The SKY130 PDK supports Virtuoso OpenAccess and has been tested with Virtuoso IC6.1.7-64b.500.15.

Virtuoso Environment Setup
--------------------------

A few environment variables must be set to load the SKY130 PDK in Cadence. Two examples for setting these variables are provided in the PDK and described below.

Module File Setup
~~~~~~~~~~~~~~~~~

Module files are a common technique for loading environment variables in a modular approach. An example module is provided in the directory $PDK_HOME/VirtuosoOA/examples/modules. The subdirectory s8 provides a module file s8phirs_10r.V1.3.0, which contains one section with site-specific environment variables:

.. code:: zsh

    ############################################
    # Site-specific PDK Installation Variables #
    ############################################
    setenv SW_PDK_ROOT /data/pdks/SkyWater
    setenv PDK_HOME $env(SW_PDK_ROOT)/s8/V1.3.0

The $SW_PDK_ROOT variable must be customized for each site. Once this is set, all subsequent variable definitions should be correct. Note that the PDK version and METAL_STACK will be updated as appropriate in future releases.

To load the module, use the command “module load s8/s8phirs_10r.V1.3.0”. Note that this module uses a separate module pdk_loaded to check if any other PDKs have been loaded. This module file is provided in the VirtuosoOA/examples/modules directory.

.cdsinit
^^^^^^^^

The .cdsinit file is automatically sourced by Cadence Virtuoso upon startup to load variables and settings.

This file also has several lines that can be used to set the variables $PDK_HOME and $METAL_STACK if required. Note that these lines have been commented out on the assumption that these will be loaded by the module.

This file also contains lines that set the default Spectre models.

Techfiles
~~~~~~~~~

User libraries can either attach to the existing technology library for s8phirs_10r, or they can compile their own techfile. The techfile for this technology is in $PDK_HOME/VirtuosoOA/techfiles/s8phirs_10r.tf.

The gds mapfile is in the technology library, $PDK_HOME/VirtuosoOA/libs/s8phirs_10r/s8phirs_10r.layermap.

Schematic Driven Layout / Layout XL
-----------------------------------

The V1.3.0 PDK supports schematic-driven layout with LayoutXL. Not all features of VirtuosoXL have been tested, nor have all device features been tested.

Device library (s8phirs_10r)
============================

All devices for the SKY130 technology reside in the design library s8phirs_10r for customer usage and legacy libraries tech and technology_library for compatibility with the IP. Categories are included in s8phirs_10r to simplify device selection.

Units
-----

All values in the pcells are specified in microns (e.g. a width of 0.5 implies a width of 0.5μm).


FETs
----

The SKY130 FET models with fixed W and L are carefully characterized to ensure optimal hardware correlation. The pcell does allow a user defined geometry ("Model name" = userDefined), but this model has not been carefully scrutinized across all configurations. This custom geometry model should only be used for evaluation purposes. All layouts and final simulations should be based on fixed geometry FET models.

The FETs are available for Layout XL in V1.3.0.

Layout XL
~~~~~~~~~

The supported nfet options are nhv, nhvesd, nhvnative, nhvnativeesd, nlowvt, nshort, and ntvnative. For additional layout options without LayoutXL compatibility, the designer may use the symbolic layout nfet_symbolic in s8phirs_10r.

The supported pfet options are phighvt, pshort, phv, plowvt, and phvesd. For additional layout options without LayoutXL compatibility, the designer may use the symbolic layout pfet_symbolic in s8phirs_10r.

The Layout XL FET pcell options include:

* Model Name: dropdown options of supported devices followed by unsupported devices in LayoutXL
* Length: dropdown options for device length
* Width Per Finger: dropdown options for device width
* Source Voltage: dropdown options for supply voltage limit\*
* Drain Voltage: dropdown options for drain voltage limit\*
* Number of Fingers (m)
* Multiplicity (mult)
* Body Contact: none or leftDetached\*

\*This option is only available for the PFET.

Simulation
~~~~~~~~~~

There are additional features in the schematic, indicated below:

* Area source [μm2]: calculated automatically
* Perimeter source [μm]: calculated automatically
* Area drain [μm2]: calculated automatically
* Perimeter drain [μm]: calculated automatically
* Source Num Squares (nrs): calculated automatically
* Drain Num Squares (nrd): calculated automatically
* No Noise?: option to remove noise from model if enabled
* Dist. Diff Edge A (sa) [μm]
* Dist. Diff Edge B (sb) [μm]
* Dist. Btwn. Fingers (sd) [μm]
* Zero bias thresh. V shift
* Enable gate resistor?: option to define gate resistance using one of two presets or a custom value

The user can modify sa, sb, and sd (in microns). The schematic below was used to simulate the effect of sweeping sa (set to psa) on current Id.

|process1|

The nfet and pfet were both in deep saturation, with the nfet’s Vgs and Vds set to VDD, and the pfet’s Vgs and Vds set to –VDD. Parameter psa was swept from 0 to 2, and generated the waveforms illustrated in Figure 2, with the nfet in purple and the pfet in white. Note that the impact of sa/sb/sd will be geometry dependent, and the plot is specific for one geometry.

|process2|

The default value of sa, sb, and sd is 0. Note that at sa equal to 0, the current is approximately equivalent to that at sa equal to 1.083. In the valid region, the nfet varies by roughly ±3% and the pfet ranges by ±6%.

Resistors
---------

S8PHIRS_10R supports a variety of resistors listed in Table 2:

.. table:: Resistor models

    +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+
    | **Device**                             | **Cell** | **Type** | **Model**    | **Description**                      | **Sheet Resistance (Ω/□)** |
    +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+
    | **Resistor**                           | res      | poly     | mrp1         | poly                                 | 48.2                       |
    +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+
    |                                        |          | li1      | mrl1         | li1                                  | 12.8                       |
    +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+
    |                                        | res3     | poly     | xhrpoly_0p35 | Fixed width poly resistor            |                            |
    +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+
    |                                        |          |          | xhrpoly_0p69 |                                      |                            |
    +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+
    |                                        |          |          | xhrpoly_1p41 |                                      | 319.8                      |
    +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+
    |                                        |          |          | xhrpoly_2p85 |                                      |                            |
    +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+
    |                                        |          |          | xhrpoly_5p73 |                                      |                            |
    +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+
    |                                        | respw    | pwell    | xpwres       | Fixed width P well resistor (in DNW) | 4400                       |
    +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+
    |                                        | resn     | diff     | mrdn         | N diffusion resistor                 | 120                        |
    +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+
    |                                        | resp     | diff     | mrdp         | P diffusion resistor                 | 197                        |
    +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+
    | **Parasitic resistance + capacitance** | rescap\* | poly     | mrp1         | parasitic poly                       | 48.2                       |
    +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+
    |                                        |          | li1      | mrl1         | parasitic li1                        | 12.8                       |
    +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+
    |                                        |          | met1     | mrm1         | parasitic metal1                     | 0.125                      |
    +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+
    |                                        |          | met2     | mrm2         | parasitic metal2                     | 0.125                      |
    +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+
    |                                        |          | met3     | mrm3         | parasitic metal3                     | 0.047                      |
    +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+
    |                                        |          | met4     | mrm4         | parasitic metal4                     | 0.047                      |
    +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+
    |                                        |          | met5     | mrm5         | parasitic metal5                     | 0.0285                     |
    +----------------------------------------+----------+----------+--------------+--------------------------------------+----------------------------+

Bent resistor symbolic layout pcells are available for res of type poly (PYbentRes), resn (nDFbentRes) and resp (pDFbentRes) resistors. Bent resistors are neither modeled nor supported in LVS.

resn, resp, res type poly and li1, and respw are all supported in LayoutXL.

res3 is not currently supported in LayoutXL.

respw is a p well resistor placed in deep NW with a fixed 2.65μm width and a variable length. The minimum length is 26.5μm.

\*rescap is a parasitic resistor/capacitor that can be used for simulation only. All of the cap models are available except the following: mcm5m4m3, mrcdlm3p1, mcm5l1p1, mcm5m3m2, mcm5m2m1.

Capacitors
----------

This PDK includes 26 vertical parallel plate (VPP) capacitors that can be simulated using 3-terminal cap_int3 and 4-terminal vppcap. The various options detailed in Table 3 are all supported in LayoutXL. Twelve of these VPPs have shields on their top layer.

.. table:: VPP Capacitors

    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | **Cell** | **Model**                       | **Size X** | **Size Y** | **Bottom Layer** | **Top Layer** | **Shield** | **Cap [fF]** | **C0 par [fF]** | **C1 par [fF]** |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | cap_int3 | xcmvpp5                         | 2.42       | 4.59       | M1               | M2            | none       | 4.37         | 0.84            | 0.29            |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | cap_int3 | xcmvpp4p4x4p6_m1m2              | 4.38       | 4.59       | M1               | M2            | none       | 7.81         | 1.24            | 0.39            |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | cap_int3 | xcmvpp4                         | 4.38       | 4.59       | M1               | M2            | none       | 9.48         | 0.81            | 0.82            |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | vppcap   | xcmvpp4p4x4p6_m3_lim5shield     | 4.38       | 4.59       | LI1              | M5            | top        | 10.80        | 1.90            | ~0              |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | cap_int3 | xcmvpp_hd5_atlas_fingercap_l5   | 2.70       | 6.10       | M1               | M4            | none       | 12.13        | 1.00            | 0.70            |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | cap_int3 | xcmvpp_hd5_atlas_fingercap2_l5  | 2.85       | 6.10       | M1               | M4            | none       | 12.65        | 1.23            | 0.71            |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | cap_int3 | xcmvpp_hd5_atlas_fingercap_l10  | 2.70       | 11.10      | M1               | M4            | none       | 23.35        | 1.51            | 1.08            |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | vppcap   | xcmvpp6p8x6p1_lim4shield        | 6.80       | 6.09       | LI1              | M4            | top        | 26.60        | 3.00            | ~0              |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | cap_int3 | xcmvpp_hd5_atlas_wafflecap2     | 5.90       | 5.90       | M1               | M4            | none       | 27.78        | 2.11            | 0.50            |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | vppcap   | xcmvpp6p8x6p1_polym4shield      | 6.84       | 6.13       | POLY             | M4            | top        | 33.80        | 6.50            | ~0              |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | cap_int3 | xcmvpp3                         | 8.58       | 7.84       | M1               | M2            | none       | 35.00        | 1.84            | 1.84            |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | vppcap   | xcmvpp8p6x7p9_m3_lim5shield     | 8.58       | 7.84       | LI1              | M5            | top        | 42.50        | 4.30            | ~0              |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | cap_int3 | xcmvpp_hd5_atlas_fingercap_l20  | 2.70       | 21.10      | M1               | M4            | none       | 45.83        | 2.49            | 1.82            |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | cap_int3 | xcmvpp11p5x11p7_m1m2            | 11.41      | 11.69      | M1               | M2            | none       | 74.60        | 4.11            | 2.01            |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | cap_int3 | xcmvpp_hd5_atlas_fingercap_l40  | 2.70       | 41.10      | M1               | M4            | none       | 91.27        | 5.99            | 2.62            |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | vppcap   | xcmvpp11p5x11p7_m3_lim5shield   | 11.41      | 11.69      | LI1              | M5            | top        | 97.30        | 7.40            | ~0              |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | cap_int3 | xcmvpp11p5x11p7_m1m4            | 11.41      | 11.69      | M1               | M5            | none       | 110.19       | 4.87            | 1.87            |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | cap_int3 | xcmvpp_hd5_atlas_wafflecap1     | 11.33      | 11.33      | M1               | M4            | none       | 110.41       | 1.76            | 1.45            |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | vppcap   | xcmvpp11p5x11p7_lim5shield      | 11.41      | 11.69      | LI1              | M5            | top        | 116.80       | 7.40            | ~0              |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | vppcap   | xcmvpp11p5x11p7_m4shield        | 11.41      | 11.69      | LI1              | M4            | top        | 118.50       | 5.00            | 2.40            |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | vppcap   | xcmvpp11p5x11p7_polym4shield    | 11.45      | 11.73      | POLY             | M4            | top        | 121.90       | 17.70           | ~0              |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | vppcap   | xcmvpp11p5x11p7_m5shield        | 11.41      | 11.69      | LI1              | M5            | top        | 137.40       | 5.40            | 2.30            |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | vppcap   | xcmvpp11p5x11p7_polym5shield    | 11.45      | 11.73      | POLY             | M5            | top        | 141.20       | 18.10           | ~0              |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | vppcap   | xcmvpp11p5x11p7_polym50p4shield | 11.45      | 11.73      | POLY             | M5            | top        | 141.20       | 18.10           | ~0              |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | vppcap   | xcmvppx4_2xnhvnative10x4        | 11.34      | 11.69      | DIFF             | M5            | top        | 340.90       | ~0              | ~0              |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+
    | cap_int3 | xcmvpp_hd5_4x2                  | 44.69      | 23.09      | POLY             | M5            | none       | 1470.00      | 51.70           | 48.60           |
    +----------+---------------------------------+------------+------------+------------------+---------------+------------+--------------+-----------------+-----------------+

Two scalable Metal-insulator-Metal (MiM) capacitors are available and supported in LayoutXL, as specified in Table 4. One is on metals 3 and 4, the other is on metals 4 and 5. These devices are defined in section tt_rc of the design_wrapper.lib.scs, which is discussed in Section 8.7.1.2. The MiM can also be made into an array by increasing the number of rows and columns from 1; currently this generates a layout pcell with the top plates connected, but the bottom plates will need to be connected as well.

.. table:: MiM Capacitor Models

    +----------+-----------+----------------------+---------------------+--------------------+
    | **Cell** | **Model** | **Description**      | **Cap**             | **Nominal Corner** |
    +----------+-----------+----------------------+---------------------+--------------------+
    | cmimc    | xcmimc1   | MiM Capacitor, M3-M4 | 2.2 fF/μm\ :sup:`2` | tt_rc              |
    +----------+-----------+----------------------+---------------------+--------------------+
    |          | xcmimc2   | MiM Capacitor, M4-M5 | 2.2 fF/μm\ :sup:`2` | tt_rc              |
    +----------+-----------+----------------------+---------------------+--------------------+

Two varactors are available as well, and described in Table 5. These varactors are supported in LayoutXL. The bulk must always be tied to ground.

.. table:: Varactor Models

    +----------+-----------+-----------------------+------------------------+--------------------+
    | **Cell** | **Model** | **Description**       | **Cap@V(c0,c1)>400mV** | **Nominal Corner** |
    +----------+-----------+-----------------------+------------------------+--------------------+
    | capbn_b  | xcnwvc    | Varactor              | >8.096fF/μm\ :sup:`2`  | tt_fet & tt_parRC  |
    +----------+-----------+-----------------------+------------------------+--------------------+
    |          | xcnwvc2   | Varactor with high Vt | >8.1297/μm\ :sup:`2`   |                    |
    +----------+-----------+-----------------------+------------------------+--------------------+

BJTs
----

S8 supports two fixed size PNPs and three fixed size NPNs intended for use in bandgap reference circuits. All of the BJTs listed in Table 6 are supported in LayoutXL. The NPNs and PNPs are defined in sections npn_t and tt_fet, respectively, of design_wrapper.lib.scs. For more information, refer to Section 8.7.1.2.

.. table:: BJT Models

    +------------+----------+----------------+-----------------+--------------------+
    | **Device** | **Cell** | **Model**      | **Description** | **Nominal Corner** |
    +------------+----------+----------------+-----------------+--------------------+
    | **NPN**    | npn4     | npnpar1x1      | NPN BJT         | npn_t              |
    +------------+----------+----------------+-----------------+--------------------+
    |            |          | npnpar1x2      |                 |                    |
    +------------+----------+----------------+-----------------+--------------------+
    |            |          | npn_1x1_2p0_hv |                 |                    |
    +------------+----------+----------------+-----------------+--------------------+
    | **PNP**    | pnp4     | pnppar         | PNP BJT         | tt_fet             |
    +------------+----------+----------------+-----------------+--------------------+
    |            |          | pnppar5x       |                 |                    |
    +------------+----------+----------------+-----------------+--------------------+

Diodes
------

The diodes (diode, lvsdiode) in SKY130 represent parasitic diodes and are not intended for forward biased usage.

Inductors
---------

The schematic elements ind4 and inductor are available for simulation. Fixed geometry inductors are not included in this PDK. Contact SkyWater for information on generating custom inductor models using EM modeling tools.

Other
-----

Additional devices in the Misc category include the seal ring, various shorts, a metal 4 fuse, pad cells, and the connectivity diode.

Seal Ring
~~~~~~~~~

The pcell advSeal_6um is the chip seal ring.

Fuse
~~~~

A fuse on metal 4 is available.

Connectivity Diode
~~~~~~~~~~~~~~~~~~

The connectivity diode (condiode_grid) is used to check the connectivity of the isolated pwell and the dnwell. This is done to ensure proper biasing of the isolated pwell by extracting the condiode. In the layout, a text label “condiode” is drawn over the isolated pwell using the text.dg layer inside the isolated pwell, which is formed using the dnwell and the nwell ring. The latchup ruledeck checks for the condiode label in the dnwell that is connected to a non-power terminal.

1. Make sure the text label inside the isolated pwell (not over the nwell drawing). Make sure to turn on the lower level hierarchy to ensure the label is not over nwell.
2. Make sure to use the text label at the level of hierarchy intended.
3. Make sure the schematic contains the condiode element.
4. Make sure the diode is connected properly in the schematic. The anode is connected to the isolated pwell term and the cathode is connected to the dnwell term.

The newly placed Condiode will have the area and perimeter set to -1 along with the text “WILL NOT EXTRACT” as in the figure.

|process3|

The element will not extract if the value is set to -1 or both area and perimeter set to 0. The user must update these parameters to the proper value. If the user tried to extract the schematic without updating the Condiode symbol, the extract will fail.

When the element is properly updated with the best estimate area and perimeter of the dnwell the symbol will show:

|process4|

Simulation Models
=================

Spectre
-------

The Spectre models have been successfully used with the Spectre simulator, and simulation results match the electrical parameter specs.

Spectre Model Qualification
~~~~~~~~~~~~~~~~~~~~~~~~~~~

Full model qualification requires the following checks:

* Confirm that all supported devices netlist and simulate when the appropriate model files are included.
* Check process corner simulation results against electrical specification limits.
* Run performance simulations on various IP and determine if results sufficiently match existing published simulation results.
* Compare simulated performance of isolated devices and IP to measured hardware results.

The V1.3.0 models have not been systematically tested with all five of those tasks. The V1.3.0 devices have been netlisted and simulated, certain characteristics have been evaluated at nominal and process corners, and a small number of IP blocks have been evaluated. The V1.3.0 models are considered functional but not fully qualified.

Spectre Model Setup
~~~~~~~~~~~~~~~~~~~

All stack-specific Spectre model files are found in the directory $PDK_HOME/MODELS/SPECTRE/s8phirs_10r /Models. The file design_wrapper.lib.scs provides the sections necessary to simulate every corner (e.g. typical tt, fast-fast ff, slow-fast sf, etc.). For the FETs, the corner naming is based on P followed by N, so sf indicates the slow PMOS fast NMOS corner. Table 6 elaborates the sections in the Design Wrapper.

.. table:: Design Wrapper Sections

    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    |                             | **Devices**                        | **Section** | **Included Files**            | **Description**                     |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    | **Transistor Corners**      | FET, PNP                           | tt_fet      | tt.cor                        | Typical pmos, typical nmos          |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    |                             |                                    | ff_fet      | ff.cor                        | Fast pmos, fast nmos                |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    |                             |                                    | ss_fet      | ss.cor                        | Slow pmos, slow nmos                |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    |                             |                                    | fs_fet      | fs.cor                        | Fast pmos, slow nmos                |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    |                             |                                    | sf_fet      | sf.cor                        | Slow pmos, fast nmos                |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    | **Parasitic Corners**       | Parasitic Capacitors and Resistors | tt_parRC    | trtc.cor                      | Typical resistor, typical capacitor |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    |                             |                                    | hl_parRC    | hrlc.cor                      | High resistor, low capacitor        |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    |                             |                                    | lh_parRC    | lrhc.cor                      | Low resistor, high capacitor        |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    | **Linear Device Corners**   | Capacitors and Resistors           | tt_rc       | trtclin.cor                   | Typical resistor, typical capacitor |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    |                             |                                    | lh_rc       | lrhclin.cor                   | Low resistor, high capacitor        |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    |                             |                                    | hl_rc       | hrlclin.cor                   | High resistor, low capacitor        |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    |                             |                                    | ll_rc       | lrlclin.cor                   | Low resistor, low capacitor         |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    |                             |                                    | hh_rc       | hrhclin.cor                   | High resistor, high capacitor       |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    | **Cell Transistor Corners** | Cell FETs, low leakage models      | tt_cell     | ttcell.cor                    | Typical pmos, typical nmos          |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    |                             |                                    | ff_cell     | ffcell.cor                    | Fast pmos, fast nmos                |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    |                             |                                    | ss_cell     | sscell.cor                    | Slow pmos, slow nmos                |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    |                             |                                    | fs_cell     | fscell.cor                    | Fast pmos, slow nmos                |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    |                             |                                    | sf_cell     | sfcell.cor                    | Slow pmos, fast nmos                |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    | **Wafer**                   | Standard FETs, BJTs                | wafer_fet   | wafer.cor                     | FET models extracted from wafer     |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    |                             | Cell FETs                          | wafer_cell  | wafer_cell.cor                | FET models extracted from wafer     |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    | **Leakage**                 | Standard FETs, BJTs                | leak_fet    | leak.cor                      | Average worst case leakage models   |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    |                             | Cell FETs                          | leak_cell   | leakcell.cor                  | Average worst case leakage models   |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    | **NPN Corners**             | NPN Corners                        | npn_t       | npn_t.cor                     | Typical NPN                         |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    |                             |                                    | npn_f       | npn_f.cor                     | Fast NPN                            |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    |                             |                                    | npn_s       | npn_s.cor                     | Slow NPN                            |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+
    | **Montecarlo**              | All devices                        | mc          | monte.cor critical_params.cor | Montecarlo process and mismatch     |
    +-----------------------------+------------------------------------+-------------+-------------------------------+-------------------------------------+

This PDK does not support process Montecarlo. The models are available but they have not been qualified. To run Montecarlo, all of the corner sections need to be excluded and the mc section needs to be included.

All units in the PDK are specified in microns (1e-6). For example, the minimum size FET has W=0.28 and L=0.15.

There is an example of automatic model file loading in the .cdsinit found in $PDK_HOME/VirtuosoOA/examples. The resulting Cadence Model Library Setup dialog is shown here.

|process5|

DRC
===

Calibre DRC flow has been verified with Mentor Graphics Calibre version 2018.1_27.18.

These Calibre rule files are provided:

- s8_drcRules: General DRC
- s8_fillRules: Metal fill creation
- s8_latchupRules: Latch-up and antenna checks
- s8_luResRules: Latch-up resistor checks
- s8_softRules: Soft-connect and floating substrate / wells checks
- s8_stressRules: Sealring checks

A clean run with drcRules, softRules, stressRules, latchupRules, and luResRules is required for the top-level of every design.

The metal fill deck is provided for parasitic capacitance estimation and timing simulation; the final metal fill will be added at tapeout.

Calibre DRC can be run using the Calibre Interactive GUI from the Virtuoso layout window using these steps:

1. Launch Calibre Interactive nmDRC by choosing Run_nmDRC from the Calibre menu in the Virtuoso layout tool.
2. At “Rules -> DRC Rules File” enter “$PDK_HOME/DRC/Calibre/<rulefile_name>”.
3. To ensure that all checks are run, at “Rules -> Check Selection Recipe:” select “All checks”.
4. At “Inputs” press “Export from layout viewer”.
5. Click “Run DRC”.

Runset files are provided for all the rule files:

- $PDK_HOME/DRC/Calibre/s8_drc_runset
- $PDK_HOME/DRC/Calibre/s8_fill_runset
- $PDK_HOME/DRC/Calibre/s8_latchup_runset
- $PDK_HOME/DRC/Calibre/s8_lures_runset
- $PDK_HOME/DRC/Calibre/s8_soft_runset
- $PDK_HOME/DRC/Calibre/s8_stress_runset

These can be loaded by choosing “File -> Load Runset…” from the “Calibre Interactive – nmDRC” form. Each runset will:

- Load the appropriate rule file;
- Set the “Check Selection Recipe” to “All checks”;
- Turn on “Export from layout viewer” on the “Inputs” tab.

LVS
===

Calibre LVS
-----------

To ensure proper processing of the schematic for LVS, the user must first create a “simulation run control file.” This file must be called “.simrc” and must reside in the work area. A sample file is provided:

$PDK_HOME/LVS/Calibre/simrc.sample

Copy this file to “.simrc” in the user’s work area.

Calibre LVS flow has been verified with Mentor Graphics Calibre version 2018.1_27.18.

To run:

1) Launch Calibre Interactive nmLVS by choosing Run_nmLVS from the Calibre menu in the Virtuoso layout tool.
2) Load one of the LVS runsets:

  - $PDK_HOME/LVS/Calibre/s8_lvs_runset - OR -
  - $PDK_HOME/LVS/Calibre/s8_lvs_runset_include

3) Click Run LVS.

The runsets are identical, except the second runset allows the use of a custom include file. This file must be called “Calibre_LVS_Include” and must reside in the user’s workarea. The custom include file allows the user to specify additional LVS settings.

If the user wants to make her own runset, she just needs to load these files as the rule file:

$PDK_HOME/LVS/Calibre/lvs_s8_opts

PVS
---

PVS LVS is for evaluation purposes only and has limited qualification.

PEX
===

CalibreXRC
----------

Calibre xRC flow has been verified with Mentor Graphics Calibre version 2018.1_27.18. This release only supports extraction with netlist output only.

1) Launch Calibre Interactive nmLVS by choosing Run_nmLVS from the Calibre menu in the Virtuoso layout tool.
2) Load one of the xRC runsets:

  - $PDK_HOME/PEX/xRC/s8_xRC_runset - OR –
  - $PDK_HOME/PEX/xRC/s8_xRC_runset_include

3) Click Run LVS.

As with LVS, the second runset allows the use of a custom include file. This file must be called “Calibre_LVS_Include” and must reside in the user’s project directory.

If the user wants to make his own runset, he just needs to load these files as the rule file:

$PDK_HOME/PEX/xRC/xrcControlFile_s8

QRC
~~~

QRC extraction is supported for Innovus and allows cell level extraction only.

.. |process0| image:: ./media/image1.jpeg
   :width: 0.19792in
   :height: 0.19792in
.. |process1| image:: ./media/image2.png
   :width: 4.58056in
   :height: 4.12708in
.. |process2| image:: ./media/image3.png
   :width: 6.50069in
   :height: 4.18681in
.. |process3| image:: ./media/image4.png
   :width: 4.20069in
   :height: 2.22708in
.. |process4| image:: ./media/image5.png
   :width: 4.26042in
   :height: 2.26042in
.. |process5| image:: ./media/image6.png
   :width: 6.5in
   :height: 2.675in