module name	exists in libs	desc available in files	Description	Equation
feedthru			Feed through virtual short	
feedthru_netalias			Feed through for creating net aliases	
short			Virtual short	
short_netalias			Virtual short for creating net aliases	
probe_p			Virtual voltage probe point	
probec_p			Virtual current probe point	
a2111o	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input AND into first input of 4-input OR 	((A1 & A2) | B1 | C1 | D1)
a2111oi	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input AND into first input of 4-input NOR 	!((A1 & A2) | B1 | C1 | D1)
a211o	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input AND into first input of 3-input OR 	((A1 & A2) | B1 | C1)
a211oi	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input AND into first input of 3-input NOR 	!((A1 & A2) | B1 | C1)
a21bo	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input AND into first input of 2-input OR, 2nd input inverted 	((A1 & A2) | (!B1N))
a21boi	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input AND into first input of 2-input NOR, 2nd input inverted 	!((A1 & A2) | (!B1N)) 
a21o	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		2-input AND into first input of 2-input OR 	((A1 & A2) | B1)
a21oi	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		2-input AND into first input of 2-input NOR 	!((A1 & A2) | B1)
a221o	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input AND into first two inputs of 3-input OR 	((A1 & A2) | (B1 & B2) | C1)
a221oi	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input AND into first two inputs of 3-input NOR 	!((A1 & A2) | (B1 & B2) | C1)
a222o	scs8hs scs8ls scs8ms		2-input AND into all inputs of 3-input OR 	((A1 & A2) | (B1 & B2) | (C1 & C2))
a222oi	scs8hd scs8hs scs8ls scs8ms		2-input AND into all inputs of 3-input NOR 	!((A1 & A2) | (B1 & B2) | (C1 & C2))
a22o	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		2-input AND into both inputs of 2-input OR 	((A1 & A2) | (B1 & B2))
a22oi	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		2-input AND into both inputs of 2-input NOR 	!((A1 & A2) | (B1 & B2))
a2bb2o	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input AND, both inputs inverted, into first input, and 2-input AND into 2nd input of 2-input OR 	((!A1 & !A2) | (B1 & B2))
a2bb2oi	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input AND, both inputs inverted, into first input, and 2-input AND into 2nd input of 2-input NOR 	!((!A1 & !A2) | (B1 & B2))
a311o	scs8hd scs8hs scs8lp scs8ls scs8ms		3-input AND into first input of 3-input OR 	((A1 & A2 & A3) | B1 | C1)
a311oi	scs8hd scs8hs scs8lp scs8ls scs8ms		3-input AND into first input of 3-input NOR 	!((A1 & A2 & A3) | B1 | C1)
a31o	scs8hd scs8hs scs8lp scs8ls scs8ms		3-input AND into first input of 2-input OR 	((A1 & A2 & A3) | B1)
a31oi	scs8hd scs8hs scs8lp scs8ls scs8ms		3-input AND into first input of 2-input NOR 	!((A1 & A2 & A3) | B1)
a32o	scs8hd scs8hs scs8lp scs8ls scs8ms		3-input AND into first input, and 2-input AND into 2nd input of 2-input OR 	((A1 & A2 & A3) | (B1 & B2))
a32oi	scs8hd scs8hs scs8lp scs8ls scs8ms		3-input AND into first input, and 2-input AND into 2nd input of 2-input NOR 	!((A1 & A2 & A3) | (B1 & B2))
a41o	scs8hd scs8hs scs8lp scs8ls scs8ms		4-input AND into first input of 2-input OR 	((A1 & A2 & A3 & A4) | B1)
a41oi	scs8hd scs8hs scs8lp scs8ls scs8ms		4-input AND into first input of 2-input NOR 	!((A1 & A2 & A3 & A4) | B1)
analog_pad	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_analog_pad.v s8iom0s8/V0.1.0/verilog/s8iom0s8_analog_pad.v s8iom0s8/V0.2.0/verilog/s8iom0s8_analog_pad.v s8iom0s8/V0.2.1/verilog/s8iom0s8_analog_pad.v	--fromfile--	
and2	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		2-input AND	
and2b	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input AND, first input inverted	
and3	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		3-input AND	
and3b	scs8hd scs8hs scs8lp scs8ls scs8ms		3-input AND, first input inverted	
and4	scs8hd scs8hs scs8lp scs8ls scs8ms		4-input AND	
and4b	scs8hd scs8hs scs8lp scs8ls scs8ms		4-input AND, first input inverted	
and4bb	scs8hd scs8hs scs8lp scs8ls scs8ms		4-input AND, first two inputs inverted	
bkeep_p	s8 s8phirs_10r	s8/V1.0.0/VirtuosoOA/libs/s8phirs_10r/bkeep_p/verilog/verilog.v s8/V1.0.0/VirtuosoOA/libs/tech/bkeep_p/verilog/verilog.v s8/V1.0.1/VirtuosoOA/libs/s8phirs_10r/bkeep_p/verilog/verilog.v s8/V1.0.1/VirtuosoOA/libs/tech/bkeep_p/verilog/verilog.v s8/V1.1.0/VirtuosoOA/libs/s8phirs_10r/bkeep_p/verilog/verilog.v s8/V1.1.0/VirtuosoOA/libs/tech/bkeep_p/verilog/verilog.v s8/V1.2.0/VirtuosoOA/libs/s8phirs_10r/bkeep_p/verilog/verilog.v s8/V1.2.0/VirtuosoOA/libs/tech/bkeep_p/verilog/verilog.v s8/V1.2.1/VirtuosoOA/libs/s8phirs_10r/bkeep_p/verilog/verilog.v s8/V1.2.1/VirtuosoOA/libs/tech/bkeep_p/verilog/verilog.v s8/V1.3.0/VirtuosoOA/libs/s8phirs_10r/bkeep_p/verilog/verilog.v s8/V1.3.0/VirtuosoOA/libs/s8phirs_10r_old/bkeep_p/verilog/verilog.v s8/V1.3.0/VirtuosoOA/libs/tech/bkeep_p/verilog/verilog.v s8/V2.0.0/VirtuosoOA/libs/s8phirs_10r/bkeep_p/verilog/verilog.v s8/V2.0.0/VirtuosoOA/libs/tech/bkeep_p/verilog/verilog.v s8/V2.0.1/VirtuosoOA/libs/s8phirs_10r/bkeep_p/verilog/verilog.v s8/V2.0.1/VirtuosoOA/libs/tech/bkeep_p/verilog/verilog.v	--fromfile--	
bleeder	scs8hd scs8ls		Current bleeder (weak pulldown to ground)	
buf	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Buffer	
bufbuf	scs8hd scs8hs scs8lp scs8ls scs8ms		Double buffer	
bufinv	scs8hd scs8hs scs8lp scs8ls scs8ms		Buffer followed by inverter	
bufkapwr	scs8lp		Buffer on keep-alive power rail	
buflp	scs8lp		Buffer, Low Power	
busdriver	scs8lp		Bus driver (pmoshvt devices)	
busdriver2	scs8lp		Bus driver (pmos devices)	
busdrivernovlp	scs8lp		Bus driver, enable gates pulldown only (pmoshvt devices)	
busdrivernovlp2	scs8lp		Bus driver, enable gates pulldown only (pmos devices)	
busdrivernovlpsleep	scs8lp		Bus driver, enable gates pulldown only, non-inverted sleep input (on kapwr rail)	
bushold	scs8lp		Bus signal holder (back-to-back inverter) with noninverting reset (gates output driver)	
bushold0	scs8lp		Bus signal holder (back-to-back inverter) with noninverting reset (gates internal node weak driver)	
busreceiver	scs8lp		Bus signal receiver	
clkbuf	scs8hd scs8hs scs8lp scs8ls scs8ms		Clock tree buffer	
clkbufkapwr	scs8hd scs8ls		Clock tree buffer on keep-alive power rail	
clkbuflp	scs8lp		Clock tree buffer, Low Power	
clkdlybuf4s15	scs8hd scs8lp		Clock Delay Buffer 4-stage 0.15um length inner stage gates	
clkdlybuf4s18	scs8hd scs8lp		Clock Delay Buffer 4-stage 0.18um length inner stage gates	
clkdlybuf4s25	scs8hd scs8lp		Clock Delay Buffer 4-stage 0.25um length inner stage gates	
clkdlybuf4s50	scs8hd scs8lp		Clock Delay Buffer 4-stage 0.59um length inner stage gates	
clkdlyinv3sd1	scs8hs scs8ls scs8ms		Clock Delay Inverter 3-stage 0.15um length inner stage gate	
clkdlyinv3sd2	scs8hs scs8ls scs8ms		Clock Delay Inverter 3-stage 0.25um length inner stage gate	
clkdlyinv3sd3	scs8hs scs8ls scs8ms		Clock Delay Inverter 3-stage 0.50um length inner stage gate	
clkdlyinv5sd1	scs8hs scs8ls scs8ms		Clock Delay Inverter 5-stage 0.15um length inner stage gate	
clkdlyinv5sd2	scs8hs scs8ls scs8ms		Clock Delay Inverter 5-stage 0.25um length inner stage gate	
clkdlyinv5sd3	scs8hs scs8ls scs8ms		Clock Delay Inverter 5-stage 0.50um length inner stage gate	
clkinv	scs8hd scs8hs scs8lp scs8ls scs8ms		Clock tree inverter	
clkinvkapwr	scs8hd scs8ls		Clock tree inverter on keep-alive rail	
clkinvlp	scs8hd scs8lp		Lower power Clock tree inverter	
clkmux2			Clock mux	
conb	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Constant value, low, high outputs	
csw_p	s8 s8phirs_10r	s8/V1.0.0/VirtuosoOA/libs/s8phirs_10r/csw_p/verilog/verilog.v s8/V1.0.0/VirtuosoOA/libs/tech/csw_p/verilog/verilog.v s8/V1.0.1/VirtuosoOA/libs/s8phirs_10r/csw_p/verilog/verilog.v s8/V1.0.1/VirtuosoOA/libs/tech/csw_p/verilog/verilog.v s8/V1.1.0/VirtuosoOA/libs/s8phirs_10r/csw_p/verilog/verilog.v s8/V1.1.0/VirtuosoOA/libs/tech/csw_p/verilog/verilog.v s8/V1.2.0/VirtuosoOA/libs/s8phirs_10r/csw_p/verilog/verilog.v s8/V1.2.0/VirtuosoOA/libs/tech/csw_p/verilog/verilog.v s8/V1.2.1/VirtuosoOA/libs/s8phirs_10r/csw_p/verilog/verilog.v s8/V1.2.1/VirtuosoOA/libs/tech/csw_p/verilog/verilog.v s8/V1.3.0/VirtuosoOA/libs/s8phirs_10r/csw_p/verilog/verilog.v s8/V1.3.0/VirtuosoOA/libs/s8phirs_10r_old/csw_p/verilog/verilog.v s8/V1.3.0/VirtuosoOA/libs/tech/csw_p/verilog/verilog.v s8/V2.0.0/VirtuosoOA/libs/s8phirs_10r/csw_p/verilog/verilog.v s8/V2.0.0/VirtuosoOA/libs/tech/csw_p/verilog/verilog.v s8/V2.0.1/VirtuosoOA/libs/s8phirs_10r/csw_p/verilog/verilog.v s8/V2.0.1/VirtuosoOA/libs/tech/csw_p/verilog/verilog.v	--fromfile--	
decap	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Decoupling capacitance filler	
decaphe	scs8ls		Shielded Decoupling capacitance filler	
decaphekapwr	scs8ls		Shielded Decoupling capacitance filler on keep-alive power rail	
decapkapwr	scs8hd scs8lp scs8ls		Decoupling capacitance filler on keep-alive rail	
dfbbn	scs8hd scs8hs scs8lp scs8ls scs8ms		Delay flop, inverted set, inverted reset, inverted clock, complementary outputs	
dfbbp	scs8hd scs8hs scs8lp scs8ls scs8ms		Delay flop, inverted set, inverted reset, complementary outputs	
dfrbp	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Delay flop, inverted reset, complementary outputs	
dfrtn	scs8hd scs8hs scs8lp scs8ls scs8ms		Delay flop, inverted reset, inverted clock, complementary outputs	
dfrtp	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Delay flop, inverted reset, single output	
dfsbp	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Delay flop, inverted set, complementary outputs	
dfstp	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Delay flop, inverted set, single output	
dfxbp	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Delay flop, complementary outputs	
dfxtp	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Delay flop, single output	
diode	scs8hd scs8hvl scs8lp scs8ls		Antenna tie-down diode	
dlclkp	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Clock gate	
dlrbn	scs8hd scs8hs scs8lp scs8ls scs8ms		Delay latch, inverted reset, inverted enable, complementary outputs	
dlrbp	scs8hd scs8hs scs8lp scs8ls scs8ms		Delay latch, inverted reset, non-inverted enable, complementary outputs	
dlrtn	scs8hd scs8hs scs8lp scs8ls scs8ms		Delay latch, inverted reset, inverted enable, single output	
dlrtp	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Delay latch, inverted reset, non-inverted enable, single output	
dlxbn	scs8hd scs8hs scs8lp scs8ls scs8ms		Delay latch, inverted enable, complementary outputs	
dlxbp	scs8hd scs8hs scs8lp scs8ls scs8ms		Delay latch, non-inverted enable, complementary outputs	
dlxtn	scs8hd scs8hs scs8lp scs8ls scs8ms		Delay latch, inverted enable, single output	
dlxtp	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Delay latch, non-inverted enable, single output	
dlybuf4s15kapwr	scs8lp		Delay Buffer 4-stage 0.15um length inner stage gates on keep-alive power rail	
dlybuf4s18kapwr	scs8lp		Delay Buffer 4-stage 0.18um length inner stage gates on keep-alive power rail	
dlybuf4s25kapwr	scs8lp		Delay Buffer 4-stage 0.25um length inner stage gates on keep-alive power rail	
dlybuf4s50kapwr	scs8lp		Delay Buffer 4-stage 0.50um length inner stage gates on keep-alive power rail	
dlygate4s15	scs8lp		Delay Buffer 4-stage 0.15um length inner stage gates	
dlygate4s18	scs8lp		Delay Buffer 4-stage 0.18um length inner stage gates	
dlygate4s50	scs8lp		Delay Buffer 4-stage 0.50um length inner stage gates	
dlygate4sd1	scs8hd scs8hs scs8ls scs8ms		Delay Buffer 4-stage 0.15um length inner stage gates	
dlygate4sd2	scs8hd scs8hs scs8ls scs8ms		Delay Buffer 4-stage 0.18um length inner stage gates	
dlygate4sd3	scs8hd scs8hs scs8ls scs8ms		Delay Buffer 4-stage 0.50um length inner stage gates	
dlymetal6s2s	scs8hd scs8hs scs8lp scs8ls scs8ms		6-inverter delay with output from 2nd stage on horizontal route	
dlymetal6s4s	scs8hd scs8hs scs8lp scs8ls scs8ms		6-inverter delay with output from 4th inverter on horizontal route	
dlymetal6s6s	scs8hd scs8hs scs8lp scs8ls scs8ms		6-inverter delay with output from 6th inverter on horizontal route	
ebufn	scs8hd scs8hs scs8lp scs8ls scs8ms		Tri-state buffer, negative enable	
edfxbp	scs8hd scs8hs scs8lp scs8ls scs8ms		Delay flop with loopback enable, non-inverted clock, complementary outputs	
edfxtp	scs8hd scs8hs scs8ls scs8ms		Delay flop with loopback enable, non-inverted clock, single output	
einv_p	s8 s8phirs_10r	s8/V1.0.0/VirtuosoOA/libs/s8phirs_10r/einv_p/verilog/verilog.v s8/V1.0.0/VirtuosoOA/libs/tech/einv_p/verilog/verilog.v s8/V1.0.1/VirtuosoOA/libs/s8phirs_10r/einv_p/verilog/verilog.v s8/V1.0.1/VirtuosoOA/libs/tech/einv_p/verilog/verilog.v s8/V1.1.0/VirtuosoOA/libs/s8phirs_10r/einv_p/verilog/verilog.v s8/V1.1.0/VirtuosoOA/libs/tech/einv_p/verilog/verilog.v s8/V1.2.0/VirtuosoOA/libs/s8phirs_10r/einv_p/verilog/verilog.v s8/V1.2.0/VirtuosoOA/libs/tech/einv_p/verilog/verilog.v s8/V1.2.1/VirtuosoOA/libs/s8phirs_10r/einv_p/verilog/verilog.v s8/V1.2.1/VirtuosoOA/libs/tech/einv_p/verilog/verilog.v s8/V1.3.0/VirtuosoOA/libs/s8phirs_10r/einv_p/verilog/verilog.v s8/V1.3.0/VirtuosoOA/libs/s8phirs_10r_old/einv_p/verilog/verilog.v s8/V1.3.0/VirtuosoOA/libs/tech/einv_p/verilog/verilog.v s8/V2.0.0/VirtuosoOA/libs/s8phirs_10r/einv_p/verilog/verilog.v s8/V2.0.0/VirtuosoOA/libs/tech/einv_p/verilog/verilog.v s8/V2.0.1/VirtuosoOA/libs/s8phirs_10r/einv_p/verilog/verilog.v s8/V2.0.1/VirtuosoOA/libs/tech/einv_p/verilog/verilog.v	--fromfile--	
einvn	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Tri-state inverter, negative enable	
einvp	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Tri-state inverter, positive enable	
fa	scs8hd scs8hs scs8lp scs8ls scs8ms		Full adder	
fah	scs8hd scs8hs scs8lp scs8ls scs8ms		Full adder	
fahcin	scs8hd scs8hs scs8lp scs8ls scs8ms		Full adder, inverted carry in	
fahcon	scs8hd scs8hs scs8lp scs8ls scs8ms		Full adder, inverted carry in, inverted carry out	
fuse	s8 s8phirs_10r	s8/V1.0.0/VirtuosoOA/libs/s8phirs_10r/fuse/verilog/verilog.v s8/V1.0.0/VirtuosoOA/libs/tech/fuse/verilog/verilog.v s8/V1.0.1/VirtuosoOA/libs/s8phirs_10r/fuse/verilog/verilog.v s8/V1.0.1/VirtuosoOA/libs/tech/fuse/verilog/verilog.v s8/V1.1.0/VirtuosoOA/libs/s8phirs_10r/fuse/verilog/verilog.v s8/V1.1.0/VirtuosoOA/libs/tech/fuse/verilog/verilog.v s8/V1.2.0/VirtuosoOA/libs/s8phirs_10r/fuse/verilog/verilog.v s8/V1.2.0/VirtuosoOA/libs/tech/fuse/verilog/verilog.v s8/V1.2.1/VirtuosoOA/libs/s8phirs_10r/fuse/verilog/verilog.v s8/V1.2.1/VirtuosoOA/libs/tech/fuse/verilog/verilog.v s8/V1.3.0/VirtuosoOA/libs/s8phirs_10r/fuse/verilog/verilog.v s8/V1.3.0/VirtuosoOA/libs/s8phirs_10r_old/fuse/verilog/verilog.v s8/V1.3.0/VirtuosoOA/libs/tech/fuse/verilog/verilog.v s8/V2.0.0/VirtuosoOA/libs/s8phirs_10r/fuse/verilog/verilog.v s8/V2.0.0/VirtuosoOA/libs/tech/fuse/verilog/verilog.v s8/V2.0.1/VirtuosoOA/libs/s8phirs_10r/fuse/verilog/verilog.v s8/V2.0.1/VirtuosoOA/libs/tech/fuse/verilog/verilog.v	--fromfile--	
fuse_lod	s8phirs_10r	s8/V2.0.0/VirtuosoOA/libs/s8phirs_10r/fuse_lod/verilog/verilog.v s8/V2.0.1/VirtuosoOA/libs/s8phirs_10r/fuse_lod/verilog/verilog.v	--fromfile--	
gnd2gnd_120x2_lv	s8_esd			
gnd2gnd_120x2_lv_isosub	s8_esd			
ha	scs8hd scs8hs scs8lp scs8ls scs8ms		Half adder	
inputiso0n	scs8hd		Input isolator with inverted enable	X = (A & SLEEP_B)
inputiso0p	scs8hd		Input isolator with non-inverted enable	X = (A & !SLEEP_B)
inputiso1n	scs8hd		Input isolation, inverted sleep	X = (A & SLEEP_B)
inputiso1p	scs8hd		Input isolation, noninverted sleep	X = (A & !SLEEP)
iso0n			????	
iso0p			????	
iso1n			????	
iso1p			????	
inputisolatch	scs8hd		Latching input isolator with inverted enable	
isolatch			????	
inv	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Inverter	
invkapwr	scs8lp		Inverter on keep-alive power rail	
invlp	scs8lp		Low Power Inverter 	
isobufsrc	scs8hd scs8lp scs8ls		Input isolation, noninverted sleep	X = (!A | SLEEP)
isobufsrckapwr	scs8hd scs8ls		Input isolation, noninverted sleep on keep-alive power rail	X = (!A | SLEEP) 
localdiode_hv	s8_esd		Can find no reference to this.	
localdiode_lv	s8_esd		Can find no reference to this.	
lsbuf			????	
lsbufiso0p			????	
lsbufiso1p			????	
lsbuf_hl	scs8ls		Level-shift buffer, high-to-low	
lsbuf_lh	scs8ls		Level-shift buffer, low-to-high	
lsbuf_lh_hl_isowell_tap	scs8hd		Level-shift buffer, low-to-high, isolated well on input buffer, vpb/vnb taps, double-row-height cell	
lsbuf_lh_isowell	scs8hd scs8ls		Level-shift buffer, low-to-high, isolated well on input buffer, no taps, double-row-height cell	
lsbuf_lh_isowell_tap	scs8hd scs8ls		Level-shift buffer, low-to-high, isolated well on input buffer, vpb/vnb taps, double-row-height cell	
lsbufhv2hv_hl	scs8hvl		Level shifting buffer, High Voltage to High Voltage, Higher Voltage to Lower Voltage	
lsbufhv2hv_lh	scs8hvl		Level shifting buffer, High Voltage to High Voltage, Lower Voltage to Higher Voltage	
lsbufhv2lv	scs8hvl		Level-shift buffer, low voltage-to-low voltage	
lsbufhv2lv_inputiso	scs8hvl		Level shifting buffer, High Voltage to Low Voltage, Input Isolating	
lsbufhv2lv_simple	scs8hvl		Level shifting buffer, High Voltage to Low Voltage, simple (hv devices in inverters on lv power rail)	
lsbuflv2hv	scs8hvl		Level-shift buffer, low voltage-to-high voltage, isolated well on input buffer, double height cell	
lsbuflv2hv_clkiso_hlkg	scs8hvl		Level-shift clock buffer, low voltage to high voltage, isolated well on input buffer, inverting sleep mode input	
lsbuflv2hv_isosrchvaon	scs8hvl		Level shift buffer, low voltage to high voltage, isolated well on input buffer, inverting sleep mode input, zero power sleep mode	
lsbuflv2hv_symmetric	scs8hvl		Level shifting buffer, Low Voltage to High Voltage, Symmetrical	
macro_sparecell	scs8hd scs8ls		Macro cell for metal-mask-only revisioning, containing inverter, 2-input NOR, 2-input NAND, and constant cell.	
maj3	scs8hd scs8hs scs8lp scs8ls scs8ms		3-input majority vote	
mux2	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		2-input multiplexer	
mux2i	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input multiplexer, output inverted	
mux4	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		4-input multiplexer	
muxb4to1			Buffered 4-input multiplexer	
muxb8to1			Buffered 8-input multiplexer	
muxb16to1			Buffered 16-input multiplexer	
nand2	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		2-input NAND	
nand2b	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input NAND, first input inverted	
nand3	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		3-input NAND	
nand3b	scs8hd scs8hs scs8lp scs8ls scs8ms		3-input NAND, first input inverted	
nand4	scs8hd scs8hs scs8lp scs8ls scs8ms		4-input NAND	
nand4b	scs8hd scs8hs scs8lp scs8ls scs8ms		4-input NAND, first input inverted	
nand4bb	scs8hd scs8hs scs8lp scs8ls scs8ms		4-input NAND, first two inputs inverted	
nor2	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		2-input NOR	
nor2b	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input NOR, first input inverted	!(A | B | C | !D)
nor3	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		3-input NOR	!(A | B | C | !D)
nor3b	scs8hd scs8hs scs8lp scs8ls scs8ms		3-input NOR, first input inverted	(!(A | B)) & !C)
nor4	scs8hd scs8hs scs8lp scs8ls scs8ms		4-input NOR	!(A | B | C | D)
nor4b	scs8hd scs8hs scs8lp scs8ls scs8ms		4-input NOR, first input inverted	
nor4bb	scs8hd scs8hs scs8lp scs8ls scs8ms		4-input NOR, first two inputs inverted	
o2111a	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input OR into first input of 4-input AND 	((A1 | A2) & B1 & C1 & D1)
o2111ai	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input OR into first input of 4-input NAND 	!((A1 | A2) & B1 & C1 & D1)
o211a	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input OR into first input of 3-input AND 	((A1 | A2) & B1 & C1)
o211ai	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input OR into first input of 3-input NAND 	!((A1 | A2) & B1 & C1)
o21a	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		2-input OR into first input of 2-input AND 	((A1 | A2) & B1)
o21ai	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		2-input OR into first input of 2-input NAND 	!((A1 | A2) & B1)
o21ba	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input OR into first input of 2-input AND, 2nd input inverted 	((A1 | A2) & !B1N)
o21bai	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input OR into first input of 2-input NAND, 2nd iput inverted 	!((A1 | A2) & !B1N)
o221a	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input OR into first two inputs of 3-input AND 	((A1 | A2) & (B1 | B2) & C1)
o221ai	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input OR into first two inputs of 3-input NAND 	!((A1 | A2) & (B1 | B2) & C1)
o22a	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		2-input OR into both inputs of 2-input AND 	((A1 | A2) & (B1 | B2))
o22ai	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		2-input OR into both inputs of 2-input NAND 	!((A1 | A2) & (B1 | B2))
o2bb2a	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input NAND and 2-input OR into 2-input AND	(!(A1 & A2) & (B1 | B2))
o2bb2ai	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input NAND and 2-input OR into 2-input NAND	!(!(A1 & A2) & (B1 | B2))
o311a	scs8hd scs8hs scs8lp scs8ls scs8ms		3-input OR into 3-input AND 	((A1 | A2 | A3) & B1 & C1)
o311ai	scs8hd scs8hs scs8lp scs8ls scs8ms		3-input OR into 3-input NAND 	!((A1 | A2 | A3) & B1 & C1)
o31a	scs8hd scs8hs scs8lp scs8ls scs8ms		3-input OR into 2-input AND 	((A1 | A2 | A3) & B1)
o31ai	scs8hd scs8hs scs8lp scs8ls scs8ms		3-input OR into 2-input NAND 	!((A1 | A2 | A3) & B1)
o32a	scs8hd scs8hs scs8lp scs8ls scs8ms		3-input OR and 2-input OR into 2-input AND  	((A1 | A2 | A3) & (B1 | B2))
o32ai	scs8hd scs8hs scs8lp scs8ls scs8ms		3-input OR and 2-input OR into 2-input NAND 	!((A1 | A2 | A3) & (B1 | B2))
o41a	scs8hd scs8hs scs8lp scs8ls scs8ms		4-input OR into 2-input AND 	((A1 | A2 | A3 | A4) & B1)
o41ai	scs8hd scs8hs scs8lp scs8ls scs8ms		4-input OR into 2-input NAND 	!((A1 | A2 | A3 | A4) & B1)
or2	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		2-input OR	
or2b	scs8hd scs8hs scs8lp scs8ls scs8ms		2-input OR, first input inverted	
or3	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		3-input OR	
or3b	scs8hd scs8hs scs8lp scs8ls scs8ms		3-input OR, first input inverted	
or4	scs8hd scs8hs scs8lp scs8ls scs8ms		4-input OR	
or4b	scs8hd scs8hs scs8lp scs8ls scs8ms		4-input OR, first input inverted	
or4bb	scs8hd scs8hs scs8lp scs8ls scs8ms		4-input OR, first two inputs inverted	
overlay_vccd_hvc	s8iom0s8		I/O overlay, connects pad to VCCD domain, for use with high voltage clamp cells	
overlay_vccd_lvc	s8iom0s8		I/O overlay, connects pad to VCCD domain, for use with low voltage clamp cells	
overlay_vdda_hvc	s8iom0s8			
overlay_vdda_lvc	s8iom0s8			
overlay_vddio_hvc	s8iom0s8			
overlay_vddio_lvc	s8iom0s8			
overlay_vssa_hvc	s8iom0s8			
overlay_vssa_lvc	s8iom0s8			
overlay_vssd_hvc	s8iom0s8			
overlay_vssd_lvc	s8iom0s8			
overlay_vssio_hvc	s8iom0s8			
overlay_vssio_lvc	s8iom0s8			
paddiode2gnd_100_dnwl_hv	s8_esd			
paddiode2gnd_100_dnwl_hv_okika	s8_esd			
paddiode2gnd_100_dnwl_hv_okika2	s8_esd			
paddiode2gnd_100_dnwl_hv_okika3	s8_esd			
paddiode2gnd_100_dnwl_hv_orig	s8_esd			
paddiode2gnd_100_hv	s8_esd			
paddiode2gnd_200_dnwl_hv	s8_esd			
paddiode2gnd_200_dnwl_hv_okika	s8_esd			
paddiode2gnd_200_dnwl_hv_orig	s8_esd			
paddiode2gnd_200_hv	s8_esd			
paddiode2gnd_300_dnwl_hv	s8_esd			
paddiode2gnd_300_dnwl_hv_okika	s8_esd			
paddiode2gnd_300_hv	s8_esd			
paddiode2pwr_100_hv	s8_esd	s8iom0s8/V0.1.0/verilog/s8iom0s8_sio_paddiode2pwr_100_hv.v s8iom0s8/V0.2.0/verilog/s8iom0s8_sio_paddiode2pwr_100_hv.v s8iom0s8/V0.2.1/verilog/s8iom0s8_sio_paddiode2pwr_100_hv.v	--fromfile--	
paddiode2pwr_200_hv	s8_esd			
paddiode2pwr_300_hv	s8_esd	s8iom0s8/V0.1.0/verilog/s8iom0s8_sio_paddiode2pwr_300_hv.v s8iom0s8/V0.2.0/verilog/s8iom0s8_sio_paddiode2pwr_300_hv.v s8iom0s8/V0.2.1/verilog/s8iom0s8_sio_paddiode2pwr_300_hv.v	--fromfile--	
pg_U_DF_N_R_NO_SLEEPB_pg	scs8ls	scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DF_N_R_NO_SLEEPB_pg.v	--fromfile--	
pg_U_DF_P	scs8hd scs8hvl scs8ls scs8ms	scs8hd/V0.0.1/verilog/scs8hd_pg_U_DF_P.v scs8hvl/V0.0.0/verilog/scs8hvl_pg_U_DF_P.v scs8hvl/V0.0.1/verilog/scs8hvl_pg_U_DF_P.v scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DF_P.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_DF_P.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_DF_P.v	--fromfile--	
pg_U_DF_P_NO_pg	scs8hd scs8hvl scs8ls scs8ms	scs8hd/V0.0.1/verilog/scs8hd_pg_U_DF_P_NO_pg.v scs8hvl/V0.0.0/verilog/scs8hvl_pg_U_DF_P_NO_pg.v scs8hvl/V0.0.1/verilog/scs8hvl_pg_U_DF_P_NO_pg.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_DF_P_NO_pg.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_DF_P_NO_pg.v	--fromfile--	
pg_U_DF_P_NO_SLEEPB_pg	scs8ls	scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DF_P_NO_SLEEPB_pg.v	--fromfile--	
pg_U_DF_P_R	scs8hd scs8hvl scs8ls scs8ms	scs8hd/V0.0.1/verilog/scs8hd_pg_U_DF_P_R.v scs8hvl/V0.0.0/verilog/scs8hvl_pg_U_DF_P_R.v scs8hvl/V0.0.1/verilog/scs8hvl_pg_U_DF_P_R.v scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DF_P_R.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_DF_P_R.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_DF_P_R.v	--fromfile--	
pg_U_DF_P_R_NO_pg	scs8hd scs8hvl scs8ls scs8ms	scs8hd/V0.0.1/verilog/scs8hd_pg_U_DF_P_R_NO_pg.v scs8hvl/V0.0.0/verilog/scs8hvl_pg_U_DF_P_R_NO_pg.v scs8hvl/V0.0.1/verilog/scs8hvl_pg_U_DF_P_R_NO_pg.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_DF_P_R_NO_pg.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_DF_P_R_NO_pg.v	--fromfile--	
pg_U_DF_P_R_NO_SLEEPB_pg	scs8ls	scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DF_P_R_NO_SLEEPB_pg.v	--fromfile--	
pg_U_DF_P_S	scs8hd scs8hvl scs8ls scs8ms	scs8hd/V0.0.1/verilog/scs8hd_pg_U_DF_P_S.v scs8hvl/V0.0.0/verilog/scs8hvl_pg_U_DF_P_S.v scs8hvl/V0.0.1/verilog/scs8hvl_pg_U_DF_P_S.v scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DF_P_S.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_DF_P_S.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_DF_P_S.v	--fromfile--	
pg_U_DF_P_S_NO_pg	scs8hd scs8hvl scs8ls scs8ms	scs8hd/V0.0.1/verilog/scs8hd_pg_U_DF_P_S_NO_pg.v scs8hvl/V0.0.0/verilog/scs8hvl_pg_U_DF_P_S_NO_pg.v scs8hvl/V0.0.1/verilog/scs8hvl_pg_U_DF_P_S_NO_pg.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_DF_P_S_NO_pg.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_DF_P_S_NO_pg.v	--fromfile--	
pg_U_DF_P_S_NO_SLEEPB_pg	scs8ls	scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DF_P_S_NO_SLEEPB_pg.v	--fromfile--	
pg_U_DFB	scs8ls			
pg_U_DFB_SETDOM	scs8hd scs8ls scs8ms			
pg_U_DFB_SETDOM_NO_pg	scs8hd scs8ls scs8ms			
pg_U_DL_P	scs8hd scs8hvl scs8ls scs8ms	scs8hd/V0.0.1/verilog/scs8hd_lpflow_pg_U_DL_P.v scs8hd/V0.0.1/verilog/scs8hd_pg_U_DL_P.v scs8hvl/V0.0.0/verilog/scs8hvl_pg_U_DL_P.v scs8hvl/V0.0.1/verilog/scs8hvl_pg_U_DL_P.v scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DL_P.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_DL_P.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_DL_P.v	--fromfile--	
pg_U_DL_P_NO_pg	scs8hd scs8hvl scs8ls scs8ms	scs8hd/V0.0.1/verilog/scs8hd_lpflow_pg_U_DL_P_NO_pg.v scs8hd/V0.0.1/verilog/scs8hd_pg_U_DL_P_NO_pg.v scs8hvl/V0.0.0/verilog/scs8hvl_pg_U_DL_P_NO_pg.v scs8hvl/V0.0.1/verilog/scs8hvl_pg_U_DL_P_NO_pg.v scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DL_P_NO_pg.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_DL_P_NO_pg.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_DL_P_NO_pg.v	--fromfile--	
pg_U_DL_P_NO_SLEEPB_pg	scs8ls	scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DL_P_NO_SLEEPB_pg.v	--fromfile--	
pg_U_DL_P_R	scs8hd scs8hvl scs8ls scs8ms	scs8hd/V0.0.1/verilog/scs8hd_pg_U_DL_P_R.v scs8hvl/V0.0.0/verilog/scs8hvl_pg_U_DL_P_R.v scs8hvl/V0.0.1/verilog/scs8hvl_pg_U_DL_P_R.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_DL_P_R.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_DL_P_R.v	--fromfile--	
pg_U_DL_P_R_NO_pg	scs8hd scs8hvl scs8ls scs8ms	scs8hd/V0.0.1/verilog/scs8hd_pg_U_DL_P_R_NO_pg.v scs8hvl/V0.0.0/verilog/scs8hvl_pg_U_DL_P_R_NO_pg.v scs8hvl/V0.0.1/verilog/scs8hvl_pg_U_DL_P_R_NO_pg.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_DL_P_R_NO_pg.v scs8ls/V0.1.0/verilog/scs8ls_udb_pg_U_DL_P_R_NO_pg.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_DL_P_R_NO_pg.v	--fromfile--	
pg_U_DL_P_R_NO_SLEEPB_pg	scs8ls	scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DL_P_R_NO_SLEEPB_pg.v	--fromfile--	
pg_U_DL_P_S	scs8ls	scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DL_P_S.v	--fromfile--	
pg_U_DL_P_S_NO_SLEEPB_pg	scs8ls	scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DL_P_S_NO_SLEEPB_pg.v	--fromfile--	
pg_U_isosrchvaon	scs8hvl			
pg_U_MUX_2	scs8hd scs8hvl scs8ls scs8ms			
pg_U_MUX_2_1_INV	scs8hd scs8ls scs8ms	scs8hd/V0.0.1/verilog/scs8hd_pg_U_MUX_2_1_INV.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_MUX_2_1_INV.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_MUX_2_1_INV.v	--fromfile--	
pg_U_MUX_4	scs8hd scs8hvl scs8ls scs8ms			
pg_U_VGND	scs8hd scs8hvl scs8ls scs8ms			
pg_U_VPWR	scs8hd scs8hvl scs8ls scs8ms			
pg_U_VPWR_VGND	scs8hd scs8hvl scs8ls scs8ms			
pg_U_VPWR_VGND_SLEEP	scs8hd scs8ls			
probe_s8p	scs8hd scs8hvl scs8ls		Virtual voltage probe point	
probec_s8p	scs8hd scs8hvl scs8ls		Virtual current probe point	
pwr2gnd_50_casc_sym_hv_2k	s8_esd			
pwr2gnd_50_casc_sym_hv_2k_dnwl	s8_esd			
pwr2gnd_50_casc_sym_hv_2k_dnwl_aup1	s8_esd			
pwr2gnd_rc_21_asym_hv_2k	s8_esd			
pwr2gnd_rc_21_sym_hv_2k	s8_esd			
pwr2gnd_rc_40_asym_lv_2k	s8_esd			
pwr2gnd_rc_40_asym_lv_2k_aup1	s8_esd			
pwr2gnd_rc_40_asym_lv_2k_aup1_revA	s8_esd			
pwr2gnd_rc_40_asym_lv_2k_dnwl	s8_esd			
pwr2gnd_rc_40_asym_lv_2k_dnwl_aup	s8_esd			
pwr2gnd_rc_40_asym_lv_2k_dnwl_aup_revB1	s8_esd			
pwr2gnd_rc_40_asym_lv_2k_dnwl_aup1	s8_esd			
pwr2gnd_rc_40_asym_lv_2k_dnwl_revA	s8_esd			
pwr2gnd_rc_40_asym_lv_2k_revA	s8_esd			
pwr2gnd_rc_40_asym_lv_2k_revA_InsideCore	s8_esd			
pwr2gnd_rc_40_asym_lv_2k_revA_west	s8_esd			
pwr2gnd_rc_40_asym_lv_2k_revB_north	s8_esd			
pwr2gnd_rc_40_asym_lv_4k	s8_esd			
pwr2gnd_rc_40_sym_hv_2k	s8_esd			
pwr2gnd_rc_40_sym_hv_2k_dnwl_aup	s8_esd			
pwr2gnd_rc_40_sym_hv_2k_dnwl_aup_revB1	s8_esd			
pwr2gnd_rc_40_sym_hv_2k_revA	s8_esd			
pwr2gnd_rc_40_sym_hv_2k_revB	s8_esd			
pwr2gnd_rc_50_asym_hv_4k	s8_esd			
pwr2gnd_rc_50_sym_hv_2k	s8_esd			
pwr2gnd_rc_50_sym_hv_2k_aup1	s8_esd			
pwr2gnd_rc_50_sym_hv_2k_aup1_b	s8_esd			
pwr2gnd_rc_50_sym_hv_2k_aup1_b_revA	s8_esd			
pwr2gnd_rc_50_sym_hv_2k_aup1_b_revB_north	s8_esd			
pwr2gnd_rc_50_sym_hv_2k_aup1_c	s8_esd			
pwr2gnd_rc_50_sym_hv_2k_aup1_c_revB_south	s8_esd			
pwr2gnd_rc_50_sym_hv_2k_aup1_revB_south	s8_esd			
pwr2gnd_rc_50_sym_hv_2k_dnwl	s8_esd			
pwr2gnd_rc_50_sym_hv_2k_dnwl_aup	s8_esd			
pwr2gnd_rc_50_sym_hv_2k_dnwl_aup_3c_50k	s8_esd			
pwr2gnd_rc_50_sym_hv_2k_dnwl_aup_3c_5k	s8_esd			
pwr2gnd_rc_50_sym_hv_2k_dnwl_aup_6c_27k	s8_esd			
pwr2gnd_rc_50_sym_hv_2k_dnwl_aup_6c_50k	s8_esd			
pwr2gnd_rc_50_sym_hv_2k_dnwl_aup_6c_5k	s8_esd			
pwr2gnd_rc_50_sym_hv_2k_dnwl_aup_revB1	s8_esd			
pwr2gnd_rc_50_sym_hv_2k_dnwl_revA	s8_esd			
pwr2gnd_rc_50_sym_hv_2k_revA	s8_esd			
pwr2gnd_rc_50_sym_hv_2k_revB_SouthEastWest	s8_esd			
pwr2gnd_rc_50_sym_hv_4k	s8_esd			
pwr2gnd_rc_50_sym_hv_4k_aup1	s8_esd			
pwr2pwr_21_sym_hv_2k	s8_esd			
pwr2pwr_40_1p3_1p3_hv_2k	s8_esd			
pwr2pwr_40_1p3_1p3_lv_2k	s8_esd			
pwr2pwr_40_1p3_1p3_lv_2k_b	s8_esd			
pwr2pwr_40_1p3_1p3_lv_2k_dnwl	s8_esd			
pwr2pwr_40_sym_hv_2k	s8_esd			
pwr2pwr_40_sym_hv_2k_aup1	s8_esd			
pwr2pwr_50_sym_hv_2k	s8_esd			
pwr2pwr_50_sym_hv_2k_aup1	s8_esd			
res250	s8_esd		250 xxOhm Resistor	
res250only	s8_esd			
res250only_small	s8_esd			
res75only	s8_esd		75 xxOhm Resistor	
res75only_noshorts	s8_esd			
res75only_noshorts_nometal	s8_esd			
res75only_small	s8_esd			
schmittbuf	scs8hvl		Schmitt Trigger Buffer	
scs8hdll	scs8hdll	scs8hdll/V0.1.0/verilog/scs8hdll.v	--fromfile--	
sdfbbn	scs8hd scs8hs scs8lp scs8ls scs8ms		Scan delay flop, inverted set, inverted reset, inverted clock, complementary outputs	
sdfbbp	scs8hd scs8hs scs8lp scs8ls scs8ms		Scan delay flop, inverted set, inverted reset, non-inverted clock, complementary outputs	
sdfrbp	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Scan delay flop, inverted reset, non-inverted clock, complementary outputs	
sdfrtn	scs8hd scs8hs scs8lp scs8ls scs8ms		Scan delay flop, inverted reset, inverted clock, single output	
sdfrtp	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Scan delay flop, inverted reset, non-inverted clock, single output	
sdfrtp_ov2	scs8lp		????	
sdfrtp2	scs8hvl		????	
sdfsbp	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Scan delay flop, inverted set, non-inverted clock, complementary outputs	
sdfstp	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Scan delay flop, inverted set, non-inverted clock, single output	
sdfxbp	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Scan delay flop, non-inverted clock, complementary outputs	
sdfxtp	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Scan delay flop, non-inverted clock, single output	
sdlclkp	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		Scan gated clock	
sdlxtp	scs8hvl		????	
sedfxbp	scs8hd scs8hs scs8ls scs8ms		Scan delay flop, data enable, non-inverted clock, complementary outputs	
sedfxtp	scs8hd scs8hs scs8ls scs8ms		Scan delay flop, data enable, non-inverted clock, single output	
short	s8 s8phirs_10r	s8/V1.0.0/VirtuosoOA/libs/s8phirs_10r/short/verilog/verilog.v s8/V1.0.0/VirtuosoOA/libs/tech/short/verilog/verilog.v s8/V1.0.1/VirtuosoOA/libs/s8phirs_10r/short/verilog/verilog.v s8/V1.0.1/VirtuosoOA/libs/tech/short/verilog/verilog.v s8/V1.1.0/VirtuosoOA/libs/s8phirs_10r/short/verilog/verilog.v s8/V1.1.0/VirtuosoOA/libs/tech/short/verilog/verilog.v s8/V1.2.0/VirtuosoOA/libs/s8phirs_10r/short/verilog/verilog.v s8/V1.2.0/VirtuosoOA/libs/tech/short/verilog/verilog.v s8/V1.2.1/VirtuosoOA/libs/s8phirs_10r/short/verilog/verilog.v s8/V1.2.1/VirtuosoOA/libs/tech/short/verilog/verilog.v s8/V1.3.0/VirtuosoOA/libs/s8phirs_10r/short/verilog/verilog.v s8/V1.3.0/VirtuosoOA/libs/s8phirs_10r_old/short/verilog/verilog.v s8/V1.3.0/VirtuosoOA/libs/tech/short/verilog/verilog.v s8/V2.0.0/VirtuosoOA/libs/s8phirs_10r/short/verilog/verilog.v s8/V2.0.0/VirtuosoOA/libs/tech/short/verilog/verilog.v s8/V2.0.1/VirtuosoOA/libs/s8phirs_10r/short/verilog/verilog.v s8/V2.0.1/VirtuosoOA/libs/tech/short/verilog/verilog.v	--fromfile--	
signal_23_asym_hv_2k	s8_esd			
signal_23_asym_hv_2k_dnwl_aup1	s8_esd			
signal_23_asym_hv_2k_dnwl_aup1_Okika	s8_esd			
signal_23_sym_hv_2k	s8_esd			
signal_23_sym_hv_2k_dnwl_aup1	s8_esd			
signal_23_sym_hv_2k_dnwl_aup1_a	s8_esd			
signal_30_sym_hv_2k	s8_esd			
signal_40_sym_hv_2k	s8_esd			
signal_40_sym_hv_2k_dnwl	s8_esd			
signal_40_sym_hv_2k_dnwl_aup1	s8_esd			
signal_40_sym_hv_2k_dnwl_aup1_b	s8_esd			
signal_5_sym_hv_local	s8_esd			
signal_5_sym_hv_local_5term	s8_esd			
signal_5_sym_hv_local_5term_dnwl	s8_esd			
signal_5_sym_lv_local	s8_esd			
signal_50_sym_hv_2k	s8_esd			
signal_50_sym_hv_2k_dnwl_aup1	s8_esd			
signal_50_sym_hv_2k_dnwl_aup1_b	s8_esd			
signal_50_sym_hv_2k_dnwl_aup1_s2g_0p5_d2g_0p66	s8_esd			
signal_50_sym_hv_2k_dnwl_aup1_s2g_0p5_d2g_1p0	s8_esd			
signal_50_sym_hv_2k_dnwl_aup1_s2g_0p5_d2g_1p34	s8_esd			
signal_50_sym_hv_2k_dnwl_aup1_s2g_0p5_d2g_1p68	s8_esd			
signal_50_sym_hv_2k_dnwl_aup1_s2g_0p5_d2g_2p02	s8_esd			
signal_50_sym_hv_2k_dnwl_aup1_s2g_0p5_d2g_2p36	s8_esd			
signal_50_sym_hv_2k_dnwl_aup1_s2g_0p5_d2g_2p70	s8_esd			
signal_50_sym_hv_2k_dnwl_aup1_s2g_1p68_d2g_2p70	s8_esd			
signal_50_sym_hv_2k_dnwl_aup1_s2g_2p70_d2g_2p70	s8_esd			
signal_50_sym_hv_4k	s8_esd			
signal_50_sym_hv_4k_dnwl_aup1	s8_esd			
sio_paddiode2pwr_100_hv	s8iom0s8	s8iom0s8/V0.1.0/verilog/s8iom0s8_sio_paddiode2pwr_100_hv.v s8iom0s8/V0.2.0/verilog/s8iom0s8_sio_paddiode2pwr_100_hv.v s8iom0s8/V0.2.1/verilog/s8iom0s8_sio_paddiode2pwr_100_hv.v	--fromfile--	
sio_paddiode2pwr_300_hv	s8iom0s8	s8iom0s8/V0.1.0/verilog/s8iom0s8_sio_paddiode2pwr_300_hv.v s8iom0s8/V0.2.0/verilog/s8iom0s8_sio_paddiode2pwr_300_hv.v s8iom0s8/V0.2.1/verilog/s8iom0s8_sio_paddiode2pwr_300_hv.v	--fromfile--	
sio_res250only_small_esd	s8iom0s8	s8iom0s8/V0.1.0/verilog/s8iom0s8_sio_res250only_small_esd.v s8iom0s8/V0.2.0/verilog/s8iom0s8_sio_res250only_small_esd.v s8iom0s8/V0.2.1/verilog/s8iom0s8_sio_res250only_small_esd.v	--fromfile--	
sio_res75only_noshorts_nometal_esd	s8iom0s8	s8iom0s8/V0.1.0/verilog/s8iom0s8_sio_res75only_noshorts_nometal_esd.v s8iom0s8/V0.2.0/verilog/s8iom0s8_sio_res75only_noshorts_nometal_esd.v s8iom0s8/V0.2.1/verilog/s8iom0s8_sio_res75only_noshorts_nometal_esd.v	--fromfile--	
sio_signal_5_sym_hv_local_5term_esd	s8iom0s8	s8iom0s8/V0.1.0/verilog/s8iom0s8_sio_signal_5_sym_hv_local_5term_esd.v s8iom0s8/V0.2.0/verilog/s8iom0s8_sio_signal_5_sym_hv_local_5term_esd.v s8iom0s8/V0.2.1/verilog/s8iom0s8_sio_signal_5_sym_hv_local_5term_esd.v	--fromfile--	
sio_signal_50_sym_hv_2k_dnwl_aup1_b_esd	s8iom0s8	s8iom0s8/V0.1.0/verilog/s8iom0s8_sio_signal_50_sym_hv_2k_dnwl_aup1_b_esd.v s8iom0s8/V0.2.0/verilog/s8iom0s8_sio_signal_50_sym_hv_2k_dnwl_aup1_b_esd.v s8iom0s8/V0.2.1/verilog/s8iom0s8_sio_signal_50_sym_hv_2k_dnwl_aup1_b_esd.v	--fromfile--	
sleep_aopwr_pargate	scs8ls			
sleep_aopwr_pargate_s8d	scs8ls			
sleep_kapwr_pargate	scs8ls			
sleep_kapwr_pargate_s8d	scs8ls			
sleep_pargate	scs8ls		connect vpwr to virtpwr when not in sleep mode	
sleep_pargate_plv	scs8lp		????	
sleep_pargate_s8d	scs8ls			
sleep_sergate_plv	scs8lp		connect vpr to virtpwr when not in sleep mode	
sleep_vnwell_pargate	scs8ls			
sleep_vnwell_pargate_s8d	scs8ls			
source_follower	s8_esd			
srdlrtp	scs8lp		????	
srdlstp	scs8lp		????	
srdlxtp	scs8lp		????	
sregrbp	scs8lp		????	
sregsbp	scs8lp		????	
srsdfrtn	scs8lp		Scan flop with sleep mode, inverted reset, inverted clock, single output	
srsdfrtp	scs8lp scs8ls		Scan flop with sleep mode, inverted reset, non-inverted clock, single output	
srsdfrtp2	scs8ls			
srsdfstp	scs8lp scs8ls		Scan flop with sleep mode, inverted set, non-inverted clock, single output	
srsdfstp2	scs8ls			
srsdfxtp	scs8lp scs8ls		Scan flop with sleep mode, non-inverted clock, single output	
srsdfxtp2	scs8ls			
stdby_pump_cell	s8_esd			
stubs_scs8hd	--na--			
stubs_scs8hd_pg	--na--			
stubs_scs8hd_pg_body	--na--			
tap	scs8hd scs8hs scs8lp scs8ls scs8ms		Tap cell with no tap connections (no contacts on metal1)	
tapmet1	scs8hs scs8ls scs8ms		Tap cell with isolated power and ground connections	
tapvgnd	scs8hd scs8hs scs8lp scs8ls scs8ms		Tap cell with tap to ground, isolated power connection 1 row down	
tapvgnd2	scs8hd scs8hs scs8lp scs8ls scs8ms		Tap cell with tap to ground, isolated power connection 2 rows down	
tapvgndnovpb	scs8ls		Substrate only tap cell	
tapvpwrvgnd	scs8hd scs8hs scs8lp scs8ls scs8ms		Substrate and well tap cell	
top_amuxsplitv2	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_amuxsplitv2.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_amuxsplitv2.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_amuxsplitv2.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_amuxsplitv2.v	--fromfile--	
top_axresv2	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_axresv2.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_axresv2.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_axresv2.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_axresv2.v	--fromfile--	
top_b2b_diode	s8iom0s8			
top_gpio	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_gpio.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_gpio.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_gpio.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_gpio.v	--fromfile--	
top_gpio_ovtv2	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_gpio_ovtv2.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_gpio_ovtv2.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_gpio_ovtv2.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_gpio_ovtv2.v	--fromfile--	
top_gpiosf	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_gpiosf.v	--fromfile--	
top_gpiosfv2	s8iom0s8			
top_gpiov2	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_gpiov2.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_gpiov2.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_gpiov2.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_gpiov2.v	--fromfile--	
top_gpiovrefv2	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_gpiovrefv2.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_gpiovrefv2.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_gpiovrefv2.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_gpiovrefv2.v	--fromfile--	
top_ground_hvc_wpad	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_ground_hvc_wpad.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_ground_hvc_wpad.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_ground_hvc_wpad.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_ground_hvc_wpad.v	--fromfile--	
top_ground_lvc_wpad	s8iom0s8		Base ground I/O pad with low voltage clamp	
top_ground_padonlyv2	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_ground_padonlyv2.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_ground_padonlyv2.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_ground_padonlyv2.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_ground_padonlyv2.v	--fromfile--	
top_hvclamp_wopad	s8iom0s8		High voltage clamp I/O cell only (no pad)	
top_hvclamp_wopad_sio	s8iom0s8			
top_hvclamp_wopadv2	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_hvclamp_wopadv2.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_hvclamp_wopadv2.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_hvclamp_wopadv2.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_hvclamp_wopadv2.v	--fromfile--	
top_lvc_b2b_wopad	s8iom0s8			
top_lvclamp	s8iom0s8			
top_padv2	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_padv2.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_padv2.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_padv2.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_padv2.v	--fromfile--	
top_power_hvc_wpad	s8iom0s8			
top_power_hvc_wpadv2	s8iom0s8			
top_power_lvc_wpad	s8iom0s8			
top_power_padonlyv2	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_power_padonlyv2.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_power_padonlyv2.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_power_padonlyv2.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_power_padonlyv2.v	--fromfile--	
top_pwrdetv2	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_pwrdetv2.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_pwrdetv2.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_pwrdetv2.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_pwrdetv2.v	--fromfile--	
top_refgen	s8iom0s8	s8iom0s8/V0.1.0/verilog/s8iom0s8_top_refgen.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_refgen.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_refgen.v	--fromfile--	
top_refgen_new	s8iom0s8	s8iom0s8/V0.1.0/verilog/s8iom0s8_top_refgen_new.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_refgen_new.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_refgen_new.v	--fromfile--	
top_sio	s8iom0s8			
top_sio_macro	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_sio_macro.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_sio_macro.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_sio_macro.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_sio_macro.v	--fromfile--	
top_tp1	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_tp1.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_tp1.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_tp1.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_tp1.v	--fromfile--	
top_tp1v2	s8iom0s8	s8iom0s8/V0.1.0/verilog/s8iom0s8_top_tp1v2.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_tp1v2.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_tp1v2.v	--fromfile--	
top_tp2	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_tp2.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_tp2.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_tp2.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_tp2.v	--fromfile--	
top_tp2v2	s8iom0s8	s8iom0s8/V0.1.0/verilog/s8iom0s8_top_tp2v2.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_tp2v2.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_tp2v2.v	--fromfile--	
top_tp3	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_tp3.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_tp3.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_tp3.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_tp3.v	--fromfile--	
top_vrefcapv2	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_vrefcapv2.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_vrefcapv2.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_vrefcapv2.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_vrefcapv2.v	--fromfile--	
top_xres	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_xres.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_xres.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_xres.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_xres.v	--fromfile--	
top_xres_2	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_xres_2.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_xres_2.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_xres_2.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_xres_2.v	--fromfile--	
top_xres2v2	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_xres2v2.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_xres2v2.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_xres2v2.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_xres2v2.v	--fromfile--	
top_xres3v2	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_xres3v2.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_xres3v2.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_xres3v2.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_xres3v2.v	--fromfile--	
top_xres4v2	s8iom0s8	s8iom0s8/V0.0.0/verilog/s8iom0s8_top_xres4v2.v s8iom0s8/V0.1.0/verilog/s8iom0s8_top_xres4v2.v s8iom0s8/V0.2.0/verilog/s8iom0s8_top_xres4v2.v s8iom0s8/V0.2.1/verilog/s8iom0s8_top_xres4v2.v	--fromfile--	
top_xresfilterv2	s8iom0s8			
U_DF_N_R_NO_SLEEPB_pg	--na-- scs8lpa	scs8hs/V0.0.0/verilog/U_DF_N_R_NO_SLEEPB_pg.v scs8lp/V0.0.0/verilog/scs8lpa_U_DF_N_R_NO_SLEEPB_pg.v scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DF_N_R_NO_SLEEPB_pg.v	--fromfile--	
U_DF_N_R_SLEEPB_pg	--na-- scs8lpa	scs8hs/V0.0.0/verilog/U_DF_N_R_SLEEPB_pg.v scs8lp/V0.0.0/verilog/scs8lpa_U_DF_N_R_SLEEPB_pg.v	--fromfile--	
U_DF_P	scs8lpa	scs8hd/V0.0.1/verilog/scs8hd_pg_U_DF_P.v scs8hvl/V0.0.0/verilog/scs8hvl_pg_U_DF_P.v scs8hvl/V0.0.1/verilog/scs8hvl_pg_U_DF_P.v scs8lp/V0.0.0/verilog/scs8lpa_U_DF_P.v scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DF_P.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_DF_P.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_DF_P.v	--fromfile--	
U_DF_P_NO_pg	--na-- scs8lpa	scs8hd/V0.0.1/verilog/scs8hd_pg_U_DF_P_NO_pg.v scs8hs/V0.0.0/verilog/U_DF_P_NO_pg.v scs8hvl/V0.0.0/verilog/scs8hvl_pg_U_DF_P_NO_pg.v scs8hvl/V0.0.1/verilog/scs8hvl_pg_U_DF_P_NO_pg.v scs8lp/V0.0.0/verilog/scs8lpa_U_DF_P_NO_pg.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_DF_P_NO_pg.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_DF_P_NO_pg.v	--fromfile--	
U_DF_P_NO_SLEEPB	--na--	scs8hs/V0.0.0/verilog/U_DF_P_NO_SLEEPB.v	--fromfile--	
U_DF_P_NO_SLEEPB_pg	--na-- scs8lpa	scs8hs/V0.0.0/verilog/U_DF_P_NO_SLEEPB_pg.v scs8lp/V0.0.0/verilog/scs8lpa_U_DF_P_NO_SLEEPB_pg.v scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DF_P_NO_SLEEPB_pg.v	--fromfile--	
U_DF_P_pg	--na--	scs8hs/V0.0.0/verilog/U_DF_P_pg.v	--fromfile--	
U_DF_P_R	scs8lpa	scs8hd/V0.0.1/verilog/scs8hd_pg_U_DF_P_R.v scs8hvl/V0.0.0/verilog/scs8hvl_pg_U_DF_P_R.v scs8hvl/V0.0.1/verilog/scs8hvl_pg_U_DF_P_R.v scs8lp/V0.0.0/verilog/scs8lpa_U_DF_P_R.v scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DF_P_R.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_DF_P_R.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_DF_P_R.v	--fromfile--	
U_DF_P_R_NO_pg	--na-- scs8lpa	scs8hd/V0.0.1/verilog/scs8hd_pg_U_DF_P_R_NO_pg.v scs8hs/V0.0.0/verilog/U_DF_P_R_NO_pg.v scs8hvl/V0.0.0/verilog/scs8hvl_pg_U_DF_P_R_NO_pg.v scs8hvl/V0.0.1/verilog/scs8hvl_pg_U_DF_P_R_NO_pg.v scs8lp/V0.0.0/verilog/scs8lpa_U_DF_P_R_NO_pg.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_DF_P_R_NO_pg.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_DF_P_R_NO_pg.v	--fromfile--	
U_DF_P_R_NO_SLEEPB	--na--	scs8hs/V0.0.0/verilog/U_DF_P_R_NO_SLEEPB.v	--fromfile--	
U_DF_P_R_NO_SLEEPB_pg	--na-- scs8lpa	scs8hs/V0.0.0/verilog/U_DF_P_R_NO_SLEEPB_pg.v scs8lp/V0.0.0/verilog/scs8lpa_U_DF_P_R_NO_SLEEPB_pg.v scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DF_P_R_NO_SLEEPB_pg.v	--fromfile--	
U_DF_P_R_pg	--na--	scs8hs/V0.0.0/verilog/U_DF_P_R_pg.v	--fromfile--	
U_DF_P_R_SLEEPB_pg	--na--	scs8hs/V0.0.0/verilog/U_DF_P_R_SLEEPB_pg.v	--fromfile--	
U_DF_P_S	scs8lpa	scs8hd/V0.0.1/verilog/scs8hd_pg_U_DF_P_S.v scs8hvl/V0.0.0/verilog/scs8hvl_pg_U_DF_P_S.v scs8hvl/V0.0.1/verilog/scs8hvl_pg_U_DF_P_S.v scs8lp/V0.0.0/verilog/scs8lpa_U_DF_P_S.v scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DF_P_S.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_DF_P_S.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_DF_P_S.v	--fromfile--	
U_DF_P_S_NO_pg	--na-- scs8lpa	scs8hd/V0.0.1/verilog/scs8hd_pg_U_DF_P_S_NO_pg.v scs8hs/V0.0.0/verilog/U_DF_P_S_NO_pg.v scs8hvl/V0.0.0/verilog/scs8hvl_pg_U_DF_P_S_NO_pg.v scs8hvl/V0.0.1/verilog/scs8hvl_pg_U_DF_P_S_NO_pg.v scs8lp/V0.0.0/verilog/scs8lpa_U_DF_P_S_NO_pg.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_DF_P_S_NO_pg.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_DF_P_S_NO_pg.v	--fromfile--	
U_DF_P_S_NO_SLEEPB	--na--	scs8hs/V0.0.0/verilog/U_DF_P_S_NO_SLEEPB.v	--fromfile--	
U_DF_P_S_NO_SLEEPB_pg	--na-- scs8lpa	scs8hs/V0.0.0/verilog/U_DF_P_S_NO_SLEEPB_pg.v scs8lp/V0.0.0/verilog/scs8lpa_U_DF_P_S_NO_SLEEPB_pg.v scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DF_P_S_NO_SLEEPB_pg.v	--fromfile--	
U_DF_P_S_pg	--na--	scs8hs/V0.0.0/verilog/U_DF_P_S_pg.v	--fromfile--	
U_DF_P_S_SLEEPB_pg	--na--	scs8hs/V0.0.0/verilog/U_DF_P_S_SLEEPB_pg.v	--fromfile--	
U_DF_P_SLEEPB_pg	--na--	scs8hs/V0.0.0/verilog/U_DF_P_SLEEPB_pg.v	--fromfile--	
U_DFB_SETDOM	scs8lpa			
U_DFB_SETDOM_NO_pg	scs8lpa			
U_DFB_SETDOM_notify_pg	--na--			
U_DFB_SETDOM_pg	--na--			
U_DL_ISOLATCH_NO_pg	--na-- scs8lpa			
U_DL_ISOLATCH_pg	--na--			
U_DL_P	scs8lpa	scs8hd/V0.0.1/verilog/scs8hd_lpflow_pg_U_DL_P.v scs8hd/V0.0.1/verilog/scs8hd_pg_U_DL_P.v scs8hvl/V0.0.0/verilog/scs8hvl_pg_U_DL_P.v scs8hvl/V0.0.1/verilog/scs8hvl_pg_U_DL_P.v scs8lp/V0.0.0/verilog/scs8lpa_U_DL_P.v scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DL_P.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_DL_P.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_DL_P.v	--fromfile--	
U_DL_P_NO_pg	--na-- scs8lpa	scs8hd/V0.0.1/verilog/scs8hd_lpflow_pg_U_DL_P_NO_pg.v scs8hd/V0.0.1/verilog/scs8hd_pg_U_DL_P_NO_pg.v scs8hs/V0.0.0/verilog/U_DL_P_NO_pg.v scs8hvl/V0.0.0/verilog/scs8hvl_pg_U_DL_P_NO_pg.v scs8hvl/V0.0.1/verilog/scs8hvl_pg_U_DL_P_NO_pg.v scs8lp/V0.0.0/verilog/scs8lpa_U_DL_P_NO_pg.v scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DL_P_NO_pg.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_DL_P_NO_pg.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_DL_P_NO_pg.v	--fromfile--	
U_DL_P_NO_SLEEPB	--na--	scs8hs/V0.0.0/verilog/U_DL_P_NO_SLEEPB.v	--fromfile--	
U_DL_P_NO_SLEEPB_pg	--na-- scs8lpa	scs8hs/V0.0.0/verilog/U_DL_P_NO_SLEEPB_pg.v scs8lp/V0.0.0/verilog/scs8lpa_U_DL_P_NO_SLEEPB_pg.v scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DL_P_NO_SLEEPB_pg.v	--fromfile--	
U_DL_P_pg	--na--	scs8hs/V0.0.0/verilog/U_DL_P_pg.v	--fromfile--	
U_DL_P_R	scs8lpa	scs8hd/V0.0.1/verilog/scs8hd_pg_U_DL_P_R.v scs8hvl/V0.0.0/verilog/scs8hvl_pg_U_DL_P_R.v scs8hvl/V0.0.1/verilog/scs8hvl_pg_U_DL_P_R.v scs8lp/V0.0.0/verilog/scs8lpa_U_DL_P_R.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_DL_P_R.v scs8ls/V0.1.0/verilog/scs8ls_udb_U_DL_P_R.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_DL_P_R.v	--fromfile--	
U_DL_P_R_NO_pg	--na-- scs8lpa	scs8hd/V0.0.1/verilog/scs8hd_pg_U_DL_P_R_NO_pg.v scs8hs/V0.0.0/verilog/U_DL_P_R_NO_pg.v scs8hvl/V0.0.0/verilog/scs8hvl_pg_U_DL_P_R_NO_pg.v scs8hvl/V0.0.1/verilog/scs8hvl_pg_U_DL_P_R_NO_pg.v scs8lp/V0.0.0/verilog/scs8lpa_U_DL_P_R_NO_pg.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_DL_P_R_NO_pg.v scs8ls/V0.1.0/verilog/scs8ls_udb_pg_U_DL_P_R_NO_pg.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_DL_P_R_NO_pg.v	--fromfile--	
U_DL_P_R_NO_SLEEPB	--na--	scs8hs/V0.0.0/verilog/U_DL_P_R_NO_SLEEPB.v	--fromfile--	
U_DL_P_R_NO_SLEEPB_pg	--na-- scs8lpa	scs8hs/V0.0.0/verilog/U_DL_P_R_NO_SLEEPB_pg.v scs8lp/V0.0.0/verilog/scs8lpa_U_DL_P_R_NO_SLEEPB_pg.v scs8ls/V0.1.0/verilog/scs8ls_lpflow_pg_U_DL_P_R_NO_SLEEPB_pg.v	--fromfile--	
U_DL_P_R_pg	--na--	scs8hs/V0.0.0/verilog/U_DL_P_R_pg.v	--fromfile--	
U_DL_P_R_SLEEPB_pg	--na-- scs8lpa	scs8hs/V0.0.0/verilog/U_DL_P_R_SLEEPB_pg.v scs8lp/V0.0.0/verilog/scs8lpa_U_DL_P_R_SLEEPB_pg.v	--fromfile--	
U_DL_P_SB_NO_SLEEPB	--na--	scs8hs/V0.0.0/verilog/U_DL_P_SB_NO_SLEEPB.v	--fromfile--	
U_DL_P_SB_NO_SLEEPB_pg	--na-- scs8lpa	scs8hs/V0.0.0/verilog/U_DL_P_SB_NO_SLEEPB_pg.v scs8lp/V0.0.0/verilog/scs8lpa_U_DL_P_SB_NO_SLEEPB_pg.v	--fromfile--	
U_DL_P_SB_SLEEPB_pg	--na-- scs8lpa	scs8hs/V0.0.0/verilog/U_DL_P_SB_SLEEPB_pg.v scs8lp/V0.0.0/verilog/scs8lpa_U_DL_P_SB_SLEEPB_pg.v	--fromfile--	
U_DL_P_SLEEPB_pg	--na-- scs8lpa	scs8hs/V0.0.0/verilog/U_DL_P_SLEEPB_pg.v scs8lp/V0.0.0/verilog/scs8lpa_U_DL_P_SLEEPB_pg.v	--fromfile--	
U_EDF_P_NO_pg	--na--	scs8hs/V0.0.0/verilog/U_EDF_P_NO_pg.v	--fromfile--	
U_EDF_P_pg	--na--	scs8hs/V0.0.0/verilog/U_EDF_P_pg.v	--fromfile--	
U_MUX_2	--na-- scs8lpa	scs8hs/V0.0.0/verilog/U_MUX_2_1.v	--fromfile--	
U_MUX_2_1_INV	--na-- scs8lpa	scs8hd/V0.0.1/verilog/scs8hd_pg_U_MUX_2_1_INV.v scs8hs/V0.0.0/verilog/U_MUX_2_1_INV.v scs8lp/V0.0.0/verilog/scs8lpa_U_MUX_2_1_INV.v scs8ls/V0.1.0/verilog/scs8ls_pg_U_MUX_2_1_INV.v scs8ms/V0.0.0/verilog/scs8ms_pg_U_MUX_2_1_INV.v	--fromfile--	
U_MUX_4	--na-- scs8lpa	scs8hs/V0.0.0/verilog/U_MUX_4_2.v	--fromfile--	
U_VPWR_VGND	--na-- scs8lpa			
U_VPWR_VGND_SLEEP	scs8lpa			
udb_a2222o	scs8ls			
udb_a2222oi	scs8ls			
udb_br0	scs8ls			
udb_bushold0	scs8ls			
udb_dec2to4	scs8ls			
udb_dlclkrn	scs8ls			
udb_dlclkrp	scs8ls			
udb_emux2	scs8ls			
udb_fasumb	scs8ls			
udb_mux3	scs8ls			
udb_pg_U_DL_P_R_NO_pg	scs8ls	scs8ls/V0.1.0/verilog/scs8ls_udb_pg_U_DL_P_R_NO_pg.v	--fromfile--	
udb_pg_U_MUX_2	scs8ls			
udb_pg_U_MUX_2_1_SEL_X	scs8ls	scs8ls/V0.1.0/verilog/scs8ls_udb_pg_U_MUX_2_1_SEL_X.v	--fromfile--	
udb_pg_U_MUX_4	scs8ls			
udb_pg_U_MUX_4_2_SEL_X	scs8ls	scs8ls/V0.1.0/verilog/scs8ls_udb_pg_U_MUX_4_2_SEL_X.v	--fromfile--	
udb_pg_U_VPWR_VGND	scs8ls			
udb_srlb	scs8ls			
udb_U_DL_P_R	scs8ls	scs8ls/V0.1.0/verilog/scs8ls_udb_U_DL_P_R.v	--fromfile--	
vcseldrv_casc_nmos	s8_esd			
vcseldrv_casc_nmos_no_power	s8_esd			
vcseldrv_casc_nmos_tmp	s8_esd			
vcseldrv_casc_nmos_tmp2	s8_esd			
vcseldrv_casc_pmos	s8_esd			
vcseldrv_casc_pmos_no_power	s8_esd			
xnor2	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		2-input exclusive NOR	!(A ^ B)
xnor3	scs8hd scs8hs scs8lp scs8ls scs8ms		3-input exclusive NOR	
xor2	scs8hd scs8hs scs8hvl scs8lp scs8ls scs8ms		2-input exclusive OR	A ^ B
xor3	scs8hd scs8hs scs8lp scs8ls scs8ms		3-input exclusive OR	A ^ B ^ C
udp_dff$NSR	scs8hd scs8hs scs8lp scs8ls scs8ms		Negative edge triggered D flip-flop (Q output UDP) with both active high reset and set (set dominate).	
udp_dff$NRS	scs8hd scs8hs scs8lp scs8ls scs8ms		Negative edge triggered D flip-flop (Q output UDP) with both active high reset and set (reset dominate).	
udp_dff$NSR_pp$PG$N	scs8hd scs8hs scs8lp scs8ls scs8ms		Negative edge triggered D flip-flop (Q output UDP) with both active high reset and set (set dominate). Includes VPWR and VGND power pins and notifier pin.	
udp_dff$NSR_pp$PG	scs8hd scs8hs scs8lp scs8ls scs8ms		Negative edge triggered D flip-flop (Q output UDP) with both active high reset and set (set dominate). Includes VPWR and VGND power pins.	
udp_isolatch_pp$PKG$sN	scs8hd scs8hs scs8lp scs8ls scs8ms		Power isolating latch. Includes VPWR, KAPWR, and VGND power pins with notifier and active low sleep pin (SLEEP_B).	
udp_isolatch_pp$PKG$s	scs8hd scs8hs scs8lp scs8ls scs8ms		Power isolating latch. Includes VPWR, KAPWR, and VGND power pins with active low sleep pin (SLEEP_B).	
udp_isolatchhv_pp$PLG$S	scs8hd scs8hs scs8lp scs8ls scs8ms		Power isolating latch (for HV). Includes VPWR, LVPWR, and VGND power pins with active high sleep pin (SLEEP).	
fill	scs8hd scs8hs scs8lp scs8ls scs8ms		Fill cell.	
fill_diode	scs8hd scs8hs scs8lp scs8ls scs8ms		Fill diode.