Change to 1port / 2port names.
diff --git a/common.py b/common.py
index ebb37b9..457e082 100755
--- a/common.py
+++ b/common.py
@@ -1631,29 +1631,57 @@
'sense_amp' : 'openram_sense_amp',
'write_driver' : 'openram_write_driver',
- 'cell_1rw_1r' : 'openram_cell_1rw_1r',
- 'col_cap_cell_1rw_1r' : 'openram_cell_1rw_1r_cap_col',
- 'dummy_cell_1rw_1r' : 'openram_cell_1rw_1r_dummy',
- 'replica_cell_1rw_1r' : 'openram_cell_1rw_1r_replica',
- 'row_cap_cell_1rw_1r' : 'openram_cell_1rw_1r_cap_row',
+ 'cell_1rw_1r' : 'openram_cell_2port',
+ 'col_cap_cell_1rw_1r' : 'openram_cell_2port_cap_col',
+ 'dummy_cell_1rw_1r' : 'openram_cell_2port_dummy',
+ 'replica_cell_1rw_1r' : 'openram_cell_2port_replica',
+ 'row_cap_cell_1rw_1r' : 'openram_cell_2port_cap_row',
- 'cell_6t' : 'openram_cell_6t',
- 'col_cap_cell_6t' : 'openram_cell_6t_cap_col',
- 'dummy_cell_6t' : 'openram_cell_6t_dummy',
- 'replica_cell_6t' : 'openram_cell_6t_replica',
- 'row_cap_cell_6t' : 'openram_cell_6t_cap_row',
+ # -----------------------------------------------------
- #'cell_1rw_1r' : 'openram_cell_1rw_1r',
- 'cell_1rw_1r_col_cap' : 'openram_cell_1rw_1r_cap_col',
- 'cell_1rw_1r_dummy' : 'openram_cell_1rw_1r_dummy',
- 'cell_1rw_1r_replica' : 'openram_cell_1rw_1r_replica',
- 'cell_1rw_1r_row_cap' : 'openram_cell_1rw_1r_cap_row',
+ #'cell_1rw_1r' : 'openram_cell_2port',
+ 'cell_1rw_1r_col_cap' : 'openram_cell_2port_cap_col',
+ 'cell_1rw_1r_dummy' : 'openram_cell_2port_dummy',
+ 'cell_1rw_1r_replica' : 'openram_cell_2port_replica',
+ 'cell_1rw_1r_row_cap' : 'openram_cell_2port_cap_row',
- #'cell_6t' : 'openram_cell_6t',
- 'cell_6t_col_cap' : 'openram_cell_6t_cap_col',
- 'cell_6t_dummy' : 'openram_cell_6t_dummy',
- 'cell_6t_replica' : 'openram_cell_6t_replica',
- 'cell_6t_row_cap' : 'openram_cell_6t_cap_row',
+ 'cell_2port' : 'openram_cell_2port',
+ 'col_cap_cell_2port' : 'openram_cell_2port_cap_col',
+ 'dummy_cell_2port' : 'openram_cell_2port_dummy',
+ 'replica_cell_2port' : 'openram_cell_2port_replica',
+ 'row_cap_cell_2port' : 'openram_cell_2port_cap_row',
+
+ #'cell_2port' : 'openram_cell_2port',
+ 'cell_2port_col_cap' : 'openram_cell_2port_cap_col',
+ 'cell_2port_dummy' : 'openram_cell_2port_dummy',
+ 'cell_2port_replica' : 'openram_cell_2port_replica',
+ 'cell_2port_row_cap' : 'openram_cell_2port_cap_row',
+
+ # -----------------------------------------------------
+
+ 'cell_6t' : 'openram_cell_1port',
+ 'col_cap_cell_6t' : 'openram_cell_1port_cap_col',
+ 'dummy_cell_6t' : 'openram_cell_1port_dummy',
+ 'replica_cell_6t' : 'openram_cell_1port_replica',
+ 'row_cap_cell_6t' : 'openram_cell_1port_cap_row',
+
+ #'cell_6t' : 'openram_cell_1port',
+ 'cell_6t_col_cap' : 'openram_cell_1port_cap_col',
+ 'cell_6t_dummy' : 'openram_cell_1port_dummy',
+ 'cell_6t_replica' : 'openram_cell_1port_replica',
+ 'cell_6t_row_cap' : 'openram_cell_1port_cap_row',
+
+ 'cell_1port' : 'openram_cell_1port',
+ 'col_cap_cell_1port' : 'openram_cell_1port_cap_col',
+ 'dummy_cell_1port' : 'openram_cell_1port_dummy',
+ 'replica_cell_1port' : 'openram_cell_1port_replica',
+ 'row_cap_cell_1port' : 'openram_cell_1port_cap_row',
+
+ #'cell_1port' : 'openram_cell_1port',
+ 'cell_1port_col_cap' : 'openram_cell_1port_cap_col',
+ 'cell_1port_dummy' : 'openram_cell_1port_dummy',
+ 'cell_1port_replica' : 'openram_cell_1port_replica',
+ 'cell_1port_row_cap' : 'openram_cell_1port_cap_row',
'L1M1_CDNS_594327665970': 'sram_l1m1',
'l1m1_cdns_594327665970': 'sram_l1m1',
@@ -1722,26 +1750,26 @@
'openram_write_driver'
>>> convert_cellname('cell_1rw_1r')
- 'openram_cell_1rw_1r'
+ 'openram_cell_2port'
>>> convert_cellname('col_cap_cell_1rw_1r')
- 'openram_cell_1rw_1r_cap_col'
+ 'openram_cell_2port_cap_col'
>>> convert_cellname('dummy_cell_1rw_1r')
- 'openram_cell_1rw_1r_dummy'
+ 'openram_cell_2port_dummy'
>>> convert_cellname('replica_cell_1rw_1r')
- 'openram_cell_1rw_1r_replica'
+ 'openram_cell_2port_replica'
>>> convert_cellname('row_cap_cell_1rw_1r')
- 'openram_cell_1rw_1r_cap_row'
+ 'openram_cell_2port_cap_row'
>>> convert_cellname('cell_6t')
- 'openram_cell_6t'
+ 'openram_cell_1port'
>>> convert_cellname('col_cap_cell_6t')
- 'openram_cell_6t_cap_col'
+ 'openram_cell_1port_cap_col'
>>> convert_cellname('dummy_cell_6t')
- 'openram_cell_6t_dummy'
+ 'openram_cell_1port_dummy'
>>> convert_cellname('replica_cell_6t')
- 'openram_cell_6t_replica'
+ 'openram_cell_1port_replica'
>>> convert_cellname('row_cap_cell_6t')
- 'openram_cell_6t_cap_row'
+ 'openram_cell_1port_cap_row'
OpenRAM prefix
--------------
@@ -1760,26 +1788,26 @@
'openram_write_driver'
>>> convert_cellname('openram_cell_1rw_1r')
- 'openram_cell_1rw_1r'
+ 'openram_cell_2port'
>>> convert_cellname('openram_col_cap_cell_1rw_1r')
- 'openram_cell_1rw_1r_cap_col'
+ 'openram_cell_2port_cap_col'
>>> convert_cellname('openram_dummy_cell_1rw_1r')
- 'openram_cell_1rw_1r_dummy'
+ 'openram_cell_2port_dummy'
>>> convert_cellname('openram_replica_cell_1rw_1r')
- 'openram_cell_1rw_1r_replica'
+ 'openram_cell_2port_replica'
>>> convert_cellname('openram_row_cap_cell_1rw_1r')
- 'openram_cell_1rw_1r_cap_row'
+ 'openram_cell_2port_cap_row'
>>> convert_cellname('openram_cell_6t')
- 'openram_cell_6t'
+ 'openram_cell_1port'
>>> convert_cellname('openram_col_cap_cell_6t')
- 'openram_cell_6t_cap_col'
+ 'openram_cell_1port_cap_col'
>>> convert_cellname('openram_dummy_cell_6t')
- 'openram_cell_6t_dummy'
+ 'openram_cell_1port_dummy'
>>> convert_cellname('openram_replica_cell_6t')
- 'openram_cell_6t_replica'
+ 'openram_cell_1port_replica'
>>> convert_cellname('openram_row_cap_cell_6t')
- 'openram_cell_6t_cap_row'
+ 'openram_cell_1port_cap_row'
SRAM prefix
-----------
@@ -1798,26 +1826,26 @@
'openram_write_driver'
>>> convert_cellname('sram_cell_1rw_1r')
- 'openram_cell_1rw_1r'
+ 'openram_cell_2port'
>>> convert_cellname('sram_col_cap_cell_1rw_1r')
- 'openram_cell_1rw_1r_cap_col'
+ 'openram_cell_2port_cap_col'
>>> convert_cellname('sram_dummy_cell_1rw_1r')
- 'openram_cell_1rw_1r_dummy'
+ 'openram_cell_2port_dummy'
>>> convert_cellname('sram_replica_cell_1rw_1r')
- 'openram_cell_1rw_1r_replica'
+ 'openram_cell_2port_replica'
>>> convert_cellname('sram_row_cap_cell_1rw_1r')
- 'openram_cell_1rw_1r_cap_row'
+ 'openram_cell_2port_cap_row'
>>> convert_cellname('sram_cell_6t')
- 'openram_cell_6t'
+ 'openram_cell_1port'
>>> convert_cellname('sram_col_cap_cell_6t')
- 'openram_cell_6t_cap_col'
+ 'openram_cell_1port_cap_col'
>>> convert_cellname('sram_dummy_cell_6t')
- 'openram_cell_6t_dummy'
+ 'openram_cell_1port_dummy'
>>> convert_cellname('sram_replica_cell_6t')
- 'openram_cell_6t_replica'
+ 'openram_cell_1port_replica'
>>> convert_cellname('sram_row_cap_cell_6t')
- 'openram_cell_6t_cap_row'
+ 'openram_cell_1port_cap_row'
>>> convert_cellname('libcell')
@@ -2702,7 +2730,7 @@
'sky130_fd_bd_sram__sram_sp_colend_cent'
>>> convert_cell_fullname('sram_cell_1rw_1r')
- 'sky130_fd_bd_sram__openram_cell_1rw_1r'
+ 'sky130_fd_bd_sram__openram_cell_2port'
>>> convert_cell_fullname('sram_dff')
'sky130_fd_bd_sram__openram_sram_dff'
