diff --git a/common.py b/common.py
index df09bed..ef9d2a7 100755
--- a/common.py
+++ b/common.py
@@ -1625,63 +1625,79 @@
 
 SRAM_CELLS = {
     'sram_dff'              : 'openram_sram_dff',
-    'nand2_dec'             : 'openram_nand2_dec',
-    'nand3_dec'             : 'openram_nand3_dec',
-    'nand4_dec'             : 'openram_nand4_dec',
     'sense_amp'             : 'openram_sense_amp',
     'write_driver'          : 'openram_write_driver',
 
-    'cell_1rw_1r'           : 'openram_cell_dp',
-    'col_cap_cell_1rw_1r'   : 'openram_cell_dp_cap_col',
-    'dummy_cell_1rw_1r'     : 'openram_cell_dp_dummy',
-    'replica_cell_1rw_1r'   : 'openram_cell_dp_replica',
-    'row_cap_cell_1rw_1r'   : 'openram_cell_dp_cap_row',
+    # -----------------------------------------------------
+
+    'nand2_dec'             : 'openram_sp_nand2_dec',
+    'nand3_dec'             : 'openram_sp_nand3_dec',
+    'nand4_dec'             : 'openram_sp_nand4_dec',
+
+    'openram_nand2_dec'     : 'openram_sp_nand2_dec',
+    'openram_nand3_dec'     : 'openram_sp_nand3_dec',
+    'openram_nand4_dec'     : 'openram_sp_nand4_dec',
+
+    'nand2_dec_2port'       : 'openram_dp_nand2_dec',
+    'nand3_dec_2port'       : 'openram_dp_nand3_dec',
+    'nand4_dec_2port'       : 'openram_dp_nand4_dec',
+
+    'openram_nand2_dec_2port' : 'openram_dp_nand2_dec',
+    'openram_nand3_dec_2port' : 'openram_dp_nand3_dec',
+    'openram_nand4_dec_2port' : 'openram_dp_nand4_dec',
+
 
     # -----------------------------------------------------
 
-    #'cell_1rw_1r'          : 'openram_cell_dp',
-    'cell_1rw_1r_col_cap'   : 'openram_cell_dp_cap_col',
-    'cell_1rw_1r_dummy'     : 'openram_cell_dp_dummy',
-    'cell_1rw_1r_replica'   : 'openram_cell_dp_replica',
-    'cell_1rw_1r_row_cap'   : 'openram_cell_dp_cap_row',
+    'cell_1rw_1r'           : 'openram_dp_cell',
+    'col_cap_cell_1rw_1r'   : 'openram_dp_cell_cap_col',
+    'dummy_cell_1rw_1r'     : 'openram_dp_cell_dummy',
+    'replica_cell_1rw_1r'   : 'openram_dp_cell_replica',
+    'row_cap_cell_1rw_1r'   : 'openram_dp_cell_cap_row',
 
-    'cell_2port'            : 'openram_cell_dp',
-    'col_cap_cell_2port'    : 'openram_cell_dp_cap_col',
-    'dummy_cell_2port'      : 'openram_cell_dp_dummy',
-    'replica_cell_2port'    : 'openram_cell_dp_replica',
-    'row_cap_cell_2port'    : 'openram_cell_dp_cap_row',
+    #'cell_1rw_1r'          : 'openram_dp_cell',
+    'cell_1rw_1r_col_cap'   : 'openram_dp_cell_cap_col',
+    'cell_1rw_1r_dummy'     : 'openram_dp_cell_dummy',
+    'cell_1rw_1r_replica'   : 'openram_dp_cell_replica',
+    'cell_1rw_1r_row_cap'   : 'openram_dp_cell_cap_row',
 
-    #'cell_2port'           : 'openram_cell_dp',
-    'cell_2port_col_cap'    : 'openram_cell_dp_cap_col',
-    'cell_2port_dummy'      : 'openram_cell_dp_dummy',
-    'cell_2port_replica'    : 'openram_cell_dp_replica',
-    'cell_2port_row_cap'    : 'openram_cell_dp_cap_row',
+    'cell_2port'            : 'openram_dp_cell',
+    'col_cap_cell_2port'    : 'openram_dp_cell_cap_col',
+    'dummy_cell_2port'      : 'openram_dp_cell_dummy',
+    'replica_cell_2port'    : 'openram_dp_cell_replica',
+    'row_cap_cell_2port'    : 'openram_dp_cell_cap_row',
+
+    #'cell_2port'           : 'openram_dp_cell',
+    'cell_2port_col_cap'    : 'openram_dp_cell_cap_col',
+    'cell_2port_dummy'      : 'openram_dp_cell_dummy',
+    'cell_2port_replica'    : 'openram_dp_cell_replica',
+    'cell_2port_row_cap'    : 'openram_dp_cell_cap_row',
 
     # -----------------------------------------------------
 
-    'cell_6t'               : 'openram_cell_sp',
-    'col_cap_cell_6t'       : 'openram_cell_sp_cap_col',
-    'dummy_cell_6t'         : 'openram_cell_sp_dummy',
-    'replica_cell_6t'       : 'openram_cell_sp_replica',
-    'row_cap_cell_6t'       : 'openram_cell_sp_cap_row',
+    'cell_6t'               : 'openram_sp_cell',
+    'col_cap_cell_6t'       : 'openram_sp_cell_cap_col',
+    'dummy_cell_6t'         : 'openram_sp_cell_dummy',
+    'replica_cell_6t'       : 'openram_sp_cell_replica',
+    'row_cap_cell_6t'       : 'openram_sp_cell_cap_row',
 
-    #'cell_6t'              : 'openram_cell_sp',
-    'cell_6t_col_cap'       : 'openram_cell_sp_cap_col',
-    'cell_6t_dummy'         : 'openram_cell_sp_dummy',
-    'cell_6t_replica'       : 'openram_cell_sp_replica',
-    'cell_6t_row_cap'       : 'openram_cell_sp_cap_row',
+    #'cell_6t'              : 'openram_sp_cell',
+    'cell_6t_col_cap'       : 'openram_sp_cell_cap_col',
+    'cell_6t_dummy'         : 'openram_sp_cell_dummy',
+    'cell_6t_replica'       : 'openram_sp_cell_replica',
+    'cell_6t_row_cap'       : 'openram_sp_cell_cap_row',
 
-    'cell_1port'            : 'openram_cell_sp',
-    'col_cap_cell_1port'    : 'openram_cell_sp_cap_col',
-    'dummy_cell_1port'      : 'openram_cell_sp_dummy',
-    'replica_cell_1port'    : 'openram_cell_sp_replica',
-    'row_cap_cell_1port'    : 'openram_cell_sp_cap_row',
+    'cell_1port'            : 'openram_sp_cell',
+    'col_cap_cell_1port'    : 'openram_sp_cell_cap_col',
+    'dummy_cell_1port'      : 'openram_sp_cell_dummy',
+    'replica_cell_1port'    : 'openram_sp_cell_replica',
+    'row_cap_cell_1port'    : 'openram_sp_cell_cap_row',
 
-    #'cell_1port'           : 'openram_cell_sp',
-    'cell_1port_col_cap'    : 'openram_cell_sp_cap_col',
-    'cell_1port_dummy'      : 'openram_cell_sp_dummy',
-    'cell_1port_replica'    : 'openram_cell_sp_replica',
-    'cell_1port_row_cap'    : 'openram_cell_sp_cap_row',
+    #'cell_1port'           : 'openram_sp_cell',
+    'cell_1port_col_cap'    : 'openram_sp_cell_cap_col',
+    'cell_1port_dummy'      : 'openram_sp_cell_dummy',
+    'cell_1port_replica'    : 'openram_sp_cell_replica',
+    'cell_1port_row_cap'    : 'openram_sp_cell_cap_row',
 
     'L1M1_CDNS_594327665970': 'sram_l1m1',
     'l1m1_cdns_594327665970': 'sram_l1m1',
@@ -1736,13 +1752,13 @@
     'openram_sram_dff'
 
     >>> convert_cellname('nand2_dec')
-    'openram_nand2_dec'
+    'openram_sp_nand2_dec'
 
     >>> convert_cellname('nand3_dec')
-    'openram_nand3_dec'
+    'openram_sp_nand3_dec'
 
     >>> convert_cellname('nand4_dec')
-    'openram_nand4_dec'
+    'openram_sp_nand4_dec'
 
     >>> convert_cellname('sense_amp')
     'openram_sense_amp'
@@ -1750,26 +1766,26 @@
     'openram_write_driver'
 
     >>> convert_cellname('cell_1rw_1r')
-    'openram_cell_dp'
+    'openram_dp_cell'
     >>> convert_cellname('col_cap_cell_1rw_1r')
-    'openram_cell_dp_cap_col'
+    'openram_dp_cell_cap_col'
     >>> convert_cellname('dummy_cell_1rw_1r')
-    'openram_cell_dp_dummy'
+    'openram_dp_cell_dummy'
     >>> convert_cellname('replica_cell_1rw_1r')
-    'openram_cell_dp_replica'
+    'openram_dp_cell_replica'
     >>> convert_cellname('row_cap_cell_1rw_1r')
-    'openram_cell_dp_cap_row'
+    'openram_dp_cell_cap_row'
 
     >>> convert_cellname('cell_6t')
-    'openram_cell_sp'
+    'openram_sp_cell'
     >>> convert_cellname('col_cap_cell_6t')
-    'openram_cell_sp_cap_col'
+    'openram_sp_cell_cap_col'
     >>> convert_cellname('dummy_cell_6t')
-    'openram_cell_sp_dummy'
+    'openram_sp_cell_dummy'
     >>> convert_cellname('replica_cell_6t')
-    'openram_cell_sp_replica'
+    'openram_sp_cell_replica'
     >>> convert_cellname('row_cap_cell_6t')
-    'openram_cell_sp_cap_row'
+    'openram_sp_cell_cap_row'
 
     OpenRAM prefix
     --------------
@@ -1784,37 +1800,37 @@
     >>> convert_cellname('openram_dff')
     'openram_dff'
     >>> convert_cellname('openram_nand2_dec')
-    'openram_nand2_dec'
+    'openram_sp_nand2_dec'
     >>> convert_cellname('openram_nand3_dec')
-    'openram_nand3_dec'
+    'openram_sp_nand3_dec'
     >>> convert_cellname('openram_nand4_dec')
-    'openram_nand4_dec'
+    'openram_sp_nand4_dec'
     >>> convert_cellname('openram_sense_amp')
     'openram_sense_amp'
     >>> convert_cellname('openram_write_driver')
     'openram_write_driver'
 
     >>> convert_cellname('openram_cell_1rw_1r')
-    'openram_cell_dp'
+    'openram_dp_cell'
     >>> convert_cellname('openram_col_cap_cell_1rw_1r')
-    'openram_cell_dp_cap_col'
+    'openram_dp_cell_cap_col'
     >>> convert_cellname('openram_dummy_cell_1rw_1r')
-    'openram_cell_dp_dummy'
+    'openram_dp_cell_dummy'
     >>> convert_cellname('openram_replica_cell_1rw_1r')
-    'openram_cell_dp_replica'
+    'openram_dp_cell_replica'
     >>> convert_cellname('openram_row_cap_cell_1rw_1r')
-    'openram_cell_dp_cap_row'
+    'openram_dp_cell_cap_row'
 
     >>> convert_cellname('openram_cell_6t')
-    'openram_cell_sp'
+    'openram_sp_cell'
     >>> convert_cellname('openram_col_cap_cell_6t')
-    'openram_cell_sp_cap_col'
+    'openram_sp_cell_cap_col'
     >>> convert_cellname('openram_dummy_cell_6t')
-    'openram_cell_sp_dummy'
+    'openram_sp_cell_dummy'
     >>> convert_cellname('openram_replica_cell_6t')
-    'openram_cell_sp_replica'
+    'openram_sp_cell_replica'
     >>> convert_cellname('openram_row_cap_cell_6t')
-    'openram_cell_sp_cap_row'
+    'openram_sp_cell_cap_row'
 
     SRAM prefix
     -----------
@@ -1822,37 +1838,37 @@
     >>> convert_cellname('sram_dff')
     'openram_sram_dff'
     >>> convert_cellname('sram_nand2_dec')
-    'openram_nand2_dec'
+    'openram_sp_nand2_dec'
     >>> convert_cellname('sram_nand3_dec')
-    'openram_nand3_dec'
+    'openram_sp_nand3_dec'
     >>> convert_cellname('sram_nand4_dec')
-    'openram_nand4_dec'
+    'openram_sp_nand4_dec'
     >>> convert_cellname('sram_sense_amp')
     'openram_sense_amp'
     >>> convert_cellname('sram_write_driver')
     'openram_write_driver'
 
     >>> convert_cellname('sram_cell_1rw_1r')
-    'openram_cell_dp'
+    'openram_dp_cell'
     >>> convert_cellname('sram_col_cap_cell_1rw_1r')
-    'openram_cell_dp_cap_col'
+    'openram_dp_cell_cap_col'
     >>> convert_cellname('sram_dummy_cell_1rw_1r')
-    'openram_cell_dp_dummy'
+    'openram_dp_cell_dummy'
     >>> convert_cellname('sram_replica_cell_1rw_1r')
-    'openram_cell_dp_replica'
+    'openram_dp_cell_replica'
     >>> convert_cellname('sram_row_cap_cell_1rw_1r')
-    'openram_cell_dp_cap_row'
+    'openram_dp_cell_cap_row'
 
     >>> convert_cellname('sram_cell_6t')
-    'openram_cell_sp'
+    'openram_sp_cell'
     >>> convert_cellname('sram_col_cap_cell_6t')
-    'openram_cell_sp_cap_col'
+    'openram_sp_cell_cap_col'
     >>> convert_cellname('sram_dummy_cell_6t')
-    'openram_cell_sp_dummy'
+    'openram_sp_cell_dummy'
     >>> convert_cellname('sram_replica_cell_6t')
-    'openram_cell_sp_replica'
+    'openram_sp_cell_replica'
     >>> convert_cellname('sram_row_cap_cell_6t')
-    'openram_cell_sp_cap_row'
+    'openram_sp_cell_cap_row'
 
 
     >>> convert_cellname('libcell')
@@ -2746,7 +2762,7 @@
     'sky130_fd_bd_sram__sram_sp_colend_cent'
 
     >>> convert_cell_fullname('sram_cell_1rw_1r')
-    'sky130_fd_bd_sram__openram_cell_dp'
+    'sky130_fd_bd_sram__openram_dp_cell'
 
     >>> convert_cell_fullname('sram_dff')
     'sky130_fd_bd_sram__openram_sram_dff'