#!/usr/bin/env python3
# Copyright 2020 The Skywater PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

import argparse
from pathlib import Path
if __name__ == '__main__':
    parser = argparse.ArgumentParser()
    parser.add_argument(
        "input_dir",
        help="The path to the directory containing diagrams and schematics",
        type=Path)
    args = parser.parse_args()
    # fix output/skywater-pdk/libraries/openfpga/Skywater_130/SRC/routing/routing.v.full
    routingsimplepath = args.input_dir / 'output/skywater-pdk/libraries/openfpga/Skywater_130/SRC/routing/routing.v.full'
    tmpfile = Path('./routing.full.v.tmp')
    with open(routingsimplepath, 'r') as routingsimple:
        with open(tmpfile, 'w') as finfile:
            for line in routingsimple:
                newline = line.replace('.v', '.simple.v')
                finfile.write(newline)
    tmpfile.rename(routingsimplepath)