
read_lef digital/sky90fd.lef
read_verilog examples/design.v
link_design "top"

initialize_floorplan \
  -die_area  "0 0 3588 5188" \
  -core_area "250 250 3338 4938" \
  -site      core12t

make_tracks

####################################
# global connections
####################################
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDPE$}
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDCE$}
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VPWR}
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VPB}
add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground
add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSSE$}
add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VGND}
add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VNB}
global_connect
####################################
# voltage domains
####################################
set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
####################################
# standard cell grid
####################################
define_pdn_grid -name {grid} -voltage_domains {CORE}

add_pdn_ring -grid grid -layer {M4Cu M5Cu} -widths 8.0 -spacings 5.0 -core_offset 5

add_pdn_stripe -grid {grid} -layer {M1Cu} -width {0.16} -pitch {7.68} -offset {0} -followpins -extend_to_core_ring
add_pdn_stripe -grid {grid} -layer {M4Cu} -width {8.0} -pitch {136.0} -snap_to_grid -extend_to_core_ring
add_pdn_stripe -grid {grid} -layer {M5Cu} -width {8.0} -pitch {136.0} -snap_to_grid -extend_to_core_ring
add_pdn_connect -grid {grid} -layers {M1Cu M4Cu}
add_pdn_connect -grid {grid} -layers {M4Cu M5Cu}

pdn::allow_repair_channels true

pdngen